From nobody Mon May 6 07:06:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85936+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85936+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642814542; cv=none; d=zohomail.com; s=zohoarc; b=LBapoI7GgoBv7tdEB/tPaDXESzABDzdBG8s1q/ES6HO8PxyalXi/Lx+f8adTrDQRvgDAamHcRoSLvLJHJkeQ+HdnPBTMcOPXfyVntPPewfvyz/x4Bt3L6v4OLFSJsRV1iFrGfcvW0wvIOmtHuTYonFAEnRO/omN0mVbPT1L+dj4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642814542; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Z7zjm3cNPk4+48KC9dNMD7nx0NTtGM5iHNCUawqKFVg=; b=nICttzkmlnpNwprL65Kpx1ZPTCKJigONruwBEt0fDa8LLFqc8sepTmRqqKf+WN7QeuF9ofLYZOeH50cOx5Tgs/qtDo5EDg/9cyFiuHVHqVjKdCrLTdg5WnxC0eCmhYAe+ShKaaGYin0vr23Xmo5uxrT8DuYCiA79BHWaBIP+B2M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85936+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642814542220219.85272300993563; Fri, 21 Jan 2022 17:22:22 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 31ncYY1788612xiCn7epF0gu; Fri, 21 Jan 2022 17:22:21 -0800 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.3110.1642814539708345311 for ; Fri, 21 Jan 2022 17:22:20 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10234"; a="226452250" X-IronPort-AV: E=Sophos;i="5.88,307,1635231600"; d="scan'208";a="226452250" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2022 17:22:19 -0800 X-IronPort-AV: E=Sophos;i="5.88,307,1635231600"; d="scan'208";a="533498546" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2022 17:22:18 -0800 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleyOpenBoardPkg/BoardPortTemplate: Add a template for board porting. Date: Fri, 21 Jan 2022 17:22:06 -0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: HdBbSlADcl7RYjTiEOTiHe66x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642814541; bh=zSQvNpUNU30m1Sok40+TS85oyhge3psk4ZUar2jxlWc=; h=Cc:Date:From:Reply-To:Subject:To; b=aJ4+KTTR8C87eSu7tD0YpX6Ho50PFzkU0Wo1GzChWjfVpsZ+NuS0nwGTjMJ3IQkEwTR cLWiM+lFSdqbp6IIXU0+cWEPXexWYN82Zg2MMzOU0NuqMuZKj5IvcqWwzpTlzfOWA3Doa 1g2GhQjwD3R9WCB0/vvFxuRe9nGn18Q1Vx4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642814543174100009 Content-Type: text/plain; charset="utf-8" The template includes the build files and UBA modules that typically need to be ported for a new board. WhitleyOpenBoardPkg/Readme.md contains instructions on use. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Nate DeSimone --- Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/Dsc/UbaSingle= BoardPei.dsc | 36 + Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/Fdf/UbaSingle= BoardDxe.fdf | 12 + Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.dsc = | 40 + Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.fdf = | 807 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 99 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 118 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 47 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 115 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 47 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 127 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 + Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/AcpiTablePcds.c | 52 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/GpioTable.c | 287 +++++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/IioBifurInit.c | 246 ++++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/KtiEparam.c | 68 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/PcdData.c | 273 +++++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/PchEarlyUpdate.c | 92 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/PeiBoardInit.h | 77 ++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/PeiBoardInitLib.c | 156 ++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/PeiBoardInitLib.inf | 166 ++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/SlotTable.c | 171 +++++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/SoftStrapFixup.c | 119 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemp= late/Pei/UsbOC.c | 124 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_board.py = | 125 +++ Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_config.cfg = | 36 + 27 files changed, 3568 insertions(+) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/D= sc/UbaSingleBoardPei.dsc b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemp= late/Include/Dsc/UbaSingleBoardPei.dsc new file mode 100644 index 0000000000..9bce2c631b --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/Dsc/UbaS= ingleBoardPei.dsc @@ -0,0 +1,36 @@ +## @file UbaSingleBoardPei.dsc +# DSC include file for a single UBA board build items +# +# @copyright +# Copyright 2012 - 2020 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Components.IA32] +# +# Board Init Peim +# +$(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf { + + NULL|$(RP_PKG)/$(BOARD_NAME)/Uba/Type$(BOARD_NAME)/Pei/PeiBoard= InitLib.inf + # + #### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!! + # + # Do not place any platform specific PeiBoardInitLib.inf entrie= s after PeiCommonBoardInitLib.inf + # The order of this libary class list is translated directly in= to the autogen.c created + # to execute the libary constructors for all the platforms in t= his list. + # PeiCommonBoardInitLib.inf depends on being the last construct= or to execute and + # assumes that a platform specific constructor has executed and= installed its UBA + # configuration information. + # + NULL|$(RP_PKG)/Uba/UbaMain/Common/Pei/PeiCommonBoardInitLib.inf +} + +[Components.X64] +# +# Platform TypeBoardPortTemplate +# +$(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/UsbOcUpdateDxe/UsbOc= UpdateDxe.inf +$(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/IioCfgUpdateDxe/IioC= fgUpdateDxe.inf +$(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/SlotDataUpdateDxe/Sl= otDataUpdateDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/F= df/UbaSingleBoardDxe.fdf b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemp= late/Include/Fdf/UbaSingleBoardDxe.fdf new file mode 100644 index 0000000000..5a0191d8b8 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Include/Fdf/UbaS= ingleBoardDxe.fdf @@ -0,0 +1,12 @@ +## @file UbaSingleBoardDxe.fdf +# FDF include file for a single UBA board build +# +# @copyright +# Copyright 2020 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/UsbOcUpdateDxe/= UsbOcUpdateDxe.inf +INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/IioCfgUpdateDxe= /IioCfgUpdateDxe.inf +INF $(RP_PKG)/$(BOARD_NAME)/Uba/TypeBoardPortTemplate/Dxe/SlotDataUpdateD= xe/SlotDataUpdateDxe.inf diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformP= kg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.d= sc new file mode 100644 index 0000000000..e3e8ceb7ce --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.dsc @@ -0,0 +1,40 @@ +## @file PlatformPkg.dsc +# BoardPortTemplate reference platform single board build target. +# +# +# @copyright +# Copyright 2008 - 2020 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + PLATFORM_NAME =3D WhitleyOpenBoardPkg + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + +!include $(RP_PKG)/PlatformPkg.dsc + +[Defines] + DEFINE BOARD_NAME =3D BoardPortTemplate + PLATFORM_GUID =3D f3518dd4-5dec-4d2c-9ac9-561121e2= 628b + OUTPUT_DIRECTORY =3D Build/$(RP_PKG) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + FLASH_DEFINITION =3D $(RP_PKG)/$(BOARD_NAME)/Platform= Pkg.fdf + +# +# Advanced feature selection/enablement +# + +[PcdsFixedAtBuild] + gPlatformTokenSpaceGuid.PcdBoardId|0x26 # TypeBoardPortTemplate + +# +# Increase debug message levels +# Several options are provided, last uncommented one will take effect +# +#!include $(RP_PKG)/Include/Dsc/EnableRichDebugMessages.dsc +#!include $(RP_PKG)/Include/Dsc/EnableAllDebugMessages.dsc + +!include $(RP_PKG)/$(BOARD_NAME)/Include/Dsc/UbaSingleBoardPei.dsc diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformP= kg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.f= df new file mode 100644 index 0000000000..ca5d135405 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.fdf @@ -0,0 +1,807 @@ +## @file +# FDF file of platform with 64-bit DXE +# This package provides platform specific modules and flash layout informa= tion. +# +# @copyright +# Copyright 2006 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + DEFINE PLATFORM_PKG =3D MinPlatformPkg + +# 0x00000060 =3D (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_F= FS_FILE_HEADER)) +DEFINE FDF_FIRMWARE_HEADER_SIZE =3D 0x00000060 + +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D = 0x90 # FV Header plus FFS header + +DEFINE VPD_HEADER_SIZE =3D 0x00000090 + +!if $(FSP_MODE) =3D=3D 0 + DEFINE FSP_BIN_DIR =3D Api +!else + DEFINE FSP_BIN_DIR =3D Dispatch +!endif + +# +# Note: FlashNv PCD naming conventions are as follows: +# Note: This should be 100% true of all PCD's in the gCpPlatFlashTo= kenSpaceGuid space, and for +# Others should be examined with an effort to work toward thi= s guideline. +# PcdFlash*Base is an address, usually in the range of 0xf* of FD's,= note change in FDF spec +# PcdFlash*Size is a hex count of the length of the FD or FV +# All Fv will have the form 'PcdFlashFv', and all Fd will have the f= orm 'PcdFlashFd' +# +# Also all values will have a PCD assigned so that they can be used = in the system, and +# the FlashMap edit tool can be used to change the values here, with= out effecting the code. +# This requires all code to only use the PCD tokens to recover the v= alues. + + +# +# 16MiB Total FLASH Image (visible in memory mapped IO) +# +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D 0xFF000000 +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D 0x01000000 + +##########################################################################= ###### +# +# FD SECPEI +# +# Contains all the SEC and PEI modules +# +# Layout: (Low address to high address) +# +# FvBsp for board specific components +# FvPostMemory for compressed post memory MinPlatform spec required co= mponents +# FvFspS for compressed post memory silicon initialization components +# FvPostMemorySilicon for silicon components +# FvFspM for pre memory silicon initialization components +# FvPreMemorySilicon for silicon components +# FvFspT for temp RAM silicon initilization components +# FvBspPreMemory for board specific components required to intialize m= emory +# FvAdvancedPreMemory FV for advanced features components +# FvPreMemory for components required by MinPlatform spec and to initi= alize memory +# FvPreMemorySecurity FV for stage 6 required components +# Contains reset vector +# +##########################################################################= ###### + +[FD.SecPei] + BaseAddress =3D 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiBase #The base address of the FLASH Device + Size =3D 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSec= PeiSize #The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x360 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # At this time, the FSP FV must be aligned at the same address they were= built to, 0xFFD00000 + # This will be corrected in the future. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D 0x0001= 0000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must =3D = 0xFFD00000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D 0x0004= 0000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D 0x0022= 1000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D 0x0000= 6000 # Size must match WhitleyFspPkg.fdf content + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize =3D 0x0000= 1000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.P= cdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize -= gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSiz= e - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset =3D 0x00= 000000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvBspPreMemorySize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvBspSize + FV =3D FvBsp + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkg= TokenSpaceGuid.PcdFlashFvPostMemorySize + FV =3D FvPostMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspSSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_S.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspMSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_M.fd + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvFspTSize + FILE =3D $(FSP_BIN_PKG)/Fsp_Rebased_T.fd + + # + # Shared FV layout + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvBspPreMemorySize + FV =3D FvBspPreMemory + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvPreMemorySize + FV =3D FvPreMemory + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase =3D gCpP= latFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid= .PcdFlashFvBspSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSp= aceGuid.PcdFlashFvPostMemorySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspSSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspMSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGui= d.PcdFlashFvFspTSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase =3D gMin= PlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgToken= SpaceGuid.PcdFlashFvBspPreMemorySize + + # + # Set duplicate PCD + # These should not need to be changed + # + + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemoryBase + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemorySize + + # + # For API mode, wrappers have some duplicate PCD as well + # + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspSBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspTBase + +##########################################################################= ###### +# +# FD Main +# +# All DXE modules and other regions +# +# Layout: (Low address to high address) +# +# FvAdvanced for advanced feature components +# Assorted advanced feature FV +# FvSecurity for MinPlatform spec required components needed to boot s= ecurely +# FvOsBoot for MinPlatform spec required components needed to boot OS +# FvLateSilicon for silicon specific components +# FvUefiBoot for MinPlatform spec required components needed to boot t= o UEFI shell +# +##########################################################################= ###### +[FD.Main] + BaseAddress =3D 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainBase # The base address of the FLASH Device + Size =3D 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFd= MainSize # The size in bytes of the FLASH Device + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x9C0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # These are out of flash layout order because FvAdvanced gets any remain= ing space + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D 0x0001= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D 0x0023= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D 0x0004= C000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.Pcd= FlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize + + # + # Calculate Offsets Once (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each offset is the prior region's offset plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D 0x0000= 0000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize + + # + # FV Layout (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvAdvancedSize + FV =3D FvAdvanced + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvSecuritySize + FV =3D FvSecurity + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvOsBootSize + FV =3D FvOsBoot + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvUefiBootSize + FV =3D FvUefiBoot + + # + # Calculate base addresses (Do not modify) + # This layout is specified by the EDK II Minimum Platform Archicture spe= cification. + # Each base is the prior region's base plus the prior region's size. + # + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase =3D gCpPla= tFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedOffset + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvAdvancedSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvSecuritySize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase =3D gMinPl= atformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpace= Guid.PcdFlashFvOsBootSize + +##########################################################################= ###### +# +# FD BINARY +# +# Contains the OPROM and other binary modules +# +# Layout: (Low address to high address) +# +# FvOpRom containing pre-built components +# FvAcmRegion containing ACM related content +# FV Header + Blank Space (1K) +# Policy block (3K) +# Blank space to align ACM on 64K boundary (60K) +# ACM binary +# FvMicrocode containing microcode update patches +# Unformatted region for PCI Gen 3 Data +# FvVpd containing PCD VPD data +# FvWhea for WHEA data recording +# FvNvStorageVariable for UEFI Variable storage +# FvNvStorageEventLog for NV Store management +# FvNvStorageFtwWorking for Fault Tolerant Write solution +# FvNvStorageFtwSpare for Fault Tolerant Write solution +# +##########################################################################= ###### +[FD.Binary] + BaseAddress =3D 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= aryBase + Size =3D 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBin= arySize + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2E0 + + # + # These must add up to the FD Size. + # This makes it easy to adjust the various sizes without having to manua= lly calculate the offsets. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize =3D = 0x00100000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize =3D = 0x00050000 + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D = 0x000D0000 + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize =3D = 0x00010000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize =3D = 0x00030000 + # + # These four items are tightly coupled. + # The spare area size must be >=3D the first three areas. + # + # There isn't really a benefit to a larger spare area unless the FLASH d= evice + # block size is larger than the size specified. + # + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D = 0x0003C000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D = 0x00002000 + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlash= TokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceG= uid.PcdFlashNvStorageFtwWorkingSize + + # + # Calculate Offsets Once (You should not need to modify this section) + # Each offset is the prior region's offset plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = =3D 0x00000000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlat= formModuleTokenSpaceGuid.PcdFlashFvVpdSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvWheaSize + SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = =3D gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPl= atFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiM= deModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically + # + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPk= gTokenSpaceGuid.PcdMicrocodeOffsetInFv + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinP= latformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv + + # + # FV Layout (You should not need to modify this section) + # + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceG= uid.PcdFlashFvOpromSize + FV =3D FvOprom + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSp= aceGuid.PcdFlashFvAcmRegionSize + FV =3D FvAcm + + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgT= okenSpaceGuid.PcdFlashFvMicrocodeSize + FV =3D FvMicrocode + + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSp= aceGuid.PcdFlashFvVpdSize + FV =3D FvVPD + + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGu= id.PcdFlashFvWheaSize + FV =3D FvWhea + + # + # Do not modify. + # See comments in size discussion above. These four areas are tightly c= oupled and should be modified with utmost care. + # + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf + gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatF= lashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeM= odulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf + gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + DATA =3D { 0xFF } # Hack to ensure build doesn't treat the next PCD as B= ase/Size to be written + + # + # Calculate base addresses (You should not need to modify this section) + # Each base is the prior region's base plus the prior region's size. + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromOffset + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvOpromSize + SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvAcmRegionSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress =3D = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatf= ormPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE) + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatform= ModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE) + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvWheaSize + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFl= ashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize + SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase =3D = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeMo= dulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + + # + # ACM details + # + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize =3D 0x3000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000 + SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize =3D 0x000400= 00 + + # + # Other duplicate PCD + # + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase =3D gCpPlatF= lashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFla= shFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize + SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize =3D gMinPlat= formPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase + SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D gCpuUnco= reTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize +##########################################################################= ###### +# +# FD FPGA +# +# Contains the FPGA modules +# +##########################################################################= ###### + +[FD.Fpga] + BaseAddress =3D 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aBase #The base address of the FPGA Device ( 4G - 48M ) + Size =3D 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpg= aSize #The size in bytes of the FPGA Device ( 32M ) + ErasePolarity =3D 1 + BlockSize =3D 0x1000 + NumBlocks =3D 0x2000 + + 0x00000000|0x02000000 + gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpac= eGuid.PcdFlashFvFpgaBbsSize + FV =3D FvFpga + +##########################################################################= ###### +# +# FV Section +# +# [FV] section is used to define what components or modules are placed wit= hin a flash +# device file. This section also defines order the components and modules= are positioned +# within the image. The [FV] section consists of define statements, set s= tatements and +# module statements. +# +##########################################################################= ###### + +[FV.FvSecurityPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 40ab290f-8494-41cf-b302-31b178b4ce0b + +[FV.FvPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 + + INF UefiCpuPkg/SecCore/SecCore.inf + INF MdeModulePkg/Core/Pei/PeiMain.inf + + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusC= odeRouterPei.inf + INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHa= ndlerPei.inf + + INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf + + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf + INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.= inf + + INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf + + INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf + + FILE PEIM =3D ac4b7f1b-e057-47d3-b2b5-1137493c0f38 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f= 1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi + SECTION UI =3D "DynamicSiLibraryPei" + } + + INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/Platform= VariableInitPei.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPla= tformInit.inf + + INF WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf + + # + # UBA common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf + + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf + + INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf + + FILE PEIM =3D ca8efb69-d7dc-4e94-aad6-9fb373649161 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb= 69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi + SECTION UI =3D "SiliconPolicyInitPreAndPostMem" + } + + INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePreMemory.fdf + + INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerTo= SvidMap.inf + + INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf + + !if $(FSP_MODE) =3D=3D 0 + FILE PEIM =3D 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F= 3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi + SECTION UI =3D "CsrPseudoOffsetInitPeim" + } + FILE PEIM =3D 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6C= ACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi + SECTION UI =3D "RegAccessPeim" + } + FILE PEIM =3D C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F { + SECTION PEI_DEPEX =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9= BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex + SECTION Align =3D 32 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_D= IR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi + SECTION UI =3D "SiliconDataInitPeim" + } + INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf + INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf + INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf + !endif + + FILE FV_IMAGE =3D 40ab290f-8494-41cf-b302-31b178b4ce0b { + SECTION FV_IMAGE =3D FvSecurityPreMemory + } + +[FV.FvAdvancedPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 + +[FV.FvBspPreMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e6c65995-8c2d-4119-a52d-7dbf1acb45a1 + + FILE FV_IMAGE =3D 09f25d44-b2ef-4225-8b2e-e0e094b51775 { + SECTION FV_IMAGE =3D FvAdvancedPreMemory + } + +# +# FvPostMemory includes common hardware, common core variable services, lo= ad and invoke DXE etc +# +[FV.FvPostMemoryUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA + +[FV.FvPostMemory] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 3298afc4-c484-47f1-a65a-5917a54b5e8c + + FILE FV_IMAGE =3D B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvPostMemoryUncompressed + } + } + +# +# FvBsp includes board specific components +# +[FV.FvBspUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D e4c65347-fd90-4143-8a41-113e1015fe07 + +[FV.FvBsp] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 9e151cf3-ca90-444f-b33b-a9941cbc772f + + FILE FV_IMAGE =3D e4c65347-fd90-4143-8a41-113e1015fe07 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvBspUncompressed + } + } + +[FV.FvUefiBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 + + INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf + INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf + INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf + INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf + + INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf + + INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.= inf + INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDx= e.inf + + INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf + INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf + INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDx= e.inf + INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf + INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf + + INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf + INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf + INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf + INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf + INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf + #ATA for IDE/AHCI/RAID support + INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf + INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf + INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestD= xe.inf + INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf + +[FV.FvUefiBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D ab9fe87b-1e37-440c-91cc-9aea03ce7bec + + FILE FV_IMAGE =3D C4D3B0E2-FB26-44f8-A05B-E95895FCB960 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvUefiBootUncompressed + } + } + +[FV.FvOsBootUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 + + # + # DXE Phase modules + # + INF MdeModulePkg/Core/Dxe/DxeMain.inf + INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf + INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStat= usCodeRouterRuntimeDxe.inf + INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandl= erRuntimeDxe.inf + + FILE FV_IMAGE =3D B7C9F0CB-15D8-26FC-CA3F-C63947B12831 { + SECTION UI =3D "FvLateSilicon" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateS= ilicon.fv + } + + INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf + + !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfr= astructurePostMemory.fdf + + # + # UBA DXE common and board specific components + # + !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf + !include WhitleyOpenBoardPkg/$(BOARD_NAME)/Include/Fdf/UbaSingleBoardDxe= .fdf + INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf + INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf + + !if ($(FSP_MODE) =3D=3D 1) + INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf + !else + INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf + !endif + + INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf + INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf + INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf + INF UefiCpuPkg/CpuDxe/CpuDxe.inf + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + + FILE FV_IMAGE =3D a0277d07-a725-4823-90f9-6cba00782111 { + SECTION UI =3D "FvLateOpenBoard" + SECTION FV_IMAGE =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateO= penBoard.fv + } + + INF MdeModulePkg/Universal/Metronome/Metronome.inf + INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf + INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntime= Dxe.inf + INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf + INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf + + INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterR= untimeDxe.inf + INF RuleOverride =3D UI MdeModulePkg/Application/UiApp/UiApp.inf + INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf + INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf + #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV. + INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf + + INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf + + INF FatPkg/EnhancedFatDxe/Fat.inf + + INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf + + INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf + + INF ShellPkg/Application/Shell/Shell.inf + + INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf + + INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf + INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf + + INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeR= outerSmm.inf + INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.i= nf + + INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf + + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + + INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf + + INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.= inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf + INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf + + INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBu= fferDxe.inf + + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecuto= rDxe.inf + + # UEFI USB stack + INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf + + INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf + INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf + INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + + INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf + INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf + +[FV.FvOsBoot] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D c7488640-5f51-4969-b63b-89fc369e1725 + + FILE FV_IMAGE =3D CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOsBootUncompressed + } + } + +[FV.FvSecuritySilicon] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D AD262F8D-BDED-4668-A8D4-8BC73516652F + +[FV.FvSecurityUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 + + FILE FV_IMAGE =3D 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecuritySilicon + } + } + +[FV.FvSecurity] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 68134833-2ff6-4d22-973b-575d0eae8ffd + + FILE FV_IMAGE =3D 03E25550-89A5-4ee6-AF60-DB0553D91FD2 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvSecurityUncompressed + } + } + +[FV.FvAdvancedUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 70aeaf57-4997-49ce-a4f7-122980745670 + +[FV.FvAdvanced] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D f21ee7a1-53a9-453d-aee3-b6a5c25bada5 + + FILE FV_IMAGE =3D 70aeaf57-4997-49ce-a4f7-122980745670 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvAdvancedUncompressed + } + } + +# +# FV for all Microcode Updates. +# +[FV.FvMicrocode] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D D2C29BA7-3809-480F-9C3D-DE389C61425A + +!if $(CPUTARGET) =3D=3D "CPX" + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/M= icrocodeUpdates.inf +!else + INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/M= icrocodeUpdates.inf +!endif + + +[FV.FvVPD] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + LOCK_STATUS =3D FALSE + FvNameGuid =3D FFC29BA7-3809-480F-9C3D-DE389C61425A + FILE RAW =3D FF7DB236-F856-4924-90F8-CDF12FB875F3 { + $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-= 850A-24F7A8D38E08.bin + } + +# +# Various Vendor UEFI Drivers (OROMs). +# +[FV.FvOpromUncompressed] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 + +[FV.FvOprom] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD + + FILE FV_IMAGE =3D B6EDE22C-DE30-45fa-BB09-CA202C1654B7 { + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRE= D =3D TRUE { + SECTION FV_IMAGE =3D FvOpromUncompressed + } + } + +[FV.FvWhea] + BlockSize =3D 0x1000 + NumBlocks =3D 0x30 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D d6a1cd70-4b33-4994-a6ea-375f2ccc5437 + +# +# FV For ACM Binary. +# +[FV.FvAcm] + BlockSize =3D 0x1000 + NumBlocks =3D 0x50 + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 11668261-8A8D-47ca-9893-052D24435E59 + +[FV.FvFpga] + !include MinPlatformPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf + FvNameGuid =3D 974650E7-6DFE-4998-A124-CEDEC5C9B47D + +##########################################################################= ###### +# +# Rules are use with the [FV] section's module INF type to define +# how an FFS file is created for a given INF file. The following Rule are = the default +# rules for the different module type. User can add the customized rules t= o define the +# content of the FFS file. +# +##########################################################################= ###### + +!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf + +[Rule.Common.USER_DEFINED.ACPITABLE] + FILE FREEFORM =3D $(NAMED_GUID) { + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + } + +[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE] + FILE DRIVER =3D $(NAMED_GUID) { + DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex + PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi + RAW ACPI Optional |.acpi + RAW ASL Optional |.aml + UI STRING=3D"$(MODULE_NAME)" Optional + VERSION STRING=3D"$(INF_VERSION)" Optional BUILD_NUM=3D$(BUILD_NUMBE= R) + } diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/Whi= tleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/IioCfgUpda= teDxe/IioCfgUpdateDxe.c new file mode 100644 index 0000000000..3f4297361a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c @@ -0,0 +1,99 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "IioCfgUpdateDxe.h" + +EFI_STATUS +UpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeIioConfigTable =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateIioConfig, + IioSlotTable, + sizeof(IioSlotTable) + +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +IioCfgUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeBoardPortTemplate\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid, + &TypeIioConfigTable, + sizeof(TypeIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_1, + &TypeIioConfigTable, + sizeof(TypeIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_2, + &TypeIioConfigTable, + sizeof(TypeIioConfigTable) + ); + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformIioConfigDataDxeGuid_3, + &TypeIioConfigTable, + sizeof(TypeIioConfigTable) + ); + + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/Whi= tleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/IioCfgUpda= teDxe/IioCfgUpdateDxe.h new file mode 100644 index 0000000000..662fa2c650 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h @@ -0,0 +1,118 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _IIOCFG_UPDATE_DXE_H_ +#define _IIOCFG_UPDATE_DXE_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 +#define NO_SLT_IMP 0xFF +#define SLT_IMP 1 +#define HIDE 1 +#define NOT_HIDE 0 +#define VPP_PORT_0 0 +#define VPP_PORT_1 1 +#define VPP_PORT_MAX 0xFF +#define VPP_ADDR_MAX 0xFF +#define PWR_VAL_MAX 0xFF +#define PWR_SCL_MAX 0xFF + +static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =3D +{ + // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev= 0.6) + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 }, + { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 }, + { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 }, +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] =3D { + // Port | Slot | Inter | Power Limit | Power Limit | H= ot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD = | Hidden + // Index | | lock | Scale | Value | P= lug | Port | Addr | Cap | VppPort | VppAddr = | + { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C = , HIDE },//Oculink + { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C = , HIDE },//Oculink + { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 11= 8 (MRL in J65) + { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 12= 1 (MRL in J287) + { SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , E= NABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 = , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 = , HIDE }, + { SOCKET_1_INDEX + + PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + { SOCKET_1_INDEX + + PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , D= ISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MA= X , NOT_HIDE }, + // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port +}; + +#endif //_IIOCFG_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/W= hitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/IioCfgUp= dateDxe/IioCfgUpdateDxe.inf new file mode 100644 index 0000000000..fd19be6c13 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf @@ -0,0 +1,47 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D IioCfgUpdateDxeBoardPortTemplate + FILE_GUID =3D 4983CB47-56FD-4341-88EC-F0C95B36DF12 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D IioCfgUpdateEntry + +[sources] + IioCfgUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeBoardPortTemplateProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel= /WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/SlotDa= taUpdateDxe/SlotDataUpdateDxe.c new file mode 100644 index 0000000000..581bc949d5 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c @@ -0,0 +1,115 @@ +/** @file + Slot Data Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "SlotDataUpdateDxe.h" + +UINT8 +GetTypeIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeBroadwayTable[] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeBroadwayTable, + GetTypeIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeBroadwayTable, + GetTypeIOU0Setting, + 0, + GetTypeIOU2Setting +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +SlotDataUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeBoardPortTemplate\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeSlotTable, + sizeof(TypeSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gPlatformSlotDataDxeGuid, + &TypeSlotTable2, + sizeof(TypeSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel= /WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/SlotDa= taUpdateDxe/SlotDataUpdateDxe.h new file mode 100644 index 0000000000..9be882b09e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h @@ -0,0 +1,57 @@ +/** @file + + @copyright + Copyright 2016 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _SLOT_DATA_UPDATE_DXE_H_ +#define _SLOT_DATA_UPDATE_DXE_H_ + + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +#endif //_SLOT_DATA_UPDATE_DXE_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Int= el/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/Slot= DataUpdateDxe/SlotDataUpdateDxe.inf new file mode 100644 index 0000000000..5cb0c87002 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf @@ -0,0 +1,47 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SlotDataUpdateDxeBoardPortTemplate + FILE_GUID =3D A29C22DA-2EE0-4a36-A4E5-CCBCEAD1DB8F + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SlotDataUpdateEntry + +[sources] + SlotDataUpdateDxe.c + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeBoardPortTemplateProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/Whitl= eyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/UsbOcUpdateD= xe/UsbOcUpdateDxe.c new file mode 100644 index 0000000000..6bf6acede1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c @@ -0,0 +1,127 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "UsbOcUpdateDxe.h" + +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] =3D { + UsbOverCurrentPinSkip, //Port00: BMC + UsbOverCurrentPinSkip, //Port01: BMC + UsbOverCurrentPin0, //Port02: Rear Panel + UsbOverCurrentPin1, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPinSkip, //Port05: NC + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPin4, //Port07: Type A intern= al + UsbOverCurrentPinSkip, //Port08: NC + UsbOverCurrentPinSkip, //Port09: NC + UsbOverCurrentPin6, //Port10: Front Panel + UsbOverCurrentPinSkip, //Port11: NC + UsbOverCurrentPin6, //Port12: Front Panel + UsbOverCurrentPinSkip, //Port13: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] =3D { + UsbOverCurrentPin6, //Port01: Front Panel + UsbOverCurrentPin6, //Port02: Front Panel + UsbOverCurrentPin0, //Port03: Rear Panel + UsbOverCurrentPin1, //Port04: Rear Panel + UsbOverCurrentPin1, //Port05: Rear Panel + UsbOverCurrentPinSkip, //Port06: NC + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICA= L_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypePlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeUsb20OverCurrentMappings[0]; + *Usb30OverCurrentMappings =3D &TypeUsb30OverCurrentMappings[0]; + + *Usb20AfeParams =3D TypeUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypePlatformUsbOcUpdateCallback +}; + +/** + The Driver Entry Point. + + The function is the driver Entry point. + + @param ImageHandle A handle for the image that is initializing this dr= iver + @param SystemTable A pointer to the EFI system table + + @retval EFI_SUCCESS: Driver initialized successfully + @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded + @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources + +**/ +EFI_STATUS +EFIAPI +UsbOcUpdateEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable +) +{ + EFI_STATUS Status; + UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol =3D NULL; + + DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeBoardPortTemplate\n")); + Status =3D gBS->LocateProtocol ( + &gUbaConfigDatabaseProtocolGuid, + NULL, + &UbaConfigProtocol + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigProtocol->AddData ( + UbaConfigProtocol, + &gDxePlatformUbaOcConfigDataGuid, + &TypeUsbOcUpdate, + sizeof(TypeUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/Whitl= eyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/UsbOcUpdateD= xe/UsbOcUpdateDxe.h new file mode 100644 index 0000000000..3813eadae9 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h @@ -0,0 +1,27 @@ +/** @file + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _USBOC_UPDATE_DXE_H_ +#define _USBOC_UPDATE_DXE_H_ + +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + + + +#endif //_USBOC_UPDATE_DXE_H_ + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/Whi= tleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Dxe/UsbOcUpdat= eDxe/UsbOcUpdateDxe.inf new file mode 100644 index 0000000000..15208d8afc --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf @@ -0,0 +1,44 @@ +## @file +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D UsbOcUpdateDxeBoardPortTemplate + FILE_GUID =3D C92F1DF7-206C-46A7-B7D4-0F9B18E0E70A + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D UsbOcUpdateEntry + +[sources] + UsbOcUpdateDxe.c + UsbOcUpdateDxe.h + +[LibraryClasses] + BaseLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + UefiRuntimeServicesTableLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + +[Guids] + +[Protocols] + gUbaConfigDatabaseProtocolGuid + +[Depex] + gEfiPlatformTypeBoardPortTemplateProtocolGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/B= oardPortTemplate/Uba/TypeBoardPortTemplate/Pei/AcpiTablePcds.c new file mode 100644 index 0000000000..d4601f610c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/AcpiTablePcds.c @@ -0,0 +1,52 @@ +/** @file + ACPI table pcds update. + + @copyright + Copyright 2015 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include + +EFI_STATUS +TypeBoardPortTemplatePlatformUpdateAcpiTablePcds ( + VOID + ) +{ + CHAR8 AcpiName10nm[] =3D "EPRP10NM"; // USED for identify ACP= I table for 10nm in systmeboard dxe driver + CHAR8 OemTableIdXhci[] =3D "xh_nccrb"; + + UINTN Size; + EFI_STATUS Status; + + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n= ")); + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + //# + //#ACPI items + //# + Size =3D AsciiStrSize (AcpiName10nm); + Status =3D PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm); + DEBUG ((DEBUG_INFO, "%a TypeBoardPortTemplate ICX\n", __FUNCTION__)); + ASSERT_EFI_ERROR (Status); + + Size =3D AsciiStrSize (OemTableIdXhci); + Status =3D PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Board= PortTemplate/Uba/TypeBoardPortTemplate/Pei/GpioTable.c new file mode 100644 index 0000000000..44278986df --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/GpioTable.c @@ -0,0 +1,287 @@ +/** @file + + @copyright + Copyright 2020 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +#include +#include +#include +#include + +// +// Board : Wilson City RP +// +static GPIO_INIT_CONFIG mGpioTable [] =3D + { + {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N + {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0 + {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1 + {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2 + {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3 + {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N + {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N + {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N + {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N + {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI + {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10 + {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N + {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N + {GPIO_SKL_H_GPP_A13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N + {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N + {GPIO_SKL_H_GPP_A15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_15_FM_SUSACK_N + {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 + {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS + {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 + {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21 + {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22 + {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23 + {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0 + {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1 + {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N +// GPIO_SKL_H_GPP_B3 - Not Owned by BIOS +// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 + {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 + {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7 + {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8 + {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 + {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N +// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N + {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_13_RST_PLTRST_N + {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR + {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N + {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N + {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N + {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT + {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 + {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, G= pioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N + {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21 + {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE + {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N + {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP + {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N + {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N + {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_9_FM_MFG_MODE + {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},/= /GPP_C_10_FM_PCH_SATA_RAID_KEY + {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N + {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 + {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 + {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N + {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 + {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 + {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 + {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 + {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_19_RST_SMB_HOST_PCH_MUX_N +// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N + {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N + {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N + {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI + {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N + {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR + {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT + {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA + {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 + {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6 + {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7 + {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL + {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9 + {GPIO_SKL_H_GPP_D10, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11 + {GPIO_SKL_H_GPP_D12, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 + {GPIO_SKL_H_GPP_D13, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL + {GPIO_SKL_H_GPP_D14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA + {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0 + {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 + {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 + {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N + {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R + {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20 + {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21 + {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22 + {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23 + {GPIO_SKL_H_GPP_E0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone,= GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N + {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 + {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 + {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 + {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N + {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N + {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N + {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N + {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N + {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N + {GPIO_SKL_H_GPP_F0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N + {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N + {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK + {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI + {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS + {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO + {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK + {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD + {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1 + {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0 + {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N + {GPIO_SKL_H_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N + {GPIO_SKL_H_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N + {GPIO_SKL_H_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N + {GPIO_SKL_H_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N + {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL + {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA + {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21 + {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK + {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD + {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 + {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 + {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 + {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 + {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 + {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 + {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 + {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 + {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 + {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 + {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 + {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 + {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0 + {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 + {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 + {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 + {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 + {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE + {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N + {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N +// GPIO_SKL_H_GPP_G20 - Not Owned by BIOS + {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N + {GPIO_SKL_H_GPP_G22, { GpioPadModeNative3, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP + {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23 + {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 + {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N + {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 + {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 + {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 + {GPIO_SKL_H_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N + {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 + {GPIO_SKL_H_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N + {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 +// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS +// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE + {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N + {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N + {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_H20, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL + {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_H22, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL + {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23 + {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0 + {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1 + {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2 + {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3 + {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4 + {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5 + {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6 + {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7 + {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N + {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N + {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 +// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS +// GPIO_SKL_H_GPD0 - Not Owned by BIOS + {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_1_PU_ACPRESENT + {GPIO_SKL_H_GPD2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N + {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N + {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_4_FM_SLPS3_N + {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_5_FM_SLPS4_N + {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_6_FM_SLPA_N + {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_7_TP_GPD_7 + {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK + {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_9_TP_GPD_9_SLP + {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_10_FM_SLPS5_N + {GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N + {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0 + {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1 + {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2 + {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3 + {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4 + {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5 + {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6 + {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7 + {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8 + {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9 + {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10 + {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11 + {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12 + {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13 + {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14 + {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15 + {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16 + {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17 + {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18 + {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19 + {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20 + {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21 + {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22 + {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23 + {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH + {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0 + {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1 + {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN + {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV + {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0 + {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1 + {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER + {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN + {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT + {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N +// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS + {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0 + {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1 + {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2 + {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3 + {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4 + {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5 + {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6 + {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7 + {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK + {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0 + {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1 + {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2 + {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3 + {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4 + {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5 + {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6 + {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7 + {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, Gpio= DirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, Gp= ioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK +}; + +EFI_STATUS +TypeBoardPortTemplateInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformGpioInitDataGuid, + &mGpioTable, + sizeof(mGpioTable) + ); + Status =3D PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTable)); + ASSERT_EFI_ERROR (Status); + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Bo= ardPortTemplate/Uba/TypeBoardPortTemplate/Pei/IioBifurInit.c new file mode 100644 index 0000000000..f325072553 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/IioBifurInit.c @@ -0,0 +1,246 @@ +/** @file + IIO Config Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + VPP_PORT_0 =3D 0, + VPP_PORT_1, + VPP_PORT_2, + VPP_PORT_3 +} VPP_PORT; + +#define ENABLE 1 +#define DISABLE 0 + + +// +// config file : Wilson_City_PCIe_Slot_Config_1p70.xlsx +// config sheet : WilsonCity_ICX +// +static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =3D +{ + + { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 = , 0xE2 , 4 }, + { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + + { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C = , 0xE2 , 4 }, + { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_= MAX, SMB_ADDR_MAX, SMB_DATA_MAX }, + { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, 0 , 0x74 = , 0xE2 , 4 } +}; + +static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] =3D { + // Port Index | Slot |Interlock |power |Power |Hotpl= ug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |= Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer = |Retimer |Mux |Mux |ExtnCard |ExtnCard |Ex= tnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard= Hotplug|ExtnCard Hotplug|Max Retimer| + // | | |Limit Scale |Limit Value |Cap = | | |Cap |Port |Address |= |Clock | |Port | |Address |Channel = |Width |Address |Channel |Support |SMBus Port |SM= Bus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port= |Vpp Address | | + {SOCKET_0_INDEX + + PORT_1A_INDEX, 6 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2A_INDEX, 7 , DISABLE , 0 , 75 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_0_INDEX + + PORT_4A_INDEX, 2 , DISABLE , 0 , 200 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_0_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 }, + {SOCKET_0_INDEX + + PORT_5A_INDEX, 10 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5B_INDEX, 11 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5C_INDEX, 12 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + {SOCKET_0_INDEX + + PORT_5D_INDEX, 13 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 = , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x1 }, + + {SOCKET_1_INDEX + + PORT_1A_INDEX, 4 , ENABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENAB= LE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2A_INDEX, 9 , DISABLE , 0 , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x44 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x44 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x46 , 0x1 }, + {SOCKET_1_INDEX + + PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x46 , 0x1 }, + {SOCKET_1_INDEX + + PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4A_INDEX, 8 , DISABLE , 0 , 25 , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISA= BLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA= _MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , S= MB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_POR= T_MAX , SMB_ADDR_MAX , 0x0 }, + {SOCKET_1_INDEX + + PORT_5A_INDEX, 14 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5B_INDEX, 15 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x40 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5C_INDEX, 16 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_0 , 0x42 , 0x1 }, + {SOCKET_1_INDEX + + PORT_5D_INDEX, 17 , DISABLE , 0 , 25 , ENAB= LE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX ,= NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 = , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0= x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_POR= T_1 , 0x42 , 0x1 } +}; + +EFI_STATUS +UpdateIioConfig ( + IN IIO_GLOBALS *IioGlobalData + ) +{ + return EFI_SUCCESS; +} + +PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeBoardPortTemplateIioConfigTable = =3D +{ + PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE, + PLATFORM_IIO_CONFIG_UPDATE_VERSION_2, + + IioBifurcationTable, + sizeof(IioBifurcationTable), + UpdateIioConfig, + IioSlotTable, + sizeof(IioSlotTable) +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeBoardPortTemplateIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr; + UINTN PlatformIioInfoSize; + + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + // + // This is config for ICX + // + PlatformIioInfoPtr =3D &TypeBoardPortTemplateIioConfigTable; + PlatformIioInfoSize =3D sizeof(TypeBoardPortTemplateIioConfigTable); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_1, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_2, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformIioConfigDataGuid_3, + PlatformIioInfoPtr, + PlatformIioInfoSize + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Board= PortTemplate/Uba/TypeBoardPortTemplate/Pei/KtiEparam.c new file mode 100644 index 0000000000..737679341c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/KtiEparam.c @@ -0,0 +1,68 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +extern EFI_GUID gPlatformKtiEparamUpdateDataGuid; + +ALL_LANES_EPARAM_LINK_INFO KtiIcxAllLanesEparamTable[] =3D { + // + // SocketID, Freq, Link, TXEQL, CTLEPEAK + // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA K= tiEparam tables + // + // + // Socket 0 + // + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE}, + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE}, + // + // Socket 1 + // + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE}, + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_1= 12GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE} +}; + +PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeBoardPortTemplateIcxKtiEparamUpdate = =3D { + PLATFORM_KTIEP_UPDATE_SIGNATURE, + PLATFORM_KTIEP_UPDATE_VERSION, + KtiIcxAllLanesEparamTable, + sizeof (KtiIcxAllLanesEparamTable), + NULL, + 0 +}; + + +EFI_STATUS +TypeBoardPortTemplateInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA (GuidHob); + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformKtiEparamUpdateDataGuid, + &TypeBoardPortTemplateIcxKtiEparamUpdate, + sizeof(TypeBoardPortTemplateIcxKtiEparamU= pdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/BoardPo= rtTemplate/Uba/TypeBoardPortTemplate/Pei/PcdData.c new file mode 100644 index 0000000000..52cd63f421 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/PcdData.c @@ -0,0 +1,273 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include +#include +#include +#include +#include +#include +#include + +#define GPIO_SKL_H_GPP_B20 0x01010014 + +VOID TypeBoardPortTemplatePlatformUpdateVrIdAddress (VOID); + +/** + Update WilsonCity IMON SVID Information + + retval N/A +**/ +VOID +TypeBoardPortTemplatePlatformUpdateImonAddress ( + VOID + ) +{ + VCC_IMON *VccImon =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (VCC_IMON); + VccImon =3D (VCC_IMON *) PcdGetPtr (PcdImonAddr); + if (VccImon =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr =3D=3D NULL\n"= )); + return; + } + + VccImon->VrSvid[0] =3D PcdGet8 (PcdWilsonCitySvidVrP1V8); + VccImon->VrSvid[1] =3D PcdGet8 (PcdWilsonCitySvidVrVccAna); + VccImon->VrSvid[2] =3D IMON_ADDR_LIST_END; // End array with 0xFF + + PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon); +} + +/** + Update WilsonCity VR ID SVID Information + + retval N/A +**/ +VOID +TypeBoardPortTemplatePlatformUpdateVrIdAddress ( + VOID + ) +{ + MEM_SVID_MAP *MemSvidMap =3D NULL; + UINTN Size =3D 0; + + Size =3D sizeof (MEM_SVID_MAP); + MemSvidMap =3D (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap); + if (MemSvidMap =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap =3D=3D NULL= \n")); + return; + } + /* + Map VR ID Address to Memory controller + The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14,= and 0x16. + Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs = (VR ID's 0x10 and 0x12). + Those are typically shared such that MC0/MC2 share the same DDR VR (as= they are on the same side of the CPU) + and MC1/MC3 share the other. Depending on motherboard layout and other= design constraints, this could change + BIT 4 =3D> 0 or 1, SVID BUS\Interface 0 or 1 respectively + BIT 0:3 =3D> SVID ADDRESS + */ + + MemSvidMap->Socket[0].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[0].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[1].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[1].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[2].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[2].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[3].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[3].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[4].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[4].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[5].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[5].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[6].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[6].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + MemSvidMap->Socket[7].Mc[0] =3D 0x10; //SVID BUS 1, ADDR 0 + MemSvidMap->Socket[7].Mc[1] =3D 0x12; //SVID BUS 1, ADDR 2 + + PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap); +} + +EFI_STATUS +TypeBoardPortTemplatePlatformPcdUpdateCallback ( + VOID +) +{ + CHAR8 FamilyName[] =3D "Whitley"; + + CHAR8 BoardName[] =3D "EPRP"; + UINT32 Data32; + UINTN Size; + UINTN PlatformFeatureFlag =3D 0; + + CHAR16 PlatformName[] =3D L"TypeBoardPortTemplate"; + UINTN PlatformNameSize =3D 0; + EFI_STATUS Status; + + //#Integer for BoardID, must match the SKU number and be unique. + Status =3D PcdSet16S (PcdOemSkuBoardID , TypeBoardP= ortTemplate); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet16S (PcdOemSkuBoardFamily , 0x30); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Number of Sockets on Board. + Status =3D PcdSet32S (PcdOemSkuBoardSocketCount, 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + // Max channel and max DIMM + Status =3D PcdSet32S (PcdOemSkuMaxChannel , 8); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetBoolS (PcdOemSkuDimmLayout, TRUE); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //Update Onboard Video Controller PCI Ven_id, Dev_id + Status =3D PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# + //# Misc. + //# + //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF + Status =3D PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //SDP Active Flag + Status =3D PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to ID family + Size =3D AsciiStrSize (FamilyName); + Status =3D PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyNa= me); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Zero terminated string to Board Name + Size =3D AsciiStrSize (BoardName); + Status =3D PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardNam= e); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + PlatformNameSize =3D sizeof (PlatformName); + Status =3D PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)Plat= formNameSize); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNam= eSize, PlatformName); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# FeaturesBasedOnPlatform + Status =3D PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)P= latformFeatureFlag); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# Assert GPIO + Data32 =3D 0; + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + Status =3D PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20); + ASSERT_EFI_ERROR(Status); + if (EFI_ERROR(Status)) { + return Status; + } + + //# UplinkPortIndex + Status =3D PcdSet8S (PcdOemSkuUplinkPortIndex, 5); + if (EFI_ERROR(Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\= n")); + Status =3D TypeBoardPortTemplatePlatformUpdateAcpiTablePcds (); + //# BMC Pcie Port Number + PcdSet8S (PcdOemSkuBmcPciePortNumber, 5); + ASSERT_EFI_ERROR(Status); + + //# Board Type Bit Mask + PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4)= ); + ASSERT_EFI_ERROR(Status); + + //Update IMON Address + TypeBoardPortTemplatePlatformUpdateImonAddress (); + + return Status; +} + +PLATFORM_PCD_UPDATE_TABLE TypeBoardPortTemplatePcdUpdateTable =3D +{ + PLATFORM_PCD_UPDATE_SIGNATURE, + PLATFORM_PCD_UPDATE_VERSION, + TypeBoardPortTemplatePlatformPcdUpdateCallback +}; + +EFI_STATUS +TypeBoardPortTemplateInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPcdConfigDataGuid, + &TypeBoardPortTemplatePcdUpdateTable, + sizeof(TypeBoardPortTemplatePcdUpdateTabl= e) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/= BoardPortTemplate/Uba/TypeBoardPortTemplate/Pei/PchEarlyUpdate.c new file mode 100644 index 0000000000..9f94360128 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/PchEarlyUpdate.c @@ -0,0 +1,92 @@ +/** @file + Pch Early update. + + @copyright + Copyright 2019 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + +#include + +#include +#include +#include +#include + +EFI_STATUS +TypeBoardPortTemplatePchLanConfig ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi =3D NULL; + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &Dy= namicSiLibraryPpi); + if (EFI_ERROR (Status)) { + ASSERT_EFI_ERROR (Status); + return Status; + } + + DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)Syst= emConfig->LomDisableByGpio); + DynamicSiLibraryPpi->PchDisableGbe (); + + return EFI_SUCCESS; +} + +EFI_STATUS +TypeBoardPortTemplateOemInitLateHook ( + IN SYSTEM_CONFIGURATION *SystemConfig +) +{ + return EFI_SUCCESS; +} + + +PLATFORM_PCH_EARLY_UPDATE_TABLE TypeBoardPortTemplatePchEarlyUpdateTable = =3D +{ + PLATFORM_PCH_EARLY_UPDATE_SIGNATURE, + PLATFORM_PCH_EARLY_UPDATE_VERSION, + TypeBoardPortTemplatePchLanConfig, + TypeBoardPortTemplateOemInitLateHook +}; + + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +EFIAPI +TypeBoardPortTemplatePchEarlyUpdate( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchEarlyConfigDataGuid, + &TypeBoardPortTemplatePchEarlyUpdateTable, + sizeof(TypeBoardPortTemplatePchEarlyUpdateT= able) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Bo= ardPortTemplate/Uba/TypeBoardPortTemplate/Pei/PeiBoardInit.h new file mode 100644 index 0000000000..df84613ce1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/PeiBoardInit.h @@ -0,0 +1,77 @@ +/** @file + PeiBoardInit. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _PEI_BOARD_INIT_PEIM_H_ +#define _PEI_BOARD_INIT_PEIM_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// TypeBoardPortTemplate +EFI_STATUS +TypeBoardPortTemplatePlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplatePlatformUpdateAcpiTablePcds ( + VOID +); + +EFI_STATUS +TypeBoardPortTemplateInstallClockgenData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplateInstallPcdData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplatePchEarlyUpdate ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplateIioPortBifurcationInit ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplateInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +EFI_STATUS +TypeBoardPortTemplateInstallKtiEparamData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); + +// TypeBoardPortTemplate +EFI_STATUS +TypeBoardPortTemplateInstallGpioData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) ; + +EFI_STATUS +TypeBoardPortTemplateInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +); +#endif // _PEI_BOARD_INIT_PEIM_H_ diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg= /BoardPortTemplate/Uba/TypeBoardPortTemplate/Pei/PeiBoardInitLib.c new file mode 100644 index 0000000000..51a64084c7 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/PeiBoardInitLib.c @@ -0,0 +1,156 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation. + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +/** + The constructor function for Board Init Libray. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_SUCCESS Table initialization successfully. + @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table. +**/ + +#include "PeiBoardInit.h" +#include +#include +#include + +EFI_STATUS +EFIAPI +TypeBoardPortTemplatePeiBoardInitLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status =3D EFI_SUCCESS; + UBA_CONFIG_DATABASE_PPI *UbaConfigPpi; + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + UINT8 SocketIndex; + UINT8 ChannelIndex; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT (GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return EFI_NOT_FOUND; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + + if (PlatformInfo->BoardId =3D=3D TypeBoardPortTemplate) { + + DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: BoardPortTemplate\n", = PlatformInfo->BoardId)); + + // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + for (ChannelIndex =3D 0; ChannelIndex < MAX_CH; ChannelIndex++) { + switch (SocketIndex) { + case 0: + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorSmt; + break; + case 1: + // Fall through since socket 1 is PTH type + default: + // Use the more restrictive type as the default case + PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = =3D DimmConnectorPth; + break; + } + } + } + + BuildGuidDataHob ( + &gEfiPlatformInfoGuid, + &(PlatformInfo), + sizeof (EFI_PLATFORM_INFO) + ); + + Status =3D PeiServicesLocatePpi ( + &gUbaConfigDatabasePpiGuid, + 0, + NULL, + &UbaConfigPpi + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->InitSku ( + UbaConfigPpi, + PlatformInfo->BoardId, + NULL, + NULL + ); + ASSERT_EFI_ERROR (Status); + + Status =3D TypeBoardPortTemplateInstallGpioData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplateInstallPcdData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplateInstallSoftStrapData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplatePchEarlyUpdate (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplatePlatformUpdateUsbOcMappings (UbaConfig= Ppi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplateInstallSlotTableData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D TypeBoardPortTemplateInstallKtiEparamData (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; SocketIndex++) { + + // + // Set default memory type connector. + // Socket 0: DimmConnectorSmt + // Socket 1: DimmConnectorPth + // + if (SocketIndex % 2 =3D=3D 0) { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orSmt); + } else { + (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketI= ndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnect= orPth); + } + } + + // + // Initialize InterposerType to InterposerUnknown + // + for (SocketIndex =3D 0; SocketIndex < MAX_SOCKET; ++SocketIndex) { + PlatformInfo->InterposerType[SocketIndex] =3D InterposerUnknown; + } + + // + // TypeBoardPortTemplateIioPortBifurcationInit will use PlatformInfo-= >InterposerType for PPO. + // + Status =3D TypeBoardPortTemplateIioPortBifurcationInit (UbaConfigPpi); + if (EFI_ERROR(Status)) { + return Status; + } + } + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardP= kg/BoardPortTemplate/Uba/TypeBoardPortTemplate/Pei/PeiBoardInitLib.inf new file mode 100644 index 0000000000..15fb9ef37d --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/PeiBoardInitLib.inf @@ -0,0 +1,166 @@ +## @file +# Component information file for BoardInitLib in PEI post memory phase. +# +# @copyright +# Copyright 2018 - 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# @par Specification Reference: +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TypeBoardPortTemplatePeiBoardInitLib + FILE_GUID =3D 14074de7-ed3e-4f58-a19c-b461656af3e0 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL|PEIM + CONSTRUCTOR =3D TypeBoardPortTemplatePeiBoardInitLibC= onstructor + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + MemoryAllocationLib + PeiServicesLib + HobLib + PeiServicesTablePointerLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleySiliconPkg/WhitleySiliconPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[Sources] + PeiBoardInitLib.c + GpioTable.c + PcdData.c + UsbOC.c + AcpiTablePcds.c + IioBifurInit.c + SlotTable.c + KtiEparam.c + PchEarlyUpdate.c + SoftStrapFixup.c + PeiBoardInit.h + +[FixedPcd] + +[Pcd] + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID + gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily + + gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName + gOemSkuTokenSpaceGuid.PcdOemSkuBoardName + + gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount + + gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel + gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel + gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13 + + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04 + gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05 + + gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName + + gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed + gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag + + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL + gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE + + gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32 + + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10 + gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11 + + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize + gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO + gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue + gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber + gOemSkuTokenSpaceGuid.PcdOemTableIdXhci + gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex + gPlatformTokenSpaceGuid.PcdBoardTypeBitmask + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8 + gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna + gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr + gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap + + gPlatformTokenSpaceGuid.PcdMemInterposerMap + gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId + gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId + +[Ppis] + gUbaConfigDatabasePpiGuid + gDynamicSiLibraryPpiGuid ## CONSUMES + +[Guids] + gPlatformGpioInitDataGuid + +[Depex] + gDynamicSiLibraryPpiGuid diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Board= PortTemplate/Uba/TypeBoardPortTemplate/Pei/SlotTable.c new file mode 100644 index 0000000000..cf47ecba6e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/SlotTable.c @@ -0,0 +1,171 @@ +/** @file + Slot Table Update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include +#include + +#define PCI_DEVICE_ON_BOARD_TRUE 0 +#define PCI_DEVICE_ON_BOARD_FALSE 1 + +typedef enum { + Iio_Socket0 =3D 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 =3D0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Iou4, + Iio_IouMax +} IIO_IOUS; + +typedef enum { + Bw5_Addr_0 =3D 0, + Bw5_Addr_1, + Bw5_Addr_2, + Bw5_Addr_3, + Bw5_Addr_Max +} BW5_ADDRESS; + +static UINT8 TypeBoardPortTemplatePchPciSlotImpementedTableData[] =3D { + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4 + PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17 + PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18 + PCI_DEVICE_ON_BOARD_FALSE // Root Port 19 +}; + +UINT8 +GetTypeBoardPortTemplateIOU0Setting ( + UINT8 IOU0Data +) +{ + // + // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled. + // + IOU0Data =3D IIO_BIFURCATE_xxx8xxx8; + return IOU0Data; +} + +UINT8 +GetTypeBoardPortTemplateIOU2Setting ( + UINT8 SkuPersonalityType, + UINT8 IOU2Data +) +{ + return IOU2Data; +} + +static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeBoardPortTemplateBroadway= Table[] =3D { + {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 }, + {Iio_Socket1, Iio_Iou1, Bw5_Addr_2}, + {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 }, +}; + + +PLATFORM_SLOT_UPDATE_TABLE TypeBoardPortTemplateSlotTable =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeBoardPortTemplateBroadwayTable, + GetTypeBoardPortTemplateIOU0Setting, + 0 +}; + +PLATFORM_SLOT_UPDATE_TABLE2 TypeBoardPortTemplateSlotTable2 =3D +{ + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + SlotTypeBoardPortTemplateBroadwayTable, + GetTypeBoardPortTemplateIOU0Setting, + 0, + GetTypeBoardPortTemplateIOU2Setting +}; + +PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeBoardPortTemplatePchPci= SlotImplementedTable =3D { + PLATFORM_SLOT_UPDATE_SIGNATURE, + PLATFORM_SLOT_UPDATE_VERSION, + + TypeBoardPortTemplatePchPciSlotImpementedTableData +}; + +/** + Entry point function for the PEIM + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @return EFI_SUCCESS If we installed our PPI + +**/ +EFI_STATUS +TypeBoardPortTemplateInstallSlotTableData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid, + &TypeBoardPortTemplateSlotTable, + sizeof(TypeBoardPortTemplateSlotTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformSlotDataGuid2, + &TypeBoardPortTemplateSlotTable2, + sizeof(TypeBoardPortTemplateSlotTable2) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPciSlotImplementedGuid, + &TypeBoardPortTemplatePchPciSlotImplement= edTable, + sizeof(TypeBoardPortTemplatePchPciSlotImp= lementedTable) + ); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/= BoardPortTemplate/Uba/TypeBoardPortTemplate/Pei/SoftStrapFixup.c new file mode 100644 index 0000000000..08ddd80a12 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/SoftStrapFixup.c @@ -0,0 +1,119 @@ +/** @file + Soft Strap update. + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" +#include + +PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeBoardPortTemplateSoftStrapTable[] = =3D +{ +// SoftStrapNumber, LowBit, BitLength, Value + {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary M= ux Select + {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control + {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2) + {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3) + {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select b= etween sSATA Port 2 and PCIe Port 8) + {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_G= P2) + {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_G= P3) + {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled + {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2 + {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3 + {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0 + {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1 + {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2 + {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3 + {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4 + {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2 + {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5 + {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6 + {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7 + {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act a= s Downlink or Uplink(PCIEUDS) + {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address + {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address + {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable + {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect + {88, 8, 2, 0x3 }, // Root Port Configuration 0 + {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between S= ATA Port 0 and PCIe Port 12 + {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between S= ATA Port 1 and PCIe Port 13 + {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between S= ATA Port 2 and PCIe Port 14 + {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between S= ATA Port 3 and PCIe Port 15 + {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between S= ATA Port 4 and PCIe Port 16 + {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between S= ATA Port 5 and PCIe Port 17 + {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between S= ATA Port 6 and PCIe Port 18 + {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between S= ATA Port 7 and PCIe Port 19 + {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0= and PCIe Port 12 + {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1= and PCIe Port 13 + {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2= and PCIe Port 14 + {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3= and PCIe Port 15 + {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4= and PCIe Port 16 + {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5= and PCIe Port 17 + {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6= and PCIe Port 18 + {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7= and PCIe Port 19 + {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection + {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled + {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled +// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled +// {133, 2, 1, 0x1 }, // Quad Output Read Enabled +// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled +// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode +// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable +// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency +// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode + +// +// END OF LIST +// + {0, 0, 0, 0} +}; + +UINT32 +TypeBoardPortTemplateSystemBoardRevIdValue (VOID) +{ + EFI_HOB_GUID_TYPE *GuidHob; + EFI_PLATFORM_INFO *PlatformInfo; + + GuidHob =3D GetFirstGuidHob (&gEfiPlatformInfoGuid); + ASSERT(GuidHob !=3D NULL); + if (GuidHob =3D=3D NULL) { + return 0xFF; + } + PlatformInfo =3D GET_GUID_HOB_DATA(GuidHob); + return PlatformInfo->TypeRevisionId; +} + +VOID +TypeBoardPortTemplatePlatformSpecificUpdate ( + IN OUT UINT8 *FlashDescriptorCopy + ) +{ +} + +PLATFORM_PCH_SOFTSTRAP_UPDATE TypeBoardPortTemplateSoftStrapUpdate =3D +{ + PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE, + PLATFORM_SOFT_STRAP_UPDATE_VERSION, + TypeBoardPortTemplateSoftStrapTable, + TypeBoardPortTemplatePlatformSpecificUpdate +}; + +EFI_STATUS +TypeBoardPortTemplateInstallSoftStrapData ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi + ) +{ + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPlatformPchSoftStrapConfigDataGuid, + &TypeBoardPortTemplateSoftStrapUpdate, + sizeof(TypeBoardPortTemplateSoftStrapUpda= te) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeB= oardPortTemplate/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/BoardPort= Template/Uba/TypeBoardPortTemplate/Pei/UsbOC.c new file mode 100644 index 0000000000..1a0d1c8426 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/Uba/TypeBoardPor= tTemplate/Pei/UsbOC.c @@ -0,0 +1,124 @@ +/** @file + + @copyright + Copyright 2018 - 2021 Intel Corporation.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include "PeiBoardInit.h" + + +#include +#include +#include +#include +#include + +USB_OVERCURRENT_PIN TypeBoardPortTemplateUsb20OverCurrentMappings[PCH_MAX_= USB2_PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPin7, + UsbOverCurrentPin7, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin6, + UsbOverCurrentPin4, + UsbOverCurrentPin5, + UsbOverCurrentPin4, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB_OVERCURRENT_PIN TypeBoardPortTemplateUsb30OverCurrentMappings[PCH_MAX_= USB3_PORTS] =3D { + UsbOverCurrentPin0, + UsbOverCurrentPin1, + UsbOverCurrentPin1, + UsbOverCurrentPin2, + UsbOverCurrentPin3, + UsbOverCurrentPin3, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip, + UsbOverCurrentPinSkip + }; + +USB2_PHY_PARAMETERS TypeBoardPortTemplateUsb20AfeParams[PCH_H_XHCI= _MAX_USB2_PHYSICAL_PORTS] =3D { + {3, 0, 3, 1}, // PP0 + {5, 0, 3, 1}, // PP1 + {3, 0, 3, 1}, // PP2 + {0, 5, 1, 1}, // PP3 + {3, 0, 3, 1}, // PP4 + {3, 0, 3, 1}, // PP5 + {3, 0, 3, 1}, // PP6 + {3, 0, 3, 1}, // PP7 + {2, 2, 1, 0}, // PP8 + {6, 0, 2, 1}, // PP9 + {2, 2, 1, 0}, // PP10 + {6, 0, 2, 1}, // PP11 + {0, 5, 1, 1}, // PP12 + {7, 0, 2, 1}, // PP13 + }; + +EFI_STATUS +TypeBoardPortTemplatePlatformUsbOcUpdateCallback ( + IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings, + IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings, + IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams +) +{ + *Usb20OverCurrentMappings =3D &TypeBoardPortTemplateUsb20OverCurrentMa= ppings[0]; + *Usb30OverCurrentMappings =3D &TypeBoardPortTemplateUsb30OverCurrentMa= ppings[0]; + + *Usb20AfeParams =3D TypeBoardPortTemplateUsb20AfeParams; + return EFI_SUCCESS; +} + +PLATFORM_USBOC_UPDATE_TABLE TypeBoardPortTemplateUsbOcUpdate =3D +{ + PLATFORM_USBOC_UPDATE_SIGNATURE, + PLATFORM_USBOC_UPDATE_VERSION, + TypeBoardPortTemplatePlatformUsbOcUpdateCallback +}; + +EFI_STATUS +TypeBoardPortTemplatePlatformUpdateUsbOcMappings ( + IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi +) +{ + //# + //# USB, see PG 104 in GZP SCH + //# + +// USB2 USB3 Port OC +// +//Port00: PORT5 Back Panel ,OC0# +//Port01: PORT2 Back Panel ,OC0# +//Port02: PORT3 Back Panel ,OC1# +//Port03: PORT0 NOT USED ,NA +//Port04: BMC1.0 ,NA +//Port05: INTERNAL_2X5_A ,OC2# +//Port06: INTERNAL_2X5_A ,OC2# +//Port07: NOT USED ,NA +//Port08: EUSB (AKA SSD) ,NA +//Port09: INTERNAL_TYPEA ,OC6# +//Port10: PORT1 Front Panel ,OC5# +//Port11: NOT USED ,NA +//Port12: BMC2.0 ,NA +//Port13: PORT4 Front Panel ,OC5# + + EFI_STATUS Status; + + Status =3D UbaConfigPpi->AddData ( + UbaConfigPpi, + &gPeiPlatformUbaOcConfigDataGuid, + &TypeBoardPortTemplateUsbOcUpdate, + sizeof(TypeBoardPortTemplateUsbOcUpdate) + ); + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_boa= rd.py b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_board.py new file mode 100644 index 0000000000..cd2842ffdd --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_board.py @@ -0,0 +1,125 @@ +# @ build_board.py +# Extensions for building SuperMicro using build_bios.py +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + +""" +This module serves as a sample implementation of the build extension +scripts +""" + +import os +import sys + +def pre_build_ex(config, functions): + """Additional Pre BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: nothing + """ + print("pre_build_ex") + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], + 'Build', + config["PLATFORM_BOARD_PACKAGE= "], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + # set BUILD_DIR path + config["BUILD_DIR"] =3D os.path.join('Build', + config["PLATFORM_BOARD_PACKAGE"], + "{}_{}".format( + config["TARGET"], + config["TOOL_CHAIN_TAG"])) + config["BUILD_X64"] =3D os.path.join(config["BUILD_DIR_PATH"], 'X64') + config["BUILD_IA32"] =3D os.path.join(config["BUILD_DIR_PATH"], 'IA32') + + if not os.path.isdir(config["BUILD_DIR_PATH"]): + try: + os.makedirs(config["BUILD_DIR_PATH"]) + except OSError: + print("Error while creating Build folder") + sys.exit(1) + + #@todo: Replace this with PcdFspModeSelection + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D0" + else: + config["EXT_BUILD_FLAGS"] +=3D " -D FSP_MODE=3D1" + + if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": + raise ValueError("FSP API Mode is currently unsupported on Ice Lak= e Xeon Scalable") + return None + +def _merge_files(files, ofile): + with open(ofile, 'wb') as of: + for x in files: + if not os.path.exists(x): + return + + with open(x, 'rb') as f: + of.write(f.read()) + +def build_ex(config, functions): + """Additional BIOS build function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + binary_fd =3D os.path.join(fv_path, "BINARY.fd") + main_fd =3D os.path.join(fv_path, "MAIN.fd") + secpei_fd =3D os.path.join(fv_path, "SECPEI.fd") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + _merge_files((binary_fd, main_fd, secpei_fd), final_fd) + return None + + +def post_build_ex(config, functions): + """Additional Post BIOS build function + + :param config: The environment variables to be used in the post + build process + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("post_build_ex") + fv_path =3D os.path.join(config["BUILD_DIR_PATH"], "FV") + board_fd =3D config["BOARD"].upper() + final_fd =3D os.path.join(fv_path, "{}.fd".format(board_fd)) + final_ifwi =3D os.path.join(fv_path, "{}.bin".format(board_fd)) + + ifwi_ingredients_path =3D os.path.join(config["WORKSPACE_PLATFORM_BIN"= ], "Ifwi", config["BOARD"]) + flash_descriptor =3D os.path.join(ifwi_ingredients_path, "FlashDescrip= tor.bin") + intel_me =3D os.path.join(ifwi_ingredients_path, "Me.bin") + _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi) + if os.path.isfile(final_fd): + print("IFWI image can be found at {}".format(final_ifwi)) + return None + + +def clean_ex(config, functions): + """Additional clean function + + :param config: The environment variables to be used in the build proce= ss + :type config: Dictionary + :param functions: A dictionary of function pointers + :type functions: Dictionary + :returns: config dictionary + :rtype: Dictionary + """ + print("clean_ex") + return None diff --git a/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_con= fig.cfg b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_config= .cfg new file mode 100644 index 0000000000..a5fee40938 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/BoardPortTemplate/build_config.cfg @@ -0,0 +1,36 @@ +# @ build_config.cfg +# This is the WilsonCityRvp board specific build settings +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# + + +[CONFIG] +WORKSPACE_PLATFORM_BIN =3D edk2-non-osi/Platform/Intel/WhitleyOpenBoardBin= Pkg +EDK_SETUP_OPTION =3D +openssl_path =3D +PLATFORM_BOARD_PACKAGE =3D WhitleyOpenBoardPkg +PROJECT =3D WhitleyOpenBoardPkg/BoardPortTemplate +BOARD =3D BoardPortTemplate +FLASH_MAP_FDF =3D WhitleyOpenBoardPkg/FspFlashOffsets.fdf +PROJECT_DSC =3D WhitleyOpenBoardPkg/BoardPortTemplate/PlatformPkg.dsc +BOARD_PKG_PCD_DSC =3D WhitleyOpenBoardPkg/PlatformPkgConfig.dsc +ADDITIONAL_SCRIPTS =3D WhitleyOpenBoardPkg/BoardPortTemplate/build_board.py +PrepRELEASE =3D DEBUG +SILENT_MODE =3D FALSE +EXT_CONFIG_CLEAR =3D +CapsuleBuild =3D FALSE +EXT_BUILD_FLAGS =3D -D CPUTARGET=3DICX -D RP_PKG=3DWhitleyOpenBoardPkg -D = SILICON_PKG=3DWhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=3D6= 4 -D MAX_THREAD=3D2 -D PLATFORM_PKG=3DMinPlatformPkg +MAX_SOCKET =3D 4 +CAPSULE_BUILD =3D 0 +TARGET =3D DEBUG +TARGET_SHORT =3D D +PERFORMANCE_BUILD =3D FALSE +FSP_WRAPPER_BUILD =3D TRUE +FSP_BIN_PKG =3D WhitleyFspBinPkg +FSP_PKG_NAME =3D WhitleyFspPkg +FSP_BINARY_BUILD =3D FALSE +FSP_TEST_RELEASE =3D FALSE +SECURE_BOOT_ENABLE =3D FALSE +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85936): https://edk2.groups.io/g/devel/message/85936 Mute This Topic: https://groups.io/mt/88598012/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 07:06:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85935+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85935+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642814541; cv=none; d=zohomail.com; s=zohoarc; b=FKE+8Y1cDo3wevReKkkYsR87AmotbOpyu8iIc2LxUJQtMHuvH2RhI7rHalC9MSRarbAtj2xCQCAlijboBlcGlEZFxhOct+Y4LXyYprbRWERS8v/O+fuK2LNB6KfAylax1to52zO8KyUbGW/uW+f6L9KXBml0V1aGDdoK48/yorM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642814541; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=/PJXvZG4HMefxWEpo5z7vkqPs2Lr6WWhUwLXHVGUeEQ=; b=NDle7WCoUDZIJKB6+3JNxcFA1IginRBcEL9XjTrWsh08p8IfRM/XBYb/fcKVVESJs0WQsShqZjLiULZaXFg6Vdkl+tLXYuQ3GprcZ4/Jsk1w6DOePumDYCzpne1AvkovR5RSKAjJFE5g0+WMDAnQ+rClzBpl2yL1Ag7be+BBd0M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85935+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642814541682681.8043566303803; Fri, 21 Jan 2022 17:22:21 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zT4iYY1788612xFJofpARoX2; Fri, 21 Jan 2022 17:22:21 -0800 X-Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web11.3200.1642814540558632484 for ; Fri, 21 Jan 2022 17:22:20 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10234"; a="226452252" X-IronPort-AV: E=Sophos;i="5.88,307,1635231600"; d="scan'208";a="226452252" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2022 17:22:19 -0800 X-IronPort-AV: E=Sophos;i="5.88,307,1635231600"; d="scan'208";a="533498550" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jan 2022 17:22:19 -0800 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg/PlatformInfo: Add board ID vendor range Date: Fri, 21 Jan 2022 17:22:07 -0800 Message-Id: <5de1209eb6bac59291b886fb99871c516ebdb62a.1642813621.git.isaac.w.oram@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: KHkkoYmboS5zdVzwBKKSr5HNx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642814541; bh=DJi8H692FmPXx+qPyM1Ozccs+pr/xg2sisCfcvz2g5o=; h=Cc:Date:From:Reply-To:Subject:To; b=ivI28iC933vTewc2qnsMEfVk2DoOGAyRSVUtOMkOeWVKAQ9voJ3Yne2t6ouXgWA72vT qssasVJh3r9Ttyf+LpTzZPtTEScGSQ32t4+NZQXkZ/pG0MXAJJoJPAX+dNVeWH32nlOjL cBWvUBk4M8XxoWYbyQ+4Xg5QU6oPxWI/kMI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642814542870100004 Content-Type: text/plain; charset="utf-8" Add a vendor reserved range to avoid collisions with Intel reference board ID future use, if any. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.= c | 3 +- Platform/Intel/WhitleyOpenBoardPkg/Readme.md = | 118 ++++++++++++++++++++ Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h = | 8 +- 3 files changed, 127 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInf= o/PlatformInfo.c index 87b4e57803..0065819d83 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c @@ -413,7 +413,8 @@ PdrGetPlatformInfo ( return Status; } =20 - if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax)) { + if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax) || + (PlatformInfoHob->BoardId >=3D TypePlatformVendorMin) && (PlatformIn= foHob->BoardId <=3D TypePlatformVendorMax)) { // // Valid Platform Identified // diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Readme.md b/Platform/Intel/= WhitleyOpenBoardPkg/Readme.md new file mode 100644 index 0000000000..cc9f9a208f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Readme.md @@ -0,0 +1,118 @@ +# **Board Porting for Intel® Whitley Platform** + +## Overview +There are currently three board ports: +* WilsonCityRvp +* CooperCityRvp +* JunctionCity + +There are corresponding binaries in edk2-non-osi/WhitleyOpenBoardBinPkg. + +And there is a template for board porting, BoardPortWhitley. See below fo= r detailed instructions on creating a new board port. + +## BoardPortTemplate +This template profides basic instructions for how to customize the Whitley= OpenBoardPkg for a new system board. + +## Board Naming Convention +The current board directories are named arbitrarily and do not conform to = code. +Within code, the key is "TypeBoardName" which shows up in code in key ways: +* EFI_PLATFORM_TYPE enum, e.g. TypeJunctionCity +* UBA Protocol, e.g. gEfiPlatformTypeJunctionCityProtocolGuid +To facilitate future convention, "BoardPortTemplate" is used to increase c= onsistency. + +## Board Porting Steps +It is desirable to pick a fairly unique name as WhitleyOpenBoardPkg UBA fe= ature is designed to make it easy to support many boards in a single binary. +For the purposes of this example, "MyBoard" is the board name in code and = filesystem. + +1. Copy WhitleyOpenBoardPkg/BoardPortTemplate to WhitleyOpenBoardPkg/MyBoa= rd +2. Rename WhitleyOpenBoardPkg/MyBoard/Uba/TypeBoardPortTemplate to Whitley= OpenBoardPkg/MyBoard/Uba/TypeMyBoard +5. Search and replace BoardPortTemplate with MyBoard in WhitleyOpenBoardPk= g/MyBoard. Do not search and replace at a higher scope as you will break t= he template examples. +6. Add a new EFI_PLATFORM_TYPE enum in edk2-platforms\Silicon\Intel\Whitle= ySiliconPkg\Include\PlatformInfoTypes.h, e.g. +``` +TypeMyBoard, // 0x80 +``` +Please update the comment for TypeBoardPortTemplate to match the new maxim= um used, e.g. +``` +TypeBoardPortTemplate // 0x81 +``` +7. Update the PcdBoardId for your board in the WhitleyOpenBoardPkg/MyBoard= /PlatformPkg.dsc, e.g. +``` +gPlatformTokenSpaceGuid.PcdBoardId|0x80 # TypeMyBoard +``` +8. Update each INF in WhitleyOpenBoardPkg/MyBoard/Uba with new GUID filena= me +9. Add a DXE UBA protocol GUID to WhitleyOpenBoardPkg/PlatformPkg.dec, *wi= th a new GUID* +``` +gEfiPlatformTypeMyBoardProtocolGuid =3D { 0xa68228c5, 0xc00f, 0x4d9a= , { 0x8d, 0xed, 0xb9, 0x6b, 0x9e, 0xef, 0xab, 0xca } } +``` +10. Add your board to the switch statement in BoardInitDxeDriverEntry (); = in WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c +``` + case TypeMyBoard: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeMyBoardProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; +``` +11. Add the gEfiPlatformTypeMyBoardProtocolGuid to the WhitleyOpenBoardPkg= /Uba/BoardInit/Dxe/BoardInitDxe.inf +12. Add a build option to edk2-platforms/Platform/Intel/build.cfg. e.g. +``` +MyBoard =3D WhitleyOpenBoardPkg/MyBoard/build_config.cfg +``` +13. At this point, you can build from edk2-platforms/Platform/Intel, e.g. +``` +build_bios.py -p MyBoard -t VS2015x86 -d +``` +14. At this point, customization is not scripted. The following are commo= n customization areas: +MyBoard/Uba/TypeBoardPortTemplate/Pei +* GPIO +* VR, IMON +* SKU info +* Board layout, sockets, memory +* Soft straps, PCH, config, USB OC +* PCI, KTI, IO port bifurcation +MyBoard/Uba/TypeBoardPortTemplate/Dxe +* IIO config update +* Slot config update +* USB overcurrent update + +## Board Builds + +**Building with the python script** + +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce or ~/Edk2Workspace in the case of a linux OS +2. If using a linux OS + * Type "cd edk2" + * Type "source edksetup.sh" + * Type "cd ../" to go back to the workspace directory +3. Type "cd edk2-platforms/Platform/Intel +4. Type "python build_bios.py -p TARGET_BOARD" + +* build_bios.py arguments: + + | Argument | Function | + | ----------------------|-------------------------------------| + | -h, --help | show this help message and exit | + | --platform, -p | the platform to build | + | --toolchain, -t | tool Chain to use in build process | + | --DEBUG, -d | debug flag | + | --RELEASE, -r | release flag | + | --TEST_RELEASE, -tr | test Release flag | + | --RELEASE_PDB, -rp | release flag | + | --list, -l | lists available platforms | + | --cleanall | cleans all | + | --clean | cleans specified platform | + | --capsule | capsule build enabled | + | --silent | silent build enabled | + | --performance | performance build enabled | + | --fsp | fsp wrapper build enabled | + | --fspapi | API mode fsp wrapper build enabled | + | --hash | Enable hash-based caching | + | --binary-destination | create cache in specified directory | + | --binary-source | Consume cache from directory | + | | + +* For more information on build options + * Type "python build_bios.py -h" diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index fae3101336..bfc6a49138 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -65,13 +65,19 @@ typedef enum { TypeBigPineKey, TypeExperWorkStationRP, TypeJunctionCity, - EndOfEfiPlatformTypeEnum + EndOfEfiPlatformTypeEnum, + // + // Vendor board range currently starts at 0x80 + // + TypeBoardPortTemplate // 0x80 } EFI_PLATFORM_TYPE; =20 #define TypePlatformUnknown 0xFF #define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 #define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 #define TypePlatformDefault TypeWilsonPointRP +#define TypePlatformVendorMin 0x80 +#define TypePlatformVendorMax TypeBoardPortTemplate - 1 =20 // // CPU type: Standard (no MCP), -F, etc --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85935): https://edk2.groups.io/g/devel/message/85935 Mute This Topic: https://groups.io/mt/88598011/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-