From nobody Tue May 7 23:23:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80735+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80735+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1631732692; cv=none; d=zohomail.com; s=zohoarc; b=hXtvna8EkUpsf+XMZ+FWeKNTWukp0corguwA9w+RVXwZlNLzaQYJatzxb2B3xEmIwQf6ebBS8DLSOR5yWPOUQFfld1mexhRHEleJvR6bsUcPR2pZvOb/lnZ2Pk0HHyHYb+9iZ0Um7h87/a9cHr+c9jshICTmOQIsB/GOc5R7AhQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631732692; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cD5gxAl1qTfqwdgwL25Adt0YjxyDL+qKh3EiZR3L2fk=; b=c+cedUMRubmLEK2cesUW4ZtxOWCFOm+d5bBhbRgFYx0Z3Dats2fD4sImmIN9xVk8B3cEWKArdX/HnJdTyNm/qjBPFmvyOcB7QfVDdCBR2F2Hn0L14tLwn0XI0JHlcq9R0eYorM4Fk4i9y8H9R4o7zIUHljpou7/6P37DWQEENNg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80735+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631732692492133.45484389892124; Wed, 15 Sep 2021 12:04:52 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 23yFYY1788612xRBaSP5KUGl; Wed, 15 Sep 2021 12:04:52 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.857.1631732689591917140 for ; Wed, 15 Sep 2021 12:04:51 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10108"; a="222068170" X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="222068170" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 12:04:51 -0700 X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="482456696" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 12:04:51 -0700 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg/FspWrapperPlatformLib: Update for large variables Date: Wed, 15 Sep 2021 12:04:40 -0700 Message-Id: <00401ec51bcef4ff40a74c1a1c623ccf808328a9.1631730773.git.isaac.w.oram@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: L3pLJ3kx45fSO3RbCFsg7bOMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631732692; bh=K0HMyWCr+nkN6z7HQ5fceEGxImIS3o/1h7Xaj+c7HrE=; h=Cc:Date:From:Reply-To:Subject:To; b=E/88RrkQVVybcgu7mRRepnr4ADP1OR8nB9wXRpsL12uBNBe3yAjiMZ9wiYDcNw2s5Cb Ark+SO8IM1tq97qJwel9pQVjHjostSFHhZKfae3/6I27j/FvZ3tRcoumc5FazMcsMi4e5 /t6yC3vnCIoBWGbyTJlL4ofRRU1tt7I1ZQk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631732694851100001 Content-Type: text/plain; charset="utf-8" Update to utilize the larger variables. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl= atformLib.c | 83 +++++++------------- Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPl= atformLib.inf | 12 +-- 2 files changed, 35 insertions(+), 60 deletions(-) diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/= FspWrapperPlatformLib.c b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrappe= rPlatformLib/FspWrapperPlatformLib.c index 453e409523..a6196a78b0 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.c +++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.c @@ -10,76 +10,52 @@ #include #include #include -#include -#include -#include #include -#include #include +#include + +#include +#include +#include =20 VOID * -GetPlatformNvs( +GetFspNvsBuffer ( + VOID ) { EFI_STATUS Status; - EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable; - VOID *DataBuffer; - UINT32 DataBufferSize; - UINTN VarAttrib; - CHAR16 EfiMemoryConfigVariable[] =3D L"MemoryConfig"; + UINTN FspNvsBufferSize; + VOID *FspNvsBufferPtr; =20 - DEBUG ((EFI_D_INFO, "Start PlatformGetNvs\n")); - - Status =3D PeiServicesLocatePpi ( - &gEfiPeiReadOnlyVariable2PpiGuid, - 0, - NULL, - (VOID **) &PeiVariable - ); - if (EFI_ERROR (Status)) { - DEBUG ((EFI_D_ERROR, "PlatformGetNvs: PeiServicesLocatePpi not found\n= ")); + FspNvsBufferPtr =3D NULL; + FspNvsBufferSize =3D 0; + Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageHob= Guid, &FspNvsBufferSize, NULL); + if (Status =3D=3D EFI_BUFFER_TOO_SMALL) { + DEBUG ((DEBUG_INFO, "FspNvsBuffer Size =3D %d\n", FspNvsBufferSize)); + FspNvsBufferPtr =3D AllocateZeroPool (FspNvsBufferSize); + if (FspNvsBufferPtr =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Error: Cannot create FspNvsBuffer, out of memo= ry!\n")); ASSERT (FALSE); return NULL; } - - VarAttrib =3D EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS; - DataBufferSize =3D 0; - DataBuffer =3D NULL; - - Status =3D PeiVariable->GetVariable ( - PeiVariable, - EfiMemoryConfigVariable, - &gFspNonVolatileStorageHobGuid, - (UINT32*)&VarAttrib, - &DataBufferSize, - NULL - ); - if (Status =3D=3D EFI_NOT_FOUND) { - DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variabl= e not found\n")); + Status =3D GetLargeVariable (L"FspNvsBuffer", &gFspNonVolatileStorageH= obGuid, &FspNvsBufferSize, FspNvsBufferPtr); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variab= le Status: %r\n", Status)); + ASSERT_EFI_ERROR (Status); return NULL; } =20 - if (Status !=3D EFI_BUFFER_TOO_SMALL) { - DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Get Err= or %r\n", Status)); - ASSERT (FALSE); + return FspNvsBufferPtr; + + } else if (Status =3D=3D EFI_NOT_FOUND) { + DEBUG ((DEBUG_INFO, "Cannot create FSP NVS Buffer, UEFI variable does = not exist (this is likely a first boot)\n")); + } else { + DEBUG ((DEBUG_ERROR, "Error: Unable to read FspNvsBuffer UEFI variable= Status: %r\n", Status)); + ASSERT_EFI_ERROR (Status); } =20 - DataBuffer =3D AllocateZeroPool(DataBufferSize); - Status =3D PeiVariable->GetVariable ( - PeiVariable, - EfiMemoryConfigVariable, - &gFspNonVolatileStorageHobGuid, - (UINT32*)&VarAttrib, - &DataBufferSize, - DataBuffer - ); - if (EFI_ERROR(Status)) { - DEBUG ((EFI_D_ERROR, "PlatformGetNvs: gEfiMemoryConfigDataGuid Variabl= e Error %r\n", Status)); return NULL; } - DEBUG ((EFI_D_INFO, "PlatformGetNvs: GetNVS %x %x\n", DataBuffer, DataBu= fferSize)); - return DataBuffer; -} =20 VOID EFIAPI @@ -164,11 +140,10 @@ UpdateFspmUpdData ( FspmUpd->FspmConfig.AllLanesSizeOfTable =3D Upi->AllLanesSizeOfTable; FspmUpd->FspmConfig.PerLaneSizeOfTable =3D Upi->PerLaneSizeOfTable; FspmUpd->FspmConfig.WaitTimeForPSBP =3D Upi->WaitTimeForPSBP; - FspmUpd->FspmConfig.IsKtiNvramDataReady =3D Upi->IsKtiNvramDataReady; FspmUpd->FspmConfig.WaSerializationEn =3D Upi->WaSerializationEn; FspmUpd->FspmConfig.KtiInEnableMktme =3D Upi->KtiInEnableMktme; FspmUpd->FspmConfig.BoardId =3D PlatformInfo->BoardId; - FspmUpd->FspmArchUpd.NvsBufferPtr =3D GetPlatformNvs(); + FspmUpd->FspmArchUpd.NvsBufferPtr =3D GetFspNvsBuffer (); } =20 /** diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/= FspWrapperPlatformLib.inf b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrap= perPlatformLib/FspWrapperPlatformLib.inf index 625337c453..3e80ea670c 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.inf +++ b/Silicon/Intel/WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrap= perPlatformLib.inf @@ -35,7 +35,6 @@ [Sources] FspWrapperPlatformLib.c =20 - ##########################################################################= ###### # # Package Dependency Section - list of Package files that are required for @@ -47,11 +46,11 @@ MdePkg/MdePkg.dec IntelFsp2Pkg/IntelFsp2Pkg.dec IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec - WhitleySiliconPkg/WhitleySiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec WhitleySiliconPkg/SiliconPkg.dec WhitleySiliconPkg/CpRcPkg.dec - WhitleyOpenBoardPkg/PlatformPkg.dec - CedarIslandFspBinPkg/CedarIslandFspBinPkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec # For LargeVariableReadLib + WhitleyFspBinPkg/WhitleyFspBinPkg.dec =20 [Ppis] gUpiSiPolicyPpiGuid @@ -63,9 +62,10 @@ =20 [LibraryClasses] PeiServicesLib + LargeVariableReadLib =20 [Pcd] gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES - gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize - gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSUMES --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80735): https://edk2.groups.io/g/devel/message/80735 Mute This Topic: https://groups.io/mt/85635751/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Tue May 7 23:23:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80736+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80736+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1631732695; cv=none; d=zohomail.com; s=zohoarc; b=CGGXhhvq7b2jXt9gX6fn9TwbifXFwb5gEEo3L443iOOng0Qio8GTy/ofhx8LXnbYrzSstTedUxlD7ikfZ4AJY63DhU0aFPE74CNHL65vjW5TleswHudUqVrg4Dp8OokzCULQlHhy0Kt1U5ghgkpNgT6OTq9U0I4nOWXxNDGMCzw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631732695; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ww4rvUEI1s/gnwh0yE2N/UTokl9wAHT3LF/iLu/0Xgw=; b=degrmly41jNBI5QItp7liU5LJ5TtrDaWKLI6BXSJwWquTD8tKIk7i3EgUjAaQhUWSltx+9VdvSKPgOhzYKLzmn6P11a32e65cDYMSuKkLxrmuFhHvgGCaIFfnRLMKBWNeeFc6Qc16S1QIziJKD3N4Fche4YdqlIAdzdNnzXZ2Hg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80736+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631732695065149.05177296244426; Wed, 15 Sep 2021 12:04:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id B1pnYY1788612xDWmE4Jx3Rd; Wed, 15 Sep 2021 12:04:54 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web12.857.1631732689591917140 for ; Wed, 15 Sep 2021 12:04:53 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10108"; a="222068185" X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="222068185" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 12:04:52 -0700 X-IronPort-AV: E=Sophos;i="5.85,296,1624345200"; d="scan'208";a="482456705" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Sep 2021 12:04:52 -0700 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 2/2] WhitleyOpenBoardPkg/SecCore: Add SecCore source code support Date: Wed, 15 Sep 2021 12:04:41 -0700 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: ASjAkj5tJQVTZEH65mPOtv5fx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631732694; bh=SydjEEjH2Ee1jIqJjpsJg78fVdYr/oVlNa1e79v9YVY=; h=Cc:Date:From:Reply-To:Subject:To; b=E9J1txhZtVWq3poWtws54oEX+3ffuncm0dj8S0ePNlBzpsB9yJTj0xnCfTKAyflX625 35SZdQkM94pS+hCS4/9dkpFdhmYJmUV70Pd24AzWScDqG15HUM84iam2/p7Bnh6Wqjo6P Do4U8glM5vjqm4XAFoC8RmQPDeIFa1MUMQw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631732696993100006 Content-Type: text/plain; charset="utf-8" Add PlatformSecLib so that we can build SecCore. This uses FSP TempRamInit API in dispatch mode, but directly tears down NEM as a workaround because the current FSP binaries do not properly produce the TEMP_RAM_EXIT_PPI. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Fsp= WrapperPlatformSecLib.c | 159 +++++++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia3= 2/Fsp.h | 43 +++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia3= 2/PeiCoreEntry.nasm | 124 +++++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia3= 2/SecEntry.nasm | 338 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Ia3= 2/Stack.nasm | 71 ++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Pla= tformInit.c | 48 +++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Sec= FspWrapperPlatformSecLib.inf | 103 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Sec= GetPerformance.c | 90 ++++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Sec= PlatformInformation.c | 79 +++++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Sec= RamInitData.c | 29 ++ Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLib/Sec= TempRamDone.c | 130 ++++++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc = | 30 +- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf = | 30 +- Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec = | 2 - 14 files changed, 1248 insertions(+), 28 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/FspWrapperPlatformSecLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Li= brary/SecFspWrapperPlatformSecLib/FspWrapperPlatformSecLib.c new file mode 100644 index 0000000000..5e0f2ff1ac --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/FspWrapperPlatformSecLib.c @@ -0,0 +1,159 @@ +/** @file + Sample to provide FSP wrapper platform sec related function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include +#include + +#include +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ); + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ); + +PEI_SEC_PERFORMANCE_PPI mSecPerformancePpi =3D { + SecGetPerformance +}; + +EFI_PEI_CORE_FV_LOCATION_PPI mPeiCoreFvLocationPpi =3D { + (VOID *) (UINTN) FixedPcdGet32 (PcdFlashFvPreMemoryBase) +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiCoreFvLocationPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gEfiPeiCoreFvLocationPpiGuid, + &mPeiCoreFvLocationPpi + } +}; + +EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformPpi[] =3D { + // + // This must be the first PPI in the list because it will be patched in = SecPlatformMain (); + // + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gTopOfTemporaryRamPpiGuid, + NULL + } +}; + +/** + A developer supplied function to perform platform specific operations. + + It's a developer supplied function to perform any operations appropriate= to a + given platform. It's invoked just before passing control to PEI core by = SEC + core. Platform developer may modify the SecCoreData passed to PEI Core. + It returns a platform specific PPI list that platform wishes to pass to = PEI core. + The Generic SEC core module will merge this list to join the final list = passed to + PEI core. + + @param[in,out] SecCoreData The same parameter as passing to PE= I core. It + could be overridden by this functio= n. + + @return The platform specific PPI list to be passed to PEI core or + NULL if there is no need of such platform specific PPI list. + +**/ +EFI_PEI_PPI_DESCRIPTOR * +EFIAPI +SecPlatformMain ( + IN OUT EFI_SEC_PEI_HAND_OFF *SecCoreData + ) +{ + EFI_PEI_PPI_DESCRIPTOR *PpiList; + UINT8 TopOfTemporaryRamPpiIndex; + UINT8 *CopyDestinationPointer; + UINTN ReservedSize; + + DEBUG((DEBUG_INFO, "SecPlatformMain\n")); + + ReservedSize =3D ALIGN_VALUE (PcdGet32 (PcdPeiTemporaryRamRcHeapSize), S= IZE_4KB); + ReservedSize +=3D ALIGN_VALUE (PcdGet32 (PcdFspTemporaryRamSize), SIZE_4= KB); + + SecCoreData->PeiTemporaryRamBase =3D (UINT8 *) SecCoreData->PeiTempora= ryRamBase + ReservedSize; + SecCoreData->PeiTemporaryRamSize -=3D ReservedSize; + + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeBase - 0x%x\n", SecCo= reData->BootFirmwareVolumeBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper BootFirmwareVolumeSize - 0x%x\n", SecCo= reData->BootFirmwareVolumeSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamBase - 0x%x\n", SecCo= reData->TemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper TemporaryRamSize - 0x%x\n", SecCo= reData->TemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamBase - 0x%x\n", SecCo= reData->PeiTemporaryRamBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper PeiTemporaryRamSize - 0x%x\n", SecCo= reData->PeiTemporaryRamSize)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackBase - 0x%x\n", SecCo= reData->StackBase)); + DEBUG ((DEBUG_INFO, "FSP Wrapper StackSize - 0x%x\n", SecCo= reData->StackSize)); + + InitializeApicTimer (0, (UINT32) -1, TRUE, 5); + + // + // Use middle of Heap as temp buffer, it will be copied by caller. + // Do not use Stack, because it will cause wrong calculation on stack by= PeiCore + // + PpiList =3D (VOID *)((UINTN) SecCoreData->PeiTemporaryRamBase + (UINTN) = SecCoreData->PeiTemporaryRamSize/2); + CopyDestinationPointer =3D (UINT8 *) PpiList; + TopOfTemporaryRamPpiIndex =3D 0; + if ((PcdGet8 (PcdFspModeSelection) =3D=3D 0) && PcdGetBool (PcdFspDispat= chModeUseFspPeiMain)) { + // + // In Dispatch mode, wrapper should provide PeiCoreFvLocationPpi. + // + CopyMem (CopyDestinationPointer, mPeiCoreFvLocationPpiList, sizeof (mP= eiCoreFvLocationPpiList)); + TopOfTemporaryRamPpiIndex =3D 1; + CopyDestinationPointer +=3D sizeof (mPeiCoreFvLocationPpiList); + } + CopyMem (CopyDestinationPointer, mPeiSecPlatformPpi, sizeof (mPeiSecPlat= formPpi)); + // + // Patch TopOfTemporaryRamPpi + // + PpiList[TopOfTemporaryRamPpiIndex].Ppi =3D (VOID *)((UINTN) SecCoreData-= >TemporaryRamBase + SecCoreData->TemporaryRamSize); + + return PpiList; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/Ia32/Fsp.h b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrap= perPlatformSecLib/Ia32/Fsp.h new file mode 100644 index 0000000000..0a8d9bf74a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/Ia32/Fsp.h @@ -0,0 +1,43 @@ +/** @file + Fsp related definitions + + @copyright + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __FSP_H__ +#define __FSP_H__ + +// +// Fv Header +// +#define FVH_SIGINATURE_OFFSET 0x28 +#define FVH_SIGINATURE_VALID_VALUE 0x4856465F // valid signature:_FVH +#define FVH_HEADER_LENGTH_OFFSET 0x30 +#define FVH_EXTHEADER_OFFSET_OFFSET 0x34 +#define FVH_EXTHEADER_SIZE_OFFSET 0x10 + +// +// Ffs Header +// +#define FSP_HEADER_GUID_DWORD1 0x912740BE +#define FSP_HEADER_GUID_DWORD2 0x47342284 +#define FSP_HEADER_GUID_DWORD3 0xB08471B9 +#define FSP_HEADER_GUID_DWORD4 0x0C3F3527 +#define FFS_HEADER_SIZE_VALUE 0x18 + +// +// Section Header +// +#define SECTION_HEADER_TYPE_OFFSET 0x03 +#define RAW_SECTION_HEADER_SIZE_VALUE 0x04 + +// +// Fsp Header +// +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/Ia32/PeiCoreEntry.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Librar= y/SecFspWrapperPlatformSecLib/Ia32/PeiCoreEntry.nasm new file mode 100644 index 0000000000..917411cac2 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/Ia32/PeiCoreEntry.nasm @@ -0,0 +1,124 @@ +;-------------------------------------------------------------------------= ----- +; @file PeiCoreEntry.nasm +; Find and call SecStartup +; +; @copyright +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+; +; SPDX-License-Identifier: BSD-2-Clause-Patent +;-------------------------------------------------------------------------= ----- + +SECTION .text + +extern ASM_PFX(SecStartup) +extern ASM_PFX(PlatformInit) + +global ASM_PFX(CallPeiCoreEntryPoint) +ASM_PFX(CallPeiCoreEntryPoint): + ; + ; Obtain the hob list pointer + ; + mov eax, [esp+4] + ; + ; Obtain the stack information + ; ECX: start of range + ; EDX: end of range + ; + mov ecx, [esp+8] + mov edx, [esp+0xC] + + ; + ; Platform init + ; + pushad + push edx + push ecx + push eax + call ASM_PFX(PlatformInit) + pop eax + pop eax + pop eax + popad + + ; + ; Set stack top pointer + ; + mov esp, edx + + ; + ; Push the hob list pointer + ; + push eax + + ; + ; Save the value + ; ECX: start of range + ; EDX: end of range + ; + mov ebp, esp + push ecx + push edx + + ; + ; Push processor count to stack first, then BIST status (AP then BSP) + ; + mov eax, 1 + cpuid + shr ebx, 16 + and ebx, 0xFF + cmp bl, 1 + jae PushProcessorCount + + ; + ; Some processors report 0 logical processors. Effectively 0 =3D 1. + ; So we fix up the processor count + ; + inc ebx + +PushProcessorCount: + push ebx + + ; + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST + ; for all processor threads + ; + xor ecx, ecx + mov cl, bl +PushBist: + movd eax, mm0 + push eax + loop PushBist + + ; Save Time-Stamp Counter + movd eax, mm5 + push eax + + movd eax, mm6 + push eax + + ; + ; Pass entry point of the PEI core + ; + mov edi, 0xFFFFFFE0 + push DWORD [edi] + + ; + ; Pass BFV into the PEI Core + ; + mov edi, 0xFFFFFFFC + push DWORD [edi] + + ; + ; Pass stack size into the PEI Core + ; + mov ecx, [ebp - 4] + mov edx, [ebp - 8] + push ecx ; RamBase + + sub edx, ecx + push edx ; RamSize + + ; + ; Pass Control into the PEI Core + ; + call ASM_PFX(SecStartup) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/Ia32/SecEntry.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Library/Se= cFspWrapperPlatformSecLib/Ia32/SecEntry.nasm new file mode 100644 index 0000000000..091990d627 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/Ia32/SecEntry.nasm @@ -0,0 +1,338 @@ +;-------------------------------------------------------------------------= ----- +; @file SecEntry.nasm +; This is the code that goes from real-mode to protected mode. +; It consumes the reset vector, calls TempRamInit API from FSP binary. +; +; @copyright +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+; +; SPDX-License-Identifier: BSD-2-Clause-Patent +;-------------------------------------------------------------------------= ----- + +#include "Fsp.h" + +SECTION .text + +extern ASM_PFX(CallPeiCoreEntryPoint) +extern ASM_PFX(FsptUpdDataPtr) +extern ASM_PFX(BoardBeforeTempRamInit) + +; Pcds +extern ASM_PFX(PcdGet32 (PcdFlashFvFspTBase)) + +;-------------------------------------------------------------------------= --- +; +; Procedure: _ModuleEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; Transition to non-paged flat-model protected mode from a +; hard-coded GDT that provides exactly two descriptors. +; This is a bare bones transition to protected mode only +; used for a while in PEI and possibly DXE. +; +; After enabling protected mode, a far jump is executed to +; transfer to PEI using the newly loaded GDT. +; +; Return: None +; +; MMX Usage: +; MM0 =3D BIST State +; MM5 =3D Save time-stamp counter value high32bit +; MM6 =3D Save time-stamp counter value low32bit. +; +;-------------------------------------------------------------------------= --- + +BITS 16 +align 4 +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + fninit ; clear any pending Floating point= exceptions + ; + ; Store the BIST value in mm0 + ; + movd mm0, eax + + ; + ; Save time-stamp counter value + ; rdtsc load 64bit time-stamp counter to EDX:EAX + ; + rdtsc + movd mm5, edx + movd mm6, eax + + ; + ; Load the GDT table in GdtDesc + ; + mov esi, GdtDesc + DB 66h + lgdt [cs:si] + + ; + ; Transition to 16 bit protected mode + ; + mov eax, cr0 ; Get control register 0 + or eax, 00000003h ; Set PE bit (bit #0) & MP bit (bit #= 1) + mov cr0, eax ; Activate protected mode + + mov eax, cr4 ; Get control register 4 + or eax, 00000600h ; Set OSFXSR bit (bit #9) & OSXMMEXCP= T bit (bit #10) + mov cr4, eax + + ; + ; Now we're in 16 bit protected mode + ; Set up the selectors for 32 bit protected mode entry + ; + mov ax, SYS_DATA_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + ; + ; Transition to Flat 32 bit protected mode + ; The jump to a far pointer causes the transition to 32 bit mode + ; + mov esi, ProtectedModeEntryLinearAddress + jmp dword far [cs:si] + +;-------------------------------------------------------------------------= --- +; +; Procedure: ProtectedModeEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; This function handles: +; Call two basic APIs from FSP binary +; Initializes stack with some early data (BIST, PEI entry, etc) +; +; Return: None +; +;-------------------------------------------------------------------------= --- + +BITS 32 +align 4 +ProtectedModeEntryPoint: + ; + ; Early board hooks + ; + mov esp, BoardBeforeTempRamInitRet + jmp ASM_PFX(BoardBeforeTempRamInit) + +BoardBeforeTempRamInitRet: + + ; Find the fsp info header + mov edi, [ASM_PFX(PcdGet32 (PcdFlashFvFspTBase))] + + mov eax, dword [edi + FVH_SIGINATURE_OFFSET] + cmp eax, FVH_SIGINATURE_VALID_VALUE + jnz FspHeaderNotFound + + xor eax, eax + mov ax, word [edi + FVH_EXTHEADER_OFFSET_OFFSET] + cmp ax, 0 + jnz FspFvExtHeaderExist + + xor eax, eax + mov ax, word [edi + FVH_HEADER_LENGTH_OFFSET] ; Bypass Fv Header + add edi, eax + jmp FspCheckFfsHeader + +FspFvExtHeaderExist: + add edi, eax + mov eax, dword [edi + FVH_EXTHEADER_SIZE_OFFSET] ; Bypass Ext Fv Header + add edi, eax + + ; Round up to 8 byte alignment + mov eax, edi + and al, 07h + jz FspCheckFfsHeader + + and edi, 0FFFFFFF8h + add edi, 08h + +FspCheckFfsHeader: + ; Check the ffs guid + mov eax, dword [edi] + cmp eax, FSP_HEADER_GUID_DWORD1 + jnz FspHeaderNotFound + + mov eax, dword [edi + 4] + cmp eax, FSP_HEADER_GUID_DWORD2 + jnz FspHeaderNotFound + + mov eax, dword [edi + 8] + cmp eax, FSP_HEADER_GUID_DWORD3 + jnz FspHeaderNotFound + + mov eax, dword [edi + 0Ch] + cmp eax, FSP_HEADER_GUID_DWORD4 + jnz FspHeaderNotFound + + add edi, FFS_HEADER_SIZE_VALUE ; Bypass the ffs header + + ; Check the section type as raw section + mov al, byte [edi + SECTION_HEADER_TYPE_OFFSET] + cmp al, 019h + jnz FspHeaderNotFound + + add edi, RAW_SECTION_HEADER_SIZE_VALUE ; Bypass the section header + jmp FspHeaderFound + +FspHeaderNotFound: + jmp $ + +FspHeaderFound: + ; Get the fsp TempRamInit Api address + mov eax, dword [edi + FSP_HEADER_IMAGEBASE_OFFSET] + add eax, dword [edi + FSP_HEADER_TEMPRAMINIT_OFFSET] + + ; Setup the hardcode stack + mov esp, TempRamInitStack + + ; Call the fsp TempRamInit Api + jmp eax + +TempRamInitDone: + cmp eax, 8000000Eh ;Check if EFI_NOT_FOUND returned. Error code for= Microcode Update not found. + je CallSecFspInit ;If microcode not found, don't hang, but continu= e. + + cmp eax, 0 ;Check if EFI_SUCCESS retuned. + jnz FspApiFailed + + ; ECX: start of range + ; EDX: end of range +CallSecFspInit: + xor eax, eax + mov esp, edx + + ; Align the stack at DWORD + add esp, 3 + and esp, 0FFFFFFFCh + + push edx + push ecx + push eax ; zero - no hob list yet + call ASM_PFX(CallPeiCoreEntryPoint) + +FspApiFailed: + jmp $ + +align 10h +TempRamInitStack: + DD TempRamInitDone + DD ASM_PFX(FsptUpdDataPtr); TempRamInitParams + +; +; ROM-based Global-Descriptor Table for the Tiano PEI Phase +; +align 16 +global ASM_PFX(BootGdtTable) + +; +; GDT[0]: 0x00: Null entry, never used. +; +NULL_SEL EQU $ - GDT_BASE ; Selector [0] +GDT_BASE: +ASM_PFX(BootGdtTable): + DD 0 + DD 0 +; +; Linear data segment descriptor +; +LINEAR_SEL EQU $ - GDT_BASE ; Selector [0x8] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 092h ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Linear code segment descriptor +; +LINEAR_CODE_SEL EQU $ - GDT_BASE ; Selector [0x10] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Bh ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; System data segment descriptor +; +SYS_DATA_SEL EQU $ - GDT_BASE ; Selector [0x18] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 0CFh ; page-granular, 32-bit + DB 0 + +; +; System code segment descriptor +; +SYS_CODE_SEL EQU $ - GDT_BASE ; Selector [0x20] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0 + DB 09Ah ; present, ring 0, data, expand-up= , writable + DB 0CFh ; page-granular, 32-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_CODE_SEL EQU $ - GDT_BASE ; Selector [0x28] + DW 0FFFFh ; limit 0xFFFFF + DW 0 ; base 0 + DB 0Eh ; Changed from F000 to E000. + DB 09Bh ; present, ring 0, code, expand-up= , writable + DB 00h ; byte-granular, 16-bit + DB 0 +; +; Spare segment descriptor +; +SYS16_DATA_SEL EQU $ - GDT_BASE ; Selector [0x30] + DW 0FFFFh ; limit 0xFFFF + DW 0 ; base 0 + DB 0 + DB 093h ; present, ring 0, data, expand-up= , not-writable + DB 00h ; byte-granular, 16-bit + DB 0 + +; +; Spare segment descriptor +; +SPARE5_SEL EQU $ - GDT_BASE ; Selector [0x38] + DW 0 ; limit 0 + DW 0 ; base 0 + DB 0 + DB 0 ; present, ring 0, data, expand-up= , writable + DB 0 ; page-granular, 32-bit + DB 0 +GDT_SIZE EQU $ - GDT_BASE ; Size, in bytes + +; +; GDT Descriptor +; +GdtDesc: ; GDT descriptor + DW GDT_SIZE - 1 ; GDT limit + DD GDT_BASE ; GDT base address + + +ProtectedModeEntryLinearAddress: +ProtectedModeEntryLinear: + DD ProtectedModeEntryPoint ; Offset of our 32 bit code + DW LINEAR_CODE_SEL diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/Ia32/Stack.nasm b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFs= pWrapperPlatformSecLib/Ia32/Stack.nasm new file mode 100644 index 0000000000..80a7a67ecf --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/Ia32/Stack.nasm @@ -0,0 +1,71 @@ +;-------------------------------------------------------------------------= ----- +; @file Stack.nasm +; Switch the stack from temporary memory to permenent memory. +; +; @copyright +; Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
+; +; SPDX-License-Identifier: BSD-2-Clause-Patent +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; SecSwitchStack ( +; UINT32 TemporaryMemoryBase, +; UINT32 PermanentMemoryBase +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(SecSwitchStack) +ASM_PFX(SecSwitchStack): + ; + ; Save three register: eax, ebx, ecx + ; + push eax + push ebx + push ecx + push edx + + ; + ; !!CAUTION!! this function address's is pushed into stack after + ; migration of whole temporary memory, so need save it to permanent + ; memory at first! + ; + + mov ebx, [esp + 20] ; Save the first parameter + mov ecx, [esp + 24] ; Save the second parameter + + ; + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory + ; + mov eax, esp + sub eax, ebx + add eax, ecx + mov edx, dword [esp] ; copy pushed register's value to perma= nent memory + mov dword [eax], edx + mov edx, dword [esp + 4] + mov dword [eax + 4], edx + mov edx, dword [esp + 8] + mov dword [eax + 8], edx + mov edx, dword [esp + 12] + mov dword [eax + 12], edx + mov edx, dword [esp + 16] ; Update this function's return address= into permanent memory + mov dword [eax + 16], edx + mov esp, eax ; From now, esp is pointed to perma= nent memory + + ; + ; Fixup the ebp point to permanent memory + ; + mov eax, ebp + sub eax, ebx + add eax, ecx + mov ebp, eax ; From now, ebp is pointed to permanent = memory + + pop edx + pop ecx + pop ebx + pop eax + ret diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/PlatformInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFsp= WrapperPlatformSecLib/PlatformInit.c new file mode 100644 index 0000000000..546b13f8a3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/PlatformInit.c @@ -0,0 +1,48 @@ +/** @file + Sample to provide platform init function. + + @copyright + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#include +#include +#include +#include +#include + +/** + Platform initialization. + + @param[in] FspHobList HobList produced by FSP. + @param[in] StartOfRange Start of temporary RAM. + @param[in] EndOfRange End of temporary RAM. +**/ +VOID +EFIAPI +PlatformInit ( + IN VOID *FspHobList, + IN VOID *StartOfRange, + IN VOID *EndOfRange + ) +{ + // + // Platform initialization + // Enable Serial port here + // + if (PcdGetBool(PcdSecSerialPortDebugEnable)) { + SerialPortInitialize (); + } + + DEBUG ((DEBUG_INFO, "PrintPeiCoreEntryPointParam in PlatformInit\n")); + DEBUG ((DEBUG_INFO, "FspHobList - 0x%x\n", FspHobList)); + DEBUG ((DEBUG_INFO, "StartOfRange - 0x%x\n", StartOfRange)); + DEBUG ((DEBUG_INFO, "EndOfRange - 0x%x\n", EndOfRange)); + + BoardAfterTempRamInit (); + + TestPointTempMemoryFunction (StartOfRange, EndOfRange); +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/WhitleyOpenBoardP= kg/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf new file mode 100644 index 0000000000..37e0a5cb63 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/SecFspWrapperPlatformSecLib.inf @@ -0,0 +1,103 @@ +## @file +# Provide FSP wrapper platform sec related function. +# +# @copyright +# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecFspWrapperPlatformSecLib + FILE_GUID =3D 8F1AC44A-CE7E-4E29-95BB-92E321BB1573 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecLib + + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperPlatformSecLib.c + SecRamInitData.c + SecPlatformInformation.c + SecGetPerformance.c + SecTempRamDone.c + PlatformInit.c + +[Sources.IA32] + Ia32/SecEntry.nasm + Ia32/PeiCoreEntry.nasm + Ia32/Stack.nasm + Ia32/Fsp.h + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + WhitleyFspBinPkg/WhitleyFspBinPkg.dec + +[LibraryClasses] + LocalApicLib + SerialPortLib + DebugLib + BaseMemoryLib + FspWrapperPlatformLib + FspWrapperApiLib + SecBoardInitLib + TestPointCheckLib + PeiServicesTablePointerLib + +[Ppis] + gEfiSecPlatformInformationPpiGuid ## CONSUMES + gPeiSecPerformancePpiGuid ## CONSUMES + gTopOfTemporaryRamPpiGuid ## PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES + gPlatformInitTempRamExitPpiGuid ## CONSUMES + +[Pcd] + gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize ## CONSU= MES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## CONSU= MES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## CONSU= MES + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase ## CONSU= MES + gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize ## CONSU= MES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase ## CONSU= MES + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## CONSU= MES diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/SecGetPerformance.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/S= ecFspWrapperPlatformSecLib/SecGetPerformance.c new file mode 100644 index 0000000000..977212737e --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/SecGetPerformance.c @@ -0,0 +1,90 @@ +/** @file + Sample to provide SecGetPerformance function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include + +/** + This interface conveys performance information out of the Security (SEC)= phase into PEI. + + This service is published by the SEC phase. The SEC phase handoff has an= optional + EFI_PEI_PPI_DESCRIPTOR list as its final argument when control is passed= from SEC into the + PEI Foundation. As such, if the platform supports collecting performance= data in SEC, + this information is encapsulated into the data structure abstracted by t= his service. + This information is collected for the boot-strap processor (BSP) on IA-3= 2. + + @param[in] PeiServices The pointer to the PEI Services Table. + @param[in] This The pointer to this instance of the PEI_SEC_PER= FORMANCE_PPI. + @param[out] Performance The pointer to performance data collected in SE= C phase. + + @retval EFI_SUCCESS The data was successfully returned. + +**/ +EFI_STATUS +EFIAPI +SecGetPerformance ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN PEI_SEC_PERFORMANCE_PPI *This, + OUT FIRMWARE_SEC_PERFORMANCE *Performance + ) +{ + UINT32 Size; + UINT32 Count; + UINTN TopOfTemporaryRam; + UINT64 Ticker; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecGetPerformance\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + // + // |--------------| <- TopOfTemporaryRam - BL + // | List Ptr | + // |--------------| + // | BL RAM Start | + // |--------------| + // | BL RAM End | + // |--------------| + // |Number of BSPs| + // |--------------| + // | BIST | + // |--------------| + // | .... | + // |--------------| + // | TSC[63:32] | + // |--------------| + // | TSC[31:00] | + // |--------------| + // + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); + TopOfTemporaryRam -=3D sizeof (UINT32) * 2; + Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)); + Size =3D Count * sizeof (UINT32); + + Ticker =3D *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - siz= eof (UINT32) * 2); + Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/SecPlatformInformation.c b/Platform/Intel/WhitleyOpenBoardPkg/Libr= ary/SecFspWrapperPlatformSecLib/SecPlatformInformation.c new file mode 100644 index 0000000000..3d1b9be21c --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/SecPlatformInformation.c @@ -0,0 +1,79 @@ +/** @file + Sample to provide SecPlatformInformation function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include + +/** + This interface conveys state information out of the Security (SEC) phase= into PEI. + + @param[in] PeiServices Pointer to the PEI Services Tab= le. + @param[in,out] StructureSize Pointer to the variable describ= ing size of the input buffer. + @param[out] PlatformInformationRecord Pointer to the EFI_SEC_PLATFORM= _INFORMATION_RECORD. + + @retval EFI_SUCCESS The data was successfully returned. + @retval EFI_BUFFER_TOO_SMALL The buffer was too small. + +**/ +EFI_STATUS +EFIAPI +SecPlatformInformation ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN OUT UINT64 *StructureSize, + OUT EFI_SEC_PLATFORM_INFORMATION_RECORD *PlatformInformationRecord + ) +{ + UINT32 *Bist; + UINT32 Size; + UINT32 Count; + UINTN TopOfTemporaryRam; + VOID *TopOfTemporaryRamPpi; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "SecPlatformInformation\n")); + + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gTopOfTemporaryRamPpiGuid, + 0, + NULL, + (VOID **) &TopOfTemporaryRamPpi + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + // + // The entries of BIST information, together with the number of them, + // reside in the bottom of stack, left untouched by normal stack operati= on. + // This routine copies the BIST information to the buffer pointed by + // PlatformInformationRecord for output. + // + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); + TopOfTemporaryRam -=3D sizeof (UINT32) * 2; + Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32))); + Size =3D Count * sizeof (IA32_HANDOFF_STATUS); + + if ((*StructureSize) < (UINT64) Size) { + *StructureSize =3D Size; + return EFI_BUFFER_TOO_SMALL; + } + + *StructureSize =3D Size; + Bist =3D (UINT32 *) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze); + + CopyMem (PlatformInformationRecord, Bist, Size); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/SecRamInitData.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecF= spWrapperPlatformSecLib/SecRamInitData.c new file mode 100644 index 0000000000..a6c7a53d33 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/SecRamInitData.c @@ -0,0 +1,29 @@ +/** @file + Sample to provide TempRamInitParams data. + + @copyright + Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include +#include +#include + +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD FsptUpdDataPtr =3D { + { + FSPT_UPD_SIGNATURE, + 0x00, + { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, + { + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), + FixedPcdGet32 (PcdFlashSecCacheRegionBase), + FixedPcdGet32 (PcdFlashSecCacheRegionSize), + } +}; + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatfo= rmSecLib/SecTempRamDone.c b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecF= spWrapperPlatformSecLib/SecTempRamDone.c new file mode 100644 index 0000000000..e6f2c1c4d6 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Library/SecFspWrapperPlatformSecLi= b/SecTempRamDone.c @@ -0,0 +1,130 @@ +/** @file + Sample to provide SecTemporaryRamDone function. + + @copyright + Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include + +#define MSR_NEM 0x000002E0 + +/** +This interface disables temporary memory in SEC Phase. +This is for dispatch mode use. We should properly produce the FSP_TEMP_RA= M_EXIT_PPI and then call +that instead, but the FSP does not produce that PPI +**/ +VOID +EFIAPI +SecPlatformDisableTemporaryMemoryDispatchHack ( + VOID + ) +{ + UINT64 MsrValue; + UINT64 MtrrDefaultType; + MSR_IA32_MTRR_DEF_TYPE_REGISTER DefType; + + // + // Force and INVD. + // + AsmInvd (); + + // + // Disable MTRRs. + // + DefType.Uint64 =3D AsmReadMsr64 (MSR_IA32_MTRR_DEF_TYPE); + MtrrDefaultType =3D DefType.Uint64; + DefType.Bits.E =3D 0; + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, DefType.Uint64); + + // + // Force and INVD to prevent MCA error. + // + AsmInvd (); + + // + // Clear NEM Run and NEM Setup bits individually. + // + MsrValue =3D AsmReadMsr64 (MSR_NEM); + MsrValue &=3D ~((UINT64) BIT1); + AsmWriteMsr64 (MSR_NEM, MsrValue); + MsrValue &=3D ~((UINT64) BIT0); + AsmWriteMsr64 (MSR_NEM, MsrValue); + + // + // Restore MTRR default setting + // + AsmWriteMsr64 (MSR_IA32_MTRR_DEF_TYPE, MtrrDefaultType); +} + +/** +This interface disables temporary memory in SEC Phase. +**/ +VOID +EFIAPI +SecPlatformDisableTemporaryMemory ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TempRamExitParam; + CONST EFI_PEI_SERVICES **PeiServices; + PLATFORM_INIT_TEMP_RAM_EXIT_PPI *PlatformInitTempRamExitPpi; + + DEBUG ((DEBUG_INFO, "SecPlatformDisableTemporaryMemory enter\n")); + PeiServices =3D GetPeiServicesTablePointer (); + ASSERT (PeiServices !=3D NULL); + if (PeiServices =3D=3D NULL) { + return ; + } + ASSERT ((*PeiServices) !=3D NULL); + if ((*PeiServices) =3D=3D NULL) { + return; + } + Status =3D (*PeiServices)->LocatePpi ( + PeiServices, + &gPlatformInitTempRamExitPpiGuid, + 0, + NULL, + (VOID **) &PlatformInitTempRamExitPpi + ); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return; + } + + Status =3D PlatformInitTempRamExitPpi->PlatformInitBeforeTempRamExit (); + ASSERT_EFI_ERROR (Status); + + if (PcdGet8 (PcdFspModeSelection) =3D=3D 1) { + // + // FSP API mode + // + TempRamExitParam =3D UpdateTempRamExitParam (); + Status =3D CallTempRamExit (TempRamExitParam); + DEBUG ((DEBUG_INFO, "TempRamExit status: 0x%x\n", Status)); + ASSERT_EFI_ERROR (Status); + } else { + SecPlatformDisableTemporaryMemoryDispatchHack (); + } + + Status =3D PlatformInitTempRamExitPpi->PlatformInitAfterTempRamExit (); + ASSERT_EFI_ERROR(Status); + + return ; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc index fa41ae923d..dc3dd0e026 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -48,6 +48,9 @@ # !include $(SILICON_PKG)/MrcCommonConfig.dsc =20 +[Packages] + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + !include $(FSP_BIN_PKG)/DynamicExPcd.dsc !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc !include $(RP_PKG)/DynamicExPcd.dsc @@ -192,8 +195,17 @@ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000 =20 + # + # Mode | FSP_MODE | PcdFspModeSelection + # ------------------|----------|-------------------- + # FSP Dispatch Mode | 1 | 0 + # FSP API Mode | 0 | 1 + # !if ($(FSP_MODE) =3D=3D 0) + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1 gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000 +!else + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0 !endif gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000 =20 @@ -310,6 +322,12 @@ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc =20 [PcdsFixedAtBuild.IA32] + # + # FSP Base address PCD will be updated in FDF basing on flash map. + # + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0 + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0 + !if ($(FSP_MODE) =3D=3D 0) gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000 @@ -543,12 +561,11 @@ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses= .Common.PEIM] -!if ($(FSP_MODE) =3D=3D 0) FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/Fs= pWrapperPlatformLib.inf FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProc= essLib/PeiFspWrapperHobProcessLib.inf -!endif + FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLi= b.inf @@ -559,6 +576,11 @@ # TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf =20 + PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapp= erPlatformSecLib.inf + SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/= SecBoardInitLibNull.inf + TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestP= ointCheckLib.inf + VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVaria= bleReadLibNull.inf + [LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM] # # ToDo: Can we remove @@ -617,6 +639,8 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf =20 [Components.IA32] + UefiCpuPkg/SecCore/SecCore.inf + !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc =20 MdeModulePkg/Universal/PCD/Pei/Pcd.inf { @@ -653,8 +677,8 @@ BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf } =20 -!if ($(FSP_MODE) =3D=3D 0) IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf +!if ($(FSP_MODE) =3D=3D 0) IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf !endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/= Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf index 927db9e210..d128f61b9d 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf @@ -14,7 +14,7 @@ DEFINE PLATFORM_PKG =3D MinPlatformPkg # 0x00000060 =3D (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_F= FS_FILE_HEADER)) DEFINE FDF_FIRMWARE_HEADER_SIZE =3D 0x00000060 =20 -DEFINE MICROCODE_HEADER_SIZE =3D 0x00000090 +SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =3D = 0x90 # FV Header plus FFS header =20 DEFINE VPD_HEADER_SIZE =3D 0x00000090 =20 @@ -153,24 +153,12 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = =3D 0x01000000 SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemoryBase SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvPreMemorySize =20 - # - # For FSP Dispatch Mode, specify the FV containing the PEI core. - # - !if $(FSP_MODE) =3D=3D 1 - # - # Tell SEC to use PEI Core from outside FSP for additional debug messa= ge control. - # - SET gSiPkgTokenSpaceGuid.PcdPeiCoreFv =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase - !endif - # # For API mode, wrappers have some duplicate PCD as well # - !if $(FSP_MODE) =3D=3D 0 - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspMBase - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspTBase - SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatfor= mPkgTokenSpaceGuid.PcdFlashFvFspSBase - !endif + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspSBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspMBase + SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D gMinPlatformP= kgTokenSpaceGuid.PcdFlashFvFspTBase =20 ##########################################################################= ###### # @@ -311,7 +299,8 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = =3D 0x01000000 # # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically # - SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + $(MICROCODE_HE= ADER_SIZE) + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = =3D gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinP= latformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPk= gTokenSpaceGuid.PcdMicrocodeOffsetInFv + SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = =3D gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinP= latformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv =20 # # FV Layout (You should not need to modify this section) @@ -410,12 +399,7 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = =3D 0x01000000 !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf FvNameGuid =3D 6522280D-28F9-4131-ADC4-F40EBFA45864 =20 - FILE SEC =3D 1BA0062E-C779-4582-8566-336AE8F78F09 { - SECTION UI =3D "SecCore" - SECTION VERSION =3D "1.0" - SECTION Align =3D 16 PE32 =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR= )/1BA0062E-C779-4582-8566-336AE8F78F09SecCore.efi - SECTION Align =3D 16 RAW =3D $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)= /ResetVec.bin - } + INF UefiCpuPkg/SecCore/SecCore.inf INF MdeModulePkg/Core/Pei/PeiMain.inf =20 INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel= /WhitleySiliconPkg/SiliconPkg.dec index d7039f65c4..ea8fd0a49b 100644 --- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec @@ -905,8 +905,6 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlSupported |FALSE|BOOLEAN= |0xF0000030 gSiPkgTokenSpaceGuid.PcdCpgcGlobalSyncCtrlEnableDefault |FALSE|BOOLEAN= |0xF0000031 =20 - gSiPkgTokenSpaceGuid.PcdPeiCoreFv |0x00000000|UI= NT32|0xF0000032 - gSiPkgTokenSpaceGuid.ReservedN|TRUE|BOOLEAN|0xF0000033 =20 # --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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