From nobody Sun Feb 8 05:21:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80299+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80299+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1631027442; cv=none; d=zohomail.com; s=zohoarc; b=Qgmi0PlCFknrR/C9a66B7GrWXJCbCZskOWgFfZypwrzKPiNaEP75xIPGsO/ovxSQ8XBUvXdrJ6eaSuP5P19llozbldOOYeM8OpoEB0QIsiLEokLfuseEtowmyoZKdrSBMoua2F8E9yxNGLBK07S72bF6up8ZbuGxs9/p6Zi+Fm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631027442; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=D0jr2+oQzOtx8UStR8HvJXOdLmuUH6fqJdXs3tBR6X4=; b=gf4HZZKIuzKBfAnAeARL+d8GnSmgVSmbrbhtB7INy7wrDkhjZ7UdjUF5Rtd9PivRbSrNs2+1wNyMFQOHA5TxxJQ+cYv0PipKdE7fxHtFyiyg5nLg9NkzCUgShUAW4BCUBMxU+VQClA9kZYqqG1M7NdpC9cYWB+MS4AUTQZ3MOEg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80299+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631027442469808.5103130946018; Tue, 7 Sep 2021 08:10:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QwKDYY1788612xgrB1m3EQXD; Tue, 07 Sep 2021 08:10:42 -0700 X-Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mx.groups.io with SMTP id smtpd.web09.11670.1630766376225933616 for ; Sat, 04 Sep 2021 07:39:36 -0700 X-IronPort-AV: E=Sophos;i="5.85,268,1624320000"; d="scan'208";a="24529042" X-Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-1e-c7f73527.us-east-1.amazon.com) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP; 04 Sep 2021 14:39:28 +0000 X-Received: from EX13D49EUC003.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-1e-c7f73527.us-east-1.amazon.com (Postfix) with ESMTPS id 594E0B588F for ; Sat, 4 Sep 2021 14:39:27 +0000 (UTC) X-Received: from ub4014a598e6c52.ant.amazon.com (10.43.162.52) by EX13D49EUC003.ant.amazon.com (10.43.164.91) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 4 Sep 2021 14:39:24 +0000 From: "Nicolas Ojeda Leon via groups.io" To: CC: Nicolas Ojeda Leon , Alexander Graf Subject: [edk2-devel] [PATCH 1/5] OvmfPkg/PlatformPei: Extend 64-bit PCI range for multiple host bridges Date: Sat, 4 Sep 2021 16:37:52 +0200 Message-ID: <2002ab24b91e9007619febab837d2c29aee5f93f.1630676569.git.ncoleon@amazon.com> In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.43.162.52] X-ClientProxiedBy: EX13D16UWC001.ant.amazon.com (10.43.162.117) To EX13D49EUC003.ant.amazon.com (10.43.164.91) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ncoleon@amazon.com X-Gm-Message-State: IISv8cx6hs9u0iNL8TTqjR1Cx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631027442; bh=oED+F3EK9EVV1Jxb2C5Y7v2EAGVHC4qJjuiu5/QEfLo=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=aGH47GpuGwbzcKz8oR2cKGWs/JpL/jDz1M4CKQIaiZB6OV7FKUjD6WZQiMfQosEOUcb Jv5T8bafo2//DtrUxqHrf881EduA0LtD5KWYGaU3oI4voXAo5O3OZ9MzytJ4Fy/GmF//1 uPyjk/bbNVPkRpKoyT7kJ5KC7UnHO/CQLrg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631028345040100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create host_bridge_info struct describing PCI host bridges' resources so that one or more host bridges can be specified by the hypervisor and their information propagated through fw-cfg. The host is able to determine the bus number, the bus number range, the NUMA proximity and all MMIO resources each root bridge uses (low and high memory both prefetchable and non-prefetchable). With the increased control we give for the host to define the resources each root bridge can use, the case may arise in which one of the ranges, particularly the 64-bit MMIO window, exceeds the usable range. Taking into account that PcdPciMmio64Size token determines, together with PcdPciMmio64Base, the usable 64-bit range, we verify if the MMIO windows set in the specification fit inside the valid range. If one of the root bridges is set to use a higher memory address space, PcdPciMmio64Size token is increased so that the intended window lies inside the valid range. For example, using PcdPciMmio64Size of 0x800000000 and a runtime calculated base address also of 0x800000000, the high memory usable addresses are restricted to 0x1000000000. With the increased flexibility to specify host bridge resources, a feasible example would be: struct host_bridge_info pci_hb_spec[] =3D { { .set_pxm =3D true, .mark_prefetchable_resources_as_cacheable =3D true, .root_bus_nr =3D 0x00, .pxm =3D 1, .num_hot_plug_slots =3D 32, .root_bur_nr_start =3D 0x00, .root_bus_nr_end =3D 0x7F, .lowmem_start =3D 0xC0000000, .lowmem_end =3D 0xD0000000 - 1, .lowmem_pref_start =3D 0xFFFFFFFF, .lowmem_pref_end =3D 0xFFFFFFFF, .highmem_start =3D 0xFFFFFFFFFFFFFFFF, .highmem_end =3D 0xFFFFFFFFFFFFFFFF, .highmem_pref_start =3D 0x800000000, .highmem_pref_end =3D 0x1000000000 - 1 }, { .set_pxm =3D true, .mark_prefetchable_resources_as_cacheable =3D true, .root_bus_nr =3D 0x80, .pxm =3D 1, .num_hot_plug_slots =3D 32, .root_bur_nr_start =3D 0x80, .root_bus_nr_end =3D 0xFF, .lowmem_start =3D 0xD0000000, .lowmem_end =3D 0xE0000000 - 1, .lowmem_pref_start =3D 0xFFFFFFFF, .lowmem_pref_end =3D 0xFFFFFFFF, .highmem_start =3D 0xFFFFFFFFFFFFFFFF, .highmem_end =3D 0xFFFFFFFFFFFFFFFF, .highmem_pref_start =3D 0x1000000000, .highmem_pref_end =3D 0x1800000000 - 1 } }; The first host bridge already uses all the available space. Consequently, the 64-bit PCI size needs to be extended. For that, the resource spec exemplified is read from fw-cfg and PcdPciMmio64Size extended to 0x1000000000 so that both host bridges fit inside the valid window. Signed-off-by: Nicolas Ojeda Leon Cc: Alexander Graf --- .../Include/Library/PciHostBridgeInfoLib.h | 43 ++++++++++ OvmfPkg/PlatformPei/MemDetect.c | 83 +++++++++++++++++++ 2 files changed, 126 insertions(+) create mode 100644 OvmfPkg/Include/Library/PciHostBridgeInfoLib.h diff --git a/OvmfPkg/Include/Library/PciHostBridgeInfoLib.h b/OvmfPkg/Inclu= de/Library/PciHostBridgeInfoLib.h new file mode 100644 index 0000000000..e09e6c496e --- /dev/null +++ b/OvmfPkg/Include/Library/PciHostBridgeInfoLib.h @@ -0,0 +1,43 @@ +/* + * Copyright 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * This program and the accompanying materials + * are licensed and made available under the terms and conditions of the B= SD License + * which accompanies this distribution. The full text of the license may = be found at + * http://opensource.org/licenses/bsd-license.php + * + * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. + */ + +#ifndef __PCI_HOST_BRIDGE_INFO_LIB_H__ +#define __PCI_HOST_BRIDGE_INFO_LIB_H__ + +// +// Root bridge resource information for parsing fw-cfg data +// +#pragma pack(1) +typedef struct { + BOOLEAN set_pxm; + BOOLEAN mark_prefetchable_resources_as_cacheable; + + UINT8 root_bus_nr; + UINT8 pxm; + UINT8 num_hot_plug_slots; + + UINT8 root_bur_nr_start; + UINT8 root_bus_nr_end; + + UINT32 lowmem_start; + UINT32 lowmem_end; + UINT32 lowmem_pref_start; + UINT32 lowmem_pref_end; + + UINT64 highmem_start; + UINT64 highmem_end; + UINT64 highmem_pref_start; + UINT64 highmem_pref_end; +} HOST_BRIDGE_INFO; +#pragma pack() + +#endif diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 2c2c4641ec..2872e805a4 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -30,6 +30,7 @@ Module Name: #include #include #include +#include #include #include #include @@ -323,6 +324,83 @@ GetSystemMemorySizeAbove4gb ( } =20 =20 +/** + Iterate over the PCI host bridges resources information optionally provi= ded + in fw-cfg. + + Find the highest address used by the PCI bridges in 64-bit MMIO space to + calculate and modify the PCI aperture size accordingly (PciMmio64Size) + + @param[in] PciMmio64Base Base address (start) of the 64-bit PCI MMIO + address space. + + @param[inout] PciMmio64Size Size of the PCI 64-bit MMIO aperture provided + as input and modified (output) if the resour= ces + indicated by fw_cfg require a larger address + space. + + @retval EFI_SUCCESS The fw_cfg host-bridges-info was found and + processed. + + @retval EFI_PROTOCOL_ERROR The host bridges information file was found, + but its size wasn't a whole multiple of + sizeof(HOST_BRIDGE_INFO). No entry was proce= ssed. + + @retval EFI_NOT_FOUND fw-cfg file with host bridges information wa= s not + found. Does not constitute an errro since th= e file + is optional and used in special cases. + + @retval EFI_UNSUPPORTED fw-cfg is unavailable + +**/ +STATIC +EFI_STATUS +ScanPci64BitApertureSize ( + IN UINT64 PciMmio64Base, + IN OUT UINT64 *PciMmio64Size + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + HOST_BRIDGE_INFO HostBridge; + UINTN FwCfgSize; + UINTN Processed; + UINT64 PciEnd; + UINT64 PcdPciEnd; + + Status =3D QemuFwCfgFindFile ("etc/host-bridge-info", &FwCfgItem, &FwCfg= Size); + if (EFI_ERROR (Status)) { + return Status; + } + if (FwCfgSize % sizeof HostBridge !=3D 0) { + return EFI_PROTOCOL_ERROR; + } + + PciEnd =3D 0; + QemuFwCfgSelectItem (FwCfgItem); + for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof HostB= ridge) { + QemuFwCfgReadBytes (sizeof HostBridge, &HostBridge); + + if (HostBridge.highmem_end !=3D MAX_UINT64 && + HostBridge.highmem_end > PciEnd) { + PciEnd =3D HostBridge.highmem_end; + } + if (HostBridge.highmem_pref_end !=3D MAX_UINT64 && + HostBridge.highmem_pref_end > PciEnd) { + PciEnd =3D HostBridge.highmem_pref_end; + } + } + + PcdPciEnd =3D PciMmio64Base + *PciMmio64Size; + if (PciEnd > PcdPciEnd) { + *PciMmio64Size =3D PciEnd - PciMmio64Base; + *PciMmio64Size =3D ALIGN_VALUE (*PciMmio64Size, (UINT64)SIZE_1GB); + } + + return EFI_SUCCESS; +} + + /** Return the highest address that DXE could possibly use, plus one. **/ @@ -452,6 +530,11 @@ GetFirstNonAddress ( // Pci64Base =3D ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size)); =20 + // + // Extend Pci64Size if fw_cfg Host bridges specification requires it + // + ScanPci64BitApertureSize (Pci64Base, &Pci64Size); + if (mBootMode !=3D BOOT_ON_S3_RESUME) { // // The core PciHostBridgeDxe driver will automatically add this range = to --=20 2.17.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80299): https://edk2.groups.io/g/devel/message/80299 Mute This Topic: https://groups.io/mt/85437209/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Feb 8 05:21:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80300+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80300+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1631027441; cv=none; d=zohomail.com; s=zohoarc; b=GZ7Q0nbu5p1HNA6vIwGRB8joCq+fdFZw+1r/pz8CHlD42pynbPXU/HcAkRTNXs6ei/3NQiI4P39U9PboUE0syIkSNJ4NDib19oqR8z8jCMBiBiugCUjrJTL49WkgFD3eDhiqpsFlRH6JWDfCtVXzG7BgW5FJ4hDeqfi8NPS/pm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631027441; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QMGYW2gXqkzzaiN03/ETlxpRHSoyXwhFZEkYQ+RSlK4=; b=Wfs+XD9Qm8XHCTFObFK5b5F8K3pkr88WhCm85QvR0iPHOG6o0avRdkIj+i4L/ZqlN2SBIukJQg175h/eaWKoozgb45Co8leda+ItgDu0WwI/QYTZnloL2VAhHnJaeWjewZQY45r3E+BzlcNU5Sg0u/klfjP7T8YKB6BfDGDw6Eo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80300+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631027441867432.72644239417866; Tue, 7 Sep 2021 08:10:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4og4YY1788612xdpEg7OJcsU; Tue, 07 Sep 2021 08:10:41 -0700 X-Received: from smtp-fw-33001.amazon.com (smtp-fw-33001.amazon.com [207.171.190.10]) by mx.groups.io with SMTP id smtpd.web08.11837.1630766529733325108 for ; Sat, 04 Sep 2021 07:42:09 -0700 X-IronPort-AV: E=Sophos;i="5.85,268,1624320000"; d="scan'208";a="145980319" X-Received: from iad12-co-svc-p1-lb1-vlan2.amazon.com (HELO email-inbound-relay-1e-27fb8269.us-east-1.amazon.com) ([10.43.8.2]) by smtp-border-fw-33001.sea14.amazon.com with ESMTP; 04 Sep 2021 14:42:02 +0000 X-Received: from EX13D49EUC003.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-1e-27fb8269.us-east-1.amazon.com (Postfix) with ESMTPS id 7EF6BA1E17 for ; Sat, 4 Sep 2021 14:42:01 +0000 (UTC) X-Received: from ub4014a598e6c52.ant.amazon.com (10.43.162.52) by EX13D49EUC003.ant.amazon.com (10.43.164.91) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 4 Sep 2021 14:41:58 +0000 From: "Nicolas Ojeda Leon via groups.io" To: CC: Nicolas Ojeda Leon , Alexander Graf Subject: [edk2-devel] [PATCH 2/5] OvmfPkg/PciHostBridgeUtilityLib: Initialize RootBridges apertures with spec Date: Sat, 4 Sep 2021 16:37:53 +0200 Message-ID: <60082b721c455f0762bdf4fd96c3544f7cdfb0c3.1630676569.git.ncoleon@amazon.com> In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.43.162.52] X-ClientProxiedBy: EX13D16UWC001.ant.amazon.com (10.43.162.117) To EX13D49EUC003.ant.amazon.com (10.43.164.91) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ncoleon@amazon.com X-Gm-Message-State: lxnVOWv8xFwkIL6L7OahRlbax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631027441; bh=6dxWC+KsrEm5s7AylKYOx26RgN9aUW915mvu/VGUiac=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=QDBPRkOwTBVisljmK/57WOGO2d+mUFFIVI5nLgy/sefFDG+fwkpH4t2aO1fZdKzKs0w 5utOOZ989Hxrj+KK9Yt+7R7TXOa2CN5vIhyN5o9Btmg4fUh1E1OHcPwNS5Fvsi3cBZuO6 p59wTW7uQw9582i0fY8aXqOOJavJ/lZhSKI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631027443015100007 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Considering the "host-bridge-info" item from fw-cfg, the apertures for all root bridges are initialized and used in the creation of the root bridge objects that determine the resources each host bridge can use. PCI MMIO apertures are merged to produce a single low memory and a single high memory apertures matching current Ovmf allocation strategy which includes the EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM attribute. Prefetchable and non-prefetchable ranges are merged together to produce a single aperture covering both ranges. Therefore, if both prefetchable and non-prefetchable apertures are defined for one of the address spaces (32-bit or 64-bit), these 2 must be contiguous. For platforms having multiple PCI host bridges, hypervisor builds and propagates the resource specification (MMIO apertures) for each of the host bridges over fw-cfg. These specifications determine the usable windows in low and high memory, overwriting any calculated range and providing both control for the hypervisor to configure the apertures as well as possibility to use multiple host bridges. Signed-off-by: Nicolas Ojeda Leon Cc: Alexander Graf --- .../PciHostBridgeUtilityLib.c | 128 +++++++++++++++++- 1 file changed, 126 insertions(+), 2 deletions(-) diff --git a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLi= b.c b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c index d2296f3308..7567da8423 100644 --- a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c +++ b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c @@ -18,6 +18,7 @@ #include #include #include +#include #include =20 =20 @@ -186,6 +187,66 @@ PciHostBridgeUtilityUninitRootBridge ( FreePool (RootBus->DevicePath); } =20 +/** + Interpret the MMIO resources in HostBridge and set the apertures + in 32-bit space (Mem) and 64-bit space (MemABove4G) accordingly. + + The 2 types of apertures in each space (prefetchable and + non-prefetchable) are merged into a single window, hence if both + types of apertures are defined for a root bridges, these must be + contiguous. + + @param[in] HostBridge Root bridge's resources specification + + @param[out] Mem 32-bit MMIO aperture + + @param[out] MemAbove4G 64-bit MMIO aperture +**/ +STATIC +VOID +InitRootBridgeApertures ( + IN HOST_BRIDGE_INFO *HostBridge, + OUT PCI_ROOT_BRIDGE_APERTURE *Mem, + OUT PCI_ROOT_BRIDGE_APERTURE *MemAbove4G + + ) +{ + if (HostBridge =3D=3D NULL || Mem =3D=3D NULL || MemAbove4G =3D=3D NULL)= { + return; + } + + MemAbove4G->Base =3D MAX_UINT64; + MemAbove4G->Limit =3D 0; + + if (HostBridge->highmem_start !=3D MAX_UINT64 && + HostBridge->highmem_end !=3D MAX_UINT64) { + MemAbove4G->Base =3D HostBridge->highmem_start; + MemAbove4G->Limit =3D HostBridge->highmem_end; + } + + if (HostBridge->highmem_pref_start !=3D MAX_UINT64 && + HostBridge->highmem_pref_end !=3D MAX_UINT64) { + if (HostBridge->highmem_pref_start < MemAbove4G->Base) + MemAbove4G->Base =3D HostBridge->highmem_pref_start; + + if (HostBridge->highmem_pref_end > MemAbove4G->Limit) + MemAbove4G->Limit =3D HostBridge->highmem_pref_end; + } + + // + // Check if prefetchable range is valid and merge both ranges into a sin= gle + // 32-bit aperture. + // In case both prefetchable and non-prefetchable ranges are defined, + // these must be contiguous. + // + Mem->Base =3D HostBridge->lowmem_start; + if (HostBridge->lowmem_pref_end !=3D MAX_UINT32) { + Mem->Limit =3D HostBridge->lowmem_pref_end; + } else { + Mem->Limit =3D HostBridge->lowmem_end; + } +} + =20 /** Utility function to return all the root bridge instances in an array. @@ -241,6 +302,7 @@ PciHostBridgeUtilityGetRootBridges ( UINTN Initialized; UINTN LastRootBridgeNumber; UINTN RootBridgeNumber; + HOST_BRIDGE_INFO *RootBridgesInfo; =20 *Count =3D 0; =20 @@ -277,13 +339,54 @@ PciHostBridgeUtilityGetRootBridges ( __FUNCTION__, ExtraRootBridges)); } =20 + // + // Initialize RootBridgeInfo pointer, so in case no fw-cfg item is found + // the default configuration is used. + // + RootBridgesInfo =3D NULL; + Initialized =3D 0; + Bridges =3D NULL; + + // + // Hypervisor can provide, over fw-cfg, resource specifications for one = or + // more PCI host bridges. + // + Status =3D QemuFwCfgFindFile ("etc/host-bridge-info", &FwCfgItem, &FwCfg= Size); + + if (!EFI_ERROR (Status)) { + UINTN RootBridgesInfoSize =3D (1 + (UINTN)ExtraRootBridges) * + sizeof(HOST_BRIDGE_INFO); + RootBridgesInfo =3D AllocatePool (RootBridgesInfoSize); + + if (RootBridgesInfo =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, + "%a: Failed to allocate memory for resources info\n", __FUNCTION__= )); + return NULL; + } + + // + // Read the resource information of all Root Bridges from fw-cfg + // + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (FwCfgSize, RootBridgesInfo); + + if (FwCfgSize !=3D RootBridgesInfoSize) { + DEBUG ((DEBUG_ERROR, + "%a: Invalid HostBridgeInfo fw-cfg item size. Expected %ld, got %l= d\n", + __FUNCTION__, RootBridgesInfoSize, FwCfgSize)); + goto FreeBridges; + } + DEBUG ((DEBUG_INFO, "%a: Resources for %Lu root buses found in fw-cfg\= n", + __FUNCTION__, ExtraRootBridges + 1)); + } + // // Allocate the "main" root bridge, and any extra root bridges. // Bridges =3D AllocatePool ((1 + (UINTN)ExtraRootBridges) * sizeof *Bridge= s); if (Bridges =3D=3D NULL) { DEBUG ((DEBUG_ERROR, "%a: %r\n", __FUNCTION__, EFI_OUT_OF_RESOURCES)); - return NULL; + goto FreeBridges; } Initialized =3D 0; =20 @@ -309,6 +412,11 @@ PciHostBridgeUtilityGetRootBridges ( } } if (Device <=3D PCI_MAX_DEVICE) { + // + // If resources obtained from fw-cfg, use those values + // + InitRootBridgeApertures(&RootBridgesInfo[Initialized], Mem, MemAbove= 4G); + // // Found the next root bus. We can now install the *previous* one, // because now we know how big a bus number range *that* one has, fo= r any @@ -341,6 +449,8 @@ PciHostBridgeUtilityGetRootBridges ( // Install the last root bus (which might be the only, ie. main, root bu= s, if // we've found no extra root buses). // + InitRootBridgeApertures(&RootBridgesInfo[Initialized], Mem, MemAbove4G); + Status =3D PciHostBridgeUtilityInitRootBridge ( Attributes, Attributes, @@ -362,6 +472,14 @@ PciHostBridgeUtilityGetRootBridges ( ++Initialized; =20 *Count =3D Initialized; + + // + // If resources were allocated for host bridges info, release them + // + if (RootBridgesInfo) { + FreePool(RootBridgesInfo); + } + return Bridges; =20 FreeBridges: @@ -370,7 +488,13 @@ FreeBridges: PciHostBridgeUtilityUninitRootBridge (&Bridges[Initialized]); } =20 - FreePool (Bridges); + if (Bridges) { + FreePool (Bridges); + } + + if (RootBridgesInfo) { + FreePool(RootBridgesInfo); + } return NULL; } =20 --=20 2.17.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80300): https://edk2.groups.io/g/devel/message/80300 Mute This Topic: https://groups.io/mt/85437210/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Feb 8 05:21:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80301+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80301+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1631027442; cv=none; d=zohomail.com; s=zohoarc; b=c84C9AFZ/AxEj9no5SWk/lb+nHY8y3cYTEuZplsMplm8o0XqQvWDraqrYEkJDPuiMRhPP90Olxx+6CUns2EipSB93S5buvcJINAHrJVk3NgUqr5yyK5Kptt80zHItOdL9meD6XZ5J/43VlZZQPIjKa6Sbzt1oANfP6GHYGpaha4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631027442; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=UWlrDNKmrsaeC2vythTCPcJV6vA4yTWosBIW7OsCtIs=; b=JvnQS5H6bWR2brbwjDg1sQ/tiLSElWEAqorXKT7dr6fO8MCptbwKtkiBrnDFkItk05dAvpyf0i8Vl4uCvHyCQ5bf6suAG5yiW2XXDdgu7JGNViA1PWOHsEX0eQcryg55Rj5kmKnyJsrotG3f2L8X6FbUSS4grUh8C9rQbB7Z8Lg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80301+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631027442870283.9074919271758; Tue, 7 Sep 2021 08:10:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id NPjdYY1788612xCHs6cNviQI; Tue, 07 Sep 2021 08:10:42 -0700 X-Received: from smtp-fw-80007.amazon.com (smtp-fw-80007.amazon.com [99.78.197.218]) by mx.groups.io with SMTP id smtpd.web08.11841.1630766541972468133 for ; Sat, 04 Sep 2021 07:42:22 -0700 X-IronPort-AV: E=Sophos;i="5.85,268,1624320000"; d="scan'208";a="24529243" X-Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-1d-5dd976cd.us-east-1.amazon.com) ([10.25.36.210]) by smtp-border-fw-80007.pdx80.corp.amazon.com with ESMTP; 04 Sep 2021 14:42:21 +0000 X-Received: from EX13D49EUC003.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-1d-5dd976cd.us-east-1.amazon.com (Postfix) with ESMTPS id EA099A28E0 for ; Sat, 4 Sep 2021 14:42:20 +0000 (UTC) X-Received: from ub4014a598e6c52.ant.amazon.com (10.43.162.52) by EX13D49EUC003.ant.amazon.com (10.43.164.91) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 4 Sep 2021 14:42:18 +0000 From: "Nicolas Ojeda Leon via groups.io" To: CC: Nicolas Ojeda Leon , Alexander Graf Subject: [edk2-devel] [PATCH 3/5] MdeModulePkg OvmfPkg: Add Pcd token for PCI pre-populated BARs Date: Sat, 4 Sep 2021 16:37:54 +0200 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.43.162.52] X-ClientProxiedBy: EX13D16UWC001.ant.amazon.com (10.43.162.117) To EX13D49EUC003.ant.amazon.com (10.43.164.91) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ncoleon@amazon.com X-Gm-Message-State: G3rttFvsZDKiesCaIl7HJvl9x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631027442; bh=k+RTs1ZxcQJE+Yg+qC1y1JN5jbMAxtgNMBzUAKPHpjI=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=eN+9s18Tq/aUte5PbOaVBghSJQNGx34wOa4ho82Mom/wg9krUzIThF5Q7sswnN3cXQY 0CQZjhJzXw1nEi+dXe7AQ1IArUtV22xkdDO4F1VDYBKEvmQPSuR44POmInD6R1cEGyudW V0XVeW5gmn6yHpemfEDOWQr0Iia7XLwZ32A= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631027445055100016 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Create a new PCD boolean token in MdeModulePkg for global use. We use this token to indicate if the configuration, parsed from fw-cfg, requires pre-populated BARs to be preserved. During creation of root bridges configurations, the flag is set according to the "pre-populated-bars" item in fw-cfg. The Pcd token is created as a dynamic item for consumption in both Pei and Dxe PCI modules. The token provides a globally accessible configuration flag to determine, during PCI BAR allocation, if pre-populated BARs must be respected. The pre-allocated PCI BARs are used in platforms in which MMIO resources are configured with host physical addresses so that DMA transactions can happen between PCI devices without packets going through the IOMMU. Performance is improved due to PCI packets travelling shorter distances and avoiding links reaching the Root Complex, which can get busy during I/O intensive periods. Signed-off-by: Nicolas Ojeda Leon Cc: Alexander Graf --- MdeModulePkg/MdeModulePkg.dec | 6 ++++++ OvmfPkg/OvmfPkgX64.dsc | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 1 + .../PciHostBridgeUtilityLib.inf | 4 ++++ OvmfPkg/PlatformPei/PlatformPei.inf | 1 + .../PciHostBridgeUtilityLib.c | 17 +++++++++++++++++ 6 files changed, 30 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 133e04ee86..44a2150628 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -1902,6 +1902,12 @@ # @Prompt Disable full PCI enumeration. gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|FALSE|BOOLEAN= |0x10000048 =20 + ## The flag to control preservation of pre-populated PCI BARs + # TRUE - Respect pre-populated PCI BARs + # FALSE - No pre-populated BARs, place all BARs + # @Prompt Enable preservsation of pre-populated PCI BARs + gEfiMdeModulePkgTokenSpaceGuid.PcdPciPreservePopulatedMappings|FALSE|BOO= LEAN|0x10000050 + ## Disk I/O - Number of Data Buffer block. # Define the size in block of the pre-allocated buffer. It provide better # performance for large Disk I/O requests. diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index e56b83d95e..fff50355b0 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -605,6 +605,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0 !endif + gEfiMdeModulePkgTokenSpaceGuid.PcdPciPreservePopulatedMappings|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|800 gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|600 gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable|FALSE diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bu= s/Pci/PciBusDxe/PciBusDxe.inf index e317169d9c..046876bb3b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -107,6 +107,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## SOMETIM= ES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdPciPreservePopulatedMappings## CONSUMES =20 [UserExtensions.TianoCore."ExtraFiles"] PciBusDxeExtra.uni diff --git a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLi= b.inf b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf index 83a734c172..3643ffd79e 100644 --- a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf +++ b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf @@ -39,5 +39,9 @@ DebugLib DevicePathLib MemoryAllocationLib + PcdLib PciLib QemuFwCfgLib + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdPciPreservePopulatedMappings diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 67eb7aa716..61bcf25999 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -93,6 +93,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved + gEfiMdeModulePkgTokenSpaceGuid.PcdPciPreservePopulatedMappings gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack diff --git a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLi= b.c b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c index 7567da8423..0a9aac5359 100644 --- a/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c +++ b/OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -298,6 +299,7 @@ PciHostBridgeUtilityGetRootBridges ( FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; UINT64 ExtraRootBridges; + UINT64 PrePopulatedBars; PCI_ROOT_BRIDGE *Bridges; UINTN Initialized; UINTN LastRootBridgeNumber; @@ -339,6 +341,21 @@ PciHostBridgeUtilityGetRootBridges ( __FUNCTION__, ExtraRootBridges)); } =20 + // + // Find file for pre-populated bars and set Pcd token if enabled + // + Status =3D QemuFwCfgFindFile ("etc/pre-populated-bars", &FwCfgItem, &FwC= fgSize); + PrePopulatedBars =3D 0; + if (!EFI_ERROR (Status) && FwCfgSize =3D=3D sizeof (PrePopulatedBars)) { + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (FwCfgSize, &PrePopulatedBars); + + if (PrePopulatedBars) { + PcdSetBoolS (PcdPciPreservePopulatedMappings, TRUE); + DEBUG ((DEBUG_INFO, "%a: Pre-populated BARs present\n", __FUNCTION__= )); + } + } + // // Initialize RootBridgeInfo pointer, so in case no fw-cfg item is found // the default configuration is used. --=20 2.17.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80301): https://edk2.groups.io/g/devel/message/80301 Mute This Topic: https://groups.io/mt/85437211/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Feb 8 05:21:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80302+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80302+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1631027443; cv=none; d=zohomail.com; s=zohoarc; b=gQeTtXox8cG4p1AkGyI9xeqMgzspbZd06K+aQ3aahwmPEowC2BgAGX6+hh9+zbAPeL1tjvf8dN2paazGOMdRBpS14k1YpsAV1CoOQWgYXsOEE4BRrd62MAu7AO8yiCcSnsUvIUSQQfPv8rMrX8Ff7SCtTd0Q5z6hiYTb2BzrHz4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631027443; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=lLkmVdZFKRIzJp+1L2fLYYnMkSdcsMkU9PKXGJxXc8g=; b=M8cHT1+lJ+/gq4Jlm7TS3RhL4CEqp/HRFEcadzdi3sfRc13zqrQvUjPiZQhS+Kl1eM2/Oj0GK9OgPtS4B9ovO/rces2M8Y4Gz7j08WR9gbuqIBjwLutNUK2EADsU5c1/+xH5em6YeiQU2/c02SxZEjGQ2j6LudZlngqc4te+/nM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80302+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1631027443720421.8445017466802; Tue, 7 Sep 2021 08:10:43 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id DFqBYY1788612xvlg4af3B4n; Tue, 07 Sep 2021 08:10:43 -0700 X-Received: from smtp-fw-6001.amazon.com (smtp-fw-6001.amazon.com [52.95.48.154]) by mx.groups.io with SMTP id smtpd.web10.11783.1630766556103250560 for ; Sat, 04 Sep 2021 07:42:36 -0700 X-IronPort-AV: E=Sophos;i="5.85,268,1624320000"; d="scan'208";a="139382571" X-Received: from iad12-co-svc-p1-lb1-vlan3.amazon.com (HELO email-inbound-relay-1e-c7f73527.us-east-1.amazon.com) ([10.43.8.6]) by smtp-border-fw-6001.iad6.amazon.com with ESMTP; 04 Sep 2021 14:42:29 +0000 X-Received: from EX13D49EUC003.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan2.iad.amazon.com [10.40.163.34]) by email-inbound-relay-1e-c7f73527.us-east-1.amazon.com (Postfix) with ESMTPS id B1289C20D1 for ; Sat, 4 Sep 2021 14:42:27 +0000 (UTC) X-Received: from ub4014a598e6c52.ant.amazon.com (10.43.162.52) by EX13D49EUC003.ant.amazon.com (10.43.164.91) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 4 Sep 2021 14:42:24 +0000 From: "Nicolas Ojeda Leon via groups.io" To: CC: Nicolas Ojeda Leon , Alexander Graf Subject: [edk2-devel] [PATCH 4/5] MdeModulePkg/Pci MdePkg: Create service to retrieve PCI base addresses Date: Sat, 4 Sep 2021 16:37:55 +0200 Message-ID: <0a176a5dd9cd1e9796737596f695f0f6f92fb105.1630676569.git.ncoleon@amazon.com> In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.43.162.52] X-ClientProxiedBy: EX13D16UWC001.ant.amazon.com (10.43.162.117) To EX13D49EUC003.ant.amazon.com (10.43.164.91) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ncoleon@amazon.com X-Gm-Message-State: TxY1hMVg1R41qE3mOqoZSGltx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631027443; bh=4qxqKIY7l4SWfxiMr0C20WhKqMqeK8nEQPYRBCsFA6Y=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=qWtyPBWASACr8lIz7YQ7KLAmf8gPiPFYyyDdcRYbxA6ZKhSActzKo7zDxrVY9ULJ+Mn QRz9jlw7irLtUDtD8ArJlytBpuE0z7w2/pkiqs52BwjS8iZrSldLLQztTNBbofxGHsHmH hGCEbL0YB8Auwq9x7IEWcE5adPqFP7QrQ2w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631027445238100020 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the PCI host bridge resource allocation protocol to include one more service that retrieves the base addresses of all resources of a given root bridge. The service is defined to provide, on runtime, the possibility to fetch the base addresses of a root bridge, replicating the address alignment used when placing the host bridge's resources in the Gcd memory map. The intention of this service, initially, is to allow the PCI allocation process to get the base addresses before allocating the individual BARs grouped under a root bridge. This enables the placing logic to be enhanced to account and calculate offsets for pre-populated BARs (PCI devices' BARs that are already configured and need to be respected). Signed-off-by: Nicolas Ojeda Leon Cc: Alexander Graf --- .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 29 +++++++ .../PciHostBridgeResourceAllocation.h | 33 ++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 10 +++ .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 80 +++++++++++++++++++ 4 files changed, 152 insertions(+) diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h index 755ab75b19..3b8432fb29 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h @@ -239,6 +239,35 @@ PreprocessController ( IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase ); =20 +/** + + Retrieve the aligned base addresses for all resources of a root bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL instance. + @param RootBridgeHandle RootBridgeHandle returned by GetNextRootBridge = to locate the + root bridge of interest among the list of root = bridges. + @param IoBase Returns the PIO aperture base address. + @param Mem32Base Returns the 32-bit aperture base address. + @param PMem32Base Returns the 32-bit prefetchable aperture base a= ddress. + @param Mem64Base Returns the 64-bit aperture base address. + @param PMem64Base Returns the 64-bit prefetchable aperture base a= ddress. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND Root bridge was not found. + +**/ +EFI_STATUS +EFIAPI +GetResourcesBases( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *IoBase, + OUT UINT64 *Mem32Base, + OUT UINT64 *PMem32Base, + OUT UINT64 *Mem64Base, + OUT UINT64 *PMem64Base + ); + /** This routine constructs the resource descriptors for all root bridges an= d call PciHostBridgeResourceConflict(). =20 diff --git a/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h b/Md= ePkg/Include/Protocol/PciHostBridgeResourceAllocation.h index 17b1b5a8d8..f42521a348 100644 --- a/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h +++ b/MdePkg/Include/Protocol/PciHostBridgeResourceAllocation.h @@ -367,6 +367,33 @@ EFI_STATUS IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase ); =20 +/** + Retrieves the base addresses of ost bridge resources. + + @param This The pointer to the EFI_PCI_HOST_BRIDGE_RESOURCE= _ALLOCATION_PROTOCOL instance. + @param RootBridgeHandle The PCI root bridge handle. + @param IoBase The pointer to PIO aperture base address. + @param Mem32Base The pointer to 32-bit aperture base address. + @param PMem32Base The pointer to 32-bit prefetchable aperture bas= e address. + @param Mem64Base The pointer to 64-bit aperture base address. + @param PMem64Base The pointer to 64-bit prefetchable aperture bas= e address. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND Root bridge was not found. + +**/ +typedef +EFI_STATUS +(EFIAPI *EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_RESOURCES_BA= SES) ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *IoBase, + OUT UINT64 *Mem32Base, + OUT UINT64 *PMem32Base, + OUT UINT64 *Mem64Base, + OUT UINT64 *PMem64Base + ); + /// /// Provides the basic interfaces to abstract a PCI host bridge resource a= llocation. /// @@ -415,6 +442,12 @@ struct _EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOC= OL { /// before enumeration. /// EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_PREPROCESS_CONTROLLER = PreprocessController; + + /// + /// Returns the aligned base addresses of the different resource windows + /// of the host bridge. Intended for use before resources are submitted. + /// + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL_GET_RESOURCES_BASES = GetResourcesBases; }; =20 extern EFI_GUID gEfiPciHostBridgeResourceAllocationProtocolGuid; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index 4caac56f1d..82147a4946 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -561,6 +561,16 @@ PciHostBridgeResourceAllocator ( PciResUsageTypical ); =20 + Status =3D PciResAlloc->GetResourcesBases( + PciResAlloc, + RootBridgeDev->Handle, + &IoBase, + &Mem32Base, + &PMem32Base, + &Mem64Base, + &PMem64Base + ); + // // Get the max ROM size that the root bridge can process // Insert to resource map so that there will be dedicate MEM32 resou= rce range for Option ROM. diff --git a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c b/MdeMod= ulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c index 4ab9415c96..0ba9e100fc 100644 --- a/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c +++ b/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c @@ -527,6 +527,7 @@ InitializePciHostBridge ( HostBridge->ResAlloc.SubmitResources =3D SubmitResources; HostBridge->ResAlloc.GetProposedResources =3D GetProposedResources; HostBridge->ResAlloc.PreprocessController =3D PreprocessController; + HostBridge->ResAlloc.GetResourcesBases =3D GetResourcesBases; =20 Status =3D gBS->InstallMultipleProtocolInterfaces ( &HostBridge->Handle, @@ -1594,3 +1595,82 @@ PreprocessController ( =20 return EFI_INVALID_PARAMETER; } + +/** + + Retrieve the aligned base addresses for all resources of a root bridge. + + @param This The EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL instance. + @param RootBridgeHandle RootBridgeHandle returned by GetNextRootBridge = to locate the + root bridge of interest among the list of root = bridges. + @param IoBase Returns the PIO aperture base address. + @param Mem32Base Returns the 32-bit aperture base address. + @param PMem32Base Returns the 32-bit prefetchable aperture base a= ddress. + @param Mem64Base Returns the 64-bit aperture base address. + @param PMem64Base Returns the 64-bit prefetchable aperture base a= ddress. + + @retval EFI_SUCCESS Succeed. + @retval EFI_NOT_FOUND Root bridge was not found. + +**/ +EFI_STATUS +EFIAPI +GetResourcesBases( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *IoBase, + OUT UINT64 *Mem32Base, + OUT UINT64 *PMem32Base, + OUT UINT64 *Mem64Base, + OUT UINT64 *PMem64Base + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *RootBridge; + LIST_ENTRY *Link; + UINT64 Alignment; + UINTN BitsOfAlignment; + + HostBridge =3D PCI_HOST_BRIDGE_FROM_THIS(This); + + for (Link =3D GetFirstNode (&HostBridge->RootBridges) + ; !IsNull (&HostBridge->RootBridges, Link) + ; Link =3D GetNextNode (&HostBridge->RootBridges, Link) + ) { + RootBridge =3D ROOT_BRIDGE_FROM_LINK (Link); + + if (RootBridgeHandle =3D=3D RootBridge->Handle) { + // + // Have to make sure Alignment is handled since we are doing direc= t address allocation + // + Alignment =3D RootBridge->ResAllocNode[TypeIo].Alignment; + BitsOfAlignment =3D MIN (15, LowBitSet64 (Alignment + 1)); + *IoBase =3D ALIGN_VALUE (RootBridge->Io.Base, Alignment + = 1); + *IoBase =3D ALIGN_VALUE (*IoBase, LShiftU64 (1, BitsOfAlig= nment)); + + Alignment =3D RootBridge->ResAllocNode[TypeMem32].Alignment; + BitsOfAlignment =3D MIN (31, LowBitSet64 (Alignment + 1)); + *Mem32Base =3D ALIGN_VALUE (RootBridge->Mem.Base, Alignment += 1); + *Mem32Base =3D ALIGN_VALUE (*Mem32Base, LShiftU64 (1, BitsOfA= lignment)); + + Alignment =3D RootBridge->ResAllocNode[TypePMem32].Alignment; + BitsOfAlignment =3D MIN (31, LowBitSet64 (Alignment + 1)); + *PMem32Base =3D ALIGN_VALUE(RootBridge->PMem.Base, Alignment += 1); + *PMem32Base =3D ALIGN_VALUE (*PMem32Base, LShiftU64 (1, BitsOf= Alignment)); + + Alignment =3D RootBridge->ResAllocNode[TypeMem64].Alignment; + BitsOfAlignment =3D MIN (63, LowBitSet64 (Alignment + 1)); + *Mem64Base =3D ALIGN_VALUE(RootBridge->MemAbove4G.Base, Align= ment + 1); + *Mem64Base =3D ALIGN_VALUE (*Mem64Base, LShiftU64 (1, BitsOfA= lignment)); + + Alignment =3D RootBridge->ResAllocNode[TypePMem64].Alignment; + BitsOfAlignment =3D MIN (63, LowBitSet64 (Alignment + 1)); + *PMem64Base =3D ALIGN_VALUE(RootBridge->PMemAbove4G.Base, Alig= nment + 1); + *PMem64Base =3D ALIGN_VALUE (*PMem64Base, LShiftU64 (1, BitsOf= Alignment)); + + return EFI_SUCCESS; + } + } + + return EFI_NOT_FOUND; +} --=20 2.17.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#80302): https://edk2.groups.io/g/devel/message/80302 Mute This Topic: https://groups.io/mt/85437212/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun Feb 8 05:21:10 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+80303+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80303+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1631027444; cv=none; d=zohomail.com; s=zohoarc; b=U9aVo2hj6RKIy5qqGNnZFEzbfmxan5gnEAqnp4vHd2MtYQA3b0Tv0t1VoV++SmdharskFT1UgH/S57xAasGcJ4SVuzWyfPRBaNATxFsCXLiS/LrMn2D+R9smDvitbZr8N8cZoUqkfkkKXiyZRgLUz0BEqAGFAw0UNC75DD5tH3w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1631027444; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cXiH2tbBaP1FolsmYZaxYn2Sq2Jb3NWfhQSWPEJDyVk=; b=HRApX+EuptljgjJybGVuDhGTUwN3sgZsw0Sj0A/1k9NMmTkcVOuITmImWzeZr1EKPvn0Dpv/g9vwcN8B1HyFzfTMQDwclKNUeBbJFqDsUNTOpqj1LTEOqogG3BIt2uk+dRbADAQSTmhLeCiX2tidu/b6D8sepfACo9Bhsg5L1hs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+80303+1787277+3901457@groups.io Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 163102744443865.58689350003806; Tue, 7 Sep 2021 08:10:44 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id veafYY1788612xiH7g3kekks; Tue, 07 Sep 2021 08:10:44 -0700 X-Received: from smtp-fw-9103.amazon.com (smtp-fw-9103.amazon.com [207.171.188.200]) by mx.groups.io with SMTP id smtpd.web12.11904.1630766560946125987 for ; Sat, 04 Sep 2021 07:42:41 -0700 X-IronPort-AV: E=Sophos;i="5.85,268,1624320000"; d="scan'208";a="955537417" X-Received: from pdx4-co-svc-p1-lb2-vlan2.amazon.com (HELO email-inbound-relay-1e-42f764a0.us-east-1.amazon.com) ([10.25.36.210]) by smtp-border-fw-9103.sea19.amazon.com with ESMTP; 04 Sep 2021 14:42:33 +0000 X-Received: from EX13D49EUC003.ant.amazon.com (iad12-ws-svc-p26-lb9-vlan3.iad.amazon.com [10.40.163.38]) by email-inbound-relay-1e-42f764a0.us-east-1.amazon.com (Postfix) with ESMTPS id A7D5BC019D for ; Sat, 4 Sep 2021 14:42:32 +0000 (UTC) X-Received: from ub4014a598e6c52.ant.amazon.com (10.43.162.52) by EX13D49EUC003.ant.amazon.com (10.43.164.91) with Microsoft SMTP Server (TLS) id 15.0.1497.23; Sat, 4 Sep 2021 14:42:29 +0000 From: "Nicolas Ojeda Leon via groups.io" To: CC: Nicolas Ojeda Leon , Alexander Graf Subject: [edk2-devel] [PATCH 5/5] MdeModulePkg/PciBusDxe: Handling of pre-populated PCI BARs Date: Sat, 4 Sep 2021 16:37:56 +0200 Message-ID: In-Reply-To: References: MIME-Version: 1.0 X-Originating-IP: [10.43.162.52] X-ClientProxiedBy: EX13D16UWC001.ant.amazon.com (10.43.162.117) To EX13D49EUC003.ant.amazon.com (10.43.164.91) Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ncoleon@amazon.com X-Gm-Message-State: BTlvxY62HS93LIJd3WhMdT3Xx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1631027444; bh=KzQg80FZ6SAHnbjOFWit7PzTf0964NS3dFw9IE6q2Bg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=lmMvbzUsP2ld/U3sw6KKk9x+gwOt/bmwBHDiDdnwKNRmR/s8bAxweoaEUhmJWdvYAPh Ua8LVOXOpj9hA8ZSC6OaAKhiZJG+SURaEI+s7Zr7mmw4DRnYpJnoOrDw3tn8OOMybHSgA sLXXONE6bhBQudWare0MH9b92LveXF1gCQE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1631027445467100023 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the PCI BAR placement logic in order to consider pre-populated resources first, if indicated by the Pcd token PcdPciPreservePopulatedMappings. The PCI_BAR type is augmented by one field for mapping the absolute address of prepopulated BARs into a root bridge relative offset. As part of the CreateResourceMap stage of the PCI resource allocation process, all the resources belonging to a root bridge are analyzed and if a BaseAddress (absolute address read from the PCI device during enumeration) is present, it is translated into a root-bridge relative offset and the space occupied by it is marked as used in the root bridge's aperture. This process is performed before the regular placement logic is executed. The remaining unassigned BARs are then placed according to default logic starting after the last pre-populated resource. The motivation behind respecting pre-populated BARs is that the hypervisor can decide on placement of some resources and the guest must use the same values to benefit from performance optimizations or specific requirements. Signed-off-by: Nicolas Ojeda Leon Cc: Alexander Graf --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + .../Bus/Pci/PciBusDxe/PciResourceSupport.h | 20 ++ .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 11 + .../Bus/Pci/PciBusDxe/PciResourceSupport.c | 281 +++++++++++++++++- 5 files changed, 312 insertions(+), 2 deletions(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciBus.h index a619a68526..06e78ac40b 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -95,6 +95,7 @@ typedef enum { // struct _PCI_BAR { UINT64 BaseAddress; + UINT64 BaseAddressOffset; UINT64 Length; UINT64 Alignment; PCI_BAR_TYPE BarType; diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h index 9f2de291ba..5f4886d6ba 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.h @@ -111,6 +111,26 @@ CalculateApertureIo16 ( IN PCI_RESOURCE_NODE *Bridge ); =20 +/** + Populate a root bridge's resource aperture according to + initial conditions ruled by individual pre-populated + resources + + @note Pre-populated PIO BARs are not supported. + + @param Bridge PCI resource node for given bridge device. + @param Base Resource aperture base address + +**/ +VOID +PopulateResourceAperture ( + IN UINT64 Mem32Base, + IN UINT64 PMem32Base, + IN UINT64 Mem64Base, + IN UINT64 PMem64Base, + IN OUT PCI_IO_DEVICE *Bridge + ); + /** This function is used to calculate the resource aperture for a given bridge device. diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index db1b35f8ef..c76b37ab05 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -1789,6 +1789,7 @@ PciParseBar ( =20 PciIoDevice->PciBar[BarIndex].BarTypeFixed =3D FALSE; PciIoDevice->PciBar[BarIndex].Offset =3D (UINT8) Offset; + PciIoDevice->PciBar[BarIndex].BaseAddressOffset =3D 0; if ((Value & 0x01) !=3D 0) { // // Device I/Os diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c b/MdeModulePkg/Bus/Pci= /PciBusDxe/PciLib.c index 82147a4946..bf82d8fdaf 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c @@ -571,6 +571,17 @@ PciHostBridgeResourceAllocator ( &PMem64Base ); =20 + // + // Handle pre-populated resources + // + PopulateResourceAperture ( + Mem32Base, + PMem32Base, + Mem64Base, + PMem64Base, + RootBridgeDev + ); + // // Get the max ROM size that the root bridge can process // Insert to resource map so that there will be dedicate MEM32 resou= rce range for Option ROM. diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModul= ePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index 4969ee0f64..ad8db9a0ca 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -325,6 +325,270 @@ CalculateApertureIo16 ( Bridge->Length =3D MAX (Bridge->Length, PaddingAperture); } =20 +/** + Analyze a single BAR and if it is pre-populated (its baseAddress is alre= ady + set), calculate the offset inside the root bridge. + + @param Bar PCI BAR to be placed if pre-populated + @param Base Base address of the root bridge + +**/ +STATIC +VOID +PrePopulateBAR ( + IN OUT PCI_BAR *Bar, + IN UINT64 Base + ) +{ + if (Base =3D=3D gAllOne) { + return; + } + + // + // Pre-populated IO space BARs are not supported + // + if (Bar->BarType =3D=3D PciBarTypeIo16 || Bar->BarType =3D=3D PciBarType= Io32) { + return ; + } + + if (Bar->BaseAddress < Base) { + return ; + } + + if (Bar->BaseAddress !=3D 0) { + Bar->BaseAddressOffset =3D Bar->BaseAddress - Base; + } +} + + + +/** + Calculate and set the address offset inside the root bridge of device + BARs that are pre-populated. + + @param Dev PCI device whose BARs are to be analyzed + @param Base Base address of the root bridge under which the device + is located. + + */ +STATIC +VOID +PopulateDeviceBars ( + IN UINT64 Mem32Base, + IN UINT64 PMem32Base, + IN UINT64 Mem64Base, + IN UINT64 PMem64Base, + IN PCI_IO_DEVICE *Dev + ) +{ + UINTN Index; + + for (Index =3D 0; Index < PCI_MAX_BAR; Index++) + { + switch (Dev->PciBar[Index].BarType) { + case PciBarTypeMem32: + PrePopulateBAR(&Dev->PciBar[Index], Mem32Base); + break; + + case PciBarTypePMem32: + PrePopulateBAR(&Dev->PciBar[Index], PMem32Base); + break; + + case PciBarTypeMem64: + PrePopulateBAR(&Dev->PciBar[Index], Mem64Base); + break; + + case PciBarTypePMem64: + PrePopulateBAR(&Dev->PciBar[Index], PMem64Base); + break; + + default: + break; + } + } +} + +/** + Considering the Bridge attributes specifying the supported resources, + merge the base addresses to fake the non-suported types belonging to + the alternative type. + + @param Mem32Base 32-bit base address + @param PMem32Base 32-bit prefetchable base address + @param Mem64Base 64-bit base address + @param PMem64Base 64-bit prefetchable base address + @param Bridge PCI resource node for given bridge device. + + */ +STATIC +VOID +MergeBridgeResourceBases ( + IN OUT UINT64 *Mem32Base, + IN OUT UINT64 *PMem32Base, + IN OUT UINT64 *Mem64Base, + IN OUT UINT64 *PMem64Base, + IN PCI_IO_DEVICE *Bridge + ) +{ + // + // if root bridge supports combined Pmem Mem decoding + // merge these two type of resource + // + if (BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM_MEM_COMBINE_SUP= PORTED)) { + *PMem32Base =3D *Mem32Base; + *PMem64Base =3D *Mem64Base; + } + + // + // If bridge doesn't support Pmem32 + // degrade it to mem32 + // + if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM32_DECODE_SUPPO= RTED)) { + *PMem32Base =3D *Mem32Base; + } + + // + // If firmware is in 32-bit mode, + // then degrade PMEM64/MEM64 requests + // + if (sizeof (UINTN) <=3D 4) { + *Mem64Base =3D *Mem32Base ; + *PMem64Base =3D *PMem32Base; + } else { + // + // if the bridge does not support MEM64, degrade MEM64 to MEM32 + // + if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_MEM64_DECODE_SUPP= ORTED)) { + *Mem64Base =3D *Mem32Base; + } + + // + // if the bridge does not support PMEM64, degrade PMEM64 to PMEM32 + // + if (!BridgeSupportResourceDecode (Bridge, EFI_BRIDGE_PMEM64_DECODE_SUP= PORTED)) { + *PMem64Base =3D *PMem32Base; + } + } +} + +/** + Populate a root bridge's resource aperture according to + initial conditions ruled by individual pre-populated + resources + + @param Bridge PCI resource node for given bridge device. + @param Base Resource aperture base address + +**/ +VOID +PopulateResourceAperture ( + IN UINT64 Mem32Base, + IN UINT64 PMem32Base, + IN UINT64 Mem64Base, + IN UINT64 PMem64Base, + IN OUT PCI_IO_DEVICE *Bridge + ) +{ + PCI_IO_DEVICE *Temp; + LIST_ENTRY *CurrentLink; + + // + // Verify if pre-populated BARs need to be respected, otherwise + // there is no need to pre-populate any resource + // + if (! PcdGetBool(PcdPciPreservePopulatedMappings)) { + return; + } + + CurrentLink =3D Bridge->ChildList.ForwardLink; + + // + // Merge base addresses of the different types depending on resource + // decoding supported by the bridge + // + MergeBridgeResourceBases( + &Mem32Base, + &PMem32Base, + &Mem64Base, + &PMem64Base, + Bridge + ); + + while (CurrentLink !=3D NULL && CurrentLink !=3D &Bridge->ChildList) { + + Temp =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); + + PopulateDeviceBars( + Mem32Base, + PMem32Base, + Mem64Base, + PMem64Base, + Temp + ); + + // + // Recursive call to analyze the hierarchical tree under a bridge + // + if (IS_PCI_BRIDGE (&Temp->Pci)) { + PopulateResourceAperture ( + Mem32Base, + PMem32Base, + Mem64Base, + PMem64Base, + Temp + ); + } + + CurrentLink =3D CurrentLink->ForwardLink; + } +} + +/** + Calculate the current used resource of the bridge provided that some + of the resources under it might have been pre-populated. + + @param Bridge PCI resource node for given bridge device. + +**/ +STATIC +UINT64 +GetBridgePopulatedAperture ( + IN PCI_RESOURCE_NODE *Bridge + ) +{ + UINT64 Aperture; + UINT64 EndAddress; + LIST_ENTRY *CurrentLink; + PCI_RESOURCE_NODE *Node; + PCI_BAR *Bar; + + Aperture =3D 0; + + // + // Analyze all resource nodes looking for the prepopulated with the + // highest address used. + // + for ( CurrentLink =3D GetFirstNode (&Bridge->ChildList) + ; !IsNull (&Bridge->ChildList, CurrentLink) + ; CurrentLink =3D GetNextNode (&Bridge->ChildList, CurrentLink) + ) { + Node =3D RESOURCE_NODE_FROM_LINK (CurrentLink); + + Bar =3D &Node->PciDev->PciBar[Node->Bar]; + + if (Bar->BaseAddress !=3D 0) { + EndAddress =3D Bar->BaseAddressOffset + Bar->Length; + + if (EndAddress > Aperture) { + Aperture =3D EndAddress; + } + } + + } + + return Aperture; +} + /** This function is used to calculate the resource aperture for a given bridge device. @@ -338,6 +602,7 @@ CalculateResourceAperture ( ) { UINT64 Aperture[2]; + UINT64 InitialAperture; LIST_ENTRY *CurrentLink; PCI_RESOURCE_NODE *Node; =20 @@ -351,8 +616,14 @@ CalculateResourceAperture ( return ; } =20 - Aperture[PciResUsageTypical] =3D 0; - Aperture[PciResUsagePadding] =3D 0; + // + // Initialize apertures at bridge's current resource usage + // which might be occupied by pre-populated resources. + // + InitialAperture =3D GetBridgePopulatedAperture(Bridge); + Aperture[PciResUsageTypical] =3D InitialAperture; + Aperture[PciResUsagePadding] =3D InitialAperture; + // // Assume the bridge is aligned // @@ -362,6 +633,12 @@ CalculateResourceAperture ( ) { Node =3D RESOURCE_NODE_FROM_LINK (CurrentLink); =20 + PCI_BAR *Bar =3D &Node->PciDev->PciBar[Node->Bar]; + if (PcdGetBool(PcdPciPreservePopulatedMappings) && Bar->BaseAddress) { + Node->Offset =3D Bar->BaseAddressOffset; + continue; + } + // // It's possible for a bridge to contain multiple padding resource // nodes due to DegradeResource(). --=20 2.17.1 Amazon Development Center Germany GmbH Krausenstr. 38 10117 Berlin Geschaeftsfuehrung: Christian Schlaeger, Jonathan Weiss Eingetragen am Amtsgericht Charlottenburg unter HRB 149173 B Sitz: Berlin Ust-ID: DE 289 237 879 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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