From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79157+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79157+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769447; cv=none; d=zohomail.com; s=zohoarc; b=FnbhC3irQIg5XwuBLBVG5+Ko264mwweoo4G5/su72HSrriU/7iAVy7jeU/qMZWmkTAuadHAZnqiEadMJBoXs1saVmNuw3emE5GgDQ1Kq0Jzb5W6AkK5BKwYjAEtFs+sEFhwLjKVfsbhyUkPaqbqWOzVAdDPq0gefka5UR4nk5+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769447; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3Q7K9YJOCxk0+pXatDn8pJa5I2LelLFq0z/XoXs8Wvc=; b=Ye63cYWsOaU3RYoMXnHRXMk9CA3UW9+k29bFjZGCH/MejxiJaBl5iVmuqk1buCoq/alWiIcwUdmWXXzb1LgX6Ch+VFo1l+0WI7TOPYJViEW7r1SG4nc9B0U9J/C8K8teJSIEnk9iRJ5ghS66BGn0GkJ1ve3b8j3Tqt06GozgR7I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79157+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769447516750.8093150052543; Thu, 12 Aug 2021 04:57:27 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jEnTYY1788612xIu8tp5aGjz; Thu, 12 Aug 2021 04:57:27 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:26 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322100" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322100" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:25 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433543" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:23 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 01/23] OvmfPkg: Add Tdx BFV/CFV PCDs and PcdOvmfImageSizeInKb Date: Thu, 12 Aug 2021 19:56:40 +0800 Message-Id: <7afbf137d786b28c100965d4cfbb0aa8012c79d2.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 93jo3CQHZieDvaJvwNLDUHm5x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769447; bh=2tpvQKnSXNJnOHcAdITl0vQ2sLuDzj3wdSCmgicQS8o=; h=Cc:Date:From:Reply-To:Subject:To; b=U7NQa2bcXkCRPu2GzJ7ja5wkASLttN/JA/OKE7ijNRa7jlMQl5W87DMNROHjt/wmluf 1d4RWCxvRZF9N/Ft4I4AdhCgy20FNziYElADyoLfj0pNuD95j27znew26EGKxATQlEeqT qr/fCcxYDJZG1mxW1kbJ8sLANVlJ2Auo8vs= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769448134100003 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Tdx Virtual Firmware (TDVF) includes one Firmware Volume (FV) known as the Boot Firmware Volume (BFV). The FV format is defined in the UEFI Platform Initialization (PI) spec. BFV includes all TDVF components required during boot. TDVF also include a configuration firmware volume (CFV) that is separated from the BFV. The reason is because the CFV is measured in RTMR, while the BFV is measured in MRTD. In practice BFV is the code part of Ovmf image. CFV is the vars part of Ovmf image (exclude the SPARE part). PcdOvmfImageSizeInKb is added which is used to calculate the offset of TdxMetadata in ResetVectorVtf0.asm. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 13 +++++++++++++ OvmfPkg/OvmfPkgDefines.fdf.inc | 10 ++++++++++ 2 files changed, 23 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 8fb6f257e8e8..ccda130f0ef6 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -329,6 +329,19 @@ gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableBase|0x0|UINT32|0x47 gUefiOvmfPkgTokenSpaceGuid.PcdQemuHashTableSize|0x0|UINT32|0x48 =20 + ## The base address and size of the TDX Cfv base and size. + gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x49 + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x4a + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x4b + + ## The base address and size of the TDX Bfv base and size. + gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x4c + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x4d + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x4e + + ## Size of the Ovmf image in KB + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb|0|UINT32|0x4f + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgDefines.fdf.inc b/OvmfPkg/OvmfPkgDefines.fdf.inc index 35fd454b97ab..777b7755b198 100644 --- a/OvmfPkg/OvmfPkgDefines.fdf.inc +++ b/OvmfPkg/OvmfPkgDefines.fdf.inc @@ -9,6 +9,7 @@ ## =20 DEFINE BLOCK_SIZE =3D 0x1000 +DEFINE VARS_OFFSET =3D 0 =20 # # A firmware binary built with FD_SIZE_IN_KB=3D1024, and a firmware binary= built @@ -66,6 +67,7 @@ DEFINE SECFV_OFFSET =3D 0x003CC000 DEFINE SECFV_SIZE =3D 0x34000 !endif =20 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb =3D $(FD_SIZE_IN_K= B) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress =3D $(FW_BASE_ADDR= ESS) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize =3D $(FW_SIZE) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize =3D $(BLOCK_SIZE) @@ -82,6 +84,14 @@ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwW= orkingSize =3D $(BLOCK_SIZ SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase =3D gUefi= OvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase + gEfiMdeModulePk= gTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D $(VAR= S_SPARE_SIZE) =20 +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase =3D $(FW_BASE_ADDRESS) +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset =3D $(VARS_OFFSET) +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize =3D $(VARS_LIVE_SIZE) + +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase =3D $(CODE_BASE_ADDRES= S) +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset =3D $(VARS_SIZE) +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize =3D $(CODE_SIZE) + !if $(SMM_REQUIRE) =3D=3D TRUE SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 =3D gUe= fiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D gUe= fiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79157): https://edk2.groups.io/g/devel/message/79157 Mute This Topic: https://groups.io/mt/84837889/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79158+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79158+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769449; cv=none; d=zohomail.com; s=zohoarc; b=FlKwkqu9wTvX/nCEpH65ZCCFE+vde4RTJYSfBrrr2Y+jb8iXiNSCixJKPVTIf727p38+3NrYY1/Fv+rKG1SE/DIuCUrY70h9XuiDEPucclDq9aJlOkIVl7qWQI/aB6l/NP8dE7G74SQZHAo5WBsSGWUNH6v2hMar8Z7aOusWOSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769449; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=oTYjWbi+WBvyH+aSojTTlW537PQCCAsPGjJqFCoLPpI=; b=dGGZ9wd2CmRA7pO7cWJhRs8uMRwp0uzcZA4/L7n1OOoiLNJ3XBQ5dye2cM1w05VQ86a5UWiRsa70BnQfrdWYFDvtck58HKNJd5GRphXj5bCSct/KURpz1wa8ZbSXvKl6kHHuT6XQokansg9idYFtxxXEgy+P7ke+F5/yM/1kpos= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79158+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769449956730.2646558471235; Thu, 12 Aug 2021 04:57:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ef4ZYY1788612xILo8ei1tgt; Thu, 12 Aug 2021 04:57:29 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:28 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322119" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322119" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:28 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433555" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:26 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 02/23] OvmfPkg/Sec: Update the check logic in SevEsIsEnabled Date: Thu, 12 Aug 2021 19:56:41 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: F56rOCHXUcVzcGCy1rgqebdax1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769449; bh=rs/4zS5DhS3SHxkKBTK7d+Dk5pLukUZDpFDBPpK7QLM=; h=Cc:Date:From:Reply-To:Subject:To; b=Dr5IjEbTUaFElkwslDML1NDHkUyjnc/ARPQirqcaSuuJGlg9Eyhgnt2WQbfOeT83HSs zYS0AaV1gKREUUVCqAnv7mfpO1lbw1vj8BKKlx+Li4mnZCTU/M5i1wBRFQlDTAPBNoce4 JAmfGcsTfMjF+RVaJ1l57pnsuVnSUj1H0DA= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769450444100008 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 SevEsIsEnabled return TRUE if SevEsWorkArea->SevEsEnabled is non-zero. It is correct when SevEsWorkArea is only used by SEV. After Intel TDX is enabled in Ovmf, the SevEsWorkArea is shared by TDX and SEV. (This is to avoid the waist of memory region in MEMFD). The value of SevEsWorkArea->SevEsEnabled now is : 0 if in Legacy guest 1 if in SEV 2 if in Tdx guest That's why the changes is made. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Sec/SecMain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index 9db67e17b2aa..e166a9389a1a 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -828,7 +828,7 @@ SevEsIsEnabled ( =20 SevEsWorkArea =3D (SEC_SEV_ES_WORK_AREA *) FixedPcdGet32 (PcdSevEsWorkAr= eaBase); =20 - return ((SevEsWorkArea !=3D NULL) && (SevEsWorkArea->SevEsEnabled !=3D 0= )); + return ((SevEsWorkArea !=3D NULL) && (SevEsWorkArea->SevEsEnabled =3D=3D= 1)); } =20 VOID --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79158): https://edk2.groups.io/g/devel/message/79158 Mute This Topic: https://groups.io/mt/84837890/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79159+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79159+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769452; cv=none; d=zohomail.com; s=zohoarc; b=DGt/fu1PYZwnqwBbB1w0FtAvoC5kEY2L8CYCFO1/UAN1hIaCt4PJDgehqm/+GLasSxHREII6G9Gc0RbMTOnrk0z5qjIN+31hblyVfvrK8mHhlMFiV0//6LqYTt/BionIfPVG0TtCcy6nO6QyG++r9CW1oN9AFEX8QvXNpbEiDr8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769452; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=alfsyKt8PceF8RQwt+3xmXJFuugTvkKmgclU1DgWQHk=; b=StMxRYd37XJM0zFAnekbHWLs5Czx9ELiDHbTiN610wD0Ow+HkTkFdEskMTjFaCflIYJjF6cywDMR58O+gOUMKNSDeDuipYCeiDm7jqcLe4sgHfCQm98WnjfSXKN+ojB0NaXCz6EDVVTp8qm4Klxwe//d210G0F/WLR3ZEUqkcA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79159+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769452514715.6836625375632; Thu, 12 Aug 2021 04:57:32 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BNV6YY1788612xUmuLm8I6zk; Thu, 12 Aug 2021 04:57:32 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:31 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322134" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322134" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:31 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433586" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:28 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 03/23] OvmfPkg/ResetVector: Enable Intel TDX in ResetVector of Ovmf Date: Thu, 12 Aug 2021 19:56:42 +0800 Message-Id: <31e974a9ef1ef191a1f76e81fa91047d12ee2169.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: hKwR0H36Tk6TixzcLeSj3HiJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769452; bh=8sstQDErykYxu8O3SLgt+/JuQQp2YzU9DbE/wcR1+6I=; h=Cc:Date:From:Reply-To:Subject:To; b=ElFU+oWXa8R5cSCBZ8B41Vo3k3gj3vxoT5IDlInzUpih6N3eU5zMe+BOGaLsduXutzZ EMkGcLmdGRnVjOkfbLi9Oq+Gxb664CP+u3cOIZ9XMYqqOORXDPE6LswuHo5e+IrALiG2K CBofae8fKDLtXuwT2wMhFEML4BLGUzPyf2s= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769454443100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Intel's Trust Domain Extensions (Intel TDX) refers to an Intel technology that extends Virtual Machines Extensions (VMX) and Multi-Key Total Memory Encryption (MKTME) with a new kind of virutal machines guest called a Trust Domain (TD). A TD is desinged to run in a CPU mode that protects the confidentiality of TD memory contents and the TD's CPU state from other software, including the hosting Virtual-Machine Monitor (VMM), unless explicitly shared by the TD itself. Note: Intel TDX only is available on X64, so the Tdx related changes are in X64 path. In IA32 path, there may be null stub to make the build success. This patch includes below major changes. 1. CC_WORK_AREA Ovmf is able to run on different types of VM guest with ONE image. These VM guest includes the Legacy guest, SEV guest and TDX guest. In ResetVector CC_WORK_AREA is such a memory region to record the VM guest information. Below is the definition of the work area. typedef struct { UINT8 Type; // 0 legacy, 1 SEV, 2 TDX UINT8 SubType; // Depends on Type UINT8 Rsvd[2]; // Reserved union VM_GUEST { TDX_WORK_AREA Tdx; SEV_WORK_AREA Sev; } Guest; } CC_WORK_AREA_HEAD; typedef struct { ... ... } TDX_WORK_AREA typedef struct { ... ... } SEV_WORK_AREA 2. X64/IntelTdxMetadata.asm IntelTdxMetadata describes the information about the image for VMM use. For example, the base address and length of the TdHob, TdMailbox, etc. Its offset is put in a GUID-ed structure which is appended in the GUID-ed chain from a fixed GPA (0xffffffd0). Below are the items in TdxMetadata: _Bfv: Boot Firmware Volume _Cfv: Configuration Firmware Volume _Stack: Initial stack _Heap: Initial heap _MailBox: TDVF reserves the memory region so each AP can receive the message sent by the guest OS. _CcWorkarea: Compute Confidential work area which is consumed by CC technologies, such as SEV, TDX. _TdHob: VMM pass the resource information in TdHob to TDVF. _TdxPageTable: If 5-level page table is supported (GPAW is 52), a top level page directory pointers (1 * 256TB entry) is generated in this page. _OvmfPageTable: Initial page table for standard Ovmf. TDVF indicate above chunk of temporary initialized memory region (_Stack/ _Heap/_MailBox/_CcWorkarea/_TdHob/_TdxPageTables/OvmfPageTable) to support TDVF code finishing the memory initialization. Because the other unaccepted memory cannot be accessed until they're accepted. Since AMD SEV has already defined some SEV specific memory region in MEMFD. TDX re-use the memory regions defined by SEV. - MailBox : PcdOvmfSecGhcbBackupBase|PcdOvmfSecGhcbBackupSize - TdHob : PcdOvmfSecGhcbBase|PcdOvmfSecGhcbSize - TdxPageTable : PcdOvmfSecGhcbPageTableBase|PcdOvmfSecGhcbPageTableSize - CcWorkArea : PcdSevEsWorkAreaBase|PcdSevEsWorkAreaSize 3. Ia32/IntelTdx.asm IntelTdx.asm includes below routines used in ResetVector - IsTdx Check if the running system is Tdx guest. - InitTdxWorkarea It initialize the CC_WORK_AREA. Because it is called by both BSP and APs and to avoid the race condition, only BSP can initialize the WORK_AREA. AP will wait until the field of TDX_WORK_AREA_PGTBL_READY is set. - ReloadFlat32 After reset all CPUs in TDX are initialized to 32-bit protected mode. But GDT register is not set. So this routine loads the GDT and set the CR0, then jump to Flat 32 protected mode. After that CR4 and other registers are set. - InitTdx This routine wrap above 3 routines together to do Tdx initialization in ResetVector phase. - PostSetCr3PageTables64Tdx It is called after SetCr3PageTables64 in Tdx guest to set CR0/CR4. If GPAW is 52, then CR3 is adjusted as well. - IsTdxEnabled It is a OneTimeCall to probe if TDX is enabled by checking the CC_WORK_AREA. 4. Ia32/AmdSev.asm AmdSev.asm includes the SEV routines used in ResetVector. This patch remove the code of clearing SEV_ES_WORK_AREA in CheckSevFeatures. The clearing of SEV_ES_WORK_AREA is called at Main16 in Main.asm. 5. Main.asm Previously OvmfPkg/ResetVector use the Main.asm in UefiCpuPkg. There is only Main16 entry point. Main32 entry point is needed in Main.asm because of Intel TDX. To reduce the complexity of Main.asm in UefiCpuPkg, OvmfPkg create its own Main.asm to meet the requirement of Intel TDX. There are below changes in this Main.asm: - A new entry point (Main32) is added. TDX guest will jump to Main32 from ResetVecotr. - In Main16 entry point, after TransitionFromReal16To32BitFlat, CC_WORK_AREA is cleared to 0. 6. Ia32/PageTables64.asm GPAW of TDX can be 48 or 52, which determines the level of page table. If Level-5(GPAW 52) paging is supported, then an extra page is needed to hold the top level Page Directory Pointers (1 * 256TB entry). 7. Ia16/ResetVectorVtf0.asm In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). But in Non-Td guest the initial state of CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used in the ResetVectorVtf0.asm. It checks the 32-bit protected mode or 16-bit real mode, then jump to the corresponding entry point. 8. ResetVector.nasmb TDX related macros and files are added in ResetVecotr.nasmb. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 39 +++ OvmfPkg/ResetVector/Ia32/AmdSev.asm | 7 - OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm | 9 + OvmfPkg/ResetVector/Ia32/IntelTdx.asm | 265 +++++++++++++++++++ OvmfPkg/ResetVector/Ia32/PageTables64.asm | 113 +++++--- OvmfPkg/ResetVector/Main.asm | 121 +++++++++ OvmfPkg/ResetVector/ResetVector.inf | 12 +- OvmfPkg/ResetVector/ResetVector.nasmb | 48 +++- OvmfPkg/ResetVector/X64/IntelTdxMetadata.asm | 110 ++++++++ 9 files changed, 679 insertions(+), 45 deletions(-) create mode 100644 OvmfPkg/ResetVector/Ia32/IntelTdx.asm create mode 100644 OvmfPkg/ResetVector/Main.asm create mode 100644 OvmfPkg/ResetVector/X64/IntelTdxMetadata.asm diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVe= ctor/Ia16/ResetVectorVtf0.asm index 7ec3c6e980c3..62feeacbee7b 100644 --- a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm +++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm @@ -47,6 +47,24 @@ TIMES (15 - ((guidedStructureEnd - guidedStructureStart = + 15) % 16)) DB 0 ; guidedStructureStart: =20 +%ifdef ARCH_X64 +; +; TDX Metadata offset block +; +; If TdxMetadata.asm is included then we need below block which describes +; the offset of TdxMetadata block in Ovmf image +; +; GUID : e47a6535-984a-4798-865e-4685a7bf8ec2 +; +tdxMetadataOffsetStart: + DD (OVMF_IMAGE_SIZE_IN_KB * 1024 - (fourGigabytes - TdxMetadataGu= id - 16)) + DD tdxMetadataOffsetEnd - tdxMetadataOffsetStart + DB 0x35, 0x65, 0x7a, 0xe4, 0x4a, 0x98, 0x98, 0x47 + DB 0x86, 0x5e, 0x46, 0x85, 0xa7, 0xbf, 0x8e, 0xc2 +tdxMetadataOffsetEnd: + +%endif + ; SEV Hash Table Block ; ; This describes the guest ram area where the hypervisor should @@ -158,10 +176,31 @@ resetVector: ; ; This is where the processor will begin execution ; +; In IA32 we follow the standard reset vector flow. While in X64, Td guest +; may be supported. Td guest requires the startup mode to be 32-bit +; protected mode but the legacy VM startup mode is 16-bit real mode. +; To make NASM generate such shared entry code that behaves correctly in +; both 16-bit and 32-bit mode, more BITS directives are added. +; +%ifdef ARCH_IA32 + nop nop jmp EarlyBspInitReal16 =20 +%else + + smsw ax + test al, 1 + jz .Real +BITS 32 + jmp Main32 +BITS 16 +.Real: + jmp EarlyBspInitReal16 + +%endif + ALIGN 16 =20 fourGigabytes: diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32= /AmdSev.asm index aa95d06eaddb..d0d9890d5c4b 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -128,13 +128,6 @@ SevEsUnexpectedRespTerminate: ; If SEV is disabled then EAX will be zero. ; CheckSevFeatures: - ; Set the first byte of the workarea to zero to communicate to the SEC - ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID - ; instruction will trigger a #VC exception where the first byte of the - ; workarea will be set to one or, if CPUID is not being intercepted, - ; the MSR check below will set the first byte of the workarea to one. - mov byte[SEV_ES_WORK_AREA], 0 - ; ; Set up exception handlers to check for SEV-ES ; Load temporary RAM stack based on PCDs (see SevEsIdtVmmComm for diff --git a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm b/OvmfPkg/ResetVec= tor/Ia32/Flat32ToFlat64.asm index c6d0d898bcd1..ea8723efd417 100644 --- a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm +++ b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm @@ -17,6 +17,14 @@ Transition32FlatTo64Flat: =20 OneTimeCall SetCr3ForPageTables64 =20 + OneTimeCall PostSetCr3PageTables64Tdx + + ; + ; If it is TDX, we're done and jump to enable paging + ; + cmp byte[CC_WORK_AREA], VM_GUEST_TDX + je EnablePaging + mov eax, cr4 bts eax, 5 ; enable PAE mov cr4, eax @@ -71,6 +79,7 @@ jumpTo64BitAndLandHere: =20 ; ; Check if the second step of the SEV-ES mitigation is to be performed. + ; If it is Tdx, ebx is cleared in PostSetCr3PageTables64Tdx. ; test ebx, ebx jz InsnCompare diff --git a/OvmfPkg/ResetVector/Ia32/IntelTdx.asm b/OvmfPkg/ResetVector/Ia= 32/IntelTdx.asm new file mode 100644 index 000000000000..f40331a5cbce --- /dev/null +++ b/OvmfPkg/ResetVector/Ia32/IntelTdx.asm @@ -0,0 +1,265 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Intel TDX routines +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%define SEC_DEFAULT_CR0 0x00000023 +%define SEC_DEFAULT_CR4 0x640 + +%define VM_GUEST_TDX 2 + +BITS 32 + +; +; Check if it is Intel Tdx +; +; Modified: EAX, EBX, ECX, EDX +; +; If it is Intel Tdx, EAX is zero +; If it is not Intel Tdx, EAX is non-zero +; +IsTdx: + ; + ; CPUID (0) + ; + mov eax, 0 + cpuid + cmp ebx, 0x756e6547 ; "Genu" + jne IsNotTdx + cmp edx, 0x49656e69 ; "ineI" + jne IsNotTdx + cmp ecx, 0x6c65746e ; "ntel" + jne IsNotTdx + + ; + ; CPUID (1) + ; + mov eax, 1 + cpuid + test ecx, 0x80000000 + jz IsNotTdx + + ; + ; CPUID[0].EAX >=3D 0x21? + ; + mov eax, 0 + cpuid + cmp eax, 0x21 + jl IsNotTdx + + ; + ; CPUID (0x21,0) + ; + mov eax, 0x21 + mov ecx, 0 + cpuid + + cmp ebx, 0x65746E49 ; "Inte" + jne IsNotTdx + cmp edx, 0x5844546C ; "lTDX" + jne IsNotTdx + cmp ecx, 0x20202020 ; " " + jne IsNotTdx + + mov eax, 0 + jmp ExitIsTdx + +IsNotTdx: + mov eax, 1 + +ExitIsTdx: + + OneTimeCallRet IsTdx + +; +; Initialize Tdx work area (CC_WORK_AREA) if it is Tdx guest. +; BSP and APs all go here. Only BSP can initialize the WORK_AREA +; +; typedef struct { +; UINT8 Type; // 0 legacy, 1 SEV, 2 TDX +; UINT8 SubType; // Depends on Type +; UINT8 Rsvd[2]; // Reserved +; union VM_GUEST { +; TDX_WORK_AREA Tdx; +; SEV_WORK_AREA Sev; +; } Guest; +; } CC_WORK_AREA_HEAD; +; +; typedef struct { +; UINT8 IsPageLevel5; +; UINT8 IsPageTableReady; +; UINT8 Rsvd[2]; +; UINT32 Gpaw; +; } TDX_WORK_AREA +; +; Param[in] EBP[6:0] CPU Supported GPAW (48 or 52) +; Param[in] ESI[31:0] vCPU ID (BSP is 0, others are AP) +; +; Modified: EBP +; +InitTdxWorkarea: + + ; + ; First check if it is Tdx + ; + OneTimeCall IsTdx + + test eax, eax + jnz ExitInitTdxWorkarea + + ; + ; In Td guest, BSP/AP shares the same entry point + ; BSP builds up the page table, while APs shouldn't do the same task. + ; Instead, APs just leverage the page table which is built by BSP. + ; APs will wait until the page table is ready. + ; + cmp esi, 0 + je TdxBspEntry + +TdxApWait: + cmp byte[TDX_WORK_AREA_PGTBL_READY], 0 + je TdxApWait + jmp ExitInitTdxWorkarea + +TdxBspEntry: + ; + ; Set Type and SubType of CC_WORK_AREA so that the + ; following code can use these information. + ; + mov byte[CC_WORK_AREA], VM_GUEST_TDX + mov byte[CC_WORK_AREA_SUBTYPE], 0 + + ; + ; EBP[6:0] CPU supported GPA width + ; + and ebp, 0x3f + cmp ebp, 52 + jl NotPageLevel5 + mov byte[TDX_WORK_AREA_PAGELEVEL5], 1 + +NotPageLevel5: + mov DWORD[TDX_WORK_AREA_GPAW], ebp + +ExitInitTdxWorkarea: + OneTimeCallRet InitTdxWorkarea + +; +; Load the GDT and set the CR0, then jump to Flat 32 protected mode. +; +; Modified: EAX, EBX, CR0, CR4, DS, ES, FS, GS, SS +; +ReloadFlat32: + + cli + mov ebx, ADDR_OF(gdtr) + lgdt [ebx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpToFlat32BitAndLandHere) + +jumpToFlat32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + OneTimeCallRet ReloadFlat32 + +; +; Tdx initialization after entering into ResetVector +; +; Modified: EAX, EBX, ECX, EDX, EBP, EDI, ESP +; +InitTdx: + ; + ; Save EBX in EBP because EBX will be changed in ReloadFlat32 + ; + mov ebp, ebx + + ; + ; First load the GDT and jump to Flat32 mode + ; + OneTimeCall ReloadFlat32 + + ; + ; Initialization of Tdx work area + ; + OneTimeCall InitTdxWorkarea + + OneTimeCallRet InitTdx + +; +; Called after SetCr3PageTables64 in Tdx guest to set CR0/CR4. +; If GPAW is 52, then CR3 is adjusted as well. +; +; Modified: EAX, EBX, CR0, CR3, CR4 +; +PostSetCr3PageTables64Tdx: + ; + ; TDX_WORK_AREA was set in InitTdx if it is Tdx guest + ; + cmp byte[CC_WORK_AREA], VM_GUEST_TDX + jne ExitPostSetCr3PageTables64Tdx + + mov eax, cr4 + bts eax, 5 ; enable PAE + + ; + ; byte[TDX_WORK_AREA_PAGELEVEL5] holds the indicator whether 52bit is + ; supported. if it is the case, need to set LA57 and use 5-level paging + ; + cmp byte[TDX_WORK_AREA_PAGELEVEL5], 0 + jz TdxSetCr4 + bts eax, 12 + +TdxSetCr4: + mov cr4, eax + mov ebx, cr3 + + ; + ; if la57 is not set, we are ok + ; if using 5-level paging, adjust top-level page directory + ; + bt eax, 12 + jnc TdxSetCr3 + mov ebx, TDX_PT_ADDR (0) + +TdxSetCr3: + mov cr3, ebx + + xor ebx, ebx + +ExitPostSetCr3PageTables64Tdx: + OneTimeCallRet PostSetCr3PageTables64Tdx + +; +; Check if TDX is enabled +; +; Modified: EAX +; +; If TDX is enabled then EAX will be 1 +; If TDX is disabled then EAX will be 0. +; +IsTdxEnabled: + xor eax, eax + cmp byte[CC_WORK_AREA], VM_GUEST_TDX + jne NotTdx + mov eax, 1 + +NotTdx: + OneTimeCallRet IsTdxEnabled + diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index eacdb69ddb9f..1f4c0c50ac2e 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -37,11 +37,81 @@ BITS 32 PAGE_READ_WRITE + \ PAGE_PRESENT) =20 +TdxBuildExtraPageTables: + ; + ; Extra page tables built by Tdx guests + ; + xor eax, eax + mov ecx, 0x400 +tdClearTdxPageTablesMemoryLoop: + mov dword [ecx * 4 + TDX_PT_ADDR(0) - 4], eax + loop tdClearTdxPageTablesMemoryLoop + + ; + ; Top level Page Directory Pointers (1 * 256TB entry) + ; + mov dword[TDX_PT_ADDR (0)], PT_ADDR(0) + PAGE_PDP_ATTR + + ; + ; Set TDX_WORK_AREA_PGTBL_READY to notify APs to go + ; + mov byte[TDX_WORK_AREA_PGTBL_READY], 1 + + OneTimeCallRet TdxBuildExtraPageTables + +SevBuildGhcbPageTables: + ; + ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted. + ; This requires the 2MB page for this range be broken down into 512 4KB + ; pages. All will be marked encrypted, except for the GHCB. + ; + mov ecx, (GHCB_BASE >> 21) + mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR + mov [ecx * 8 + PT_ADDR (0x2000)], eax + + ; + ; Page Table Entries (512 * 4KB entries =3D> 2MB) + ; + mov ecx, 512 +pageTableEntries4kLoop: + mov eax, ecx + dec eax + shl eax, 12 + add eax, GHCB_BASE & 0xFFE0_0000 + add eax, PAGE_4K_PDE_ATTR + mov [ecx * 8 + GHCB_PT_ADDR - 8], eax + mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx + loop pageTableEntries4kLoop + + ; + ; Clear the encryption bit from the GHCB entry + ; + mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12 + mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0 + + mov ecx, GHCB_SIZE / 4 + xor eax, eax +clearGhcbMemoryLoop: + mov dword[ecx * 4 + GHCB_BASE - 4], eax + loop clearGhcbMemoryLoop + + OneTimeCallRet SevBuildGhcbPageTables + ; ; Modified: EAX, EBX, ECX, EDX ; SetCr3ForPageTables64: =20 + cmp byte[CC_WORK_AREA], VM_GUEST_TDX + jne CheckSev + + cmp byte[TDX_WORK_AREA_PGTBL_READY], 1 + je SetCr3 + + xor edx, edx + jmp SevNotActive + +CheckSev: OneTimeCall CheckSevFeatures xor edx, edx test eax, eax @@ -101,44 +171,19 @@ pageTableEntriesLoop: mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop =20 + OneTimeCall IsTdxEnabled + test eax, eax + jz IsSevEs + + OneTimeCall TdxBuildExtraPageTables + jmp SetCr3 + +IsSevEs: OneTimeCall IsSevEsEnabled test eax, eax jz SetCr3 =20 - ; - ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted. - ; This requires the 2MB page for this range be broken down into 512 4KB - ; pages. All will be marked encrypted, except for the GHCB. - ; - mov ecx, (GHCB_BASE >> 21) - mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR - mov [ecx * 8 + PT_ADDR (0x2000)], eax - - ; - ; Page Table Entries (512 * 4KB entries =3D> 2MB) - ; - mov ecx, 512 -pageTableEntries4kLoop: - mov eax, ecx - dec eax - shl eax, 12 - add eax, GHCB_BASE & 0xFFE0_0000 - add eax, PAGE_4K_PDE_ATTR - mov [ecx * 8 + GHCB_PT_ADDR - 8], eax - mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx - loop pageTableEntries4kLoop - - ; - ; Clear the encryption bit from the GHCB entry - ; - mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12 - mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0 - - mov ecx, GHCB_SIZE / 4 - xor eax, eax -clearGhcbMemoryLoop: - mov dword[ecx * 4 + GHCB_BASE - 4], eax - loop clearGhcbMemoryLoop + OneTimeCall SevBuildGhcbPageTables =20 SetCr3: ; diff --git a/OvmfPkg/ResetVector/Main.asm b/OvmfPkg/ResetVector/Main.asm new file mode 100644 index 000000000000..fb1731728af5 --- /dev/null +++ b/OvmfPkg/ResetVector/Main.asm @@ -0,0 +1,121 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Main routine of the pre-SEC code up through the jump into SEC +; +; Copyright (c) 2008 - 2009, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + + +BITS 16 + +; +; Modified: EBX, ECX, EDX, EBP +; +; @param[in,out] RAX/EAX Initial value of the EAX register +; (BIST: Built-in Self Test) +; @param[in,out] DI 'BP': boot-strap processor, or +; 'AP': application processor +; @param[out] RBP/EBP Address of Boot Firmware Volume (BFV) +; @param[out] DS Selector allowing flat access to all addresses +; @param[out] ES Selector allowing flat access to all addresses +; @param[out] FS Selector allowing flat access to all addresses +; @param[out] GS Selector allowing flat access to all addresses +; @param[out] SS Selector allowing flat access to all addresses +; +; @return None This routine jumps to SEC and does not return +; +Main16: + OneTimeCall EarlyInit16 + + ; + ; Transition the processor from 16-bit real mode to 32-bit flat mode + ; + OneTimeCall TransitionFromReal16To32BitFlat + +BITS 32 +%ifdef ARCH_X64 + ; + ; Clear the first 2 bytes of CC_WORK_AREA. + ; + mov word[CC_WORK_AREA], 0 + + jmp SearchBfv + +; +; Entry point of Main32 +; +Main32: + OneTimeCall InitTdx + +SearchBfv: + +%endif + ; + ; Search for the Boot Firmware Volume (BFV) + ; + OneTimeCall Flat32SearchForBfvBase + + ; + ; EBP - Start of BFV + ; + + ; + ; Search for the SEC entry point + ; + OneTimeCall Flat32SearchForSecEntryPoint + + ; + ; ESI - SEC Core entry point + ; EBP - Start of BFV + ; + +%ifdef ARCH_IA32 + + ; + ; Restore initial EAX value into the EAX register + ; + mov eax, esp + + ; + ; Jump to the 32-bit SEC entry point + ; + jmp esi + +%else + + ; + ; Transition the processor from 32-bit flat mode to 64-bit flat mode + ; + OneTimeCall Transition32FlatTo64Flat + +BITS 64 + + ; + ; Some values were calculated in 32-bit mode. Make sure the upper + ; 32-bits of 64-bit registers are zero for these values. + ; + mov rax, 0x00000000ffffffff + and rsi, rax + and rbp, rax + and rsp, rax + + ; + ; RSI - SEC Core entry point + ; RBP - Start of BFV + ; + + ; + ; Restore initial EAX value into the RAX register + ; + mov rax, rsp + + ; + ; Jump to the 64-bit SEC entry point + ; + jmp rsi + +%endif + + diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index d028c92d8cfa..0cf3a8036b97 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -1,7 +1,7 @@ ## @file # Reset Vector # -# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -35,6 +35,7 @@ =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase @@ -43,6 +44,15 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb + gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize + gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize =20 [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index acec46a32450..528a6603a20e 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -67,6 +67,44 @@ %error "This implementation inherently depends on PcdOvmfSecGhcbBase n= ot straddling a 2MB boundary" %endif =20 + %define TDX_BFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdBfvRawDataOffset) + %define TDX_BFV_RAW_DATA_SIZE FixedPcdGet32 (PcdBfvRawDataSize) + %define TDX_BFV_MEMORY_BASE FixedPcdGet32 (PcdBfvBase) + %define TDX_BFV_MEMORY_SIZE FixedPcdGet32 (PcdBfvRawDataSize) + + %define TDX_CFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdCfvRawDataOffset) + %define TDX_CFV_RAW_DATA_SIZE FixedPcdGet32 (PcdCfvRawDataSize) + %define TDX_CFV_MEMORY_BASE FixedPcdGet32 (PcdCfvBase), + %define TDX_CFV_MEMORY_SIZE FixedPcdGet32 (PcdCfvRawDataSize), + + %define TDX_HEAP_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecPeiTempRamBas= e) + %define TDX_HEAP_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSiz= e) / 2 + + %define TDX_STACK_MEMORY_BASE (TDX_HEAP_MEMORY_BASE + TDX_HEAP_MEMOR= Y_SIZE) + %define TDX_STACK_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSiz= e) / 2 + + %define TDX_HOB_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBase) + %define TDX_HOB_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbSize) + + %define TDX_MAILBOX_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBackupBas= e) + %define TDX_MAILBOX_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbBackupSiz= e) + + %define OVMF_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecPageTablesBas= e) + %define OVMF_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecPageTablesSiz= e) + + %define TDX_EXTRA_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Base) + %define TDX_EXTRA_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Size) + + %define CC_WORK_AREA_MEMORY_BASE FixedPcdGet32 (PcdSevEsWorkAreaBase) + %define CC_WORK_AREA_MEMORY_SIZE FixedPcdGet32 (PcdSevEsWorkAreaSize) + %define CC_WORK_AREA (CC_WORK_AREA_MEMORY_BASE) + %define CC_WORK_AREA_SUBTYPE (CC_WORK_AREA + 1) + %define TDX_WORK_AREA_PAGELEVEL5 (CC_WORK_AREA + 4) + %define TDX_WORK_AREA_PGTBL_READY (CC_WORK_AREA + 5) + %define TDX_WORK_AREA_GPAW (CC_WORK_AREA + 8) + + %define TDX_PT_ADDR(Offset) (TDX_EXTRA_PAGE_TABLE_BASE + (Offset)) + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) =20 %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) @@ -76,9 +114,12 @@ %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + = 8) %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) = + 16) %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) -%include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/AmdSev.asm" -%include "Ia32/PageTables64.asm" + + %include "X64/IntelTdxMetadata.asm" + %include "Ia32/IntelTdx.asm" + %include "Ia32/Flat32ToFlat64.asm" + %include "Ia32/AmdSev.asm" + %include "Ia32/PageTables64.asm" %endif =20 %include "Ia16/Real16ToFlat32.asm" @@ -91,5 +132,6 @@ %define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize) %define SEV_FW_HASH_BLOCK_BASE FixedPcdGet32 (PcdQemuHashTableBase) %define SEV_FW_HASH_BLOCK_SIZE FixedPcdGet32 (PcdQemuHashTableSize) + %define OVMF_IMAGE_SIZE_IN_KB FixedPcdGet32 (PcdOvmfImageSizeInKb) %include "Ia16/ResetVectorVtf0.asm" =20 diff --git a/OvmfPkg/ResetVector/X64/IntelTdxMetadata.asm b/OvmfPkg/ResetVe= ctor/X64/IntelTdxMetadata.asm new file mode 100644 index 000000000000..97b1e915d899 --- /dev/null +++ b/OvmfPkg/ResetVector/X64/IntelTdxMetadata.asm @@ -0,0 +1,110 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Tdx Virtual Firmware metadata +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 64 + +%define TDX_METADATA_SECTION_TYPE_BFV 0 +%define TDX_METADATA_SECTION_TYPE_CFV 1 +%define TDX_METADATA_SECTION_TYPE_TD_HOB 2 +%define TDX_METADATA_SECTION_TYPE_TEMP_MEM 3 +%define TDX_METADATA_VERSION 1 +%define TDX_METADATA_ATTRIBUTES_EXTENDMR 0x00000001 + +ALIGN 16 +TIMES (15 - ((TdxGuidedStructureEnd - TdxGuidedStructureStart + 15) % 16))= DB 0 + +TdxGuidedStructureStart: + +; +; TDVF meta data +; +TdxMetadataGuid: + DB 0xf3, 0xf9, 0xea, 0xe9, 0x8e, 0x16, 0xd5, 0x44 + DB 0xa8, 0xeb, 0x7f, 0x4d, 0x87, 0x38, 0xf6, 0xae + +_Descriptor: + DB 'T','D','V','F' ; Signature + DD TdxGuidedStructureEnd - _Descriptor ; Length + DD TDX_METADATA_VERSION ; Version + DD (TdxGuidedStructureEnd - _Descriptor - 16)/32 ; Number of sections + +_Bfv: + DD TDX_BFV_RAW_DATA_OFFSET + DD TDX_BFV_RAW_DATA_SIZE + DQ TDX_BFV_MEMORY_BASE + DQ TDX_BFV_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_BFV + DD TDX_METADATA_ATTRIBUTES_EXTENDMR + +_Cfv: + DD TDX_CFV_RAW_DATA_OFFSET + DD TDX_CFV_RAW_DATA_SIZE + DQ TDX_CFV_MEMORY_BASE + DQ TDX_CFV_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_CFV + DD 0 + +_Stack: + DD 0 + DD 0 + DQ TDX_STACK_MEMORY_BASE + DQ TDX_STACK_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_Heap: + DD 0 + DD 0 + DQ TDX_HEAP_MEMORY_BASE + DQ TDX_HEAP_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_MailBox: + DD 0 + DD 0 + DQ TDX_MAILBOX_MEMORY_BASE + DQ TDX_MAILBOX_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_CcWorkarea: + DD 0 + DD 0 + DQ CC_WORK_AREA_MEMORY_BASE + DQ CC_WORK_AREA_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_TdHob: + DD 0 + DD 0 + DQ TDX_HOB_MEMORY_BASE + DQ TDX_HOB_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TD_HOB + DD 0 + +_TdxPageTable: + DD 0 + DD 0 + DQ TDX_EXTRA_PAGE_TABLE_BASE + DQ TDX_EXTRA_PAGE_TABLE_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_OvmfPageTable: + DD 0 + DD 0 + DQ OVMF_PAGE_TABLE_BASE + DQ OVMF_PAGE_TABLE_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +TdxGuidedStructureEnd: +ALIGN 16 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79159): https://edk2.groups.io/g/devel/message/79159 Mute This Topic: https://groups.io/mt/84837891/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79160+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79160+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769454; cv=none; d=zohomail.com; s=zohoarc; b=FNbweWYXq/QJ1AwoyiPHouxHWz0lXuedURA8v7o+r16EUGGTeUkB1aySgoc2skaDY74bXKsjhTg3EmJ+bvh2zJcfVLdiGnFf0dADqJDf04+wA32ZsAc3TzXWNIjxhQ4cRb/l3wj1RyaB9QNptsEDzfGi4f0kfJTkTrCcUXlTK1o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769454; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cOKjT3xLJ6rhDxUPF+7KEdfkKVYmoHcsrniJhtiL5ao=; b=hF6ap7auZGuFJgIfrYbHzNb72SP5E2Re0GlNn9t5Jbaux+P9GAX6ck2k9+NRre65qPDFoXl9Xe4ZLHmcbOBdLOlo85YFdg/6Isug2AEHWHkvk89Irxs33NfZItI38U9Z0ckLK8NqkDzJUhIFmKIUkrY6K7R+IbpIjBafuEsq5Qc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79160+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769454119514.8280582275702; Thu, 12 Aug 2021 04:57:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id i0rUYY1788612xIpnTgemUFC; Thu, 12 Aug 2021 04:57:33 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:33 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322144" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322144" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:32 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433591" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:31 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu Subject: [edk2-devel] [PATCH 04/23] MdePkg: Add Tdx.h Date: Thu, 12 Aug 2021 19:56:43 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: yb7ATgmk99dLHUreLuBG9Awnx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769453; bh=8Y1SuUQN9gdWTqJmOA4VruHTQ/3JKesjfNdbgZtR8Kk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=OPWlW1O8sBocQJDzgXa//SQr5ilgr21e5fwS2gPJgCcxgiTjZuuvUx04VfBQBTxWqIz ZYRGfURgGOl9BIRO8jCa2bo/yHtmO9KtuBlxyYIwjsUIdgYAZ3s1L86yR+sdhsv6NqZyR 38sXttS+myTejsR71KsDPS1niWfwFtUm9x8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769455060100006 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Tdx.h includes the Intel Trust Domain Extension definitions. Detailed information can be found in below document: https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-module-1eas-v0.85.039.pdf Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Signed-off-by: Min Xu --- MdePkg/Include/IndustryStandard/Tdx.h | 200 ++++++++++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/Tdx.h diff --git a/MdePkg/Include/IndustryStandard/Tdx.h b/MdePkg/Include/Industr= yStandard/Tdx.h new file mode 100644 index 000000000000..c50470708b56 --- /dev/null +++ b/MdePkg/Include/IndustryStandard/Tdx.h @@ -0,0 +1,200 @@ +/** @file + Intel Trust Domain Extension definitions + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MDE_PKG_TDX_H_ +#define MDE_PKG_TDX_H_ + +#define EXIT_REASON_EXTERNAL_INTERRUPT 1 +#define EXIT_REASON_TRIPLE_FAULT 2 + +#define EXIT_REASON_PENDING_INTERRUPT 7 +#define EXIT_REASON_NMI_WINDOW 8 +#define EXIT_REASON_TASK_SWITCH 9 +#define EXIT_REASON_CPUID 10 +#define EXIT_REASON_HLT 12 +#define EXIT_REASON_INVD 13 +#define EXIT_REASON_INVLPG 14 +#define EXIT_REASON_RDPMC 15 +#define EXIT_REASON_RDTSC 16 +#define EXIT_REASON_VMCALL 18 +#define EXIT_REASON_VMCLEAR 19 +#define EXIT_REASON_VMLAUNCH 20 +#define EXIT_REASON_VMPTRLD 21 +#define EXIT_REASON_VMPTRST 22 +#define EXIT_REASON_VMREAD 23 +#define EXIT_REASON_VMRESUME 24 +#define EXIT_REASON_VMWRITE 25 +#define EXIT_REASON_VMOFF 26 +#define EXIT_REASON_VMON 27 +#define EXIT_REASON_CR_ACCESS 28 +#define EXIT_REASON_DR_ACCESS 29 +#define EXIT_REASON_IO_INSTRUCTION 30 +#define EXIT_REASON_MSR_READ 31 +#define EXIT_REASON_MSR_WRITE 32 +#define EXIT_REASON_INVALID_STATE 33 +#define EXIT_REASON_MSR_LOAD_FAIL 34 +#define EXIT_REASON_MWAIT_INSTRUCTION 36 +#define EXIT_REASON_MONITOR_TRAP_FLAG 37 +#define EXIT_REASON_MONITOR_INSTRUCTION 39 +#define EXIT_REASON_PAUSE_INSTRUCTION 40 +#define EXIT_REASON_MCE_DURING_VMENTRY 41 +#define EXIT_REASON_TPR_BELOW_THRESHOLD 43 +#define EXIT_REASON_APIC_ACCESS 44 +#define EXIT_REASON_EOI_INDUCED 45 +#define EXIT_REASON_GDTR_IDTR 46 +#define EXIT_REASON_LDTR_TR 47 +#define EXIT_REASON_EPT_VIOLATION 48 +#define EXIT_REASON_EPT_MISCONFIG 49 +#define EXIT_REASON_INVEPT 50 +#define EXIT_REASON_RDTSCP 51 +#define EXIT_REASON_PREEMPTION_TIMER 52 +#define EXIT_REASON_INVVPID 53 +#define EXIT_REASON_WBINVD 54 +#define EXIT_REASON_XSETBV 55 +#define EXIT_REASON_APIC_WRITE 56 +#define EXIT_REASON_RDRAND 57 +#define EXIT_REASON_INVPCID 58 +#define EXIT_REASON_VMFUNC 59 +#define EXIT_REASON_ENCLS 60 +#define EXIT_REASON_RDSEED 61 +#define EXIT_REASON_PML_FULL 62 +#define EXIT_REASON_XSAVES 63 +#define EXIT_REASON_XRSTORS 64 + +// TDCALL API Function Completion Status Codes +#define TDX_EXIT_REASON_SUCCESS 0x0000000000000000 +#define TDX_EXIT_REASON_PAGE_ALREADY_ACCEPTED 0x00000B0A00000000 +#define TDX_EXIT_REASON_PAGE_SIZE_MISMATCH 0xC0000B0B00000000 +#define TDX_EXIT_REASON_OPERAND_INVALID 0xC000010000000000 +#define TDX_EXIT_REASON_OPERAND_BUSY 0x8000020000000000 + +// TDCALL [TDG.MEM.PAGE.ACCEPT] page size +#define TDCALL_ACCEPT_PAGE_SIZE_4K 0 +#define TDCALL_ACCEPT_PAGE_SIZE_2M 1 +#define TDCALL_ACCEPT_PAGE_SIZE_1G 2 + +#define TDCALL_TDVMCALL 0 +#define TDCALL_TDINFO 1 +#define TDCALL_TDEXTENDRTMR 2 +#define TDCALL_TDGETVEINFO 3 +#define TDCALL_TDREPORT 4 +#define TDCALL_TDSETCPUIDVE 5 +#define TDCALL_TDACCEPTPAGE 6 + +#define TDVMCALL_CPUID 0x0000a +#define TDVMCALL_HALT 0x0000c +#define TDVMCALL_IO 0x0001e +#define TDVMCALL_RDMSR 0x0001f +#define TDVMCALL_WRMSR 0x00020 +#define TDVMCALL_MMIO 0x00030 +#define TDVMCALL_PCONFIG 0x00041 + +#define TDVMCALL_GET_TDVMCALL_INFO 0x10000 +#define TDVMCALL_MAPGPA 0x10001 +#define TDVMCALL_GET_QUOTE 0x10002 +#define TDVMCALL_REPORT_FATAL_ERR 0x10003 +#define TDVMCALL_SETUP_EVENT_NOTIFY 0x10004 + +#pragma pack(1) +typedef struct { + UINT64 Data[6]; +} TDCALL_GENERIC_RETURN_DATA; + +typedef struct { + UINT64 Gpaw; + UINT64 Attributes; + UINT32 MaxVcpus; + UINT32 NumVcpus; + UINT64 Resv[3]; +} TDCALL_INFO_RETURN_DATA; + +typedef union { + UINT64 Val; + struct { + UINT32 Size:3; + UINT32 Direction:1; + UINT32 String:1; + UINT32 Rep:1; + UINT32 Encoding:1; + UINT32 Resv:9; + UINT32 Port:16; + UINT32 Resv2; + } Io; +} VMX_EXIT_QUALIFICATION; + +typedef struct { + UINT32 ExitReason; + UINT32 Resv; + VMX_EXIT_QUALIFICATION ExitQualification; + UINT64 GuestLA; + UINT64 GuestPA; + UINT32 ExitInstructionLength; + UINT32 ExitInstructionInfo; + UINT32 Resv1; +} TDCALL_VEINFO_RETURN_DATA; + +typedef union { + TDCALL_GENERIC_RETURN_DATA Generic; + TDCALL_INFO_RETURN_DATA TdInfo; + TDCALL_VEINFO_RETURN_DATA VeInfo; +} TD_RETURN_DATA; + +/* data structure used in TDREPORT_STRUCT */ +typedef struct { + UINT8 Type; + UINT8 Subtype; + UINT8 Version; + UINT8 Rsvd; +} TD_REPORT_TYPE; + +typedef struct { + TD_REPORT_TYPE ReportType; + UINT8 Rsvd1[12]; + UINT8 CpuSvn[16]; + UINT8 TeeTcbInfoHash[48]; + UINT8 TeeInfoHash[48]; + UINT8 ReportData[64]; + UINT8 Rsvd2[32]; + UINT8 Mac[32]; +} REPORTMACSTRUCT; + +typedef struct { + UINT8 Seam[2]; + UINT8 Rsvd[14]; +} TEE_TCB_SVN; + +typedef struct { + UINT8 Valid[8]; + TEE_TCB_SVN TeeTcbSvn; + UINT8 Mrseam[48]; + UINT8 Mrsignerseam[48]; + UINT8 Attributes[8]; + UINT8 Rsvd[111]; +} TEE_TCB_INFO; + +typedef struct { + UINT8 Attributes[8]; + UINT8 Xfam[8]; + UINT8 Mrtd[48]; + UINT8 Mrconfigid[48]; + UINT8 Mrowner[48]; + UINT8 Mrownerconfig[48]; + UINT8 Rtmrs[4][48]; + UINT8 Rsvd[112]; +} TDINFO; + +typedef struct { + REPORTMACSTRUCT ReportMacStruct; + TEE_TCB_INFO TeeTcbInfo; + UINT8 Rsvd[17]; + TDINFO Tdinfo; +} TDREPORT_STRUCT; + +#pragma pack() + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79160): https://edk2.groups.io/g/devel/message/79160 Mute This Topic: https://groups.io/mt/84837892/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79161+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79161+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769457; cv=none; d=zohomail.com; s=zohoarc; b=NCUhqP4sA8BKwiSV1TWFXVl4/lDIRw13zjcD0+hwU6s79tKnaOwQ9wlPLtXIVclgWhgJ6YX9a+VjGaBm8vUvbwjdGgrcBtE4lKOrZ5kGnO+KkQfWzmzq3/yOVw6RLqJni/BEr3j9abQ1M84JM0aAlKS1TnnDgyRtCUM23xEkaFU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769457; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=u+I91iQeTKAZ55uQDu0ixxD2JPaYnG1QrOARwPgg3Ek=; b=I0N3yRgrZ7eFOr/S3ipoiCcr2YypKbMwfKcya7iJ50SMQ+I1qQa2FiqV8giJzYWbJbCQtbksds+FgnIflxCiFTbx25jPDqoVJ/eBLb7KdeNIoWsW0f/B2bEd4imKdHD3CKT1dHqJuaweI1nkz17AWAXi3SvhrDZOx5TnQznPgIk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79161+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16287694571481014.5637960648054; Thu, 12 Aug 2021 04:57:37 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id QXG7YY1788612x7eRU4taGL9; Thu, 12 Aug 2021 04:57:36 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:36 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322167" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322167" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:35 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433603" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:32 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 05/23] MdePkg: Add TdxProbeLib to probe Intel Tdx Date: Thu, 12 Aug 2021 19:56:44 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: f2cCAjekp5QxrDGFTgjL46fFx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769456; bh=CBWhqYtul+qUi0tWjfTsgp7FECZvY8pzaLWTZhh0aWc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=WgPSFemc6e5DhiCCpaXfUZZXsu5DGz6qP35UlFLzXUZ0EKD2rIm5QwdfjpYMHYZsplS ZvHOT7CbpKAwuJzLmwtTFE9ID3k4M8FMJKvPTMSE1Lg4zWnoV6WCCwmscFJXhLUk0ibnA sw8VmALYrB8ThQe+KuDfRZHPvaj2cmr0jv8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769459055100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Guest software can be designed to run either as a TD, as a legacy virtual machine, or directly on the CPU, based on enumeration of its run-time environment. CPUID leaf 0x21 emulation is done by the Intel TDX module. Sub-leaf 0 returns the values of "IntelTDX " in EBX/EDX/ECX. TdxProbeLib provides *TdxIsEnabled* to determine Td or Non-Td. On IA32 it always return FALSE because Intel TDX only works on X64. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- MdePkg/Include/Library/TdxProbeLib.h | 25 +++++ MdePkg/Library/TdxProbeLib/InternalTdxProbe.h | 25 +++++ MdePkg/Library/TdxProbeLib/TdProbeNull.c | 25 +++++ MdePkg/Library/TdxProbeLib/TdxProbeLib.c | 35 +++++++ MdePkg/Library/TdxProbeLib/TdxProbeLib.inf | 34 +++++++ MdePkg/Library/TdxProbeLib/X64/TdProbe.nasm | 97 +++++++++++++++++++ MdePkg/MdePkg.dec | 3 + MdePkg/MdePkg.dsc | 1 + 8 files changed, 245 insertions(+) create mode 100644 MdePkg/Include/Library/TdxProbeLib.h create mode 100644 MdePkg/Library/TdxProbeLib/InternalTdxProbe.h create mode 100644 MdePkg/Library/TdxProbeLib/TdProbeNull.c create mode 100644 MdePkg/Library/TdxProbeLib/TdxProbeLib.c create mode 100644 MdePkg/Library/TdxProbeLib/TdxProbeLib.inf create mode 100644 MdePkg/Library/TdxProbeLib/X64/TdProbe.nasm diff --git a/MdePkg/Include/Library/TdxProbeLib.h b/MdePkg/Include/Library/= TdxProbeLib.h new file mode 100644 index 000000000000..d4fa4ba4cdf8 --- /dev/null +++ b/MdePkg/Include/Library/TdxProbeLib.h @@ -0,0 +1,25 @@ +/** @file + TdxProbeLib definitions + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_PROBE_LIB_H_ +#define TDX_PROBE_LIB_H_ + +#include + +/** + Whether Intel TDX is enabled. + + @return TRUE TDX enabled + @return FALSE TDX not enabled +**/ +BOOLEAN +EFIAPI +TdxIsEnabled ( + VOID); + +#endif diff --git a/MdePkg/Library/TdxProbeLib/InternalTdxProbe.h b/MdePkg/Library= /TdxProbeLib/InternalTdxProbe.h new file mode 100644 index 000000000000..53cbbeda8cd8 --- /dev/null +++ b/MdePkg/Library/TdxProbeLib/InternalTdxProbe.h @@ -0,0 +1,25 @@ +/** @file + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef INTERNAL_TDX_PROBE_H_ +#define INTERNAL_TDX_PROBE_H_ + +#define PROBE_IS_TD_GUEST 0 +#define PROBE_NOT_TD_GUEST 1 + +/** + The internal Td Probe implementation. + + @return 0 TD guest + @return others Non-TD guest +**/ +UINTN +EFIAPI +TdProbe ( + VOID + ); + +#endif diff --git a/MdePkg/Library/TdxProbeLib/TdProbeNull.c b/MdePkg/Library/TdxP= robeLib/TdProbeNull.c new file mode 100644 index 000000000000..12e9e1f8a7d4 --- /dev/null +++ b/MdePkg/Library/TdxProbeLib/TdProbeNull.c @@ -0,0 +1,25 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include "InternalTdxProbe.h" + +/** + TDX only works in X64. So allways return -1 to indicate Non-Td. + + @return 0 TD guest + @return others Non-TD guest +**/ +UINTN +EFIAPI +TdProbe ( + VOID + ) +{ + return PROBE_NOT_TD_GUEST; +} diff --git a/MdePkg/Library/TdxProbeLib/TdxProbeLib.c b/MdePkg/Library/TdxP= robeLib/TdxProbeLib.c new file mode 100644 index 000000000000..3f4524dc16a6 --- /dev/null +++ b/MdePkg/Library/TdxProbeLib/TdxProbeLib.c @@ -0,0 +1,35 @@ +/** @file + instance of TdxProbeLib + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include +#include "InternalTdxProbe.h" + +BOOLEAN mTdxEnabled =3D FALSE; +BOOLEAN mTdxProbed =3D FALSE; + +/** + Whether Intel TDX is enabled. + + @return TRUE TDX enabled + @return FALSE TDX not enabled +**/ +BOOLEAN +EFIAPI +TdxIsEnabled ( + VOID) +{ + if (mTdxProbed) { + return mTdxEnabled; + } + + mTdxEnabled =3D TdProbe () =3D=3D PROBE_IS_TD_GUEST; + mTdxProbed =3D TRUE; + return mTdxEnabled; +} diff --git a/MdePkg/Library/TdxProbeLib/TdxProbeLib.inf b/MdePkg/Library/Td= xProbeLib/TdxProbeLib.inf new file mode 100644 index 000000000000..59fc12c41569 --- /dev/null +++ b/MdePkg/Library/TdxProbeLib/TdxProbeLib.inf @@ -0,0 +1,34 @@ +## @file +# Tdx Probe library instance +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TdxProbeLib + FILE_GUID =3D 26BF0B58-6E9D-4375-A363-52FD83FB82CE + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxProbeLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + TdxProbeLib.c + InternalTdxProbe.h + +[Sources.X64] + X64/TdProbe.nasm + +[Sources.IA32] + TdProbeNull.c + +[Packages] + MdePkg/MdePkg.dec diff --git a/MdePkg/Library/TdxProbeLib/X64/TdProbe.nasm b/MdePkg/Library/T= dxProbeLib/X64/TdProbe.nasm new file mode 100644 index 000000000000..ed941830f0ca --- /dev/null +++ b/MdePkg/Library/TdxProbeLib/X64/TdProbe.nasm @@ -0,0 +1,97 @@ +;-------------------------------------------------------------------------= ----- +;* +;* CPUID leaf 0x21 emulation is done by the Intel TDX module. Sub-leaf 0 +;* returns the values of "IntelTDX " in EBX/EDX/ECX. +;* +;* Copyright (c) 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%define TD_PROBE_TD_GUEST 0 +%define TD_PROBE_NOT_TD_GUEST 1 + +%macro td_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro td_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + + +global ASM_PFX(TdProbe) +ASM_PFX(TdProbe): + + td_push_regs + + ; + ; CPUID (0) + ; + mov eax, 0 + cpuid + cmp ebx, 0x756e6547 ; "Genu" + jne .not_td + cmp edx, 0x49656e69 ; "ineI" + jne .not_td + cmp ecx, 0x6c65746e ; "ntel" + jne .not_td + + ; + ; CPUID (1) + ; + mov eax, 1 + cpuid + test ecx, 0x80000000 + jz .not_td + + ; + ; CPUID[0].EAX >=3D 0x21? + ; + mov eax, 0 + cpuid + cmp eax, 0x21 + jl .not_td + + ; + ; CPUID (0x21,0) + ; + mov eax, 0x21 + mov ecx, 0 + cpuid + + cmp ebx, 0x65746E49 ; "Inte" + jne .not_td + cmp edx, 0x5844546C ; "lTDX" + jne .not_td + cmp ecx, 0x20202020 ; " " + jne .not_td + + mov rax, TD_PROBE_TD_GUEST + jmp .exit + +.not_td: + mov rax, TD_PROBE_NOT_TD_GUEST + +.exit: + td_pop_regs + ret diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index a28a2daaffa8..5702b0596499 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -296,6 +296,9 @@ ## @libraryclass Provides services to log the SMI handler registration. SmiHandlerProfileLib|Include/Library/SmiHandlerProfileLib.h =20 + ## @libraryclass Provides function to support TDX probe processing. + TdxProbeLib|Include/Library/TdxProbeLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index a94959169b2f..a62a9504bc12 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -130,6 +130,7 @@ MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib= .inf =20 MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf + MdePkg/Library/TdxProbeLib/TdxProbeLib.inf =20 [Components.IA32, Components.X64, Components.ARM, Components.AARCH64] # --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79161): https://edk2.groups.io/g/devel/message/79161 Mute This Topic: https://groups.io/mt/84837894/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79162+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79162+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769459; cv=none; d=zohomail.com; s=zohoarc; b=CVjKtdzBSfismO9GfAk50YBaGGlktbAzn+phUTFtSWwi1U3DAqZjGtupkBu/3HR2tGyIJEEKZHUnzyyTxXoBB4MT/E4ffOpWjobgEn0x6XKon558KWBaI94AeKehroW4YF2OrxGIyq2B1Y6aUQEYt/Xoj7i8P7namQh7BqEZUYw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769459; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=7eycZCUSXhY3C89cdqQ/Vqwn0lzDoCg4gU36PI63JBw=; b=fr4kVsqO7N6JDaXCUw8VTg/oYWoaSFvFuxjaRwYj4ZQSnGnRhHQfEwyi7YnnDZMRQFeYzGZfFPhWUfRk16Rj2+u7NN7eV49VClFxZlCG4PsMCxcBkaM6WVsES/k0lO2foHhlBxawrdO728JQkno6+OvojWkzZEZlacO+IhKgSLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79162+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769459608345.73496277955917; Thu, 12 Aug 2021 04:57:39 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 879DYY1788612xRDv8fEnFoy; Thu, 12 Aug 2021 04:57:39 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:38 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322179" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322179" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:38 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433635" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:35 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 06/23] MdePkg: Add TdxLib to wrap Tdx operations Date: Thu, 12 Aug 2021 19:56:45 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: Dh4IK5wxVwz0B86KTuRBWECFx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769459; bh=RODeJjQC4mgMdIG2wrulW5yLQWcV/RRzLiAH58wol14=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=W4XCgEep0NVGMB4DUEJqjDYUYbLG0HFvYs/oWCY5bl2Ij9yvnhaPW1VCMh85WFyMYNR hiSDINTE/91EXf84sOzY2CM0cs81dynKMMZRALQrvfHUp4E2lRRzlh7TmnXInmaOL1lAW 5DN8JC2a11N3gm14rONVUTUlAkmbMzr78bw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769461257100002 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 TdxLib is created with functions to perform the related Tdx operation. This includes functions for: - TdCall : Cause a VM exit to the Intel TDX module. - TdVmCall : It helps invoke services from the host VMM to pass/ receive information. - TdVmCallCpuid : Enable the TD guest to request VMM to emulate CPUID - TdAcceptPages : Accept pending private pages and initialize the pages to all-0 using the TD ephemeral private key. - TdExtendRtmr : Extend measurement to one of the RTMR registers. - TdSharedPageMask: Get the Td guest shared page mask which indicates it is a Shared or Private page. - TdMaxVCpuNum : Get the maximum number of virutal CPUs. - TdVCpuNum : Get the number of virtual CPUs. (In some case VMM may add more vCPU in runtime). Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- MdePkg/Include/Library/TdxLib.h | 167 +++++++++++++++++++ MdePkg/Library/TdxLib/AcceptPages.c | 136 ++++++++++++++++ MdePkg/Library/TdxLib/Rtmr.c | 118 ++++++++++++++ MdePkg/Library/TdxLib/TdInfo.c | 101 ++++++++++++ MdePkg/Library/TdxLib/TdxLib.inf | 39 +++++ MdePkg/Library/TdxLib/TdxLibNull.c | 192 ++++++++++++++++++++++ MdePkg/Library/TdxLib/X64/Tdcall.nasm | 120 ++++++++++++++ MdePkg/Library/TdxLib/X64/Tdvmcall.nasm | 206 ++++++++++++++++++++++++ MdePkg/MdePkg.dec | 3 + MdePkg/MdePkg.dsc | 1 + 10 files changed, 1083 insertions(+) create mode 100644 MdePkg/Include/Library/TdxLib.h create mode 100644 MdePkg/Library/TdxLib/AcceptPages.c create mode 100644 MdePkg/Library/TdxLib/Rtmr.c create mode 100644 MdePkg/Library/TdxLib/TdInfo.c create mode 100644 MdePkg/Library/TdxLib/TdxLib.inf create mode 100644 MdePkg/Library/TdxLib/TdxLibNull.c create mode 100644 MdePkg/Library/TdxLib/X64/Tdcall.nasm create mode 100644 MdePkg/Library/TdxLib/X64/Tdvmcall.nasm diff --git a/MdePkg/Include/Library/TdxLib.h b/MdePkg/Include/Library/TdxLi= b.h new file mode 100644 index 000000000000..43a7d709657e --- /dev/null +++ b/MdePkg/Include/Library/TdxLib.h @@ -0,0 +1,167 @@ +/** @file + TdxLib definitions + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef TDX_LIB_H_ +#define TDX_LIB_H_ + +#include +#include +#include +#include + +/** + This function accepts a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + @param[in] StartAddress Guest physical address of the private page + to accept. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Accept 2M/4K page size. + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT64 PageSize + ); + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ); + + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ); + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ); + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ); + + +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +EFI_STATUS +EFIAPI +TdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ); + +/** + TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from t= he + host VMM to pass/receive information. + + @param[in] Leaf Number of sub-functions + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in] Arg4 Arg4 + @param[in,out] Results Returned result of the sub-function + + @return EFI_SUCCESS + @return Other See individual sub-functions + +**/ +EFI_STATUS +EFIAPI +TdVmCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN UINT64 Arg4, + IN OUT VOID *Results + ); + +/** + This function enable the TD guest to request the VMM to emulate CPUID + operation, especially for non-architectural, CPUID leaves. + + @param[in] Eax Main leaf of the CPUID + @param[in] Ecx Sub-leaf of the CPUID + @param[out] Results Returned result of CPUID operation + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdVmCallCpuid ( + IN UINT64 Eax, + IN UINT64 Ecx, + OUT VOID *Results + ); + +#endif diff --git a/MdePkg/Library/TdxLib/AcceptPages.c b/MdePkg/Library/TdxLib/Ac= ceptPages.c new file mode 100644 index 000000000000..8941dc05b114 --- /dev/null +++ b/MdePkg/Library/TdxLib/AcceptPages.c @@ -0,0 +1,136 @@ +/** @file + + Unaccepted memory is a special type of private memory. In Td guest + TDCALL [TDG.MEM.PAGE.ACCEPT] is invoked to accept the unaccepted + memory before use it. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +UINT64 mNumberOfDuplicatedAcceptedPages; + +// PageSize is mapped to PageLevel like below: +// 4KB - 0, 2MB - 1 +UINT64 mTdxAcceptPageLevelMap[2] =3D { + SIZE_4KB, + SIZE_2MB +}; + +/** + This function gets the PageLevel according to the input page size. + + @param[in] PageSize Page size + + @return UINTN The mapped page level +**/ +UINTN +GetGpaPageLevel ( + UINT64 PageSize + ) +{ + UINTN Index; + + for (Index =3D 0; Index < sizeof (mTdxAcceptPageLevelMap) / sizeof (mTdx= AcceptPageLevelMap[0]); Index++) { + if (mTdxAcceptPageLevelMap[Index] =3D=3D PageSize) { + break; + } + } + + return Index; +} + +/** + This function accept a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + Sometimes TDCALL [TDG.MEM.PAGE.ACCEPT] may return + TDX_EXIT_REASON_PAGE_SIZE_MISMATCH. It indicates the input PageLevel is + not workable. In this case we need to try to fallback to a smaller + PageLevel if possible. + + @param[in] StartAddress Guest physical address of the private + page to accept. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Only accept 1G/2M/4K size. + + @return EFI_SUCCESS Accept successfully + @return others Indicate other errors +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT64 PageSize + ) +{ + EFI_STATUS Status; + UINT64 Address; + UINT64 TdxStatus; + UINT64 Index; + UINT64 GpaPageLevel; + UINT64 PageSize2; + + Address =3D StartAddress; + + GpaPageLevel =3D (UINT64) GetGpaPageLevel (PageSize); + if (GpaPageLevel > sizeof (mTdxAcceptPageLevelMap) / sizeof (mTdxAcceptP= ageLevelMap[0])) { + DEBUG ((DEBUG_ERROR, "Accept page size must be 4K/2M. Invalid page siz= e - 0x%llx\n", PageSize)); + return EFI_INVALID_PARAMETER; + } + + Status =3D EFI_SUCCESS; + for (Index =3D 0; Index < NumberOfPages; Index++) { + TdxStatus =3D TdCall (TDCALL_TDACCEPTPAGE, Address | GpaPageLevel, 0, = 0, 0); + if (TdxStatus !=3D TDX_EXIT_REASON_SUCCESS) { + if ((TdxStatus & ~0xFFFFULL) =3D=3D TDX_EXIT_REASON_PAGE_ALREADY_A= CCEPTED) { + // + // Already accepted + // + mNumberOfDuplicatedAcceptedPages++; + } else if ((TdxStatus & ~0xFFFFULL) =3D=3D TDX_EXIT_REASON_PAGE_SI= ZE_MISMATCH) { + // + // GpaPageLevel is mismatch, fall back to a smaller GpaPageLevel= if possible + // + DEBUG ((DEBUG_VERBOSE, "Address %llx cannot be accepted in PageL= evel of %d\n", Address, GpaPageLevel)); + + if (GpaPageLevel =3D=3D 0) { + // + // Cannot fall back to smaller page level + // + DEBUG ((DEBUG_ERROR, "AcceptPage cannot fallback from PageLeve= l %d\n", GpaPageLevel)); + Status =3D EFI_INVALID_PARAMETER; + break; + } else { + // + // Fall back to a smaller page size + // + PageSize2 =3D mTdxAcceptPageLevelMap [GpaPageLevel - 1]; + Status =3D TdAcceptPages(Address, 512, PageSize2); + if (EFI_ERROR (Status)) { + break; + } + } + }else { + + // + // Other errors + // + DEBUG ((DEBUG_ERROR, "Address %llx (%d) failed to be accepted. E= rror =3D 0x%llx\n", + Address, Index, TdxStatus)); + Status =3D EFI_INVALID_PARAMETER; + break; + } + } + Address +=3D PageSize; + } + return Status; +} diff --git a/MdePkg/Library/TdxLib/Rtmr.c b/MdePkg/Library/TdxLib/Rtmr.c new file mode 100644 index 000000000000..c86902ae21bc --- /dev/null +++ b/MdePkg/Library/TdxLib/Rtmr.c @@ -0,0 +1,118 @@ +/** @file + + Extends one of the RTMR measurement registers in TDCS with the provided + extension data in memory. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include + +#define RTMR_COUNT 4 +#define TD_EXTEND_BUFFER_LEN (64 + 64) +#define EXTEND_BUFFER_ADDRESS_MASK 0x3f + + +#pragma pack(16) +typedef struct { + UINT8 Buffer[TD_EXTEND_BUFFER_LEN]; +} TDX_EXTEND_BUFFER; +#pragma pack() + +UINT8 *mExtendBufferAddress =3D NULL; +TDX_EXTEND_BUFFER mExtendBuffer; + +/** + TD.RTMR.EXTEND requires 64B-aligned guest physical address of + 48B-extension data. In runtime we walk thru the Buffer to find + out a 64B-aligned start address. + + @return Start address of the extend buffer + +**/ +UINT8 * +EFIAPI +GetExtendBuffer ( + VOID + ) +{ + UINT8 *ExtendBufferAddress; + UINT64 Gap; + + if (mExtendBufferAddress !=3D NULL) { + return mExtendBufferAddress; + } + + ExtendBufferAddress =3D mExtendBuffer.Buffer; + + Gap =3D 0x40 - ((UINT64)(UINTN)ExtendBufferAddress & EXTEND_BUFFER_ADDRE= SS_MASK); + mExtendBufferAddress =3D (UINT8*)((UINT64)(UINTN)ExtendBufferAddress + G= ap); + + DEBUG ((DEBUG_VERBOSE, "ExtendBufferAddress: 0x%p, Gap: 0x%x\n", ExtendB= ufferAddress, Gap)); + DEBUG ((DEBUG_VERBOSE, "mExtendBufferAddress: 0x%p\n", mExtendBufferAddr= ess)); + + ASSERT (mExtendBufferAddress + 64 <=3D ExtendBufferAddress + TD_EXTEND_B= UFFER_LEN); + + return mExtendBufferAddress; +} + + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ) +{ + EFI_STATUS Status; + UINT64 TdCallStatus; + UINT8 *ExtendBuffer; + + Status =3D EFI_SUCCESS; + + ASSERT (Index >=3D 0 && Index < RTMR_COUNT); + ASSERT (DataLen =3D=3D SHA384_DIGEST_SIZE); + + ExtendBuffer =3D GetExtendBuffer(); + ASSERT (ExtendBuffer !=3D NULL); + ZeroMem (ExtendBuffer, SHA384_DIGEST_SIZE); + CopyMem (ExtendBuffer, Data, SHA384_DIGEST_SIZE); + + TdCallStatus =3D TdCall (TDCALL_TDEXTENDRTMR, (UINT64)(UINTN)ExtendBuffe= r, Index, 0, 0); + + if (TdCallStatus =3D=3D TDX_EXIT_REASON_SUCCESS) { + Status =3D EFI_SUCCESS; + } else if (TdCallStatus =3D=3D TDX_EXIT_REASON_OPERAND_INVALID) { + Status =3D EFI_INVALID_PARAMETER; + } else { + Status =3D EFI_DEVICE_ERROR; + } + + if (Status !=3D EFI_SUCCESS) { + DEBUG ((DEBUG_ERROR, "Error returned from TdExtendRtmr call - 0x%lx\n"= , TdCallStatus)); + } + + return Status; +} diff --git a/MdePkg/Library/TdxLib/TdInfo.c b/MdePkg/Library/TdxLib/TdInfo.c new file mode 100644 index 000000000000..ed07fc522f26 --- /dev/null +++ b/MdePkg/Library/TdxLib/TdInfo.c @@ -0,0 +1,101 @@ +/** @file + + Fetch the Tdx info. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +UINT64 mTdSharedPageMask =3D 0; +UINT32 mTdMaxVCpuNum =3D 0; + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ) +{ + UINT64 Status; + UINT8 Gpaw; + TD_RETURN_DATA TdReturnData; + + if (mTdSharedPageMask !=3D 0) { + return mTdSharedPageMask; + } + + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D TDX_EXIT_REASON_SUCCESS); + + Gpaw =3D (UINT8)(TdReturnData.TdInfo.Gpaw & 0x3f); + ASSERT(Gpaw =3D=3D 48 || Gpaw =3D=3D 52); + mTdSharedPageMask =3D 1ULL << (Gpaw - 1); + return mTdSharedPageMask; +} + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ) +{ + UINT64 Status; + TD_RETURN_DATA TdReturnData; + + if (mTdMaxVCpuNum !=3D 0) { + return mTdMaxVCpuNum; + } + + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D TDX_EXIT_REASON_SUCCESS); + + mTdMaxVCpuNum =3D TdReturnData.TdInfo.MaxVcpus; + + return mTdMaxVCpuNum; +} + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ) +{ + UINT64 Status; + TD_RETURN_DATA TdReturnData; + + // + // Due to the possible change of vcpu num in run-time, do the Td call + // for every query. + // + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT (Status =3D=3D TDX_EXIT_REASON_SUCCESS); + + return TdReturnData.TdInfo.NumVcpus; +} diff --git a/MdePkg/Library/TdxLib/TdxLib.inf b/MdePkg/Library/TdxLib/TdxLi= b.inf new file mode 100644 index 000000000000..772abcc49d8b --- /dev/null +++ b/MdePkg/Library/TdxLib/TdxLib.inf @@ -0,0 +1,39 @@ +## @file +# Tdx library +# +# Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TdxLib + FILE_GUID =3D 032A8E0D-0C27-40C0-9CAA-23B731C1B223 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources.IA32] + TdxLibNull.c + +[Sources.X64] + AcceptPages.c + Rtmr.c + TdInfo.c + X64/Tdcall.nasm + X64/Tdvmcall.nasm + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib diff --git a/MdePkg/Library/TdxLib/TdxLibNull.c b/MdePkg/Library/TdxLib/Tdx= LibNull.c new file mode 100644 index 000000000000..5a8f19c6d8d2 --- /dev/null +++ b/MdePkg/Library/TdxLib/TdxLibNull.c @@ -0,0 +1,192 @@ +/** @file + + Null stub of TdxLib + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + This function accepts a pending private page, and initialize the page to + all-0 using the TD ephemeral private key. + + @param[in] StartAddress Guest physical address of the private page + to accept. + @param[in] NumberOfPages Number of the pages to be accepted. + @param[in] PageSize GPA page size. Accept 1G/2M/4K page size. + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdAcceptPages ( + IN UINT64 StartAddress, + IN UINT64 NumberOfPages, + IN UINT64 PageSize + ) +{ + return EFI_UNSUPPORTED; +} + +/** + This function extends one of the RTMR measurement register + in TDCS with the provided extension data in memory. + RTMR extending supports SHA384 which length is 48 bytes. + + @param[in] Data Point to the data to be extended + @param[in] DataLen Length of the data. Must be 48 + @param[in] Index RTMR index + + @return EFI_SUCCESS + @return EFI_INVALID_PARAMETER + @return EFI_DEVICE_ERROR + +**/ +EFI_STATUS +EFIAPI +TdExtendRtmr ( + IN UINT32 *Data, + IN UINT32 DataLen, + IN UINT8 Index + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + This function gets the Td guest shared page mask. + + The guest indicates if a page is shared using the Guest Physical Address + (GPA) Shared (S) bit. If the GPA Width(GPAW) is 48, the S-bit is bit-47. + If the GPAW is 52, the S-bit is bit-51. + + @return Shared page bit mask +**/ +UINT64 +EFIAPI +TdSharedPageMask ( + VOID + ) +{ + return 0; +} + + +/** + This function gets the maximum number of Virtual CPUs that are usable for + Td Guest. + + @return maximum Virtual CPUs number +**/ +UINT32 +EFIAPI +TdMaxVCpuNum ( + VOID + ) +{ + return 0; +} + + +/** + This function gets the number of Virtual CPUs that are usable for Td + Guest. + + @return Virtual CPUs number +**/ +UINT32 +EFIAPI +TdVCpuNum ( + VOID + ) +{ + return 0; +} + + +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + Leaf functions are described at + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +EFI_STATUS +EFIAPI +TdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + TDVMALL is a leaf function 0 for TDCALL. It helps invoke services from t= he + host VMM to pass/receive information. + + @param[in] Leaf Number of sub-functions + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in] Arg4 Arg4 + @param[in,out] Results Returned result of the sub-function + + @return EFI_SUCCESS + @return Other See individual sub-functions + +**/ +EFI_STATUS +EFIAPI +TdVmCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN UINT64 Arg4, + IN OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} + + +/** + This function enable the TD guest to request the VMM to emulate CPUID + operation, especially for non-architectural, CPUID leaves. + + @param[in] Eax Main leaf of the CPUID + @param[in] Ecx Sub-leaf of the CPUID + @param[out] Results Returned result of CPUID operation + + @return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +TdVmCallCpuid ( + IN UINT64 Eax, + IN UINT64 Ecx, + OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/MdePkg/Library/TdxLib/X64/Tdcall.nasm b/MdePkg/Library/TdxLib/= X64/Tdcall.nasm new file mode 100644 index 000000000000..eebd4880e2dc --- /dev/null +++ b/MdePkg/Library/TdxLib/X64/Tdcall.nasm @@ -0,0 +1,120 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +%macro tdcall_regs_preamble 2 + mov rax, %1 + + mov ecx, %2 + + ; R10 =3D 0 (standard TDVMCALL) + + xor r10d, r10d + + ; Zero out unused (for standard TDVMCALL) registers to avoid leaking + ; secrets to the VMM. + + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor edx, edx + xor ebp, ebp + xor r8d, r8d + xor r9d, r9d +%endmacro + +%macro tdcall_regs_postamble 0 + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor ecx, ecx + xor edx, edx + xor r8d, r8d + xor r9d, r9d + xor r10d, r10d + xor r11d, r11d +%endmacro + +; TdCall ( +; UINT64 Leaf, // Rcx +; UINT64 P1, // Rdx +; UINT64 P2, // R8 +; UINT64 P3, // R9 +; UINT64 Results, // rsp + 0x28 +; ) +global ASM_PFX(TdCall) +ASM_PFX(TdCall): + tdcall_push_regs + + mov rax, rcx + mov rcx, rdx + mov rdx, r8 + mov r8, r9 + + tdcall + + ; exit if tdcall reports failure. + test rax, rax + jnz .exit + + ; test if caller wanted results + mov r12, [rsp + first_variable_on_stack_offset ] + test r12, r12 + jz .exit + mov [r12 + 0 ], rcx + mov [r12 + 8 ], rdx + mov [r12 + 16], r8 + mov [r12 + 24], r9 + mov [r12 + 32], r10 + mov [r12 + 40], r11 +.exit: + tdcall_pop_regs + ret diff --git a/MdePkg/Library/TdxLib/X64/Tdvmcall.nasm b/MdePkg/Library/TdxLi= b/X64/Tdvmcall.nasm new file mode 100644 index 000000000000..33bb811a3a25 --- /dev/null +++ b/MdePkg/Library/TdxLib/X64/Tdvmcall.nasm @@ -0,0 +1,206 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%define TDVMCALL_EXPOSE_REGS_MASK 0xffec +%define TDVMCALL 0x0 +%define EXIT_REASON_CPUID 0xa + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +%macro tdcall_regs_preamble 2 + mov rax, %1 + + mov ecx, %2 + + ; R10 =3D 0 (standard TDVMCALL) + + xor r10d, r10d + + ; Zero out unused (for standard TDVMCALL) registers to avoid leaking + ; secrets to the VMM. + + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor edx, edx + xor ebp, ebp + xor r8d, r8d + xor r9d, r9d +%endmacro + +%macro tdcall_regs_postamble 0 + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor ecx, ecx + xor edx, edx + xor r8d, r8d + xor r9d, r9d + xor r10d, r10d + xor r11d, r11d +%endmacro + +;-------------------------------------------------------------------------= ----- +; 0 =3D> RAX =3D TDCALL leaf +; M =3D> RCX =3D TDVMCALL register behavior +; 1 =3D> R10 =3D standard vs. vendor +; RDI =3D> R11 =3D TDVMCALL function / nr +; RSI =3D R12 =3D p1 +; RDX =3D> R13 =3D p2 +; RCX =3D> R14 =3D p3 +; R8 =3D> R15 =3D p4 + +; UINT64 +; EFIAPI +; TdVmCall ( +; UINT64 Leaf, // Rcx +; UINT64 P1, // Rdx +; UINT64 P2, // R8 +; UINT64 P3, // R9 +; UINT64 P4, // rsp + 0x28 +; UINT64 *Val // rsp + 0x30 +; ) +global ASM_PFX(TdVmCall) +ASM_PFX(TdVmCall): + tdcall_push_regs + + mov r11, rcx + mov r12, rdx + mov r13, r8 + mov r14, r9 + mov r15, [rsp + first_variable_on_stack_offset ] + + tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK + + tdcall + + ; ignore return dataif TDCALL reports failure. + test rax, rax + jnz .no_return_data + + ; Propagate TDVMCALL success/failure to return value. + mov rax, r10 + + ; Retrieve the Val pointer. + mov r9, [rsp + second_variable_on_stack_offset ] + test r9, r9 + jz .no_return_data + + ; On success, propagate TDVMCALL output value to output param + test rax, rax + jnz .no_return_data + mov [r9], r11 +.no_return_data: + tdcall_regs_postamble + + tdcall_pop_regs + + ret + +;-------------------------------------------------------------------------= ----- +; 0 =3D> RAX =3D TDCALL leaf +; M =3D> RCX =3D TDVMCALL register behavior +; 1 =3D> R10 =3D standard vs. vendor +; RDI =3D> R11 =3D TDVMCALL function / nr +; RSI =3D R12 =3D p1 +; RDX =3D> R13 =3D p2 +; RCX =3D> R14 =3D p3 +; R8 =3D> R15 =3D p4 + +; UINT64 +; EFIAPI +; TdVmCallCpuid ( +; UINT64 EaxIn, // Rcx +; UINT64 EcxIn, // Rdx +; UINT64 *Results // R8 +; ) +global ASM_PFX(TdVmCallCpuid) +ASM_PFX(TdVmCallCpuid): + tdcall_push_regs + + mov r11, EXIT_REASON_CPUID + mov r12, rcx + mov r13, rdx + + ; Save *results pointers + push r8 + + tdcall_regs_preamble TDVMCALL, TDVMCALL_EXPOSE_REGS_MASK + + tdcall + + ; Panic if TDCALL reports failure. + test rax, rax + jnz .no_return_data + + ; Propagate TDVMCALL success/failure to return value. + mov rax, r10 + test rax, rax + jnz .no_return_data + + ; Retrieve *Results + pop r8 + test r8, r8 + jz .no_return_data + ; Caller pass in buffer so store results r12-r15 contains eax-edx + mov [r8 + 0], r12 + mov [r8 + 8], r13 + mov [r8 + 16], r14 + mov [r8 + 24], r15 + +.no_return_data: + tdcall_regs_postamble + + tdcall_pop_regs + + ret + +.panic: + ud2 diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index 5702b0596499..94160588018f 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -299,6 +299,9 @@ ## @libraryclass Provides function to support TDX probe processing. TdxProbeLib|Include/Library/TdxProbeLib.h =20 + ## @libraryclass Provides function to support TDX processing. + TdxLib|Include/Library/TdxLib.h + [Guids] # # GUID defined in UEFI2.1/UEFI2.0/EFI1.1 diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index a62a9504bc12..b7f99b2f2772 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -176,6 +176,7 @@ MdePkg/Library/SmiHandlerProfileLibNull/SmiHandlerProfileLibNull.inf MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf MdePkg/Library/MmUnblockMemoryLib/MmUnblockMemoryLibNull.inf + MdePkg/Library/TdxLib/TdxLib.inf =20 [Components.EBC] MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79162): https://edk2.groups.io/g/devel/message/79162 Mute This Topic: https://groups.io/mt/84837895/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79163+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79163+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769462; cv=none; d=zohomail.com; s=zohoarc; b=iArZcw2CtuD2X5LV38Sjer2Ikm84828MMvKWkr5i/VjCIFLGbc7Yn8Q0FhG5Y8WujiMBvUxWsicK/Lwimp54OneyrnBrXMtXjkocEpehSh1tb9Q9eD95PD3w87d2gMcWiO1UVVBrcssENMzLIdmpS2Bdscoc+SLAR/70fciXCvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769462; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=+Yxk4IlDjXjy7xSRbKfTBkLqE+zWlR6vf5WrJeG2WXY=; b=edJJUUDv8AU+OBYQWbkzoTcfbTWWpinn9AtlkXmTZdNWqzcudiPuMGSUQpX3oyAIiEOU9O/UWxhglhiSYHnjTgha/24Jiz5RqbgkwaCQDvrKaWi8Qvcd+shXJMI9tL0MOLI8QnuKkAvzDKxsTPxT4YCbF0muYMANCdQVJANiZK0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79163+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769462649280.66671593863543; Thu, 12 Aug 2021 04:57:42 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id Sg68YY1788612xWNGoML6qe9; Thu, 12 Aug 2021 04:57:42 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:41 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322198" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322198" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:40 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433657" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:38 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 07/23] MdePkg: Update BaseIoLibIntrinsicSev to support Tdx Date: Thu, 12 Aug 2021 19:56:46 +0800 Message-Id: <8f56e6f50477bf00d5121e6515388fe68525b1e2.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: k1nsZWyybKOqi81k7EkTMMCax1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769462; bh=7xSzARV/lNx8Vxdh9eGaQKOqxo1u0snUpcCZVNg707o=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=BMzHHasJPVBTdULmdyqYDUoZ/VFNgHz+oF0oUmkSNVmCbDYll4W0gUMYR7kqkgdhhHY RKqjsWQMquS2X9YFPw9151BHo470iwBQuYZpA/0WehyRmGCJtlpmfN1JB7BP+I+FoebG/ jCwffB54+ItUKzX4AYDnLuhlV9HELRAD97I= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769463650100006 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Intel TDX architecture does not prescribe a specific software convention to perform I/O from the guest TD. Guest TD providers have many choices to provide I/O to the guest. The common I/O models are emulated devices, para-virtualized devices, SRIOV devices and Direct Device assignments. TDVF chooses para-virtualized I/O (Choice-A) which use the TDG.VP.VMCALL function to invoke the funtions provided by the host VMM to perform I/O. Another choice (Choice-B) is the emulation performed by the #VE handler. There are 2 benefits of para-virtualized I/O: 1. Performance. VMEXIT/VMENTRY is skipped so that the performance is better than #VE handler. 2. De-couple with #VE handler. Choice-B depends on the #VE handler which means I/O is not available until #VE handler is installed. For example, in PEI phase #VE handler is installed in CpuMpPei, while communication with Qemu (via I/O port) happen earlier than it. BaseIoLibIntrinsicSev.inf is the IoLib used by OvmfPkg. TDVF updates BaseIoLibIntrinsicSev to support I/O in Td guest. Below files are updated to support I/O in Td guest. - IoLib.c - IoLibGcc.c - IoLibMsc.c - X64/IoFifoSev.nasm In the I/O functions of above files, if IsTdxGuest() returns TRUE, then Td I/O routine is called, otherwise the legacy I/O routine is called. Td I/O routines are declared in IoLibTdx.h and implemented in IoLibInternalTdx.c. BaseIoLibIntrinsic.inf is the IoLib used by other packages. It will not support I/O in Td guest. But some files are shared between BaseIoLibIntrinsic and BaseIoLibIntrinsicSev (IoLib.c is the example). So IoLibInternalTdxNull.c is created which holds the null stub of the Td I/O routines. IoLibInternalTdxNull.c is included in BaseIoLibIntrinsic.inf. BaseIoLibIntrinsic.inf doesn't import TdxProbeLib/TdxLib so that the Pkgs which include BaseIoLibIntrinsic.inf need not include TdxProbeLib/TdxLib. BaseIoLibIntrinsicArmVirt.inf is not touched because it shares no files with BaseIoLibIntrinsicSev. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- .../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 2 + .../BaseIoLibIntrinsicSev.inf | 6 +- MdePkg/Library/BaseIoLibIntrinsic/IoLib.c | 97 ++- MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c | 49 +- .../BaseIoLibIntrinsic/IoLibInternalTdx.c | 690 ++++++++++++++++++ .../BaseIoLibIntrinsic/IoLibInternalTdxNull.c | 499 +++++++++++++ MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c | 73 +- MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h | 411 +++++++++++ .../BaseIoLibIntrinsic/X64/IoFifoSev.nasm | 133 ++++ 9 files changed, 1911 insertions(+), 49 deletions(-) create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c create mode 100644 MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 97eeada0656e..27b15d9ae256 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -34,6 +34,8 @@ IoLibMmioBuffer.c BaseIoLibIntrinsicInternal.h IoHighLevel.c + IoLibInternalTdxNull.c + IoLibTdx.h =20 [Sources.IA32] IoLibGcc.c | GCC diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf b/= MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf index 34f9d1d1062f..53ff8d6fd37d 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicSev.inf @@ -30,17 +30,20 @@ IoLibMmioBuffer.c BaseIoLibIntrinsicInternal.h IoHighLevel.c + IoLibTdx.h =20 [Sources.IA32] IoLibGcc.c | GCC IoLibMsc.c | MSFT IoLib.c + IoLibInternalTdxNull.c Ia32/IoFifoSev.nasm =20 [Sources.X64] IoLibGcc.c | GCC IoLibMsc.c | MSFT IoLib.c + IoLibInternalTdx.c X64/IoFifoSev.nasm =20 [Packages] @@ -50,4 +53,5 @@ DebugLib BaseLib RegisterFilterLib - + TdxLib + TdxProbeLib diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c b/MdePkg/Library/Bas= eIoLibIntrinsic/IoLib.c index d0d7044f0901..68298749ee56 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLib.c @@ -7,6 +7,7 @@ **/ =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 /** Reads a 64-bit I/O port. @@ -70,6 +71,8 @@ IoWrite64 ( =20 If 8-bit MMIO register operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -86,9 +89,13 @@ MmioRead8 ( =20 Flag =3D FilterBeforeMmIoRead (FilterWidth8, Address, &Value); if (Flag) { - MemoryFence (); - Value =3D *(volatile UINT8*)Address; - MemoryFence (); + if (IsTdxGuest ()) { + Value =3D TdMmioRead8 (Address); + } else { + MemoryFence (); + Value =3D *(volatile UINT8*)Address; + MemoryFence (); + } } FilterAfterMmIoRead (FilterWidth8, Address, &Value); =20 @@ -104,6 +111,8 @@ MmioRead8 ( =20 If 8-bit MMIO register operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -121,9 +130,13 @@ MmioWrite8 ( =20 Flag =3D FilterBeforeMmIoWrite (FilterWidth8, Address, &Value); if (Flag) { - MemoryFence (); - *(volatile UINT8*)Address =3D Value; - MemoryFence (); + if (IsTdxGuest ()) { + TdMmioWrite8 (Address, Value); + } else { + MemoryFence (); + *(volatile UINT8*)Address =3D Value; + MemoryFence (); + } } FilterAfterMmIoWrite (FilterWidth8, Address, &Value); =20 @@ -140,6 +153,8 @@ MmioWrite8 ( If 16-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -157,9 +172,13 @@ MmioRead16 ( ASSERT ((Address & 1) =3D=3D 0); Flag =3D FilterBeforeMmIoRead (FilterWidth16, Address, &Value); if (Flag) { - MemoryFence (); - Value =3D *(volatile UINT16*)Address; - MemoryFence (); + if (IsTdxGuest ()) { + Value =3D TdMmioRead16 (Address); + } else { + MemoryFence (); + Value =3D *(volatile UINT16*)Address; + MemoryFence (); + } } FilterAfterMmIoRead (FilterWidth16, Address, &Value); =20 @@ -176,6 +195,8 @@ MmioRead16 ( If 16-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -195,9 +216,13 @@ MmioWrite16 ( =20 Flag =3D FilterBeforeMmIoWrite (FilterWidth16, Address, &Value); if (Flag) { - MemoryFence (); - *(volatile UINT16*)Address =3D Value; - MemoryFence (); + if (IsTdxGuest ()) { + TdMmioWrite16 (Address, Value); + } else { + MemoryFence (); + *(volatile UINT16*)Address =3D Value; + MemoryFence (); + } } FilterAfterMmIoWrite (FilterWidth16, Address, &Value); =20 @@ -214,6 +239,8 @@ MmioWrite16 ( If 32-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -232,9 +259,13 @@ MmioRead32 ( =20 Flag =3D FilterBeforeMmIoRead (FilterWidth32, Address, &Value); if (Flag) { - MemoryFence (); - Value =3D *(volatile UINT32*)Address; - MemoryFence (); + if (IsTdxGuest ()) { + Value =3D TdMmioRead32 (Address); + } else { + MemoryFence (); + Value =3D *(volatile UINT32*)Address; + MemoryFence (); + } } FilterAfterMmIoRead (FilterWidth32, Address, &Value); =20 @@ -251,6 +282,8 @@ MmioRead32 ( If 32-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -270,9 +303,13 @@ MmioWrite32 ( =20 Flag =3D FilterBeforeMmIoWrite (FilterWidth32, Address, &Value); if (Flag) { - MemoryFence (); - *(volatile UINT32*)Address =3D Value; - MemoryFence (); + if (IsTdxGuest ()) { + TdMmioWrite32 (Address, Value); + } else { + MemoryFence (); + *(volatile UINT32*)Address =3D Value; + MemoryFence (); + } } FilterAfterMmIoWrite (FilterWidth32, Address, &Value); =20 @@ -289,6 +326,8 @@ MmioWrite32 ( If 64-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 64-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to read MMIO registers. + @param Address The MMIO register to read. =20 @return The value read. @@ -307,9 +346,13 @@ MmioRead64 ( =20 Flag =3D FilterBeforeMmIoRead (FilterWidth64, Address, &Value); if (Flag) { - MemoryFence (); - Value =3D *(volatile UINT64*)Address; - MemoryFence (); + if (IsTdxGuest ()) { + Value =3D TdMmioRead64 (Address); + } else { + MemoryFence (); + Value =3D *(volatile UINT64*)Address; + MemoryFence (); + } } FilterAfterMmIoRead (FilterWidth64, Address, &Value); =20 @@ -326,6 +369,8 @@ MmioRead64 ( If 64-bit MMIO register operations are not supported, then ASSERT(). If Address is not aligned on a 64-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_MMIO is invoked to write MMIO registers. + @param Address The MMIO register to write. @param Value The value to write to the MMIO register. =20 @@ -343,9 +388,13 @@ MmioWrite64 ( =20 Flag =3D FilterBeforeMmIoWrite (FilterWidth64, Address, &Value); if (Flag) { - MemoryFence (); - *(volatile UINT64*)Address =3D Value; - MemoryFence (); + if (IsTdxGuest ()) { + TdMmioWrite64 (Address, Value); + } else { + MemoryFence (); + *(volatile UINT64*)Address =3D Value; + MemoryFence (); + } } FilterAfterMmIoWrite (FilterWidth64, Address, &Value); =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibGcc.c index ecf9ed61911f..42b5d5743a4f 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibGcc.c @@ -17,6 +17,7 @@ =20 =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 /** Reads an 8-bit I/O port. @@ -25,7 +26,9 @@ This function must guarantee that all I/O read and write operations are serialized. =20 - If 8-bit I/O port operations are not supported, then ASSERT(). + If 8-bit I/O port operations are not supported, then ASSERT() + + For Td guest TDVMCALL_IO is invoked to read I/O port. =20 @param Port The I/O port to read. =20 @@ -43,7 +46,11 @@ IoRead8 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth8, Port, &Data); if (Flag) { - __asm__ __volatile__ ("inb %w1,%b0" : "=3Da" (Data) : "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + Data =3D TdIoRead8 (Port); + } else { + __asm__ __volatile__ ("inb %w1,%b0" : "=3Da" (Data) : "d" ((UINT16)P= ort)); + } } FilterAfterIoRead (FilterWidth8, Port, &Data); =20 @@ -59,6 +66,8 @@ IoRead8 ( =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -76,7 +85,11 @@ IoWrite8 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth8, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + TdIoWrite8 (Port, Value); + } else { + __asm__ __volatile__ ("outb %b0,%w1" : : "a" (Value), "d" ((UINT16)P= ort)); + } } FilterAfterIoWrite (FilterWidth8, Port, &Value); =20 @@ -93,6 +106,8 @@ IoWrite8 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -111,7 +126,11 @@ IoRead16 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth16, Port, &Data); if (Flag) { + if (IsTdxGuest ()) { + Data =3D TdIoRead16 (Port); + } else { __asm__ __volatile__ ("inw %w1,%w0" : "=3Da" (Data) : "d" ((UINT16)Po= rt)); + } } FilterAfterIoRead (FilterWidth16, Port, &Data); =20 @@ -128,6 +147,8 @@ IoRead16 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -148,7 +169,11 @@ IoWrite16 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth16, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)Por= t)); + if (IsTdxGuest ()) { + TdIoWrite16 (Port, Value); + } else { + __asm__ __volatile__ ("outw %w0,%w1" : : "a" (Value), "d" ((UINT16)P= ort)); + } } FilterAfterIoWrite (FilterWidth16, Port, &Value); =20 @@ -165,6 +190,8 @@ IoWrite16 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -183,7 +210,11 @@ IoRead32 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth32, Port, &Data); if (Flag) { - __asm__ __volatile__ ("inl %w1,%0" : "=3Da" (Data) : "d" ((UINT16)Port= )); + if (IsTdxGuest ()) { + Data =3D TdIoRead32 (Port); + } else { + __asm__ __volatile__ ("inl %w1,%0" : "=3Da" (Data) : "d" ((UINT16)Po= rt)); + } } FilterAfterIoRead (FilterWidth32, Port, &Data); =20 @@ -200,6 +231,8 @@ IoRead32 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -219,7 +252,11 @@ IoWrite32 ( =20 Flag =3D FilterBeforeIoWrite (FilterWidth32, Port, &Value); if (Flag) { - __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Port= )); + if (IsTdxGuest ()) { + TdIoWrite32 (Port, Value); + } else { + __asm__ __volatile__ ("outl %0,%w1" : : "a" (Value), "d" ((UINT16)Po= rt)); + } } FilterAfterIoWrite (FilterWidth32, Port, &Value); =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c b/MdePkg/= Library/BaseIoLibIntrinsic/IoLibInternalTdx.c new file mode 100644 index 000000000000..4c342f6d3873 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdx.c @@ -0,0 +1,690 @@ +/** @file + TDX I/O Library routines. + + Copyright (c) 2020-2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include "BaseIoLibIntrinsicInternal.h" +#include +#include +#include +#include "IoLibTdx.h" + +// Size of TDVMCALL Access, including IO and MMIO +#define TDVMCALL_ACCESS_SIZE_1 1 +#define TDVMCALL_ACCESS_SIZE_2 2 +#define TDVMCALL_ACCESS_SIZE_4 4 +#define TDVMCALL_ACCESS_SIZE_8 8 + +// Direction of TDVMCALL Access, including IO and MMIO +#define TDVMCALL_ACCESS_READ 0 +#define TDVMCALL_ACCESS_WRITE 1 + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ) +{ + return TdxIsEnabled (); +} + + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return (UINT8) Val; +} + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 1) =3D=3D 0); + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return (UINT16) Val; +} + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 3) =3D=3D 0); + + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCES= S_READ, Port, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return (UINT32) Val; +} + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + UINT64 Status; + UINT64 Val; + + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return Value; +} + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 1) =3D=3D 0); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return Value; +} + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Port & 3) =3D=3D 0); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_IO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACCES= S_WRITE, Port, Val, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + return Value; +} + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACC= ESS_READ, Address, 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64*) Address; + } + MemoryFence (); + + return (UINT8) Value; +} + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Value + ) +{ + UINT64 Val; + UINT64 Status; + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_1, TDVMCALL_ACC= ESS_WRITE, Address, Val, 0); + if (Status !=3D 0) { + *(volatile UINT8*) Address =3D Value; + } + MemoryFence (); + + return Value; +} + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACC= ESS_READ, Address, 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64*) Address; + } + MemoryFence (); + + return (UINT16) Value; +} + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Value + ) +{ + UINT64 Val; + UINT64 Status; + + ASSERT ((Address & 1) =3D=3D 0); + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_2, TDVMCALL_ACC= ESS_WRITE, Address, Val, 0); + if (Status !=3D 0) { + *(volatile UINT16*) Address =3D Value; + } + MemoryFence (); + + return Value; +} + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACC= ESS_READ, Address, 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64*)Address; + } + MemoryFence (); + + return (UINT32)Value; +} + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Value + ) +{ + UINT64 Val; + UINT64 Status; + + ASSERT ((Address & 3) =3D=3D 0); + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_4, TDVMCALL_ACC= ESS_WRITE, Address, Val, 0); + if (Status !=3D 0) { + *(volatile UINT32*)Address =3D Value; + } + MemoryFence (); + + return Value; +} + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ) +{ + UINT64 Value; + UINT64 Status; + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACC= ESS_READ, Address, 0, &Value); + if (Status !=3D 0) { + Value =3D *(volatile UINT64*)Address; + } + MemoryFence (); + + return Value; +} + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + UINT64 Status; + UINT64 Val; + + ASSERT ((Address & 7) =3D=3D 0); + + Address |=3D TdSharedPageMask (); + + MemoryFence (); + Val =3D Value; + Status =3D TdVmCall (TDVMCALL_MMIO, TDVMCALL_ACCESS_SIZE_8, TDVMCALL_ACC= ESS_WRITE, Address, Val, 0); + if (Status !=3D 0) { + *(volatile UINT64*)Address =3D Value; + } + MemoryFence (); + return Value; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT8 *Buf8; + UINTN Index; + + Buf8 =3D (UINT8 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf8[Index] =3D TdIoRead8 (Port); + } +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT8 *Buf8; + UINTN Index; + + Buf8 =3D (UINT8 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite8 (Port, Buf8[Index]); + } +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead16 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT16 *Buf16; + UINTN Index; + + Buf16 =3D (UINT16 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf16[Index] =3D TdIoRead16 (Port); + } +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT16 *Buf16; + UINTN Index; + + Buf16 =3D (UINT16 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite16 (Port, Buf16[Index]); + } +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead32 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + UINT32 *Buf32; + UINTN Index; + + Buf32 =3D (UINT32 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + Buf32[Index] =3D TdIoRead32 (Port); + } +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + UINT32 *Buf32; + UINTN Index; + + Buf32 =3D (UINT32 *) Buffer; + for (Index =3D 0; Index < Count; Index++) { + TdIoWrite32 (Port, Buf32[Index]); + } +} + diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c b/Mde= Pkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c new file mode 100644 index 000000000000..f518d8ffd825 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibInternalTdxNull.c @@ -0,0 +1,499 @@ +/** @file + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + + +#include +#include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ) +{ + return FALSE; +} + + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Val + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead8 is invoked to read the I/O port fifo. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite8 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead16 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite16 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoRead32 is invoked to read data from the I/O port. + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + ASSERT (FALSE); +} + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + In TDX a serial of TdIoWrite32 is invoked to write data to the I/O port. + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ) +{ + ASSERT (FALSE); +} diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibMsc.c index d2bc5f527cf6..4d7945ae496f 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibMsc.c @@ -16,6 +16,7 @@ =20 =20 #include "BaseIoLibIntrinsicInternal.h" +#include "IoLibTdx.h" =20 // // Microsoft Visual Studio 7.1 Function Prototypes for I/O Intrinsics. @@ -54,6 +55,8 @@ void _ReadWriteBarrier (void); =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -70,9 +73,13 @@ IoRead8 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth8, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D (UINT8)_inp ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead8 (Port); + } else { + _ReadWriteBarrier (); + Value =3D (UINT8)_inp ((UINT16)Port); + _ReadWriteBarrier (); + } } FilterAfterIoRead (FilterWidth8, Port, &Value); =20 @@ -88,6 +95,8 @@ IoRead8 ( =20 If 8-bit I/O port operations are not supported, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -105,9 +114,13 @@ IoWrite8 ( =20 Flag =3D FilterBeforeIoWrite(FilterWidth8, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - (UINT8)_outp ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite8 (Port, Value); + } else { + _ReadWriteBarrier (); + (UINT8)_outp ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } FilterAfterIoWrite (FilterWidth8, Port, &Value); =20 @@ -124,6 +137,8 @@ IoWrite8 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -142,9 +157,13 @@ IoRead16 ( =20 Flag =3D FilterBeforeIoRead (FilterWidth16, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D _inpw ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead16 (Port); + } else { + _ReadWriteBarrier (); + Value =3D _inpw ((UINT16)Port); + _ReadWriteBarrier (); + } } FilterBeforeIoRead (FilterWidth16, Port, &Value); =20 @@ -161,6 +180,8 @@ IoRead16 ( If 16-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 16-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -180,9 +201,13 @@ IoWrite16 ( =20 Flag =3D FilterBeforeIoWrite(FilterWidth16, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - _outpw ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite16 (Port, Value); + } else { + _ReadWriteBarrier (); + _outpw ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } FilterAfterIoWrite (FilterWidth16, Port, &Value); =20 @@ -199,6 +224,8 @@ IoWrite16 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to read I/O port. + @param Port The I/O port to read. =20 @return The value read. @@ -217,9 +244,13 @@ IoRead32 ( =20 Flag =3D FilterBeforeIoRead(FilterWidth32, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - Value =3D _inpd ((UINT16)Port); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + Value =3D TdIoRead32 (Port); + } else { + _ReadWriteBarrier (); + Value =3D _inpd ((UINT16)Port); + _ReadWriteBarrier (); + } } FilterAfterIoRead (FilterWidth32, Port, &Value); =20 @@ -236,6 +267,8 @@ IoRead32 ( If 32-bit I/O port operations are not supported, then ASSERT(). If Port is not aligned on a 32-bit boundary, then ASSERT(). =20 + For Td guest TDVMCALL_IO is invoked to write I/O port. + @param Port The I/O port to write. @param Value The value to write to the I/O port. =20 @@ -255,9 +288,13 @@ IoWrite32 ( =20 Flag =3D FilterBeforeIoWrite(FilterWidth32, Port, &Value); if (Flag) { - _ReadWriteBarrier (); - _outpd ((UINT16)Port, Value); - _ReadWriteBarrier (); + if (IsTdxGuest ()) { + TdIoWrite32 (Port, Value); + } else { + _ReadWriteBarrier (); + _outpd ((UINT16)Port, Value); + _ReadWriteBarrier (); + } } FilterAfterIoWrite (FilterWidth32, Port, &Value); =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h b/MdePkg/Library/= BaseIoLibIntrinsic/IoLibTdx.h new file mode 100644 index 000000000000..3aad197d3b39 --- /dev/null +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibTdx.h @@ -0,0 +1,411 @@ +/** @file + Header file for Tdx IO library. + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef IOLIB_TDX_H_ +#define IOLIB_TDX_H_ + +/** + Check if it is Tdx guest. + + @return TRUE It is Tdx guest + @return FALSE It is not Tdx guest + +**/ +BOOLEAN +EFIAPI +IsTdxGuest ( + VOID + ); + + +/** + Reads an 8-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdIoRead8 ( + IN UINTN Port + ); + +/** + Reads a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdIoRead16 ( + IN UINTN Port + ); + +/** + Reads a 32-bit I/O port. + + TDVMCALL_IO is invoked to read I/O port. + + @param Port The I/O port to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdIoRead32 ( + IN UINTN Port + ); + +/** + Writes an 8-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT8 +EFIAPI +TdIoWrite8 ( + IN UINTN Port, + IN UINT8 Value + ); + +/** + Writes a 16-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT16 +EFIAPI +TdIoWrite16 ( + IN UINTN Port, + IN UINT16 Value + ); + +/** + Writes a 32-bit I/O port. + + TDVMCALL_IO is invoked to write I/O port. + + @param Port The I/O port to write. + @param Value The value to write to the I/O port. + + @return The value written the I/O port. + +**/ +UINT32 +EFIAPI +TdIoWrite32 ( + IN UINTN Port, + IN UINT32 Value + ); + +/** + Reads an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT8 +EFIAPI +TdMmioRead8 ( + IN UINTN Address + ); + +/** + Writes an 8-bit MMIO register. + + TDVMCALL_MMIO is invoked to read write registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT8 +EFIAPI +TdMmioWrite8 ( + IN UINTN Address, + IN UINT8 Val + ); + +/** + Reads a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT16 +EFIAPI +TdMmioRead16 ( + IN UINTN Address + ); + +/** + Writes a 16-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT16 +EFIAPI +TdMmioWrite16 ( + IN UINTN Address, + IN UINT16 Val + ); + +/** + Reads a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT32 +EFIAPI +TdMmioRead32 ( + IN UINTN Address + ); + +/** + Writes a 32-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + + @return Value. + +**/ +UINT32 +EFIAPI +TdMmioWrite32 ( + IN UINTN Address, + IN UINT32 Val + ); + +/** + Reads a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to read MMIO registers. + + @param Address The MMIO register to read. + + @return The value read. + +**/ +UINT64 +EFIAPI +TdMmioRead64 ( + IN UINTN Address + ); + +/** + Writes a 64-bit MMIO register. + + TDVMCALL_MMIO is invoked to write MMIO registers. + + @param Address The MMIO register to write. + @param Value The value to write to the MMIO register. + +**/ +UINT64 +EFIAPI +TdMmioWrite64 ( + IN UINTN Address, + IN UINT64 Value + ); + +/** + Reads an 8-bit I/O port fifo into a block of memory in Tdx. + + Reads the 8-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo in Tdx. + + Writes the 8-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 16-bit I/O port fifo into a block of memory in Tdx. + + Reads the 16-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 16-bit I/O port fifo in Tdx. + + Writes the 16-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Reads a 32-bit I/O port fifo into a block of memory in Tdx. + + Reads the 32-bit I/O fifo port specified by Port. + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +TdIoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 32-bit I/O port fifo in Tdx. + + Writes the 32-bit I/O fifo port specified by Port. + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to retrieve the write data from. + +**/ +VOID +EFIAPI +TdIoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + IN VOID *Buffer + ); + +#endif diff --git a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm b/MdePkg/= Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm index 106f8881c55c..7f426495bbe3 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm +++ b/MdePkg/Library/BaseIoLibIntrinsic/X64/IoFifoSev.nasm @@ -10,6 +10,79 @@ DEFAULT REL SECTION .text =20 +extern ASM_PFX(TdIoReadFifo8) +extern ASM_PFX(TdIoReadFifo16) +extern ASM_PFX(TdIoReadFifo32) +extern ASM_PFX(TdIoWriteFifo8) +extern ASM_PFX(TdIoWriteFifo16) +extern ASM_PFX(TdIoWriteFifo32) + +;-------------------------------------------------------------------------= ----- +; Check whether we need to unroll the String I/O in Tdx guest +; +; Return // eax (1 - unroll, 0 - no unroll) +;-------------------------------------------------------------------------= ----- +global ASM_PFX(TdxNoRepIo) +ASM_PFX(TdxNoRepIo): + ; CPUID clobbers ebx, ecx and edx + push rbx + push rcx + push rdx + + ; + ; CPUID (0) + ; + mov eax, 0 + cpuid + cmp ebx, 0x756e6547 ; "Genu" + jne @NoTdx + cmp edx, 0x49656e69 ; "ineI" + jne @NoTdx + cmp ecx, 0x6c65746e ; "ntel" + jne @NoTdx + + ; + ; CPUID (1) + ; + mov eax, 1 + cpuid + test ecx, 0x80000000 + jz @NoTdx + + ; + ; CPUID[0].EAX >=3D 0x21? + ; + mov eax, 0 + cpuid + cmp eax, 0x21 + jl @NoTdx + + ; + ; CPUID (0x21,0) + ; + mov eax, 0x21 + mov ecx, 0 + cpuid + + cmp ebx, 0x65746E49 ; "Inte" + jne @NoTdx + cmp edx, 0x5844546C ; "lTDX" + jne @NoTdx + cmp ecx, 0x20202020 ; " " + jne @NoTdx + + mov rax, 1 + jmp @ExitTdxNoRepIo + +@NoTdx: + mov rax, 0 + +@ExitTdxNoRepIo: + pop rdx + pop rcx + pop rbx + ret + ;-------------------------------------------------------------------------= ----- ; Check whether we need to unroll the String I/O in SEV guest ; @@ -75,6 +148,16 @@ ASM_PFX(SevNoRepIo): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoReadFifo8) ASM_PFX(IoReadFifo8): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoReadFifo8 + + sub rsp, 020h + call TdIoReadFifo8 + add rsp, 020h + ret + +@NonTd_IoReadFifo8: xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -111,6 +194,16 @@ ASM_PFX(IoReadFifo8): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoReadFifo16) ASM_PFX(IoReadFifo16): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoReadFifo16 + + sub rsp, 020h + call TdIoReadFifo16 + add rsp, 020h + ret + +@NonTd_IoReadFifo16: xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -147,6 +240,16 @@ ASM_PFX(IoReadFifo16): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoReadFifo32) ASM_PFX(IoReadFifo32): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoReadFifo32 + + sub rsp, 020h + call TdIoReadFifo32 + add rsp, 020h + ret + +@NonTd_IoReadFifo32: xchg rcx, rdx xchg rdi, r8 ; rdi: buffer address; r8: save rdi =20 @@ -183,6 +286,16 @@ ASM_PFX(IoReadFifo32): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoWriteFifo8) ASM_PFX(IoWriteFifo8): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoWriteFifo8 + + sub rsp, 020h + call TdIoWriteFifo8 + add rsp, 020h + ret + +@NonTd_IoWriteFifo8: xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 @@ -219,6 +332,16 @@ ASM_PFX(IoWriteFifo8): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoWriteFifo16) ASM_PFX(IoWriteFifo16): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoWriteFifo16 + + sub rsp, 020h + call TdIoWriteFifo16 + add rsp, 020h + ret + +@NonTd_IoWriteFifo16: xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 @@ -255,6 +378,16 @@ ASM_PFX(IoWriteFifo16): ;-------------------------------------------------------------------------= ----- global ASM_PFX(IoWriteFifo32) ASM_PFX(IoWriteFifo32): + call ASM_PFX(TdxNoRepIo) + test rax, rax + jz @NonTd_IoWriteFifo32 + + sub rsp, 020h + call TdIoWriteFifo32 + add rsp, 020h + ret + +@NonTd_IoWriteFifo32: xchg rcx, rdx xchg rsi, r8 ; rsi: buffer address; r8: save rsi =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79163): https://edk2.groups.io/g/devel/message/79163 Mute This Topic: https://groups.io/mt/84837896/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79164+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79164+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769465; cv=none; d=zohomail.com; s=zohoarc; b=D8mW5B2UtDKFbHhTG0wfXvg0sJ+9Ajrk0W2tMsmKzfBel4mY/Go0Ged8NnA9FxKbjmYL5KDKPw8jTqcD/c4ZX4xMa5MFt4q1oo//wiiUnPuH34leQ+5M56QWuTC/0B8DXXPLWXWz2z7bX00oxjQb22xAGoMHeyRBflIneN+pBAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769465; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=6TseOXIgdbDVXLf8xAaatE8T3f9kNcu94AAZCKe21zs=; b=dBvQsVXZNLWuW4xlgNfrcvx05s3myirmB5WYjPGJtEat6nNJi5Dq0bltAlGjO3a6WvruIMIPQJm8YgjOoHN1zHqYLwDi8l2w55L/9sZeV5RwsHt/YRctZ3pBRxh/mZKkaMWoijVqwI9hR39fv33boOS4EiZJuAOdf9BH7YY5Wss= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79164+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769465396987.026290137058; Thu, 12 Aug 2021 04:57:45 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fSH2YY1788612xhzHAPxeUwa; Thu, 12 Aug 2021 04:57:44 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:44 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322209" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322209" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:43 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433665" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:41 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Eric Dong , Ray Ni , Rahul Kumar , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 08/23] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib Date: Thu, 12 Aug 2021 19:56:47 +0800 Message-Id: <2285a62534d0ec4e19051d1ee9236fea7d87ed9e.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: cIbkubIpIKsBdbnyH884OgxZx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769464; bh=gpnKysz2yHSPaMkIyuQiWHXypFARzXw+SuDVLoIdP8c=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=CCEo62RXLaF9s/8yCbm8htQHrOYKBJ5cvWd7WzbHBMxaBUAIh1XhsAtE165j5HaZ9PP 0RZGOUQ3f06zncrd1M0BFvRYHqUkZ1db9k2fhqBjVGIBIzzSfyHLg4sdi7NTjxilbDnry uRelYZbnjwdN6yUrKYp8CMyDAS7mnyR/Za0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769465852100002 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed directly from/to CPU. Some should be accessed via explicit requests from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the help of TdxLib. Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 172 +++++++++++++++++- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf | 2 + UefiCpuPkg/UefiCpuPkg.dsc | 2 + 3 files changed, 168 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index cdcbca046191..793ea61b50fa 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -23,11 +23,166 @@ #include #include #include +#include +#include +#include =20 // // Library internal functions // =20 +/** + Some MSRs in TDX are directly read/write from/to CPU. + + @param MsrIndex Index of the MSR + @retval TRUE MSR direct read/write from/to CPU. + @retval FALSE MSR not direct read/write from/to CPU. + +**/ +BOOLEAN +EFIAPI +AccessMsrNative ( + IN UINT32 MsrIndex + ) +{ + switch (MsrIndex) { + case MSR_IA32_X2APIC_TPR: + case MSR_IA32_X2APIC_PPR: + case MSR_IA32_X2APIC_EOI: + case MSR_IA32_X2APIC_ISR0: + case MSR_IA32_X2APIC_ISR1: + case MSR_IA32_X2APIC_ISR2: + case MSR_IA32_X2APIC_ISR3: + case MSR_IA32_X2APIC_ISR4: + case MSR_IA32_X2APIC_ISR5: + case MSR_IA32_X2APIC_ISR6: + case MSR_IA32_X2APIC_ISR7: + case MSR_IA32_X2APIC_TMR0: + case MSR_IA32_X2APIC_TMR1: + case MSR_IA32_X2APIC_TMR2: + case MSR_IA32_X2APIC_TMR3: + case MSR_IA32_X2APIC_TMR4: + case MSR_IA32_X2APIC_TMR5: + case MSR_IA32_X2APIC_TMR6: + case MSR_IA32_X2APIC_TMR7: + case MSR_IA32_X2APIC_IRR0: + case MSR_IA32_X2APIC_IRR1: + case MSR_IA32_X2APIC_IRR2: + case MSR_IA32_X2APIC_IRR3: + case MSR_IA32_X2APIC_IRR4: + case MSR_IA32_X2APIC_IRR5: + case MSR_IA32_X2APIC_IRR6: + case MSR_IA32_X2APIC_IRR7: + return TRUE; + default: + break; + } + return FALSE; +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 64-bit Value of MSR. + +**/ +UINT64 +EFIAPI +ReadMsrReg64 ( + IN UINT32 MsrIndex + ) +{ + UINT64 Val; + UINT64 Status; + if (!AccessMsrNative (MsrIndex) && TdxIsEnabled ()) { + Status =3D TdVmCall (TDVMCALL_RDMSR, (UINT64) MsrIndex, 0, 0, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + Val =3D AsmReadMsr64 (MsrIndex); + } + return Val; +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Val Value to be written to the MSR + +**/ +VOID +EFIAPI +WriteMsrReg64 ( + IN UINT32 MsrIndex, + IN UINT64 Val + ) +{ + UINT64 Status; + if (!AccessMsrNative (MsrIndex) && TdxIsEnabled ()) { + Status =3D TdVmCall (TDVMCALL_WRMSR, (UINT64) MsrIndex, Val, 0, 0, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + AsmWriteMsr64 (MsrIndex, Val); + } +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 32-bit Value of MSR. + +**/ +UINT32 +EFIAPI +ReadMsrReg32 ( + IN UINT32 MsrIndex + ) +{ + UINT64 Val; + UINT64 Status; + if (!AccessMsrNative (MsrIndex) && TdxIsEnabled ()) { + Status =3D TdVmCall (TDVMCALL_RDMSR, (UINT64) MsrIndex, 0, 0, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + Val =3D AsmReadMsr32 (MsrIndex); + } + return (UINT32)(UINTN) Val; +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Val Value to be written to the MSR + +**/ +VOID +EFIAPI +WriteMsrReg32 ( + IN UINT32 MsrIndex, + IN UINT32 Val + ) +{ + UINT64 Status; + if (!AccessMsrNative (MsrIndex) && TdxIsEnabled ()) { + Status =3D TdVmCall (TDVMCALL_WRMSR, (UINT64) MsrIndex, (UINT64) Val, = 0, 0, 0); + if (Status !=3D 0) { + DEBUG((DEBUG_ERROR, "WriteMsrReg32 returned failure. Status=3D0x%llx= \n", Status)); + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + AsmWriteMsr32 (MsrIndex, Val); + } +} + /** Determine if the CPU supports the Local APIC Base Address MSR. =20 @@ -77,7 +232,7 @@ GetLocalApicBaseAddress ( return PcdGet32 (PcdCpuLocalApicBaseAddress); } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D ReadMsrReg64 (MSR_IA32_APIC_BASE); =20 return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHi, 32)) + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); @@ -108,12 +263,12 @@ SetLocalApicBaseAddress ( return; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D ReadMsrReg64 (MSR_IA32_APIC_BASE); =20 ApicBaseMsr.Bits.ApicBase =3D (UINT32) (BaseAddress >> 12); ApicBaseMsr.Bits.ApicBaseHi =3D (UINT32) (RShiftU64((UINT64) BaseAddress= , 32)); =20 - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + WriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } =20 /** @@ -153,7 +308,7 @@ ReadLocalApicReg ( ASSERT (MmioOffset !=3D XAPIC_ICR_HIGH_OFFSET); =20 MsrIndex =3D (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS; - return AsmReadMsr32 (MsrIndex); + return ReadMsrReg32 (MsrIndex); } } =20 @@ -202,7 +357,7 @@ WriteLocalApicReg ( // Use memory fence here to force the serializing semantics to be cons= isent with xAPIC mode. // MemoryFence (); - AsmWriteMsr32 (MsrIndex, Value); + WriteMsrReg32 (MsrIndex, Value); } } =20 @@ -309,7 +464,7 @@ GetApicMode ( return LOCAL_APIC_MODE_XAPIC; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D ReadMsrReg64 (MSR_IA32_APIC_BASE); // // Local APIC should have been enabled // @@ -350,13 +505,14 @@ SetApicMode ( =20 CurrentMode =3D GetApicMode (); if (CurrentMode =3D=3D LOCAL_APIC_MODE_XAPIC) { + switch (ApicMode) { case LOCAL_APIC_MODE_XAPIC: break; case LOCAL_APIC_MODE_X2APIC: - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D ReadMsrReg64 (MSR_IA32_APIC_BASE); ApicBaseMsr.Bits.EXTD =3D 1; - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + WriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); break; default: ASSERT (FALSE); diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf b= /UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf index 1e2a4f8b790f..2367a3349008 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.inf @@ -39,6 +39,8 @@ IoLib PcdLib UefiCpuLib + TdxLib + TdxProbeLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds ## SOMETIMES= _CONSUMES diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 699c91626bd8..47768b10d5be 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -61,6 +61,8 @@ TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf + TdxProbeLib|MdePkg/Library/TdxProbeLib/TdxProbeLib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf =20 [LibraryClasses.common.SEC] PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79164): https://edk2.groups.io/g/devel/message/79164 Mute This Topic: https://groups.io/mt/84837898/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79165+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79165+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769467; cv=none; d=zohomail.com; s=zohoarc; b=R8nubtZXq8/qmgkQzrJuobVLx34nS/nUAzsn0t1OjNd3ZpN0xzfCK3Rz/jSSYw1+qw9xK4krx/Yd+LrT/ZJUEhd57SWQ0DARVoz5E1KLKMirnaDzW80UarON8OmLaodVyDv01Vl8iusdacNP3vGsfJfsQxnJ5vNgwDhtbq3OgMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769467; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NNq6AA6EM7A9QKE7BBvGaTix3AEG73ZobkQQCz6xO3M=; b=eSSFt5fN80np+EQXf+QdF4ljOV98zl6rvJBZuJ0EXV0PhwvwHmwN41u2ZVM5Fw7y+vP1Wkac10O3ROnub0uXdmqlfzslWIMVxhZfmIrB7XRReXT6yVihxkSVDGv4gY+tILo9SKZ/Vn2ApaUFZKjbdtpdHOm7WZNRL8BNd42ryqw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79165+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769467623158.85568315702199; Thu, 12 Aug 2021 04:57:47 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XK7pYY1788612xycXKvgi9jp; Thu, 12 Aug 2021 04:57:47 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.21190.1628769444911593052 for ; Thu, 12 Aug 2021 04:57:46 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215322234" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215322234" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:46 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433687" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:43 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH 09/23] UefiCpuPkg: Add VmTdExitLibNull Date: Thu, 12 Aug 2021 19:56:48 +0800 Message-Id: <49363decf945abf16d1ce18049e81a509a795062.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: wqUCO04k5bnmuzqcpFUGRvgrx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769467; bh=eirlm0fsacbZm2iHjHdPE3+D3fAn8hWQ+oc7NGo+HCg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ajux77i+CsRarRDcJd/a25aZkBYW5prhcayrKSqkLrhncsiaBrb3fQzuNhL2aBTzCp4 ZLWnJ12v5SmD2nq9AQaeDBQE729QBfGkaNplEdAFTG7W6v+6FTC1x79H3KbJfjfOJw5CS 0LLt0YJyXo3NneWv8F0DCgdce1gtveng0nE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769468101100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 VmTdExitLib performs the necessary processing to handle a #VE exception. VmTdExitLibNull is a NULL instance of VmTdExitLib which provides a default limited interface. A full feature version of VmTdExitLib should be created later (for example in OvmfPkg). PcdTdxIsEnabled indicates if Tdx is enabled. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Min Xu --- UefiCpuPkg/Include/Library/VmTdExitLib.h | 47 +++++++++++++++++++ .../Library/VmTdExitLibNull/VmTdExitLibNull.c | 37 +++++++++++++++ .../VmTdExitLibNull/VmTdExitLibNull.inf | 34 ++++++++++++++ UefiCpuPkg/UefiCpuPkg.dec | 9 ++++ UefiCpuPkg/UefiCpuPkg.dsc | 2 + 5 files changed, 129 insertions(+) create mode 100644 UefiCpuPkg/Include/Library/VmTdExitLib.h create mode 100644 UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.c create mode 100644 UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf diff --git a/UefiCpuPkg/Include/Library/VmTdExitLib.h b/UefiCpuPkg/Include/= Library/VmTdExitLib.h new file mode 100644 index 000000000000..a55a76dc7a30 --- /dev/null +++ b/UefiCpuPkg/Include/Library/VmTdExitLib.h @@ -0,0 +1,47 @@ +/** @file + Public header file for the VMTDEXIT Support library class. + + This library class defines some routines used when invoking the VMEXIT + instruction in support of VMX and TDX to handle #VE exceptions. + + Copyright (c) 2020 - 2021, Intel Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef VMTD_EXIT_LIB_H_ +#define VMTD_EXIT_LIB_H_ + +#include +#include +#include + +#define VE_EXCEPTION 20 + +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + The base library function returns an error equal to VE_EXCEPTION, + to be propagated to the standard exception handling stack. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + +#endif diff --git a/UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.c b/UefiCpu= Pkg/Library/VmTdExitLibNull/VmTdExitLibNull.c new file mode 100644 index 000000000000..a632abfab498 --- /dev/null +++ b/UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.c @@ -0,0 +1,37 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include + +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + *ExceptionType =3D VE_EXCEPTION; + + return EFI_UNSUPPORTED; +} diff --git a/UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf b/UefiC= puPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf new file mode 100644 index 000000000000..ae9af1b7f56b --- /dev/null +++ b/UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf @@ -0,0 +1,34 @@ +## @file +# VMTDEXIT Support Library. +# +# Copyright (c) 2020, Intel Inc. All rights reserved.
+# Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VmTdExitLibNull + FILE_GUID =3D 79BD5323-6CF4-4ECF-A132-F7D31EEADC1E + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VmTdExitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 IA32 +# + +[Sources.common] + VmTdExitLibNull.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 62acb291f309..fdc7f9ff48e9 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -62,6 +62,9 @@ ## @libraryclass Provides function for loading microcode. MicrocodeLib|Include/Library/MicrocodeLib.h =20 + ## @libraryclass Provides function to support VMTDEXIT processing. + VmgExitLib|Include/Library/VmTdExitLib.h + [Guids] gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} @@ -396,5 +399,11 @@ # @Prompt SEV-ES Status gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016 =20 + ## This dynamic PCD indicates whether Intel TDX is enabled + # TRUE - Intel TDX is enabled + # FALSE - Intel TDX is not enabled + # @Prompt Intel TDX Status + gUefiCpuPkgTokenSpaceGuid.PcdTdxIsEnabled|FALSE|BOOLEAN|0x60000017 + [UserExtensions.TianoCore."ExtraFiles"] UefiCpuPkgExtra.uni diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 47768b10d5be..a7853f6f6097 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -60,6 +60,7 @@ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf MicrocodeLib|UefiCpuPkg/Library/MicrocodeLib/MicrocodeLib.inf TdxProbeLib|MdePkg/Library/TdxProbeLib/TdxProbeLib.inf TdxLib|MdePkg/Library/TdxLib/TdxLib.inf @@ -160,6 +161,7 @@ UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/StandaloneMmCpuFeaturesLib.inf UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf UefiCpuPkg/SecCore/SecCore.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79165): https://edk2.groups.io/g/devel/message/79165 Mute This Topic: https://groups.io/mt/84837899/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79166+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79166+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769475; cv=none; d=zohomail.com; s=zohoarc; b=eOXHT+1ISpiuXfnAW0UQ/v7zHBOTCFntPwhr7DHQos+QgSvc3NvxOEeNivB612TR+8MHLbAIePJ4KLfcj6y7plb4ha+Y++dN09xxUU/2xTNaNZnpOEMGszAHL3RIZteOgIl6mPzmc7Ts9Hoh9QtZeKvL8s96t9TUX0kAtuNEeEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769475; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=QxOxkzH0KxrOEX+9BecDEWhjjFNYJ4dWCdqKNlomrhM=; b=epVFhCHxYNNnSHMlr0Qd8qJB73DU5GJUDE5Urhl+zdr+5H5G1F5YaWCRnFV0dD+oTHDJEiwJwoEZQ+73QwkwntiwbiZuP94//qmM5ZlZeZ7MBqaqGtlawMWBimgMDJ39P+X3XXIqdKsr0wJj4waM/WraFv6gBquoJPcSIPZS4N0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79166+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769475474667.646146513426; Thu, 12 Aug 2021 04:57:55 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4KEPYY1788612xXOcK14tHFh; Thu, 12 Aug 2021 04:57:55 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.21136.1628769474200055695 for ; Thu, 12 Aug 2021 04:57:54 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215065565" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215065565" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:53 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433710" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:46 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 10/23] OvmfPkg: Prepare OvmfPkg to use the VmTdExitLib library Date: Thu, 12 Aug 2021 19:56:49 +0800 Message-Id: <34ca962070029434d1ebf4834d99391f72c49bc6.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: VSSZ0neozoMWlUvvq8gcckyXx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769475; bh=ydS50AeHp8o2UsPK+zMwy0U3ZaD/wYihDq8UQhjINaY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=AuyYph2ulmX7uQsRPq9Mw+UNbmjBbA2uYZ0OqDDEjziYxkH78gjxto8tFLJFXapBOGr iXgchKer79Tkftvt7sXM+dcuB0+/JAPNB6WFbotSvAWuLULXbu/YUto6XgkCA5HSMHFfG E+iWYnKvA+/iRkV/iURyVnCi/HyLfJTStAk= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769476685100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Various CpuExceptionHandlerLib libraries will updated to use the new VmTdExitLib library. To prevent any build breakage, update the OvmfPkg DSC files that use a form of the CpuExceptionHandlerLib library to include the VmTdExitLib library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/OvmfXen.dsc | 1 + 4 files changed, 4 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index d1d92c97bae3..1e1765060e3f 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -243,6 +243,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a467ab7090fb..2eadb51683c9 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -247,6 +247,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index e56b83d95e09..3376c4f4c2f9 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -247,6 +247,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf + VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 3c1ca6bfd493..d8d559dacca6 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -227,6 +227,7 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf =20 [LibraryClasses.common.SEC] QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79166): https://edk2.groups.io/g/devel/message/79166 Mute This Topic: https://groups.io/mt/84837901/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79167+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79167+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769476; cv=none; d=zohomail.com; s=zohoarc; b=WWj4zxA1j7FuaaqCRwI/9yvq8jsrQL3M2XM3E7bs/wGbRFLT2YKrt/sxOawfsRmQ+uVf2M+8KEjSi9jmEpGVoq+doAT4OMT/xJSf7wW76WKfCS8SGAc33OfOiIftZn09dGh2803/x23LKcpLLkWFBRv1rGFnJVAxBruV/W3ps18= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769476; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=OYghdv3i98IijIYqPbMT3TWA1fXDHZQHAzOAII5xEbg=; b=fajMzHcEQe6XqYNnwTLCM4WX/cyZjYmKKMPSEMjzaYrJ8mhJqMHvb6T5bpW8zoLw1UloKJIOZnh6arjUMHfkX/jHXrWUuyORQhrbfEGoXk6/UPxOqExqH7IJ82CRZPfUDCIj0dD6aFr8l39fLUb+HnAKqsAG2PqzeY6KYnVtI/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79167+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769476351265.5149848845293; Thu, 12 Aug 2021 04:57:56 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id WbDnYY1788612xMReVPwEvcc; Thu, 12 Aug 2021 04:57:56 -0700 X-Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.21136.1628769474200055695 for ; Thu, 12 Aug 2021 04:57:55 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="215065570" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="215065570" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:54 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433729" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:52 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jiewen Yao , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Tom Lendacky Subject: [edk2-devel] [PATCH 11/23] OvmfPkg: Implement library support for VmTdExitLib in Ovmf Date: Thu, 12 Aug 2021 19:56:50 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: X8ia8BJ93SyoHTj60ZuvNrYyx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769476; bh=r8Amh6jssFeusrRsAI8UO3EZ1mv/SLvOzlzZ7t0Ruz4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=l7ojZHXNj4/BZa616VUynvXuYa2HuD9meNPRxORbY34uHrZiG5kdUFa7DR7PpEDHKWd YpCGT+ROmgcwOnT4a9yCJVtDytbBkdsg9Eluu4viwaO2axdNvvvlOKtG16u5apPMIi6es D4LRgenfMAYBXGLg608Oj5paf3iLzR/tp7Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769476751100004 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 The base VmTdExitLib library provides a default limited interface. As it does not provide full support, create an OVMF version of this library to begin the process of providing full support of TDX within OVMF. PcdIgnoreVeHalt is created in OvmfPkg.dec to ignore the VE halt in TDX. Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Library/VmTdExitLib/VmTdExitLib.inf | 41 ++ .../Library/VmTdExitLib/VmTdExitVeHandler.c | 515 ++++++++++++++++++ OvmfPkg/OvmfPkg.dec | 3 + 3 files changed, 559 insertions(+) create mode 100644 OvmfPkg/Library/VmTdExitLib/VmTdExitLib.inf create mode 100644 OvmfPkg/Library/VmTdExitLib/VmTdExitVeHandler.c diff --git a/OvmfPkg/Library/VmTdExitLib/VmTdExitLib.inf b/OvmfPkg/Library/= VmTdExitLib/VmTdExitLib.inf new file mode 100644 index 000000000000..0d9430034330 --- /dev/null +++ b/OvmfPkg/Library/VmTdExitLib/VmTdExitLib.inf @@ -0,0 +1,41 @@ +## @file +# VMTDEXIT Support Library. +# +# Copyright (c) 2020, Intel Inc. All rights reserved.
+# Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VmTdExitLib + FILE_GUID =3D b29eabb0-f9a3-11ea-8b6e-0800200c9a66 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VmTdExitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources.common] + VmTdExitVeHandler.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + TdxLib + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdIgnoreVeHalt + + diff --git a/OvmfPkg/Library/VmTdExitLib/VmTdExitVeHandler.c b/OvmfPkg/Libr= ary/VmTdExitLib/VmTdExitVeHandler.c new file mode 100644 index 000000000000..6e41261cd108 --- /dev/null +++ b/OvmfPkg/Library/VmTdExitLib/VmTdExitVeHandler.c @@ -0,0 +1,515 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include + +typedef union { + struct { + UINT32 Eax; + UINT32 Edx; + } Regs; + UINT64 Val; +} MSR_DATA; + +typedef union { + UINT8 Val; + struct { + UINT8 B:1; + UINT8 X:1; + UINT8 R:1; + UINT8 W:1; + } Bits; +} REX; + +typedef union { + UINT8 Val; + struct { + UINT8 Rm:3; + UINT8 Reg:3; + UINT8 Mod:2; + } Bits; +} MODRM; + +typedef struct { + UINT64 Regs[4]; +} CPUID_DATA; + +/** + Handle an CPUID event. + + Use the TDVMCALL instruction to handle cpuid #ve + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +EFIAPI +CpuIdExit ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + CPUID_DATA CpuIdData; + UINT64 Status; + + Status =3D TdVmCallCpuid (Regs->Rax, Regs->Rcx, &CpuIdData); + + if (Status =3D=3D 0) { + Regs->Rax =3D CpuIdData.Regs[0]; + Regs->Rbx =3D CpuIdData.Regs[1]; + Regs->Rcx =3D CpuIdData.Regs[2]; + Regs->Rdx =3D CpuIdData.Regs[3]; + } + + return Status; +} + +/** + Handle an IO event. + + Use the TDVMCALL instruction to handle either an IO read or an IO write. + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +EFIAPI +IoExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + BOOLEAN Write; + UINTN Size; + UINTN Port; + UINT64 Val; + UINT64 RepCnt; + UINT64 Status; + + Val =3D 0; + Write =3D Veinfo->ExitQualification.Io.Direction ? FALSE : TRUE; + Size =3D Veinfo->ExitQualification.Io.Size + 1; + Port =3D Veinfo->ExitQualification.Io.Port; + + if (Veinfo->ExitQualification.Io.String) { + // + // If REP is set, get rep-cnt from Rcx + // + RepCnt =3D Veinfo->ExitQualification.Io.Rep ? Regs->Rcx : 1; + + while (RepCnt) { + Val =3D 0; + if (Write =3D=3D TRUE) { + CopyMem (&Val, (VOID *) Regs->Rsi, Size); + Regs->Rsi +=3D Size; + } + + Status =3D TdVmCall (EXIT_REASON_IO_INSTRUCTION, Size, Write, Port, = Val, (Write ? NULL : &Val)); + if (Status !=3D 0) { + break; + } + if (Write =3D=3D FALSE) { + CopyMem ((VOID *) Regs->Rdi, &Val, Size); + Regs->Rdi +=3D Size; + } + + if (Veinfo->ExitQualification.Io.Rep) { + Regs->Rcx -=3D 1; + } + RepCnt -=3D 1; + } + } else { + if (Write =3D=3D TRUE) { + CopyMem (&Val, (VOID *) &Regs->Rax, Size); + } + Status =3D TdVmCall (EXIT_REASON_IO_INSTRUCTION, Size, Write, Port, Va= l, (Write ? NULL : &Val)); + if ((Status =3D=3D 0) && (Write =3D=3D FALSE)) { + CopyMem ((VOID *) &Regs->Rax, &Val, Size); + } + } + return Status; +} + +/** + Handle an READ MSR event. + + Use the TDVMCALL instruction to handle msr read + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +ReadMsrExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + MSR_DATA Data; + UINT64 Status; + + Status =3D TdVmCall (EXIT_REASON_MSR_READ, Regs->Rcx, 0, 0, 0, &Data); + if (Status =3D=3D 0) { + Regs->Rax =3D Data.Regs.Eax; + Regs->Rdx =3D Data.Regs.Edx; + } + + return Status; +} + +/** + Handle an WRITE MSR event. + + Use the TDVMCALL instruction to handle msr write + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +UINT64 +WriteMsrExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + UINT64 Status; + MSR_DATA Data; + + Data.Regs.Eax =3D (UINT32) Regs->Rax; + Data.Regs.Edx =3D (UINT32) Regs->Rdx; + + Status =3D TdVmCall (EXIT_REASON_MSR_WRITE, Regs->Rcx, Data.Val, 0, 0, = NULL); + + return Status; +} + +STATIC +VOID +EFIAPI +TdxDecodeInstruction ( + IN UINT8 *Rip +) +{ + UINTN i; + DEBUG ((DEBUG_INFO,"TDX: #TD[EPT] instruction (%p):", Rip)); + for (i =3D 0; i < 15; i++) { + DEBUG ((DEBUG_INFO, "%02x:", Rip[i])); + } + DEBUG ((DEBUG_INFO, "\n")); +} + +#define TDX_DECODER_BUG_ON(x) \ + if ((x)) { \ + TdxDecodeInstruction(Rip); \ + TdVmCall(TDVMCALL_HALT, 0, 0, 0, 0, 0); \ + } + +STATIC +UINT64 * +EFIAPI +GetRegFromContext ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN UINTN RegIndex +) +{ + switch (RegIndex) { + case 0: return &Regs->Rax; break; + case 1: return &Regs->Rcx; break; + case 2: return &Regs->Rdx; break; + case 3: return &Regs->Rbx; break; + case 4: return &Regs->Rsp; break; + case 5: return &Regs->Rbp; break; + case 6: return &Regs->Rsi; break; + case 7: return &Regs->Rdi; break; + case 8: return &Regs->R8; break; + case 9: return &Regs->R9; break; + case 10: return &Regs->R10; break; + case 11: return &Regs->R11; break; + case 12: return &Regs->R12; break; + case 13: return &Regs->R13; break; + case 14: return &Regs->R14; break; + case 15: return &Regs->R15; break; + } + return NULL; +} + +/** + Handle an MMIO event. + + Use the TDVMCALL instruction to handle either an mmio read or an mmio wr= ite. + + @param[in, out] Regs x64 processor context + @param[in] Veinfo VE Info + + @retval 0 Event handled successfully + @return New exception value to propagate +**/ +STATIC +INTN +EFIAPI +MmioExit ( + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN TDCALL_VEINFO_RETURN_DATA *Veinfo + ) +{ + UINT64 Status; + UINT32 MmioSize; + UINT32 RegSize;; + UINT8 OpCode; + BOOLEAN SeenRex; + UINT64 *Reg; + UINT8 *Rip; + UINT64 Val; + UINT32 OpSize; + MODRM ModRm; + REX Rex; + + Rip =3D (UINT8 *) Regs->Rip; + Val =3D 0; + Rex.Val =3D 0; + SeenRex =3D FALSE; + + // + // Default to 32bit transfer + // + OpSize =3D 4; + + do { + OpCode =3D *Rip++; + if (OpCode =3D=3D 0x66) { + OpSize =3D 2; + } else if (OpCode =3D=3D 0x64 || OpCode =3D=3D 0x65 || OpCode =3D=3D 0= x67) { + continue; + } else if (OpCode >=3D 0x40 && OpCode <=3D 0x4f) { + SeenRex =3D TRUE; + Rex.Val =3D OpCode; + } else { + break; + } + } while (TRUE); + + // + // We need to have at least 2 more bytes for this instruction + // + TDX_DECODER_BUG_ON(((UINT64)Rip - Regs->Rip) > 13); + + OpCode =3D *Rip++; + // + // Two-byte opecode, get next byte + // + if (OpCode =3D=3D 0x0F) { + OpCode =3D *Rip++; + } + + switch (OpCode) { + case 0x88: + case 0x8A: + case 0xB6: + MmioSize =3D 1; + break; + case 0xB7: + MmioSize =3D 2; + break; + default: + MmioSize =3D Rex.Bits.W ? 8 : OpSize; + break; + } + + /* Punt on AH/BH/CH/DH unless it shows up. */ + ModRm.Val =3D *Rip++; + TDX_DECODER_BUG_ON(MmioSize =3D=3D 1 && ModRm.Bits.Reg > 4 && !SeenRex &= & OpCode !=3D 0xB6); + Reg =3D GetRegFromContext (Regs, ModRm.Bits.Reg | ((int)Rex.Bits.R << 3)= ); + TDX_DECODER_BUG_ON(!Reg); + + if (ModRm.Bits.Rm =3D=3D 4) + ++Rip; /* SIB byte */ + + if (ModRm.Bits.Mod =3D=3D 2 || (ModRm.Bits.Mod =3D=3D 0 && ModRm.Bits.Rm= =3D=3D 5)) + Rip +=3D 4; /* DISP32 */ + else if (ModRm.Bits.Mod =3D=3D 1) + ++Rip; /* DISP8 */ + + switch (OpCode) { + case 0x88: + case 0x89: + CopyMem ((void *)&Val, Reg, MmioSize); + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 1, Veinfo->GuestPA, Va= l, 0); + break; + case 0xC7: + CopyMem ((void *)&Val, Rip, OpSize); + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 1, Veinfo->GuestPA, Va= l, 0); + Rip +=3D OpSize; + default: + // + // 32-bit write registers are zero extended to the full register + // Hence 'MOVZX r[32/64], r/m16' is + // hardcoded to reg size 8, and the straight MOV case has a reg + // size of 8 in the 32-bit read case. + // + switch (OpCode) { + case 0xB6: + RegSize =3D Rex.Bits.W ? 8 : OpSize; + break; + case 0xB7: + RegSize =3D 8; + break; + default: + RegSize =3D MmioSize =3D=3D 4 ? 8 : MmioSize; + break; + } + + Status =3D TdVmCall (TDVMCALL_MMIO, MmioSize, 0, Veinfo->GuestPA, 0,= &Val); + if (Status =3D=3D 0) { + ZeroMem (Reg, RegSize); + CopyMem (Reg, (void *)&Val, MmioSize); + } + } + + if (Status =3D=3D 0) { + TDX_DECODER_BUG_ON(((UINT64)Rip - Regs->Rip) > 15); + + // + // We change instruction length to reflect true size so handler can + // bump rip + // + Veinfo->ExitInstructionLength =3D (UINT32)((UINT64)Rip - Regs->Rip); + } + + return Status; +} + +/** + Handle a #VE exception. + + Performs the necessary processing to handle a #VE exception. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VE not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VE handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmTdExitHandleVe ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + UINT64 Status; + TD_RETURN_DATA ReturnData; + EFI_SYSTEM_CONTEXT_X64 *Regs; + + Regs =3D SystemContext.SystemContextX64; + Status =3D TdCall (TDCALL_TDGETVEINFO, 0, 0, 0, &ReturnData); + ASSERT (Status =3D=3D 0); + if (Status !=3D 0) { + DEBUG ((DEBUG_ERROR, "#VE happened. TDGETVEINFO failed with Status =3D= 0x%llx\n", Status)); + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + + switch (ReturnData.VeInfo.ExitReason) { + case EXIT_REASON_CPUID: + Status =3D CpuIdExit (Regs, &ReturnData.VeInfo); + DEBUG ((DEBUG_VERBOSE , + "CPUID #VE happened, ExitReasion is %d, ExitQualification =3D 0x= %x.\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val + )); + break; + + case EXIT_REASON_HLT: + if (FixedPcdGetBool (PcdIgnoreVeHalt) =3D=3D FALSE) { + Status =3D TdVmCall (EXIT_REASON_HLT, 0, 0, 0, 0, 0); + } + break; + + case EXIT_REASON_IO_INSTRUCTION: + Status =3D IoExit (Regs, &ReturnData.VeInfo); + DEBUG ((DEBUG_VERBOSE , + "IO_Instruction #VE happened, ExitReasion is %d, ExitQualificati= on =3D 0x%x.\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val + )); + break; + + case EXIT_REASON_MSR_READ: + Status =3D ReadMsrExit (Regs, &ReturnData.VeInfo); + DEBUG ((DEBUG_VERBOSE , + "RDMSR #VE happened, ExitReasion is %d, ExitQualification =3D 0x= %x. Regs->Rcx=3D0x%llx, Status =3D 0x%llx\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val, Regs->Rcx, Status + )); + break; + + case EXIT_REASON_MSR_WRITE: + Status =3D WriteMsrExit (Regs, &ReturnData.VeInfo); + DEBUG ((DEBUG_VERBOSE , + "WRMSR #VE happened, ExitReasion is %d, ExitQualification =3D 0x= %x. Regs->Rcx=3D0x%llx, Status =3D 0x%llx\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val, Regs->Rcx, Status + )); + break; + + case EXIT_REASON_EPT_VIOLATION: + Status =3D MmioExit (Regs, &ReturnData.VeInfo); + DEBUG ((DEBUG_VERBOSE , + "MMIO #VE happened, ExitReasion is %d, ExitQualification =3D 0x%= x.\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val + )); + break; + + case EXIT_REASON_VMCALL: + case EXIT_REASON_MWAIT_INSTRUCTION: + case EXIT_REASON_MONITOR_INSTRUCTION: + case EXIT_REASON_WBINVD: + case EXIT_REASON_RDPMC: + /* Handle as nops. */ + break; + + default: + DEBUG ((DEBUG_ERROR, + "Unsupported #VE happened, ExitReason is %d, ExitQualification = =3D 0x%x.\n", + ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQualificatio= n.Val + )); + + ASSERT (FALSE); + CpuDeadLoop (); + } + if (Status) { + DEBUG ((DEBUG_ERROR, + "#VE Error (0x%llx) returned from host, ExitReason is %d, ExitQu= alification =3D 0x%x.\n", + Status, ReturnData.VeInfo.ExitReason, ReturnData.VeInfo.ExitQual= ification.Val + )); + + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + SystemContext.SystemContextX64->Rip +=3D ReturnData.VeInfo.ExitInstructi= onLength; + return EFI_SUCCESS; +} diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index ccda130f0ef6..8d1f3b03488c 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -342,6 +342,9 @@ ## Size of the Ovmf image in KB gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb|0|UINT32|0x4f =20 + ## Ignore the VE halt in Tdx + gUefiOvmfPkgTokenSpaceGuid.PcdIgnoreVeHalt|FALSE|BOOLEAN|0x50 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79167): https://edk2.groups.io/g/devel/message/79167 Mute This Topic: https://groups.io/mt/84837902/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79168+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79168+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769482; cv=none; d=zohomail.com; s=zohoarc; b=SWeoXjhh+uS1KiXvZK28KMnLWuQiDdBnrpkIwurH16uCBFV0P0fcJ934erz4L6fqRuaFSr2E+BMx9so+e5q7cJWDRC8m53SNeoIfn4g2IjIInYdHMvwZ0b2xZMaldwtEcga4X5MtcqZAlOoJHsPiDjPgjNRk+8WqzJo9twAkspI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769482; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cJEJhDCCkd1G/1yg9dTOb79XComskDK3f5uGXLW8S3g=; b=Wp488PFhZy0K5jMv3qmTtV1K7+VU34II3pqcjIOMwSU+l954jGGPpbeFCk8IZ6S/JbylqPv2EI3ZNrdech3zrn+Y0cQRpZZ4PgVcagzS/iaogZ0GVxPjgwYo97oZ+fNhcJxYfUiT5kMmMTUY9JkqDvPJKXeW312mFiVZZFtHk5I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79168+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769482978871.7953103522239; Thu, 12 Aug 2021 04:58:02 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id w05MYY1788612xgG1om1928U; Thu, 12 Aug 2021 04:58:02 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:02 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524262" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524262" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:00 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433751" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:57:54 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH 12/23] UefiCpuPkg/CpuExceptionHandler: Add base support for the #VE exception Date: Thu, 12 Aug 2021 19:56:51 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: EPwJHvrhGNoJP6xfc25fWHNvx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769482; bh=SGHzKu0ciXZC+GXkCX0W1n1HECQCD5hAmg/ol9XpEp8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=cKSUgsf2AsJMSFy5AzTYbMQj7mmbF8LtYWddHzXaDl4HCx5pR3M0VTr2mCutQPvUmv6 ZqAIdl0y7Cfz11bRLWwoFJ5JhY5wlxhtEf/zScZnsU3UWa14l36P+QjVWEEoYK8LZkXaH 6OdLstB4PK0Gz8gBbk6nVOIaDNop2pRDq+o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769485189100005 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Add base support to handle #VE exceptions. Update the common exception handlers to invoke the VmTdExitHandleVe () function of the VmTdExitLib library when a #VE is encountered. A non-zero return code will propagate to the targeted exception handler. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Min Xu --- .../DxeCpuExceptionHandlerLib.inf | 1 + .../PeiCpuExceptionHandlerLib.inf | 1 + .../PeiDxeSmmCpuException.c | 18 ++++++++++++++++++ .../SecPeiCpuException.c | 19 +++++++++++++++++++ .../SecPeiCpuExceptionHandlerLib.inf | 1 + .../SmmCpuExceptionHandlerLib.inf | 1 + .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 1 + 7 files changed, 42 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index e7a81bebdb13..630a83bf003b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -61,3 +61,4 @@ MemoryAllocationLib DebugLib VmgExitLib + VmTdExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index cf5bfe40832b..63a7abfb6242 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -53,6 +53,7 @@ MemoryAllocationLib SynchronizationLib VmgExitLib + VmTdExitLib =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuExceptio= n.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 892d349d4b37..0976a880825b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include #include +#include #include "CpuExceptionCommon.h" =20 /** @@ -45,6 +46,23 @@ CommonExceptionHandlerWorker ( } } =20 + if (ExceptionType =3D=3D VE_EXCEPTION) { + EFI_STATUS Status; + // + // #VE needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface. + // + // Handle the #VE: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmTdExitHandleVe (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + ExceptionHandlerContext =3D (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (Syst= emContext.SystemContextIa32); ReservedVectors =3D ExceptionHandlerData->ReservedVectors; ExternalInterruptHandler =3D ExceptionHandlerData->ExternalInterruptHand= ler; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 01b5a2f1f4fc..173047a6b494 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include #include +#include #include "CpuExceptionCommon.h" =20 CONST UINTN mDoFarReturnFlag =3D 0; @@ -43,6 +44,24 @@ CommonExceptionHandler ( } } =20 + if (ExceptionType =3D=3D VE_EXCEPTION) { + EFI_STATUS Status; + // + // #VE needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface + // (which isn't supported under Sec and Pei anyway). + // + // Handle the #VE: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmTdExitHandleVe (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + // // Initialize the serial port before dumping. // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 8ae4feae6238..4aeab2057b08 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -49,6 +49,7 @@ LocalApicLib PeCoffGetEntryPointLib VmgExitLib + VmTdExitLib =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index c9f20da05860..2622e48103f3 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -52,6 +52,7 @@ PeCoffGetEntryPointLib DebugLib VmgExitLib + VmTdExitLib =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index a15f125d5b5e..36ccb7ef97ec 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -54,6 +54,7 @@ LocalApicLib PeCoffGetEntryPointLib VmgExitLib + VmTdExitLib =20 [FeaturePcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackGuard ## CONS= UMES --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79168): https://edk2.groups.io/g/devel/message/79168 Mute This Topic: https://groups.io/mt/84837904/1787277 Mute #ve:https://edk2.groups.io/g/devel/mutehashtag/ve Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79169+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79169+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769484; cv=none; d=zohomail.com; s=zohoarc; b=fkvJ0pprq0aamY44nCMAISoTNBXrAUCVdppwnQCU9+CqARs0BGhIGgVdXXlrbKIYK9V3GU5byq4X3bsNsN9EnZ2H8fcncJUJhCNQ5wgkx+cybGv+NnfVu42agCS647hrji1IgGVw+8KYbjfuK0xuyCZITNGY4p1lKUrkt1qrlPc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769484; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=4kxtoDcM+/831mK2eKXyDo5zHKw2iq/zKzaYOEz6Kqk=; b=iRTRMLumgiOwiE7oanhSIIq1/hMp/Sgb7ep1KM7UoScP9rMWsPgceJuko6Nec7AJjN8YdmTl6M0QBg15PZt9VRaUbbuoTnw1px/g1GbyujxKYueKwHkIfdBEpVuy0kvEFOTWwEm2n9Xv5eoRBvgxZmUQ4h63LHMp9X0c8W4m8/g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79169+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769484282538.987440797927; Thu, 12 Aug 2021 04:58:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id h6csYY1788612x4ZZ0LYucpv; Thu, 12 Aug 2021 04:58:03 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:03 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524274" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524274" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:02 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433773" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:00 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH 13/23] UefiCpuPkg: Enable Tdx support in MpInitLib Date: Thu, 12 Aug 2021 19:56:52 +0800 Message-Id: <88cf26946cb606b11c1821323a43dbceacaf2cf2.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: cPkbQrHuEeSsdZcmUy0aHtpLx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769483; bh=8gEinrW6K+5LKcDrCtNjPcxZIZ21beZGyKJ7Y3FuQz4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=T+E1ZF+va2wei/fOHVw8ei14JLkXmdHIenzj87ShxkQvq7ktO0Ryab09WMiHDQeAA+s cBbbEahe3CLKe7kdvohDA5j3B0bG8+ER69zhYSilkwXu41X0/hV+shD1B0AHVAHwQrnYZ dW0H8F1+/uLBKtMLLc0AUx8bea6riOMOVW0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769485441100008 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDVF BSP and APs are simplified. BSP is the vCPU-0, while the others are treated as APs. So MP intialization is rather simple. The processor info is retrieved by TDCALL, ApWorker is not supported, BSP is always the working processor, while the APs are just in a wait-for-precedure state. Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Min Xu --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 5 + UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 14 +- UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h | 107 +++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 26 ++++ UefiCpuPkg/Library/MpInitLib/MpLibTdx.c | 142 ++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c | 117 +++++++++++++++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 5 + .../Library/MpInitLib/X64/IntelTdcall.nasm | 120 +++++++++++++++ 8 files changed, 535 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdx.c create mode 100644 UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c create mode 100644 UefiCpuPkg/Library/MpInitLib/X64/IntelTdcall.nasm diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index d34419c2a524..2e1cc34d2657 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -22,10 +22,13 @@ # =20 [Sources.IA32] + MpLibTdxNull.c Ia32/MpFuncs.nasm =20 [Sources.X64] + MpLibTdx.c X64/MpFuncs.nasm + X64/IntelTdcall.nasm =20 [Sources.common] MpEqu.inc @@ -33,6 +36,7 @@ MpLib.c MpLib.h Microcode.c + MpIntelTdx.h =20 [Packages] MdePkg/MdePkg.dec @@ -76,3 +80,4 @@ gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## = SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## = CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## = CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdTdxIsEnabled ## = CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 93fc63bf93e3..b7275db3d564 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -7,6 +7,7 @@ **/ =20 #include "MpLib.h" +#include "MpIntelTdx.h" =20 #include #include @@ -15,7 +16,6 @@ #include #include #include - #include =20 #define AP_SAFE_STACK_SIZE 128 @@ -801,6 +801,10 @@ MpInitLibStartupThisAP ( { EFI_STATUS Status; =20 + if (MpTdxIsEnabled ()) { + return EFI_UNSUPPORTED; + } + // // temporarily stop checkAllApsStatus for avoid resource dead-lock. // @@ -857,6 +861,10 @@ MpInitLibSwitchBSP ( EFI_TIMER_ARCH_PROTOCOL *Timer; UINT64 TimerPeriod; =20 + if (MpTdxIsEnabled ()) { + return EFI_UNSUPPORTED; + } + TimerPeriod =3D 0; // // Locate Timer Arch Protocol @@ -930,6 +938,10 @@ MpInitLibEnableDisableAP ( EFI_STATUS Status; BOOLEAN TempStopCheckState; =20 + if (MpTdxIsEnabled ()) { + return EFI_UNSUPPORTED; + } + TempStopCheckState =3D FALSE; // // temporarily stop checkAllAPsStatus for initialize parameters. diff --git a/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h b/UefiCpuPkg/Library= /MpInitLib/MpIntelTdx.h new file mode 100644 index 000000000000..cbb45d2eaf0a --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpIntelTdx.h @@ -0,0 +1,107 @@ +/** @file + Intel Tdx header file. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef MP_INTEL_TDX_H_ +#define MP_INTEL_TDX_H_ + +#include +#include +#include +#include +#include + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ); + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ); + +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +EFI_STATUS +EFIAPI +MyTdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ); + +/** + Whether Intel TDX is enabled. + + @return TRUE TDX enabled + @return FALSE TDX not enabled +**/ +BOOLEAN +EFIAPI +MpTdxIsEnabled ( + VOID + ); + +#endif diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index b9a06747edbf..d03ad8ff483e 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -9,6 +9,7 @@ **/ =20 #include "MpLib.h" +#include "MpIntelTdx.h" #include #include #include @@ -1965,6 +1966,10 @@ MpInitLibInitialize ( UINTN BackupBufferAddr; UINTN ApIdtBase; =20 + if (MpTdxIsEnabled ()) { + return EFI_SUCCESS; + } + OldCpuMpData =3D GetCpuMpDataFromGuidedHob (); if (OldCpuMpData =3D=3D NULL) { MaxLogicalProcessorNumber =3D PcdGet32(PcdCpuMaxLogicalProcessorNumber= ); @@ -2215,6 +2220,10 @@ MpInitLibGetProcessorInfo ( CPU_INFO_IN_HOB *CpuInfoInHob; UINTN OriginalProcessorNumber; =20 + if (MpTdxIsEnabled ()) { + return TdxMpInitLibGetProcessorInfo (ProcessorNumber, ProcessorInfoBuf= fer, HealthData); + } + CpuMpData =3D GetCpuMpData (); CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; =20 @@ -2446,6 +2455,10 @@ EnableDisableApWorker ( CPU_MP_DATA *CpuMpData; UINTN CallerNumber; =20 + if (MpTdxIsEnabled ()) { + return EFI_UNSUPPORTED; + } + CpuMpData =3D GetCpuMpData (); =20 // @@ -2506,6 +2519,11 @@ MpInitLibWhoAmI ( return EFI_INVALID_PARAMETER; } =20 + if (MpTdxIsEnabled ()) { + *ProcessorNumber =3D 0; + return EFI_SUCCESS; + } + CpuMpData =3D GetCpuMpData (); =20 return GetProcessorNumber (CpuMpData, ProcessorNumber); @@ -2544,6 +2562,10 @@ MpInitLibGetNumberOfProcessors ( UINTN EnabledProcessorNumber; UINTN Index; =20 + if (MpTdxIsEnabled ()) { + return TdxMpInitLibGetNumberOfProcessors(NumberOfProcessors, NumberOfE= nabledProcessors); + } + CpuMpData =3D GetCpuMpData (); =20 if ((NumberOfProcessors =3D=3D NULL) && (NumberOfEnabledProcessors =3D= =3D NULL)) { @@ -2629,6 +2651,10 @@ StartupAllCPUsWorker ( BOOLEAN HasEnabledAp; CPU_STATE ApState; =20 + if (MpTdxIsEnabled ()) { + return EFI_SUCCESS; + } + CpuMpData =3D GetCpuMpData (); =20 if (FailedCpuList !=3D NULL) { diff --git a/UefiCpuPkg/Library/MpInitLib/MpLibTdx.c b/UefiCpuPkg/Library/M= pInitLib/MpLibTdx.c new file mode 100644 index 000000000000..2c4445ff02b6 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpLibTdx.c @@ -0,0 +1,142 @@ +/** @file + CPU MP Initialize Library common functions. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MpLib.h" +#include "MpIntelTdx.h" + +#include +#include +#include + + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ) +{ + EFI_STATUS Status; + TD_RETURN_DATA TdReturnData; + + if (ProcessorInfoBuffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Status =3D MyTdCall(TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT(Status =3D=3D EFI_SUCCESS); + + if (ProcessorNumber >=3D TdReturnData.TdInfo.NumVcpus) { + return EFI_NOT_FOUND; + } + + ProcessorInfoBuffer->ProcessorId =3D ProcessorNumber; + ProcessorInfoBuffer->StatusFlag =3D 0; + if (ProcessorNumber =3D=3D 0) { + ProcessorInfoBuffer->StatusFlag |=3D PROCESSOR_AS_BSP_BIT; + } + ProcessorInfoBuffer->StatusFlag |=3D PROCESSOR_ENABLED_BIT; + + // + // Get processor location information + // + GetProcessorLocationByApicId ( + (UINT32)ProcessorNumber, + &ProcessorInfoBuffer->Location.Package, + &ProcessorInfoBuffer->Location.Core, + &ProcessorInfoBuffer->Location.Thread + ); + + if (HealthData !=3D NULL) { + HealthData->Uint32 =3D 0; + } + + return Status; +} + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ) +{ + EFI_STATUS Status; + TD_RETURN_DATA TdReturnData; + + if ((NumberOfProcessors =3D=3D NULL) && (NumberOfEnabledProcessors =3D= =3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + Status =3D MyTdCall(TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + ASSERT(Status =3D=3D EFI_SUCCESS); + + if (NumberOfProcessors !=3D NULL) { + *NumberOfProcessors =3D TdReturnData.TdInfo.NumVcpus; + } + if (NumberOfEnabledProcessors !=3D NULL) { + *NumberOfEnabledProcessors =3D TdReturnData.TdInfo.MaxVcpus; + } + + return Status; +} + +/** + Whether Intel TDX is enabled. + + @return TRUE TDX enabled + @return FALSE TDX not enabled +**/ +BOOLEAN +EFIAPI +MpTdxIsEnabled ( + VOID + ) +{ + return PcdGetBool (PcdTdxIsEnabled); +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c b/UefiCpuPkg/Libra= ry/MpInitLib/MpLibTdxNull.c new file mode 100644 index 000000000000..b00c8deefb5f --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpLibTdxNull.c @@ -0,0 +1,117 @@ +/** @file + CPU MP Initialize Library common functions. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2020, AMD Inc. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "MpLib.h" +#include "MpIntelTdx.h" +#include + +/** + Gets detailed MP-related information on the requested processor at the + instant this call is made. This service may only be called from the BSP. + + @param[in] ProcessorNumber The handle number of processor. + @param[out] ProcessorInfoBuffer A pointer to the buffer where informat= ion for + the requested processor is deposited. + @param[out] HealthData Return processor health data. + + @retval EFI_SUCCESS Processor information was returned. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER ProcessorInfoBuffer is NULL. + @retval EFI_NOT_FOUND The processor with the handle specified = by + ProcessorNumber does not exist in the pl= atform. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetProcessorInfo ( + IN UINTN ProcessorNumber, + OUT EFI_PROCESSOR_INFORMATION *ProcessorInfoBuffer, + OUT EFI_HEALTH_FLAGS *HealthData OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Retrieves the number of logical processor in the platform and the number= of + those logical processors that are enabled on this boot. This service may= only + be called from the BSP. + + @param[out] NumberOfProcessors Pointer to the total number of l= ogical + processors in the system, includ= ing the BSP + and disabled APs. + @param[out] NumberOfEnabledProcessors Pointer to the number of enabled= logical + processors that exist in system,= including + the BSP. + + @retval EFI_SUCCESS The number of logical processors and ena= bled + logical processors was retrieved. + @retval EFI_DEVICE_ERROR The calling processor is an AP. + @retval EFI_INVALID_PARAMETER NumberOfProcessors is NULL and NumberOfE= nabledProcessors + is NULL. + @retval EFI_NOT_READY MP Initialize Library is not initialized. + +**/ +EFI_STATUS +EFIAPI +TdxMpInitLibGetNumberOfProcessors ( + OUT UINTN *NumberOfProcessors, OPTIONAL + OUT UINTN *NumberOfEnabledProcessors OPTIONAL + ) +{ + ASSERT (FALSE); + return EFI_UNSUPPORTED; +} + +/** + Whether Intel TDX is enabled. + + @return TRUE TDX enabled + @return FALSE TDX not enabled +**/ +BOOLEAN +EFIAPI +MpTdxIsEnabled ( + VOID + ) +{ + return FALSE; +} + +/** + The TDCALL instruction causes a VM exit to the Intel TDX module. It is + used to call guest-side Intel TDX functions, either local or a TD exit + to the host VMM, as selected by Leaf. + Leaf functions are described at + + @param[in] Leaf Leaf number of TDCALL instruction + @param[in] Arg1 Arg1 + @param[in] Arg2 Arg2 + @param[in] Arg3 Arg3 + @param[in,out] Results Returned result of the Leaf function + + @return EFI_SUCCESS + @return Other See individual leaf functions +**/ +EFI_STATUS +EFIAPI +MyTdCall ( + IN UINT64 Leaf, + IN UINT64 Arg1, + IN UINT64 Arg2, + IN UINT64 Arg3, + IN OUT VOID *Results + ) +{ + return EFI_UNSUPPORTED; +} diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 36fcb96b5852..fe246b74aaef 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -22,10 +22,13 @@ # =20 [Sources.IA32] + MpLibTdxNull.c Ia32/MpFuncs.nasm =20 [Sources.X64] + MpLibTdx.c X64/MpFuncs.nasm + X64/IntelTdcall.nasm =20 [Sources.common] MpEqu.inc @@ -33,6 +36,7 @@ MpLib.c MpLib.h Microcode.c + MpIntelTdx.h =20 [Packages] MdePkg/MdePkg.dec @@ -65,6 +69,7 @@ gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOME= TIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdTdxIsEnabled ## CONS= UMES =20 [Ppis] gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/X64/IntelTdcall.nasm b/UefiCpuPkg= /Library/MpInitLib/X64/IntelTdcall.nasm new file mode 100644 index 000000000000..9f83b9e73acb --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/X64/IntelTdcall.nasm @@ -0,0 +1,120 @@ +;-------------------------------------------------------------------------= ----- +;* +;* Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+;* SPDX-License-Identifier: BSD-2-Clause-Patent +;* +;* +;-------------------------------------------------------------------------= ----- + +DEFAULT REL +SECTION .text + +%macro tdcall 0 + db 0x66,0x0f,0x01,0xcc +%endmacro + +%macro tdcall_push_regs 0 + push rbp + mov rbp, rsp + push r15 + push r14 + push r13 + push r12 + push rbx + push rsi + push rdi +%endmacro + +%macro tdcall_pop_regs 0 + pop rdi + pop rsi + pop rbx + pop r12 + pop r13 + pop r14 + pop r15 + pop rbp +%endmacro + +%define number_of_regs_pushed 8 +%define number_of_parameters 4 + +; +; Keep these in sync for push_regs/pop_regs, code below +; uses them to find 5th or greater parameters +; +%define first_variable_on_stack_offset \ + ((number_of_regs_pushed * 8) + (number_of_parameters * 8) + 8) +%define second_variable_on_stack_offset \ + ((first_variable_on_stack_offset) + 8) + +%macro tdcall_regs_preamble 2 + mov rax, %1 + + mov ecx, %2 + + ; R10 =3D 0 (standard TDVMCALL) + + xor r10d, r10d + + ; Zero out unused (for standard TDVMCALL) registers to avoid leaking + ; secrets to the VMM. + + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor edx, edx + xor ebp, ebp + xor r8d, r8d + xor r9d, r9d +%endmacro + +%macro tdcall_regs_postamble 0 + xor ebx, ebx + xor esi, esi + xor edi, edi + + xor ecx, ecx + xor edx, edx + xor r8d, r8d + xor r9d, r9d + xor r10d, r10d + xor r11d, r11d +%endmacro + +; TdCall ( +; UINT64 Leaf, // Rcx +; UINT64 P1, // Rdx +; UINT64 P2, // R8 +; UINT64 P3, // R9 +; UINT64 Results, // rsp + 0x28 +; ) +global ASM_PFX(MyTdCall) +ASM_PFX(MyTdCall): + tdcall_push_regs + + mov rax, rcx + mov rcx, rdx + mov rdx, r8 + mov r8, r9 + + tdcall + + ; exit if tdcall reports failure. + test rax, rax + jnz .exit + + ; test if caller wanted results + mov r12, [rsp + first_variable_on_stack_offset ] + test r12, r12 + jz .exit + mov [r12 + 0 ], rcx + mov [r12 + 8 ], rdx + mov [r12 + 16], r8 + mov [r12 + 24], r9 + mov [r12 + 32], r10 + mov [r12 + 40], r11 +.exit: + tdcall_pop_regs + ret --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79169): https://edk2.groups.io/g/devel/message/79169 Mute This Topic: https://groups.io/mt/84837905/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79170+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79170+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769486; cv=none; d=zohomail.com; s=zohoarc; b=c5J+3284bEWytzzDhWpr/bF1QDPe247l/MntrgKXI/BfacO9grvjmmZkSMsLGWd5KO36l2jbPmYAYMxWQXjclzcFXyT9HKyniD1tdydb0zMS04/tSMhmddRL4XuWhqvT0CBJ4Mz3e7HxtvBCk6ip2frLaXiEXl04wruYQrOCCsM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769486; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=nxYXcRzKt7Tg6fWRNIhhuNOJ+A+p6lyVCtIY5yWYAh0=; b=YuSHQMoD18EbyGovOVHacjCh9El7dCgBY5QoqnxzCc36rguDCFt5THu6HFLV9ZbhJiMeog8g3GCLI7H0d+kHbJ7ibjsJHeu1Ty/mzppdbQEPAXNfPXLqDPqAbSaL0BTGMYg5uPbACD1HfRNoWJBXzrpJEeOomgu3kC65SvLJMOY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79170+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769486540977.9844700870739; Thu, 12 Aug 2021 04:58:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id moAzYY1788612x2mHnVf8lx4; Thu, 12 Aug 2021 04:58:06 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:05 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524278" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524278" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:05 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433784" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:02 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 14/23] OvmfPkg: Update SecEntry.nasm to support Tdx Date: Thu, 12 Aug 2021 19:56:53 +0800 Message-Id: <9cdeeb846222a3e191e93449fd73a285b07ed7a3.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: qkkZGOK9iVt1L4FDVkhf576rx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769486; bh=siCu7XwYSbIrSHUb8h2drwP+rB9sT8LazEghOZQaMlM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=oS+o/sdUZIo6FurovbIg6E/bd876QEQpRgN9y70kebbBY5vKO6NL1A9qUC5miszafxi fuM15nktqdt/DO+IljUl8jre17tN1YWvKj3v5AWrz4t8xZGZdCWDOzYhfZJgcdVa6K5+H roWgUpTFrVB04vxq0Su5LgdjHIEntt5OdO0= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769487673100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDX BSP and APs goes to the same entry point in SecEntry.nasm. BSP initialize the temporary stack and then jumps to SecMain, just as legacy Ovmf does. APs spin in a modified mailbox loop using initial mailbox structure. Its structure defition is in OvmfPkg/Include/IndustryStandard/IntelTdx.h. APs wait for command to see if the command is for me. If so execute the command. There are 2 commands are supported: - WakeUp: BSP issues this command to move APs to final OS spinloop and Mailbox in reserved memory. - AcceptPages: To mitigate the performance impact of accepting pages in SEC phase on BSP, BSP will parse memory resources and assign each AP the task of accepting a subset of pages. This command may be called several times until all memory resources are processed. In accepting pages, PageLevel may fall back to smaller one if SIZE_MISMATCH error is returned. TdxCommondefs.inc is added which includes the common definitions used by the APs in SecEntry.nasm. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Include/TdxCommondefs.inc | 51 +++++ OvmfPkg/Sec/SecMain.inf | 1 + OvmfPkg/Sec/X64/SecEntry.nasm | 313 ++++++++++++++++++++++++++++++ 3 files changed, 365 insertions(+) create mode 100644 OvmfPkg/Include/TdxCommondefs.inc diff --git a/OvmfPkg/Include/TdxCommondefs.inc b/OvmfPkg/Include/TdxCommond= efs.inc new file mode 100644 index 000000000000..970eac96592a --- /dev/null +++ b/OvmfPkg/Include/TdxCommondefs.inc @@ -0,0 +1,51 @@ +;-------------------------------------------------------------------------= ----- +; @file +; TDX Common defitions used by the APs in mailbox +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +CommandOffset equ 00h +ApicidOffset equ 04h +WakeupVectorOffset equ 08h +OSArgsOffset equ 10h +FirmwareArgsOffset equ 800h +WakeupArgsRelocatedMailBox equ 800h +AcceptPageArgsPhysicalStart equ 800h +AcceptPageArgsPhysicalEnd equ 808h +AcceptPageArgsChunkSize equ 810h +AcceptPageArgsPageSize equ 818h +CpuArrivalOffset equ 900h +CpusExitingOffset equ 0a00h +TalliesOffset equ 0a08h +ErrorsOffset equ 0e08h + +SIZE_4KB equ 1000h +SIZE_2MB equ 200000h +SIZE_1GB equ 40000000h + +PAGE_ACCEPT_LEVEL_4K equ 0 +PAGE_ACCEPT_LEVEL_2M equ 1 +PAGE_ACCEPT_LEVEL_1G equ 2 + +TDX_PAGE_ALREADY_ACCEPTED equ 0x00000b0a +TDX_PAGE_SIZE_MISMATCH equ 0xc0000b0b + +; Errors of APs in Mailbox +ERROR_NON equ 0 +ERROR_INVALID_ACCEPT_PAGE_SIZE equ 1 +ERROR_ACCEPT_PAGE_ERROR equ 2 +ERROR_INVALID_FALLBACK_PAGE_LEVEL equ 3 + +MpProtectedModeWakeupCommandNoop equ 0 +MpProtectedModeWakeupCommandWakeup equ 1 +MpProtectedModeWakeupCommandSleep equ 2 +MpProtectedModeWakeupCommandAcceptPages equ 3 + +MailboxApicIdInvalid equ 0xffffffff +MailboxApicidBroadcast equ 0xfffffffe + +%define TDCALL_TDINFO 0x1 +%define TDCALL_TDACCEPTPAGE 0x6 diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 7f78dcee2772..75cd5ee7264b 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -70,6 +70,7 @@ gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire diff --git a/OvmfPkg/Sec/X64/SecEntry.nasm b/OvmfPkg/Sec/X64/SecEntry.nasm index 1cc680a70716..8c4d9047e070 100644 --- a/OvmfPkg/Sec/X64/SecEntry.nasm +++ b/OvmfPkg/Sec/X64/SecEntry.nasm @@ -10,12 +10,17 @@ ;-------------------------------------------------------------------------= ----- =20 #include +%include "TdxCommondefs.inc" =20 DEFAULT REL SECTION .text =20 extern ASM_PFX(SecCoreStartupWithStack) =20 +%macro tdcall 0 + db 0x66, 0x0f, 0x01, 0xcc +%endmacro + ; ; SecCore Entry Point ; @@ -35,6 +40,31 @@ extern ASM_PFX(SecCoreStartupWithStack) global ASM_PFX(_ModuleEntryPoint) ASM_PFX(_ModuleEntryPoint): =20 + ; + ; Td guest flag is stored in TDX_WORK_AREA which is in Mailbox[0x10,0x= 20] + ; + %define CC_WORK_AREA FixedPcdGet32 (PcdSevEsWorkAreaBase) + mov eax, CC_WORK_AREA + cmp byte[eax], 2 + jne InitStack + + mov rax, TDCALL_TDINFO + tdcall + + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; Td Guest set the VCPU0 as the BSP, others are the APs + ; APs jump to spinloop and get released by DXE's MpInitLib + ; + mov rax, r9 + and rax, 0xffff + test rax, rax + jne ParkAp + +InitStack: + ; ; Fill the temporary RAM with the initial stack value. ; The loop below will seed the heap as well, but that's harmless. @@ -67,3 +97,286 @@ ASM_PFX(_ModuleEntryPoint): sub rsp, 0x20 call ASM_PFX(SecCoreStartupWithStack) =20 + ; + ; Note: BSP never gets here. APs will be unblocked by DXE + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; +ParkAp: + + mov rbp, r9 + +.do_wait_loop: + mov rsp, FixedPcdGet32 (PcdOvmfSecGhcbBackupBase) + + ; + ; register itself in [rsp + CpuArrivalOffset] + ; + mov rax, 1 + lock xadd dword [rsp + CpuArrivalOffset], eax + inc eax + +.check_arrival_cnt: + cmp eax, r8d + je .check_command + mov eax, dword[rsp + CpuArrivalOffset] + jmp .check_arrival_cnt + +.check_command: + mov eax, dword[rsp + CommandOffset] + cmp eax, MpProtectedModeWakeupCommandNoop + je .check_command + + cmp eax, MpProtectedModeWakeupCommandWakeup + je .do_wakeup + + cmp eax, MpProtectedModeWakeupCommandAcceptPages + jne .check_command + + ; + ; AP Accept Pages + ; + ; Accept Pages in TDX is time-consuming, especially for big memory. + ; One of the mitigation is to accept pages by BSP and APs parallely. + ; + ; For example, there are 4 CPUs (1 BSP and 3 APs). Totally there are + ; 1G memory to be accepted. + ; + ; BSP is responsible for the memory regions of: + ; Start : StartAddress + ChunkSize * (4) * Index + ; Length: ChunkSize + ; APs is reponsible for the memory regions of: + ; Start : StartAddress + ChunkSize * (4) * Index + ChunkSize * CpuId + ; Length: ChunkSize + ; + ; TDCALL_TDACCEPTPAGE supports the PageSize of 4K and 2M. Sometimes wh= en + ; the PageSize is 2M, TDX_PAGE_SIZE_MISMATCH is returned as the error = code. + ; In this case, TDVF need fall back to 4k PageSize to accept again. + ; + ; If any errors happened in accept pages, an error code is recorded in + ; Mailbox [ErrorsOffset + CpuIndex] + ; +.ap_accept_page: + + ; + ; Clear the errors and fallback flag + ; + mov al, ERROR_NON + mov byte[rsp + ErrorsOffset + rbp], al + xor r12, r12 + + ; + ; Get PhysicalAddress/ChunkSize/PageSize + ; + mov rcx, [rsp + AcceptPageArgsPhysicalStart] + mov rbx, [rsp + AcceptPageArgsChunkSize] + + ; + ; Set AcceptPageLevel based on the AcceptPagesize + ; Currently only 2M/4K page size is acceptable + ; + mov r15, [rsp + AcceptPageArgsPageSize] + cmp r15, SIZE_4KB + je .set_4kb + cmp r15, SIZE_2MB + je .set_2mb + + mov al, ERROR_INVALID_ACCEPT_PAGE_SIZE + mov byte[rsp + ErrorsOffset + rbp], al + jmp .do_finish_command + +.set_4kb: + mov r15, PAGE_ACCEPT_LEVEL_4K + jmp .physical_address + +.set_2mb: + mov r15, PAGE_ACCEPT_LEVEL_2M + +.physical_address: + ; + ; PhysicalAddress +=3D (CpuId * ChunkSize) + ; + xor rdx, rdx + mov eax, ebp + mul ebx + add rcx, rax + shl rdx, 32 + add rcx, rdx + +.do_accept_next_range: + ; + ; Make sure we don't accept page beyond ending page + ; This could happen is ChunkSize crosses the end of region + ; + cmp rcx, [rsp + AcceptPageArgsPhysicalEnd ] + jge .do_finish_command + + ; + ; Save starting address for this region + ; + mov r11, rcx + + ; + ; Size =3D MIN(ChunkSize, PhysicalEnd - PhysicalAddress); + ; + mov rax, [rsp + AcceptPageArgsPhysicalEnd] + sub rax, rcx + cmp rax, rbx + jge .do_accept_loop + mov rbx, rax + +.do_accept_loop: + ; + ; RCX: Accept address + ; R15: Accept Page Level + ; R12: Flag of fall back accept + ; + mov rax, TDCALL_TDACCEPTPAGE + xor rdx, rdx + or rcx, r15 + + tdcall + + ; + ; Check status code in RAX + ; + test rax, rax + jz .accept_success + + shr rax, 32 + cmp eax, TDX_PAGE_ALREADY_ACCEPTED + jz .already_accepted + + cmp eax, TDX_PAGE_SIZE_MISMATCH + jz .accept_size_mismatch + + ; + ; other error + ; + mov al, ERROR_ACCEPT_PAGE_ERROR + mov byte[rsp + ErrorsOffset + rbp], al + jmp .do_finish_command + +.accept_size_mismatch: + ; + ; Check the current PageLevel. + ; ACCEPT_LEVEL_4K is the least level and cannot fall back any more. + ; If in this case, just record the error and return + ; + cmp r15, PAGE_ACCEPT_LEVEL_4K + jne .do_fallback_accept + mov al, ERROR_INVALID_FALLBACK_PAGE_LEVEL + mov byte[rsp + ErrorsOffset + rbp], al + jmp .do_finish_command + +.do_fallback_accept: + ; + ; In fall back accept, just loop 512 times (2M =3D 512 * 4K) + ; Save the rcx in r13. + ; Decrease the PageLevel in R15. + ; R12 indicates it is in a fall back accept loop. + ; + mov r14, 512 + and rcx, ~0x3ULL + mov r13, rcx + xor rdx, rdx + dec r15 + mov r12, 1 + + jmp .do_accept_loop + +.accept_success: + ; + ; Keep track of how many accepts per cpu + ; + inc dword[rsp + TalliesOffset + rbp * 4] + + ; + ; R12 indicate whether it is a fall back accept + ; If it is a success of fall back accept + ; Just loop 512 times to .do_accept_loop + ; + test r12, r12 + jz .normal_accept_success + + ; + ; This is fallback accept success + ; + add rcx, SIZE_4KB + dec r14 + test r14, r14 + jz .fallback_accept_done + jmp .do_accept_loop + +.fallback_accept_done: + ; + ; Fall back accept done. + ; Restore the start address to RCX from R13 + ; Clear the fall back accept flag + ; + mov rcx, r13 + inc r15 + xor r12, r12 + +.already_accepted: + ; + ; Handle the sitution of fall back accpet + ; + test r12, r12 + jnz .accept_success + +.normal_accept_success: + ; + ; Reduce accept size by a PageSize, and increment address + ; + mov r12, [rsp + AcceptPageArgsPageSize] + sub rbx, r12 + add rcx, r12 + xor r12, r12 + + ; + ; We may be given multiple pages to accept, make sure we + ; aren't done + ; + test rbx, rbx + jne .do_accept_loop + + ; + ; Restore address before, and then increment by stride (num-cpus * Chu= nkSize) + ; + xor rdx, rdx + mov rcx, r11 + mov eax, r8d + mov ebx, [rsp + AcceptPageArgsChunkSize] + mul ebx + add rcx, rax + shl rdx, 32 + add rcx, rdx + jmp .do_accept_next_range + +.do_finish_command: + mov eax, 0FFFFFFFFh + lock xadd dword [rsp + CpusExitingOffset], eax + dec eax + +.check_exiting_cnt: + cmp eax, 0 + je .do_wait_loop + mov eax, dword[rsp + CpusExitingOffset] + jmp .check_exiting_cnt + +.do_wakeup: + ; + ; BSP sets these variables before unblocking APs + ; RAX: WakeupVectorOffset + ; RBX: Relocated mailbox address + ; RBP: vCpuId + ; + mov rax, 0 + mov eax, dword[rsp + WakeupVectorOffset] + mov rbx, [rsp + WakeupArgsRelocatedMailBox] + nop + jmp rax + jmp $ --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79170): https://edk2.groups.io/g/devel/message/79170 Mute This Topic: https://groups.io/mt/84837906/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79171+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79171+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769489; cv=none; d=zohomail.com; s=zohoarc; b=eZsfc8Cwh1Cv6TraIMLunxymf1NZg5+otE97murJRV7Z6yw6TT82hh43L/nzyXppKbnVJLQoxF6qYsVIAStMb1B9Sb4lRgfVnxaYkqrcc2y3Xc4w3rLGSdBnRPUltBbokIk4bWOHjQGSgmYYQMC8BWlqu+X02fcxK6uIdB/u6r8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769489; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3ap3v512ZajcUGVJ1AO1XYPx9K7jj5UGUdas7XLnxUk=; b=SfQp6egvZkc2tnFtlwBlvowIYTpW6dFRV7i57vTSkWCtZW4dZ9J+CgR2RvJQIqpqK9hOTSs1hwnIDdIgCHUlHak3ywDSVtYo0m90eIh+eQCC76hM6j03YvYMScmQW0uQPE+sYUBPGYQVrI3pWciEwNtxNtA1+SL5noLpUw25I9Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79171+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769489024277.84484107730395; Thu, 12 Aug 2021 04:58:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id JykNYY1788612x02sOw0FVQs; Thu, 12 Aug 2021 04:58:08 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:08 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524290" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524290" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:07 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433795" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:05 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 15/23] OvmfPkg: Add IntelTdx.h in OvmfPkg/Include/IndustryStandard Date: Thu, 12 Aug 2021 19:56:54 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: sHbpvIU1VXQ4Qba1YLnkMIU0x1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769488; bh=ev9NuLsLrl2Y8Wjupl9fAL7LoP3o4g4Tp002l4Yhb9k=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ChlXhtRtPTHtEnI7TH97wRk/zhTxNAW7RKuoMJyWZ6/Yrb5y8Cdbky7c7d+T6YcWIWt X6u7QqAH3e7RuKUmK5J/ZWsdQJrh+P9l1g17sZnG/65fa2WhWHmnwwJAggbuiq1fBHjLo 98BmbcV+nWVaAO6AWpXSzMWzgdOAhE1x8tQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769489766100005 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 IntelTdx.h defines the defitions used by TDX in OvmfPkg: - Mailbox related defitions,such as the data structure, command code, AP relocation defitions. - EFI_HOB_PLATFORM_INFO describes the TDX platform information Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Include/IndustryStandard/IntelTdx.h | 77 +++++++++++++++++++++ 1 file changed, 77 insertions(+) create mode 100644 OvmfPkg/Include/IndustryStandard/IntelTdx.h diff --git a/OvmfPkg/Include/IndustryStandard/IntelTdx.h b/OvmfPkg/Include/= IndustryStandard/IntelTdx.h new file mode 100644 index 000000000000..2370f18289a1 --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/IntelTdx.h @@ -0,0 +1,77 @@ +/** @file + TBD + + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _OVMF_INTEL_TDX__H_ +#define _OVMF_INTEL_TDX__H_ + +#include +#include +#include +#include + +#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID 0xFFFFFFFF +#define MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST 0xFFFFFFFE + +typedef enum { + MpProtectedModeWakeupCommandNoop =3D 0, + MpProtectedModeWakeupCommandWakeup =3D 1, + MpProtectedModeWakeupCommandSleep =3D 2, + MpProtectedModeWakeupCommandAcceptPages =3D 3, +} MP_CPU_PROTECTED_MODE_WAKEUP_CMD; + +#pragma pack (1) + + // + // Describes the CPU MAILBOX control structure use to + // wakeup cpus spinning in long mode + // + typedef struct { + UINT16 Command; + UINT16 Resv; + UINT32 ApicId; + UINT64 WakeUpVector; + UINT8 ResvForOs[2032]; + // + // Arguments available for wakeup code + // + UINT64 WakeUpArgs1; + UINT64 WakeUpArgs2; + UINT64 WakeUpArgs3; + UINT64 WakeUpArgs4; + UINT8 Pad1[0xe0]; + UINT64 NumCpusArriving; + UINT8 Pad2[0xf8]; + UINT64 NumCpusExiting; + UINT32 Tallies[256]; + UINT8 Errors[256]; + UINT8 Pad3[0xf8]; + } MP_WAKEUP_MAILBOX; + + +// +// AP relocation code information including code address and size, +// this structure will be shared be C code and assembly code. +// It is natural aligned by design. +// +typedef struct { + UINT8 *RelocateApLoopFuncAddress; + UINTN RelocateApLoopFuncSize; +} MP_RELOCATION_MAP; + +typedef struct { + /// + EFI_HOB_GUID_TYPE GuidHeader; + UINT64 RelocatedMailBox; + UINT16 HostBridgePciDevId; + BOOLEAN SetNxForStack; + UINT8 SystemStates[6]; +} EFI_HOB_PLATFORM_INFO; + +#pragma pack() + +#endif --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79171): https://edk2.groups.io/g/devel/message/79171 Mute This Topic: https://groups.io/mt/84837908/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79172+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79172+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769491; cv=none; d=zohomail.com; s=zohoarc; b=j5ybvauYhPSp7nal7MgsY0M6Niq7ZCJ7JPn5rDB6fxtrBbQzbk/hUd49h3hH5sqUuaAZdEfA8qdpjSA4hD83zcmfxHlzO4KqMqaj8nKbq5gQUzzimdNqeQo/ZpeO5+bLGFOPnDYKfTypSYu6LcHgWAwwS+7cm29NQZfpJeqZ1HQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769491; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=R3jkQjy+etuuXwY0A3tkDhUShKBxHfscgqbOva+B5ag=; b=MGNQ2RztmuiQycv2x8o0VCAqV7g/QHmq1MV6VMK+OpH1xCy5JcH28tDmXKAJwEn60F3VOGyhKFlnNbC8ZsVQoTeXG6EZ/0NPFNzeQBsSqxi1w2ToswOBp5TI5MacIJLwaRwHaDtAMoziYN4y3jfxazanPAAK/prN8+N6mRtnu1Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79172+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162876949153534.70033063966093; Thu, 12 Aug 2021 04:58:11 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9qlfYY1788612xoJnxQK9HfV; Thu, 12 Aug 2021 04:58:11 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:10 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524323" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524323" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:10 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433823" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:07 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 16/23] OvmfPkg: Add TdxMailboxLib Date: Thu, 12 Aug 2021 19:56:55 +0800 Message-Id: <871fc1a74da918668325504149ed5033aabc1a37.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: QmhsOBWuherfitH16RSWRFwkx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769491; bh=tPlszeX3VvMNROLKR2o7lryCnlHrzTPLK/nh1AoDzgU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=wstr8yRTYXOYLZw/fo1H6C1Y9fwO6ASaOHP5tq1NbBMbaLj1xPREAndCTgALI6Yd9lI F+y9Dwe0WRx1x9/80l9QOvxvQIjCMY5HrszSVV5BMdFZmW1l6HIOyP+ZRRV4gImYf0HVq LqZncUFo1xeL8rXDEtz8NZTxJHoTVUSlUro= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769491998100015 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In Tdx BSP may issues commands to APs for some task, for example, to accept pages paralelly. BSP also need to wait until all the APs have done the task. TdxMailboxLib wraps these common funtions for BSP. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Include/Library/TdxMailboxLib.h | 75 ++++++++++ OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c | 138 ++++++++++++++++++ .../Library/TdxMailboxLib/TdxMailboxLib.inf | 52 +++++++ .../Library/TdxMailboxLib/TdxMailboxNull.c | 86 +++++++++++ OvmfPkg/OvmfPkg.dec | 4 + 5 files changed, 355 insertions(+) create mode 100644 OvmfPkg/Include/Library/TdxMailboxLib.h create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf create mode 100644 OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c diff --git a/OvmfPkg/Include/Library/TdxMailboxLib.h b/OvmfPkg/Include/Libr= ary/TdxMailboxLib.h new file mode 100644 index 000000000000..a410a9618495 --- /dev/null +++ b/OvmfPkg/Include/Library/TdxMailboxLib.h @@ -0,0 +1,75 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __TDX_MAILBOX_LIB_H__ +#define __TDX_MAILBOX_LIB_H__ + +#include +#include +#include +#include +#include +#include + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID +); + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID +); + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 +); + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ); + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ); + +#endif diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c b/OvmfPkg/Library/T= dxMailboxLib/TdxMailbox.c new file mode 100644 index 000000000000..688ac6ca8262 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailbox.c @@ -0,0 +1,138 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +volatile VOID *mMailBox =3D NULL; +UINT32 mNumOfCpus =3D 0; + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID + ) +{ + if (mNumOfCpus =3D=3D 0) { + mNumOfCpus =3D TdVCpuNum (); + } + + return mNumOfCpus; +} + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID + ) +{ + if (mMailBox =3D=3D NULL) { + mMailBox =3D (VOID *)(UINTN) PcdGet32 (PcdOvmfSecGhcbBackupBase); + } + + return mMailBox; +} + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand ( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 +) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + + MailBox =3D (volatile MP_WAKEUP_MAILBOX *) GetTdxMailBox (); + MailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALID; + MailBox->WakeUpVector =3D 0; + MailBox->Command =3D MpProtectedModeWakeupCommandNoop; + MailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_BROADCAST; + MailBox->WakeUpVector =3D WakeupVector; + MailBox->WakeUpArgs1 =3D WakeupArgs1; + MailBox->WakeUpArgs2 =3D WakeupArgs2; + MailBox->WakeUpArgs3 =3D WakeupArgs3; + MailBox->WakeUpArgs4 =3D WakeupArgs4; + AsmCpuid (0x01, NULL, NULL, NULL, NULL); + MailBox->Command =3D Command; + AsmCpuid (0x01, NULL, NULL, NULL, NULL); + return; +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + UINT32 NumOfCpus; + + NumOfCpus =3D GetCpusNum (); + MailBox =3D (volatile MP_WAKEUP_MAILBOX *) GetTdxMailBox (); + + DEBUG ((DEBUG_VERBOSE, "Waiting for APs to arriving. NumOfCpus=3D%d, Mai= lBox=3D%p\n", NumOfCpus, MailBox)); + while (MailBox->NumCpusArriving !=3D ( NumOfCpus -1 )) { + CpuPause (); + } + DEBUG ((DEBUG_VERBOSE, "Releasing APs\n")); + MailBox->NumCpusExiting =3D NumOfCpus; + InterlockedIncrement ((UINT32 *) &MailBox->NumCpusArriving); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ) +{ + volatile MP_WAKEUP_MAILBOX *MailBox; + + MailBox =3D (volatile MP_WAKEUP_MAILBOX *) GetTdxMailBox (); + DEBUG ((DEBUG_VERBOSE, "Waiting for APs to finish\n")); + while (MailBox->NumCpusExiting !=3D 1 ) { + CpuPause (); + } + DEBUG ((DEBUG_VERBOSE, "Restarting APs\n")); + MailBox->Command =3D MpProtectedModeWakeupCommandNoop; + MailBox->NumCpusArriving =3D 0; + InterlockedDecrement ((UINT32 *) &MailBox->NumCpusExiting); +} diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf b/OvmfPkg/Libr= ary/TdxMailboxLib/TdxMailboxLib.inf new file mode 100644 index 000000000000..3cf3690a16c7 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf @@ -0,0 +1,52 @@ +#/** @file +# +# TBD +# +# Copyright (c) 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2008, Apple Inc. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +#**/ + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D TdxMailboxLib + FILE_GUID =3D 2F81A9BA-748E-4519-BB11-A63A039D561E + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D TdxMailboxLib + +# +# VALID_ARCHITECTURES =3D X64 IA32 +# + +[Sources.IA32] + TdxMailboxNull.c + +[Sources.X64] + TdxMailbox.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + OvmfPkg/OvmfPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + BaseMemoryLib + PcdLib + UefiCpuLib + DebugAgentLib + IoLib + SynchronizationLib + MemoryAllocationLib + +[Guids] + +[Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize diff --git a/OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c b/OvmfPkg/Libra= ry/TdxMailboxLib/TdxMailboxNull.c new file mode 100644 index 000000000000..f15222d51f45 --- /dev/null +++ b/OvmfPkg/Library/TdxMailboxLib/TdxMailboxNull.c @@ -0,0 +1,86 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + + +/** + This function will be called by BSP to get the CPU number. + + @retval CPU number +**/ +UINT32 +EFIAPI +GetCpusNum ( + VOID + ) +{ + ASSERT (FALSE); + return 0; +} + +/** + Get the address of Td mailbox. +**/ +volatile VOID * +EFIAPI +GetTdxMailBox ( + VOID + ) +{ + ASSERT (FALSE); + return (volatile VOID *) NULL; +} + +/** + This function will be called by BSP to wakeup APs the are spinning on ma= ilbox + in protected mode + + @param[in] Command Command to send APs + @param[in] WakeupVector If used, address for APs to start executing + @param[in] WakeArgsX Args to pass to APs for excuting commands +**/ +VOID +EFIAPI +MpSendWakeupCommand ( + IN UINT16 Command, + IN UINT64 WakeupVector, + IN UINT64 WakeupArgs1, + IN UINT64 WakeupArgs2, + IN UINT64 WakeupArgs3, + IN UINT64 WakeupArgs4 +) +{ + ASSERT (FALSE); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is started. +**/ +VOID +EFIAPI +MpSerializeStart ( + VOID + ) +{ + ASSERT (FALSE); +} + +/** + BSP wait until all the APs arriving. It means the task triggered by BSP = is ended. +**/ +VOID +EFIAPI +MpSerializeEnd ( + VOID + ) +{ + ASSERT (FALSE); +} diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 8d1f3b03488c..d478a4b8e418 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -109,6 +109,10 @@ # XenPlatformLib|Include/Library/XenPlatformLib.h =20 + ## @libraryclass TdxMailboxLib + # + TdxMailboxLib|Include/Library/TdxMailboxLib.h + [Guids] gUefiOvmfPkgTokenSpaceGuid =3D {0x93bb96af, 0xb9f2, 0x4eb8, {= 0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}} gEfiXenInfoGuid =3D {0xd3b46f3b, 0xd441, 0x1244, {= 0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}} --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79172): https://edk2.groups.io/g/devel/message/79172 Mute This Topic: https://groups.io/mt/84837910/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79173+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79173+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769493; cv=none; d=zohomail.com; s=zohoarc; b=BkyEn2FcrCrJq+ZFoB5SdPVenORwcx7Q6nIdep+80W26eYBRzroQ2FAgrnSHyVRG8nfcvlOX8LIzhaKneFdBmJF5xKUUOm5WWyLhRmkKP7aQg0kzDAb++Y6TGbdwGdSuxexDO2kY17am42E8ZBM9yrfkO/ZE9ml01bjNJlQDhOw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769493; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rnWXg9lZ+a9bpJJvoiFYffdhKJI8PTcT7NG9a2admjE=; b=CQtMrxgW/bAV+L/RRhYBJx1ItNRSqkEYFRgoNYvl92MWz7kXkMwmqlbTtyXqreCpwzCyTfoQMCiKu/2LoirntOeFnMkihlDB7cvbHbgsWyhbpQUYLU18eGL/GWlVB4iGtNnKGZADiuIPi6zyS7ZD2HRy9tjkdhD98Nk4CoxZM3w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79173+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769493863576.8512491935024; Thu, 12 Aug 2021 04:58:13 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZL9gYY1788612xaDoxAX8aAm; Thu, 12 Aug 2021 04:58:13 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:13 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524343" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524343" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:12 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433849" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:10 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 17/23] MdePkg: Add EFI_RESOURCE_ATTRIBUTE_ENCRYPTED in PiHob.h Date: Thu, 12 Aug 2021 19:56:56 +0800 Message-Id: <414fa1dfc21dea84cba3b1e26ec59f5e0825362b.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: XNV8GqzFGdR96AiBXT3A6n0Jx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769493; bh=65/M4j81/1O5h0Oj1r0bJWAyAVGvuhSXKihP5G95Yhs=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=aRtJ7Xt7+HSQN1ELwmiQmjTp/6hYkLs88lhXbnaMXQxpkTasv1wsLCXHoL+tJUR/+Ri TSvFJTERwC5WAULWTB8v2PgrZK63nSAOEBOGqlRqfJroKnlVYV/3XLG00gf+3POMA//ty 05FEVH0P7XWBO6teXhUfaKDjNWCWP4IZv6U= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769494201100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 EFI_RESOURCE_ATTRIBUTE_ENCRYPTED is Physical memory encrypted attribute. It indicates the memory uses platform encrpytion capabilities for protection. If this bit is clear, the memory does not use platform encryption protection. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- MdePkg/Include/Pi/PiHob.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MdePkg/Include/Pi/PiHob.h b/MdePkg/Include/Pi/PiHob.h index 62c07742a688..600ec2d4919e 100644 --- a/MdePkg/Include/Pi/PiHob.h +++ b/MdePkg/Include/Pi/PiHob.h @@ -298,6 +298,14 @@ typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; // #define EFI_RESOURCE_ATTRIBUTE_MORE_RELIABLE 0x02000000 =20 +// +// Physical memory encrypted attribute. This +// memory uses platform encrpytion capabilities for +// protection. If this bit is clear, the memory does +// not use platform encryption protection +// +#define EFI_RESOURCE_ATTRIBUTE_ENCRYPTED 0x04000000 + /// /// Describes the resource properties of all fixed, /// nonrelocatable resource ranges found on the processor --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79173): https://edk2.groups.io/g/devel/message/79173 Mute This Topic: https://groups.io/mt/84837912/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79174+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79174+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769496; cv=none; d=zohomail.com; s=zohoarc; b=e/xSBqVquIdbnRNaT8FIv54MYbi5HmHhMJV1ONJlZuIN3e3nM97MAPtXFLPIwLPSVV6pu84g4jrpEqmWvChToQR3Ae4guYHZlRHfcdSTGUOSTDmtpPIWkPk9XZxdl+1ncVTYLNc6ju5B3iEGJcN7wr7X968Z01C8n1p4T3GlVdA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769496; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=xcCrk4flv/IftJlbKRJhOupZmYNOoNPKkz9QgA82nkM=; b=jXFFf2Y/B1uec2FrZLpbnj/eSmV7wX06XjOX/C2o3C4uCKw4NunyZqqLT996P4S6opYu6/sjBio2ZiPG5uN0IqRSptKZsVzVtmbW3ZNFefrLtG5RzKseFNS9ZOd+VRxDArj0LXLOzn8jC2mNUboIvIxjawMvCmK+LvQbMyPmCZA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79174+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769496712900.393481953217; Thu, 12 Aug 2021 04:58:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pfR2YY1788612xN3u4FfD17e; Thu, 12 Aug 2021 04:58:16 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:15 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524356" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524356" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:15 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433887" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:12 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Date: Thu, 12 Aug 2021 19:56:57 +0800 Message-Id: <95f116893a4a17c7e0966e240a650f871c9f9392.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: K5BmDpwiJkWnehdYWogG18Y1x1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769496; bh=b9FXz0HXQrrThP2YJoTalrV90znAyQCqKNQizYEZLFI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=UKUHs2nH7iAwfmm0V71dlfWUBoxjpAoe/gnlDBbfyhhGpoqFaTsS165n+FRRXREQGYN cKSRx/DpQDPubSqLmvvH2jGbOv/xViPxd7hBjvROdQ4+REo2Z+UvhbHtbXhLNUtbpd4VK KtOuovHbr4KRhuULXgGQn+x0J7x5Nq+97W4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769498406100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 When host VMM create the Td guest, the system memory informations are stored in TdHob, which is a memory region described in Tdx metadata. The system memory region in TdHob should be accepted before it can be accessed. So the major task of this patch set is to process the TdHobList to accept the memory. After that TDVF follow the standard OVMF flow and jump to PEI phase. 2 PCDs are added for page accepting. They're the default settings of the chunk size and the Accept page size. 4 Tdx specific libs are used by OvmfPkgX64: - VmTdExitLib - TdxLib - TdxProbeLib - TdxMailboxLib TDX only works on X64, so the code is only valid in X64 arch. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 6 + OvmfPkg/OvmfPkgIa32.dsc | 3 + OvmfPkg/OvmfPkgIa32X64.dsc | 3 + OvmfPkg/OvmfPkgX64.dsc | 5 +- OvmfPkg/Sec/IntelTdx.c | 608 +++++++++++++++++++++++++++++++++++++ OvmfPkg/Sec/IntelTdx.h | 33 ++ OvmfPkg/Sec/SecMain.c | 43 ++- OvmfPkg/Sec/SecMain.inf | 6 + 8 files changed, 700 insertions(+), 7 deletions(-) create mode 100644 OvmfPkg/Sec/IntelTdx.c create mode 100644 OvmfPkg/Sec/IntelTdx.h diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index d478a4b8e418..a9765f2a60be 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -349,6 +349,12 @@ ## Ignore the VE halt in Tdx gUefiOvmfPkgTokenSpaceGuid.PcdIgnoreVeHalt|FALSE|BOOLEAN|0x50 =20 + ## The chunk size of Tdx accept page + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptChunkSize|0x2000000|UINT64|0x51 + + ## The Tdx accept page size. 0x1000(4k),0x200000(2M) + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize|0x1000|UINT64|0x52 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 1e1765060e3f..27c70d233c68 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -244,6 +244,9 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf + TdxProbeLib|MdePkg/Library/TdxProbeLib/TdxProbeLib.inf + TdxMailboxLib|OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 2eadb51683c9..54c664382ef1 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -248,6 +248,9 @@ BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf + TdxProbeLib|MdePkg/Library/TdxProbeLib/TdxProbeLib.inf + TdxMailboxLib|OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 3376c4f4c2f9..b2e07233ebd6 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -247,7 +247,10 @@ [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf - VmTdExitLib|UefiCpuPkg/Library/VmTdExitLibNull/VmTdExitLibNull.inf + VmTdExitLib|OvmfPkg/Library/VmTdExitLib/VmTdExitLib.inf + TdxLib|MdePkg/Library/TdxLib/TdxLib.inf + TdxProbeLib|MdePkg/Library/TdxProbeLib/TdxProbeLib.inf + TdxMailboxLib|OvmfPkg/Library/TdxMailboxLib/TdxMailboxLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/Sec/IntelTdx.c b/OvmfPkg/Sec/IntelTdx.c new file mode 100644 index 000000000000..e4bbd0fdea4e --- /dev/null +++ b/OvmfPkg/Sec/IntelTdx.c @@ -0,0 +1,608 @@ +/** @file + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "IntelTdx.h" + +#define ALIGNED_2MB_MASK 0x1fffff + +/** + BSP call this function to accept memory in a range. + + @param[in] StartAddress Start address of the memory region + @param[in] Length Length of the memory region + @param[in] AcceptChunkSize Accept chunk size + @param[in] AcceptPageSize Accept page size + @retval EFI_SUCCESS Successfully accept the memory region + @retval Others Indicate the other errors +**/ +EFI_STATUS +EFIAPI +BspAcceptMemoryResourceRange ( + IN EFI_PHYSICAL_ADDRESS StartAddress, + IN UINT64 Length, + IN UINT64 AcceptChunkSize, + IN UINT64 AcceptPageSize + ) +{ + EFI_STATUS Status; + UINT64 Pages; + UINT64 Stride; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + volatile MP_WAKEUP_MAILBOX *MailBox; + + Status =3D EFI_SUCCESS; + PhysicalAddress =3D StartAddress; + Stride =3D GetCpusNum () * AcceptChunkSize; + MailBox =3D (volatile MP_WAKEUP_MAILBOX *) GetTdxMailBox (); + + while (!EFI_ERROR(Status) && PhysicalAddress < StartAddress + Length) { + // + // Decrease size of near end of resource if needed. + // + Pages =3D MIN (AcceptChunkSize, StartAddress + Length - PhysicalAddres= s) / AcceptPageSize; + + MailBox->Tallies[0] +=3D (UINT32)Pages; + + Status =3D TdAcceptPages (PhysicalAddress, Pages, AcceptPageSize); + // + // Bump address to next chunk this cpu is responisble for + // + PhysicalAddress +=3D Stride; + } + + return Status; +} + +/** + This function will be called to accept pages. BSP and APs are invokded + to do the task together. + + TDCALL(ACCEPT_PAGE) supports the accept page size of 4k and 2M. To + simplify the implementation, the Memory to be accpeted is splitted + into 3 parts: + ----------------- <-- StartAddress1 (not 2M aligned) + | part 1 | Length1 < 2M + |---------------| <-- StartAddress2 (2M aligned) + | | Length2 =3D Integer multiples of 2M + | part 2 | + | | + |---------------| <-- StartAddress3 + | part 3 | Length3 < 2M + |---------------| + + part 1) will be accepted in 4k and by BSP. + Part 2) will be accepted in 2M and by BSP/AP. + Part 3) will be accepted in 4k and by BSP. + + @param[in] PhysicalAddress Start physical adress + @param[in] PhysicalEnd End physical address + + @retval EFI_SUCCESS Accept memory successfully + @retval Others Other errors as indicated +**/ +EFI_STATUS +EFIAPI +MpAcceptMemoryResourceRange ( + IN EFI_PHYSICAL_ADDRESS PhysicalAddress, + IN EFI_PHYSICAL_ADDRESS PhysicalEnd + ) +{ + EFI_STATUS Status; + UINT64 AcceptChunkSize; + UINT64 AcceptPageSize; + UINT64 StartAddress1; + UINT64 StartAddress2; + UINT64 StartAddress3; + UINT64 TotalLength; + UINT64 Length1; + UINT64 Length2; + UINT64 Length3; + UINT32 Index; + UINT32 CpusNum; + volatile MP_WAKEUP_MAILBOX *MailBox; + + AcceptChunkSize =3D FixedPcdGet64 (PcdTdxAcceptChunkSize); + AcceptPageSize =3D FixedPcdGet64 (PcdTdxAcceptPageSize); + TotalLength =3D PhysicalEnd - PhysicalAddress; + StartAddress1 =3D 0; + StartAddress2 =3D 0; + StartAddress3 =3D 0; + Length1 =3D 0; + Length2 =3D 0; + Length3 =3D 0; + + if (AcceptPageSize =3D=3D SIZE_4KB || TotalLength <=3D SIZE_2MB) { + // + // if total length is less than 2M, then we accept pages in 4k + // + StartAddress1 =3D 0; + Length1 =3D 0; + StartAddress2 =3D PhysicalAddress; + Length2 =3D PhysicalEnd - PhysicalAddress; + StartAddress3 =3D 0; + Length3 =3D 0; + AcceptPageSize =3D SIZE_4KB; + } else if (AcceptPageSize =3D=3D SIZE_2MB) { + // + // Total length is bigger than 2M and Page Accept size 2M is supported. + // + if ((PhysicalAddress & ALIGNED_2MB_MASK) =3D=3D 0) { + // + // Start address is 2M aligned + // + StartAddress1 =3D 0; + Length1 =3D 0; + StartAddress2 =3D PhysicalAddress; + Length2 =3D TotalLength & ~(UINT64)ALIGNED_2MB_MASK; + + if (TotalLength > Length2) { + // + // There is remaining part 3) + // + StartAddress3 =3D StartAddress2 + Length2; + Length3 =3D TotalLength - Length2; + ASSERT (Length3 < SIZE_2MB); + } + } else { + // + // Start address is not 2M aligned and total length is bigger than 2= M. + // + StartAddress1 =3D PhysicalAddress; + ASSERT (TotalLength > SIZE_2MB); + Length1 =3D SIZE_2MB - (PhysicalAddress & ALIGNED_2MB_MASK); + if (TotalLength - Length1 < SIZE_2MB) { + // + // The Part 2) length is less than 2MB, so let's accept all the + // memory in 4K + // + Length1 =3D TotalLength; + + } else { + StartAddress2 =3D PhysicalAddress + Length1; + Length2 =3D (TotalLength - Length1) & ~(UINT64)ALIGNED_2MB_MASK; + Length3 =3D TotalLength - Length1 - Length2; + StartAddress3 =3D Length3 > 0 ? StartAddress2 + Length2 : 0; + ASSERT (Length3 < SIZE_2MB); + } + } + } + + DEBUG ((DEBUG_INFO, "TdAccept: 0x%llx - 0x%llx\n", PhysicalAddress, Tota= lLength)); + DEBUG ((DEBUG_INFO, " Part1: 0x%llx - 0x%llx\n", StartAddress1, Length= 1)); + DEBUG ((DEBUG_INFO, " Part2: 0x%llx - 0x%llx\n", StartAddress2, Length= 2)); + DEBUG ((DEBUG_INFO, " Part3: 0x%llx - 0x%llx\n", StartAddress3, Length= 3)); + DEBUG ((DEBUG_INFO, " Chunk: 0x%llx, Page : 0x%llx\n", AcceptChunkSize= , AcceptPageSize)); + + MpSerializeStart (); + + if (Length2 > 0) { + MpSendWakeupCommand ( + MpProtectedModeWakeupCommandAcceptPages, + 0, + StartAddress2, + StartAddress2 + Length2, + AcceptChunkSize, + AcceptPageSize); + + Status =3D BspAcceptMemoryResourceRange ( + StartAddress2, + Length2, + AcceptChunkSize, + AcceptPageSize); + ASSERT (!EFI_ERROR (Status)); + } + + if (Length1 > 0) { + Status =3D BspAcceptMemoryResourceRange ( + StartAddress1, + Length1, + AcceptChunkSize, + SIZE_4KB); + ASSERT (!EFI_ERROR (Status)); + } + + if (Length3 > 0) { + Status =3D BspAcceptMemoryResourceRange ( + StartAddress3, + Length3, + AcceptChunkSize, + SIZE_4KB); + ASSERT (!EFI_ERROR (Status)); + } + + MpSerializeEnd (); + + CpusNum =3D GetCpusNum (); + MailBox =3D (volatile MP_WAKEUP_MAILBOX *) GetTdxMailBox (); + + DEBUG ((DEBUG_INFO, "AcceptPage Tallies:\n")); + DEBUG ((DEBUG_INFO, " ")); + for (Index =3D 0; Index < CpusNum; Index++) { + DEBUG ((DEBUG_INFO, "%8d", MailBox->Tallies[Index])); + if (Index % 8 =3D=3D 7) { + DEBUG ((DEBUG_INFO, "\n")); + DEBUG ((DEBUG_INFO, " ")); + } + } + DEBUG ((DEBUG_INFO, "\n")); + + for (Index =3D 0; Index < CpusNum; Index++) { + if (MailBox->Errors[Index] > 0) { + Status =3D EFI_DEVICE_ERROR; + DEBUG ((DEBUG_ERROR, "Error(%d) of CPU-%d when accepting memory\n", + MailBox->Errors[Index], Index)); + } + } + + return Status; +} + +/** + Dump out the hob list + + @param[in] HobStart Start address of the hob list +**/ +VOID +EFIAPI +DEBUG_HOBLIST ( + IN CONST VOID *HobStart + ) +{ + EFI_PEI_HOB_POINTERS Hob; + Hob.Raw =3D (UINT8 *) HobStart; + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + DEBUG ((DEBUG_INFO, "HOB(%p) : %x %x\n", Hob, Hob.Header->HobType, Hob= .Header->HobLength)); + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + DEBUG ((DEBUG_INFO, "\t: %x %x %llx %llx\n", + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength)); + + break; + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + DEBUG ((DEBUG_INFO, "\t: %llx %llx %x\n", + Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress, + Hob.MemoryAllocation->AllocDescriptor.MemoryLength, + Hob.MemoryAllocation->AllocDescriptor.MemoryType)); + break; + default: + break; + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } +} + +/** + Check the value whether in the valid list. + + @param[in] Value A value + @param[in] ValidList A pointer to valid list + @param[in] ValidListLength Length of valid list + + @retval TRUE The value is in valid list. + @retval FALSE The value is not in valid list. + +**/ +BOOLEAN +EFIAPI +IsInValidList ( + IN UINT32 Value, + IN UINT32 *ValidList, + IN UINT32 ValidListLength +) { + UINT32 index; + + if (ValidList =3D=3D NULL) { + return FALSE; + } + + for (index =3D 0; index < ValidListLength; index ++) { + if (ValidList[index] =3D=3D Value) { + return TRUE; + } + } + + return FALSE; +} + +/** + Check the integrity of VMM Hob List. + + @param[in] VmmHobList A pointer to Hob List + + @retval TRUE The Hob List is valid. + @retval FALSE The Hob List is invalid. + +**/ +BOOLEAN +EFIAPI +ValidateHobList ( + IN CONST VOID *VmmHobList + ) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 EFI_BOOT_MODE_LIST[12] =3D { BOOT_WITH_FULL_CONFIGURATION, + BOOT_WITH_MINIMAL_CONFIGURATION, + BOOT_ASSUMING_NO_CONFIGURATION_CHANGES, + BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAG= NOSTICS, + BOOT_WITH_DEFAULT_SETTINGS, + BOOT_ON_S4_RESUME, + BOOT_ON_S5_RESUME, + BOOT_WITH_MFG_MODE_SETTINGS, + BOOT_ON_S2_RESUME, + BOOT_ON_S3_RESUME, + BOOT_ON_FLASH_UPDATE, + BOOT_IN_RECOVERY_MODE + }; + + UINT32 EFI_RESOURCE_TYPE_LIST[8] =3D { EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_IO, + EFI_RESOURCE_FIRMWARE_DEVICE, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT, + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_IO_RESERVED, + EFI_RESOURCE_MAX_MEMORY_TYPE + }; + + if (VmmHobList =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "HOB: HOB data pointer is NULL\n")); + return FALSE; + } + + Hob.Raw =3D (UINT8 *) VmmHobList; + + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->Reserved !=3D (UINT32) 0) { + DEBUG ((DEBUG_ERROR, "HOB: Hob header Reserved filed should be zero\= n")); + return FALSE; + } + + if (Hob.Header->HobLength =3D=3D 0) { + DEBUG ((DEBUG_ERROR, "HOB: Hob header LEANGTH should not be zero\n= ")); + return FALSE; + } + + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_HANDOFF: + if (Hob.Header->HobLength !=3D sizeof(EFI_HOB_HANDOFF_INFO_TABLE))= { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_HANDOFF)); + return FALSE; + } + + if (IsInValidList (Hob.HandoffInformationTable->BootMode, EFI_BOOT= _MODE_LIST, 12) =3D=3D FALSE) { + DEBUG ((DEBUG_ERROR, "HOB: Unknow HandoffInformationTable BootMo= de type. Type: 0x%08x\n", Hob.HandoffInformationTable->BootMode)); + return FALSE; + } + + if ((Hob.HandoffInformationTable->EfiFreeMemoryTop % 4096) !=3D 0)= { + DEBUG ((DEBUG_ERROR, "HOB: HandoffInformationTable EfiFreeMemory= Top address must be 4-KB aligned to meet page restrictions of UEFI.\ + Address: 0x%016lx\n", Hob.HandoffInformatio= nTable->EfiFreeMemoryTop)); + return FALSE; + } + break; + + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + if (Hob.Header->HobLength !=3D sizeof(EFI_HOB_RESOURCE_DESCRIPTOR)= ) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_RESOURCE_DESCRIPTOR)); + return FALSE; + } + + if (IsInValidList (Hob.ResourceDescriptor->ResourceType, EFI_RESOU= RCE_TYPE_LIST, 8) =3D=3D FALSE) { + DEBUG ((DEBUG_ERROR, "HOB: Unknow ResourceDescriptor ResourceTyp= e type. Type: 0x%08x\n", Hob.ResourceDescriptor->ResourceType)); + return FALSE; + } + + if ((Hob.ResourceDescriptor->ResourceAttribute & (~(EFI_RESOURCE_A= TTRIBUTE_PRESENT | + EFI_RESOURCE_ATT= RIBUTE_INITIALIZED | + EFI_RESOURCE_ATT= RIBUTE_TESTED | + EFI_RESOURCE_ATT= RIBUTE_READ_PROTECTED | + EFI_RESOURCE_ATT= RIBUTE_WRITE_PROTECTED | + EFI_RESOURCE_ATT= RIBUTE_EXECUTION_PROTECTED | + EFI_RESOURCE_ATT= RIBUTE_PERSISTENT | + EFI_RESOURCE_ATT= RIBUTE_SINGLE_BIT_ECC | + EFI_RESOURCE_ATT= RIBUTE_MULTIPLE_BIT_ECC | + EFI_RESOURCE_ATT= RIBUTE_ECC_RESERVED_1 | + EFI_RESOURCE_ATT= RIBUTE_ECC_RESERVED_2 | + EFI_RESOURCE_ATT= RIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATT= RIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATT= RIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATT= RIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATT= RIBUTE_16_BIT_IO | + EFI_RESOURCE_ATT= RIBUTE_32_BIT_IO | + EFI_RESOURCE_ATT= RIBUTE_64_BIT_IO | + EFI_RESOURCE_ATT= RIBUTE_UNCACHED_EXPORTED | + EFI_RESOURCE_ATT= RIBUTE_READ_PROTECTABLE | + EFI_RESOURCE_ATT= RIBUTE_WRITE_PROTECTABLE | + EFI_RESOURCE_ATT= RIBUTE_EXECUTION_PROTECTABLE | + EFI_RESOURCE_ATT= RIBUTE_PERSISTABLE | + EFI_RESOURCE_ATT= RIBUTE_READ_ONLY_PROTECTED | + EFI_RESOURCE_ATT= RIBUTE_READ_ONLY_PROTECTABLE | + EFI_RESOURCE_ATT= RIBUTE_MORE_RELIABLE | + EFI_RESOURCE_ATT= RIBUTE_ENCRYPTED))) !=3D 0) { + DEBUG ((DEBUG_ERROR, "HOB: Unknow ResourceDescriptor ResourceAtt= ribute type. Type: 0x%08x\n", Hob.ResourceDescriptor->ResourceAttribute)); + return FALSE; + } + break; + + // EFI_HOB_GUID_TYPE is variable length data, so skip check + case EFI_HOB_TYPE_GUID_EXTENSION: + break; + + case EFI_HOB_TYPE_FV: + if (Hob.Header->HobLength !=3D sizeof (EFI_HOB_FIRMWARE_VOLUME)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV)); + return FALSE; + } + break; + + case EFI_HOB_TYPE_FV2: + if (Hob.Header->HobLength !=3D sizeof(EFI_HOB_FIRMWARE_VOLUME2)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV2)); + return FALSE; + } + break; + + case EFI_HOB_TYPE_FV3: + if (Hob.Header->HobLength !=3D sizeof(EFI_HOB_FIRMWARE_VOLUME3)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_FV3)); + return FALSE; + } + break; + + case EFI_HOB_TYPE_CPU: + if (Hob.Header->HobLength !=3D sizeof(EFI_HOB_CPU)) { + DEBUG ((DEBUG_ERROR, "HOB: Hob length is not equal corresponding= hob structure. Type: 0x%04x\n", EFI_HOB_TYPE_CPU)); + return FALSE; + } + + for (UINT32 index =3D 0; index < 6; index ++) { + if (Hob.Cpu->Reserved[index] !=3D 0) { + DEBUG ((DEBUG_ERROR, "HOB: Cpu Reserved field will always be s= et to zero.\n")); + return FALSE; + } + } + break; + + default: + DEBUG ((DEBUG_ERROR, "HOB: Hob type is not know. Type: 0x%04x\n", = Hob.Header->HobType)); + return FALSE; + } + // Get next HOB + Hob.Raw =3D (UINT8 *) (Hob.Raw + Hob.Header->HobLength); + } + + return TRUE; +} + +/** + Processing the incoming HobList for the TDX + + Firmware must parse list, and accept the pages of memory before their ca= n be + use by the guest. + + @param[in] VmmHobList The Hoblist pass the firmware + + @retval EFI_SUCCESS Process the HobList successfully + @retval Others Other errors as indicated + +**/ +EFI_STATUS +EFIAPI +ProcessHobList ( + IN CONST VOID *VmmHobList + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + EFI_PHYSICAL_ADDRESS PhysicalEnd; + + Status =3D EFI_SUCCESS; + ASSERT (VmmHobList !=3D NULL); + Hob.Raw =3D (UINT8 *) VmmHobList; + + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + DEBUG ((DEBUG_INFO, "\nResourceType: 0x%x\n", Hob.ResourceDescriptor= ->ResourceType)); + + if (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM_= MEMORY) { + DEBUG ((DEBUG_INFO, "ResourceAttribute: 0x%x\n", Hob.ResourceDescr= iptor->ResourceAttribute)); + DEBUG ((DEBUG_INFO, "PhysicalStart: 0x%llx\n", Hob.ResourceDescrip= tor->PhysicalStart)); + DEBUG ((DEBUG_INFO, "ResourceLength: 0x%llx\n", Hob.ResourceDescri= ptor->ResourceLength)); + DEBUG ((DEBUG_INFO, "Owner: %g\n\n", &Hob.ResourceDescriptor->Owne= r)); + + PhysicalEnd =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Resour= ceDescriptor->ResourceLength; + + Status =3D MpAcceptMemoryResourceRange ( + Hob.ResourceDescriptor->PhysicalStart, + PhysicalEnd); + if (EFI_ERROR (Status)) { + break; + } + } + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + return Status; +} + +/** + In Tdx guest, some information need to be passed from host VMM to guest + firmware. For example, the memory resource, etc. These information are + prepared by host VMM and put in HobList which is described in TdxMetadat= a. + + Information in HobList is treated as external input. From the security + perspective before it is consumed, it should be validated. + + @retval EFI_SUCCESS Successfully process the hoblist + @retval Others Other error as indicated +**/ +EFI_STATUS +EFIAPI +ProcessTdxHobList ( + VOID + ) +{ + EFI_STATUS Status; + VOID *TdHob; + TD_RETURN_DATA TdReturnData; + + TdHob =3D (VOID *) (UINTN) FixedPcdGet32 (PcdOvmfSecGhcbBase); + Status =3D TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData); + if (EFI_ERROR (Status)) { + return Status; + } + + DEBUG ((DEBUG_INFO, + "Intel Tdx Started with (GPAW: %d, Cpus: %d)\n", + TdReturnData.TdInfo.Gpaw, + TdReturnData.TdInfo.NumVcpus + )); + + // + // Validate HobList + // + if (ValidateHobList (TdHob) =3D=3D FALSE) { + return EFI_INVALID_PARAMETER; + } + + // + // Process Hoblist to accept memory + // + Status =3D ProcessHobList (TdHob); + + return Status; +} diff --git a/OvmfPkg/Sec/IntelTdx.h b/OvmfPkg/Sec/IntelTdx.h new file mode 100644 index 000000000000..9420f586b176 --- /dev/null +++ b/OvmfPkg/Sec/IntelTdx.h @@ -0,0 +1,33 @@ +/** @file + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __INTEL_TDX_H__ +#define __INTEL_TDX_H__ + +#include +#include +#include +#include +#include + +/** + In Tdx guest, some information need to be passed from host VMM to guest + firmware. For example, the memory resource, etc. These information are + prepared by host VMM and put in HobList which is described in TdxMetadat= a. + + Information in HobList is treated as external input. From the security + perspective before it is consumed, it should be validated. + + @retval EFI_SUCCESS Successfully process the hoblist + @retval Others Other error as indicated +**/ +EFI_STATUS +EFIAPI +ProcessTdxHobList ( + VOID + ); +#endif diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index e166a9389a1a..9792d7abe2d3 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -29,8 +29,11 @@ #include #include #include - +#include +#include +#include #include +#include "IntelTdx.h" =20 #define SEC_IDT_ENTRY_COUNT 34 =20 @@ -844,6 +847,19 @@ SecCoreStartupWithStack ( UINT32 Index; volatile UINT8 *Table; =20 +#if defined (MDE_CPU_X64) + if (TdxIsEnabled ()) { + // + // For Td guests, the memory map info is in TdHobLib. It should be pro= cessed + // first so that the memory is accepted. Otherwise access to the unacc= epted + // memory will trigger tripple fault. + // + if (ProcessTdxHobList () !=3D EFI_SUCCESS) { + CpuDeadLoop (); + } + } +#endif + // // To ensure SMM can't be compromised on S3 resume, we must force re-ini= t of // the BaseExtractGuidedSectionLib. Since this is before library contruc= tors @@ -861,13 +877,20 @@ SecCoreStartupWithStack ( // we use a loop rather than CopyMem. // IdtTableInStack.PeiService =3D NULL; + for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { - UINT8 *Src; - UINT8 *Dst; - UINTN Byte; + // + // Declare the local variables that actually move the data elements as + // volatile to prevent the optimizer from replacing this function with + // the intrinsic memcpy() + // + CONST UINT8 *Src; + volatile UINT8 *Dst; + UINTN Byte; + + Src =3D (CONST UINT8 *) &mIdtEntryTemplate; + Dst =3D (volatile UINT8 *) &IdtTableInStack.IdtTable[Index]; =20 - Src =3D (UINT8 *) &mIdtEntryTemplate; - Dst =3D (UINT8 *) &IdtTableInStack.IdtTable[Index]; for (Byte =3D 0; Byte < sizeof (mIdtEntryTemplate); Byte++) { Dst[Byte] =3D Src[Byte]; } @@ -913,6 +936,14 @@ SecCoreStartupWithStack ( AsmEnableCache (); } =20 + if (TdxIsEnabled ()) { + // + // InitializeCpuExceptionHandlers () should be called in Td guests so = that + // #VE exceptions can be handled correctly. + // + InitializeCpuExceptionHandlers (NULL); + } + DEBUG ((DEBUG_INFO, "SecCoreStartupWithStack(0x%x, 0x%x)\n", (UINT32)(UINTN)BootFv, diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 75cd5ee7264b..7d19ce1f4524 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -28,6 +28,7 @@ Ia32/SecEntry.nasm =20 [Sources.X64] + IntelTdx.c X64/SecEntry.nasm =20 [Packages] @@ -51,6 +52,9 @@ ExtractGuidedSectionLib LocalApicLib CpuExceptionHandlerLib + TdxLib + TdxMailboxLib + TdxProbeLib =20 [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED @@ -71,6 +75,8 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd gEfiMdeModulePkgTokenSpaceGuid.PcdInitValueInTempStack gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptChunkSize + gUefiOvmfPkgTokenSpaceGuid.PcdTdxAcceptPageSize =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79174): https://edk2.groups.io/g/devel/message/79174 Mute This Topic: https://groups.io/mt/84837914/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79175+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79175+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769498; cv=none; d=zohomail.com; s=zohoarc; b=K0aFf35SIlBq8iWTrYhdPVYTaSuMmYp5bNE8RlK08eL9n3SLvs0QK6N5ILnem8xVXnd4+Ro86SiRoacpK9Jki7srHceg2VEAlhq1BMVi7hx+E9rp4EUeaXBLeU52So3oxESyfnndolJ3FLUKsNFmztHBPzllNrQVDk5gmU9Hv6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769498; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=3GuyTMpzdqOTfXtYWLesgjpHNHcUeWFkiZhjVspEZdo=; b=BgXu15RHUBXFvpp/FwmkJ1ylsooEr2nLjDcW1tFDNbMCpGaaghSW2DjEZWS9yoGSoMPjAypn4FDcl4W5R5zw3nS5/XxexnLkDpndPGGJtvvtGFyeJRpAaovP7FnjbjxcAoKQ+qDH6Nmgt4HrRWkaPoWHCz8ZfbEHQvFq3NW7hQU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79175+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769498906344.78753996624414; Thu, 12 Aug 2021 04:58:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id fMKSYY1788612xQXTC4964nE; Thu, 12 Aug 2021 04:58:18 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:18 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524373" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524373" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:17 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433905" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:15 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 19/23] OvmfPkg: Check Tdx in QemuFwCfgPei to avoid DMA operation Date: Thu, 12 Aug 2021 19:56:58 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 4ta1hUNNiFsKLuwdFpjWGdZ8x1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769498; bh=o1uVByV4/ts13yTXYrcIIOZdjLXd/fsv+4gx4eMBP8I=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=UE6I0gtWnx/z+CCscMJ55pbQ7fDE9to6/aamYmR/DP+x4CBhymADykpLRoFiiImdYMr OYeqFhy6YR2f68NZ6OrSxyyvEzFfrVK7abjM8V7wqoBjr7TlicIxKXQ58QoxLA2lrCaah xVtYOeeh7eyIb716bgmTVqBa8YXYjtC4wFw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769500657100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 If TDX is enabled then we do not support DMA operation in PEI phase. This is mainly because DMA in TDX guest requires using bounce buffer (which need to allocate dynamic memory and allocating a PAGE size'd buffer can be challenge in PEI phase). Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c | 15 +++++++++++++++ OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf | 1 + 2 files changed, 16 insertions(+) diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c b/OvmfPkg/Library/= QemuFwCfgLib/QemuFwCfgPei.c index ecabd88fab66..aae5f2fcb51f 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPei.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include "QemuFwCfgLibInternal.h" =20 @@ -82,6 +83,14 @@ QemuFwCfgInitialize ( // if (MemEncryptSevIsEnabled ()) { DEBUG ((DEBUG_INFO, "SEV: QemuFwCfg fallback to IO Port interface.\n= ")); + } else if (TdxIsEnabled ()) { + // + // If TDX is enabled then we do not support DMA operations in PEI ph= ase. + // This is mainly because DMA in TDX guest requires using bounce buf= fer + // (which need to allocate dynamic memory and allocating a PAGE size= 'd + // buffer can be challenge in PEI phase) + // + DEBUG ((DEBUG_INFO, "TDX: QemuFwCfg fallback to IO Port interface.\n= ")); } else { mQemuFwCfgDmaSupported =3D TRUE; DEBUG ((DEBUG_INFO, "QemuFwCfg interface (DMA) is supported.\n")); @@ -162,6 +171,12 @@ InternalQemuFwCfgDmaBytes ( // ASSERT (!MemEncryptSevIsEnabled ()); =20 + // + // TDX does not support DMA operations in PEI stage, we should + // not have reached here. + // + ASSERT (!TdxIsEnabled ()); + Access.Control =3D SwapBytes32 (Control); Access.Length =3D SwapBytes32 (Size); Access.Address =3D SwapBytes64 ((UINTN)Buffer); diff --git a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf b/OvmfPkg/Lib= rary/QemuFwCfgLib/QemuFwCfgPeiLib.inf index 9f9af7d03201..808cb16f75e1 100644 --- a/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf +++ b/OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf @@ -42,4 +42,5 @@ IoLib MemoryAllocationLib MemEncryptSevLib + TdxProbeLib =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79175): https://edk2.groups.io/g/devel/message/79175 Mute This Topic: https://groups.io/mt/84837915/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79176+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79176+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769501; cv=none; d=zohomail.com; s=zohoarc; b=U43orypnPBDDet9K0KU4P7FprB6c+SFvt+ferx/GttYehn5KIE53vBcmQGSMgGPvxabyGoT9DZtUkf79DCM5HSSBtN781uiVpd0ALT76uwhvqVx+aXQU4y19oaeC1i1+W11+AcG+BIGCGygqxNelAfWAmu4jo8JfxRE6USRo8xQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769501; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=guu/Fg+jNev6R77/3qISAUsW8OKZbVMONGMdZnoivNQ=; b=J1CxfrAjf2/nBnNoUK685uNu/HL7EK0CkxPJKM463wq7epEn3PB4LOeFnPPUfw1Ht6By2vq4z+7ZwtT1//K/yk+KFn7thMKLnN6nT/kNit0XHRjwXtBgcXJom96trLLBcQZIJWt1410EyGfH9SqOP6LibyCRtt8IoysjKwKiTNo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79176+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769501251955.7463474449692; Thu, 12 Aug 2021 04:58:21 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 5JcNYY1788612xYO9XPFx29N; Thu, 12 Aug 2021 04:58:20 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:20 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524387" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524387" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:20 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433917" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:17 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Michael D Kinney , Liming Gao , Zhiguang Liu , Jiewen Yao Subject: [edk2-devel] [PATCH 20/23] MdePkg: Add AllocatePagesWithMemoryType support in PeiMemoryAllocationLib Date: Thu, 12 Aug 2021 19:56:59 +0800 Message-Id: <6924228fa3969ae944d6aebbe653d4046b6cef54.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: kN9zvFAk7lB3pIXqbhC7i4Tux1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769500; bh=26wFjmx3L4yACzga/sFN2BJXFujIIczLz4/l0l2zVrg=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=syyyWtWMq/bGEuHRGYWYUjywhvKQfPNyQETObd2w/0wDHgj19SNRjm2G1s/mxSMOsPt 07YB4WH/x/Ym1GrNHlGN+g0taLrZkAS6X5kZhkLlXOOPo8+MlSU3qzYBR6hLNXRgRRQcB G7VuGdRJ03ww6HFMzKRwyNR4iEWnR7dKqlc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769502941100002 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Allocates one or more 4KB pages of given type MemoryType. Allocates the number of 4KB pages of MemoryType and returns a pointer to the allocated buffer. The buffer returned is aligned on a 4KB boundary. If Pages is 0, then NULL is returned. If there is not enough memory remaining to satisfy the request, then NULL is returned. Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Jiewen Yao Signed-off-by: Min Xu --- MdePkg/Include/Library/MemoryAllocationLib.h | 21 +++++++++++++++ .../MemoryAllocationLib.c | 27 +++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/MdePkg/Include/Library/MemoryAllocationLib.h b/MdePkg/Include/= Library/MemoryAllocationLib.h index 65a30cf146dd..2bdc0592ef3e 100644 --- a/MdePkg/Include/Library/MemoryAllocationLib.h +++ b/MdePkg/Include/Library/MemoryAllocationLib.h @@ -484,4 +484,25 @@ FreePool ( IN VOID *Buffer ); =20 +/** + Allocates one or more 4KB pages of given type MemoryType. + + Allocates the number of 4KB pages of MemoryType and returns a pointer to= the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If P= ages + is 0, then NULL is returned. If there is not enough memory remaining to = satisfy + the request, then NULL is returned. + + @param MemoryType Type of memory to use for this allocation. + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocatePagesWithMemoryType ( + IN UINTN MemoryType, + IN UINTN Pages + ); + #endif diff --git a/MdePkg/Library/PeiMemoryAllocationLib/MemoryAllocationLib.c b/= MdePkg/Library/PeiMemoryAllocationLib/MemoryAllocationLib.c index b3f9df74f139..dcb313349729 100644 --- a/MdePkg/Library/PeiMemoryAllocationLib/MemoryAllocationLib.c +++ b/MdePkg/Library/PeiMemoryAllocationLib/MemoryAllocationLib.c @@ -839,4 +839,31 @@ FreePool ( // } =20 +/** + Allocates one or more 4KB pages of given type MemoryType. =20 + Allocates the number of 4KB pages of MemoryType and returns a pointer to= the + allocated buffer. The buffer returned is aligned on a 4KB boundary. If P= ages + is 0, then NULL is returned. If there is not enough memory remaining to = satisfy + the request, then NULL is returned. + + @param MemoryType Type of memory to use for this allocation. + @param Pages The number of 4 KB pages to allocate. + + @return A pointer to the allocated buffer or NULL if allocation fails. + +**/ +VOID * +EFIAPI +AllocatePagesWithMemoryType ( + IN UINTN MemoryType, + IN UINTN Pages + ) +{ + if (MemoryType >=3D EfiMaxMemoryType) { + ASSERT (FALSE); + return NULL; + } + + return InternalAllocatePages (MemoryType, Pages); +} --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79176): https://edk2.groups.io/g/devel/message/79176 Mute This Topic: https://groups.io/mt/84837917/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79177+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79177+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769503; cv=none; d=zohomail.com; s=zohoarc; b=K18gxvZxkeBSTGBoztUqPztDJ3XfcTAzg52bgCz9GLS06RlxCjnAS0vg7KOjmCF4njpH6x3vF2muqXt4gQ1RL9vsUjA5DwotbQGCR13bwAiatHZrQPwy8zA7LgH2AofDht/2DfQda5Y1Ja/3Nhd3m16lvsDFibd3GIdQaJjBnnA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769503; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=0doyxNlkdfFkTaruJ9Uc4W64XX6NYsSras0DC1mxchc=; b=FU3iBtG07AgMk28WGwMNVyuaUWeeDE5c9KTmnwMObvC/9jnKsCzMZizWrE4+tMNvQ2Ve39cZwqlELXT/EwTcX9tbZAwPRAMXnDTfOVX78viX8hLL9hR5iTjqeXjWsv4no495yjPDK9U9S89C6o6tbN2VJxCp/BxOFHqO8WgjLMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79177+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769503365847.4717612744103; Thu, 12 Aug 2021 04:58:23 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id gdzYYY1788612x1e8sWVLoGW; Thu, 12 Aug 2021 04:58:23 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:22 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524400" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524400" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:22 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433948" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:19 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 21/23] OvmfPkg: Add PcdUse1GPageTable support for TDX Date: Thu, 12 Aug 2021 19:57:00 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: BYSEfzyxcw8C8MrTbS3khMHdx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769503; bh=v7aFeVbdxVdftD7g/euiMHxN3KkPpfuLG1wSGjEyrzk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=jdhBqeprhKNs6MPVBKzlrnqcnnfqxuqm7KBgnjKgXOVx9ZVlIoXUA6q7Ru1K4kWJEPc B7BMjSwdEf8WQbLS4Pm7o2iuNyRtP6EbqUEfkaUTaIICdMhH5LNgz34OWnaM/y2EfY76O 2YMpr7Dl+iZdp8TzffxMLSSH3PzxO736g+Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769505133100001 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Intel TDX uses 1G page table. But PcdUse1GPageTable is set to FALSE by default in OvmfPkgX64.dsc. It gives no chance to support 1G page table. To support 1G page table in TDX this PCD is set to TRUE in OvmfPkgX64.dsc. From the code in VirtualMemory.c (MdeModulePkg\Core\DxeIplPeim\X64), even PcdUse1GPageTable is TRUE, Page1GSupport is FALSE until more checking is done. So setting PcdUse1GPageTable to TRUE is to give a chance to check if 1G page table is supported. Page1GSupport =3D FALSE; if (PcdGetBool(PcdUse1GPageTable)) { AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); if (RegEax >=3D 0x80000001) { AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx); if ((RegEdx & BIT26) !=3D 0) { Page1GSupport =3D TRUE; } } } Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkgX64.dsc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index b2e07233ebd6..97c923423d3f 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -576,6 +576,10 @@ gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode|0x100 gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData|0x100 =20 + # + # TDX need 1G PageTable support + gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE + # # Network Pcds # --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79177): https://edk2.groups.io/g/devel/message/79177 Mute This Topic: https://groups.io/mt/84837919/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79178+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79178+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769506; cv=none; d=zohomail.com; s=zohoarc; b=ZByBybGLmZHGX1GTWG9FJZ5gVmHQQ893yMDLujQkK7or+Hc2zzQhl9nM/CKTwSkQ4gd82FeKPoc8EP9ULpSyU8/lwLGVuAy+AzxGI/R7ChkOqDZCsvo90G3NCxjsmfLlk98dxLMz9Ek4txypJSOd3zZYG5Ofw2sgHeszj9cmYw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769506; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qbtnu00WcT3g5Fzlek04Zt8oYPhmyLZWl6wguDmcXVM=; b=Ubj+4FBmJHxZ4d2vdJd+h0DFXt/Bj4yM02oFfnbAoIYFtOsKbuHYajXEjIKEwHXXqVeQ/GVW5t+5Rsgm9UIprWWs0xT/TmyaX2+Uj3qCp84k4awWS/HwU4uLaVjeOz1XfeatPioFOGeGoTac834pGZqWuniHdfTueqaK7yIjGzI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79178+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162876950657765.43632599653176; Thu, 12 Aug 2021 04:58:26 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id jwKQYY1788612xPmXJKah5se; Thu, 12 Aug 2021 04:58:26 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:25 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524416" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524416" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:24 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433974" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:22 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Jian J Wang , Hao A Wu , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 22/23] MdeModulePkg: EFER should not be changed in TDX Date: Thu, 12 Aug 2021 19:57:01 +0800 Message-Id: <0b64c2c2c6e4c7ecd8562fc295f5b1d92ec214b1.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: FwiyQqKthdsJLBrPQXxUbOH6x1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769506; bh=Kj/SlxbFLv2ZAd55RBjmEDkhyq+Xkjz+NniLqtkX2d0=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=kFMVWOXuTNIykXDQIYlWRGGzigIMJz135+8cs5w7aBAfMV3H7ZDzRInsTRn207G8OFA W5FDDf9gzk5n1hJFWmgl3bx9HJRs8O9PCINqSCAY0UZB7D1n3YhQl9mh2X1y3g5HrvqWa OdOMwDDlb1eHPz7NUKXy4tDPe56aB4dt/2w= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769507479100002 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In TDX IA32_ERER is RO to host VMM. It could not be changed. PcdIa32EferChangeAllowed is added in MdeModulePkg.dec and it is to be set to FALSE in Tdx guest. Cc: Jian J Wang Cc: Hao A Wu Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 1 + MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c | 6 ++++++ MdeModulePkg/MdeModulePkg.dec | 5 +++++ 3 files changed, 12 insertions(+) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 19b8a4c8aefa..106b679b6bd0 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -117,6 +117,7 @@ gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 6831946c54d3..8a3b72509310 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -148,6 +148,12 @@ IsEnableNonExecNeeded ( return FALSE; } =20 + // + // Intel TDX sets this flag to FALSE. + // + if (!PcdGetBool (PcdIa32EferChangeAllowed)) { + return FALSE; + } // // XD flag (BIT63) in page table entry is only valid if IA32_EFER.NXE is= set. // Features controlled by Following PCDs need this feature to be enabled. diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 133e04ee86ca..007044a311c2 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2138,6 +2138,11 @@ # @Prompt GHCB Pool Size gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008 =20 + ## This dynamic PCD indicates if IA32_EFER can be changed. The default v= alue is TRUE but in + # Intel TDX change of IA32_EFER is not allowed. + # @Prompt The flag which indicates if IA32_EFER is allowed to be changed. + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed|TRUE|BOOLEAN|0x0= 0030009 + [PcdsDynamicEx] ## This dynamic PCD enables the default variable setting. # Its value is the default store ID value. The default value is zero as= Standard default. --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79178): https://edk2.groups.io/g/devel/message/79178 Mute This Topic: https://groups.io/mt/84837921/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri May 3 12:02:58 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+79179+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79179+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1628769508; cv=none; d=zohomail.com; s=zohoarc; b=JLVT4+kaaMfTapVxsTMepT88JFOsovPsdm5qg+HUfDovqpsMzmOdTi+kBl5pNxTcH2OM6KeY2Wo1FMmnrFw1g6sYCIKSI6Et3JjKk3y6TZKulDUYDSFbacgqRuSmoKEMpdQ2IPi+pzbpraTXTIBSTKphVwSOsOB6rIXZiWoUHig= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1628769508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=RhCrTiD3+Abh8b3goSuubVdSgsQWd3bcmIwXnUY+xOQ=; b=LjC8VpBX5xgleH174aR62Cgyse8IjTYw3S7ieUHrxFnUw94MM/SoqIjQdJaqAGn27uQ71YvrYS8SSPpWl1zsJ3iGYhrhAPnHrK6ODn1lvpbVyBRmTW1GYzLWON9SLsiJytaCbTVKcn4ZuUGILCNbVEIxcpjYpNTL8gVYgGoEUww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+79179+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1628769508565254.0271828985317; Thu, 12 Aug 2021 04:58:28 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3qEEYY1788612xQBGOmmMD9Q; Thu, 12 Aug 2021 04:58:28 -0700 X-Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web09.21069.1628769481864596349 for ; Thu, 12 Aug 2021 04:58:27 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10073"; a="202524434" X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="202524434" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:27 -0700 X-IronPort-AV: E=Sophos;i="5.84,315,1620716400"; d="scan'208";a="517433987" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.248]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Aug 2021 04:58:24 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH 23/23] OvmfPkg: Update PlatformPei to support TDX Date: Thu, 12 Aug 2021 19:57:02 +0800 Message-Id: <50a57dfb90f362399d19dcdb19aa0063a2a12176.1628767741.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: zzYUOsajXKtu2t8idBnjnSakx1787277AA= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1628769508; bh=9e/7Iv0gRRzoB6XU90JLfCTEMSVE5yi0q3kMMO/jfvA=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=lJhmapWo1XpqpoK4auSl5ujFZHOiVxiF3S1LffW3h3pPpj2YLQa45ymYgoA430iDGtI t+xLiuA1ytaSAk/qPJHsesJAe4tiTBVR7XUq62nRJT7M89Tg8euGxml0NerY0ox5FBmBz 4S8C91yvHItrg+Gd9PY3OW3eMHoJ7blA8rU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1628769509650100006 RFC=EF=BC=9A https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Intel TDX has its own requirement in InitializePlatform (PlatformPei). 1. Publish the ram region Host VMM pass the memory region to TDVF in TD Hob. These memory are accepted by TDVF before they're available for access. TDVF publish these memory information in the final hoblist for DXE. 2. Relocate mailbox At the beginning of system boot, a 4K-aligned, 4K-size memory (Td mailbox) is pre-allocated by host VMM. BSP & APs do the page accept together in that memory region. After that TDVF is designed to relocate the mailbox to a 4K-aligned, 4K-size memory block which is allocated in the ACPI Nvs memory. APs are waken up and spin around the relocated mailbox waiting for further command. 3. Create PlatformInfoHob PlatformInfoHob contains the TDX specific information, for example, the relocated Mailbox address. gUefiOvmfPkgTdxPlatformGuid is the new GUID added in OvmfPkg.dec for this purpose. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 1 + OvmfPkg/PlatformPei/FeatureControl.c | 9 +- OvmfPkg/PlatformPei/IntelTdx.c | 268 +++++++++++++++++++++++++ OvmfPkg/PlatformPei/IntelTdxNull.c | 35 ++++ OvmfPkg/PlatformPei/MemDetect.c | 20 +- OvmfPkg/PlatformPei/Platform.c | 2 + OvmfPkg/PlatformPei/Platform.h | 17 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 14 ++ OvmfPkg/PlatformPei/X64/ApRunLoop.nasm | 83 ++++++++ 9 files changed, 447 insertions(+), 2 deletions(-) create mode 100644 OvmfPkg/PlatformPei/IntelTdx.c create mode 100644 OvmfPkg/PlatformPei/IntelTdxNull.c create mode 100644 OvmfPkg/PlatformPei/X64/ApRunLoop.nasm diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index a9765f2a60be..2ad0b5de25e1 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -128,6 +128,7 @@ gQemuKernelLoaderFsMediaGuid =3D {0x1428f772, 0xb64a, 0x441e, {= 0xb8, 0xc3, 0x9e, 0xbd, 0xd7, 0xf8, 0x93, 0xc7}} gGrubFileGuid =3D {0xb5ae312c, 0xbc8a, 0x43b1, {= 0x9c, 0x62, 0xeb, 0xb8, 0x26, 0xdd, 0x5d, 0x07}} gConfidentialComputingSecretGuid =3D {0xadf956ad, 0xe98c, 0x484c, {= 0xae, 0x11, 0xb5, 0x1c, 0x7d, 0x33, 0x64, 0x47}} + gUefiOvmfPkgTdxPlatformGuid =3D {0xdec9b486, 0x1f16, 0x47c7, {= 0x8f, 0x68, 0xdf, 0x1a, 0x41, 0x88, 0x8b, 0xa5}} =20 [Ppis] # PPI whose presence in the PPI database signals that the TPM base addre= ss diff --git a/OvmfPkg/PlatformPei/FeatureControl.c b/OvmfPkg/PlatformPei/Fea= tureControl.c index dccf9505dd7b..36451d0c9c24 100644 --- a/OvmfPkg/PlatformPei/FeatureControl.c +++ b/OvmfPkg/PlatformPei/FeatureControl.c @@ -12,6 +12,9 @@ #include #include #include +#include +#include +#include =20 #include "Platform.h" =20 @@ -37,7 +40,11 @@ WriteFeatureControl ( IN OUT VOID *WorkSpace ) { - AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + if (TdxIsEnabled ()) { + TdVmCall (TDVMCALL_WRMSR, (UINT64) MSR_IA32_FEATURE_CONTROL, mFeatureC= ontrolValue, 0, 0, 0); + } else { + AsmWriteMsr64 (MSR_IA32_FEATURE_CONTROL, mFeatureControlValue); + } } =20 /** diff --git a/OvmfPkg/PlatformPei/IntelTdx.c b/OvmfPkg/PlatformPei/IntelTdx.c new file mode 100644 index 000000000000..598286d8ae2b --- /dev/null +++ b/OvmfPkg/PlatformPei/IntelTdx.c @@ -0,0 +1,268 @@ +/** @file + Initialize Intel TDX support. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "Platform.h" + +VOID +EFIAPI +DEBUG_HOBLIST ( + IN CONST VOID *HobStart + ) +{ + EFI_PEI_HOB_POINTERS Hob; + Hob.Raw =3D (UINT8 *) HobStart; + // + // Parse the HOB list until end of list or matching type is found. + // + while (!END_OF_HOB_LIST (Hob)) { + DEBUG ((DEBUG_INFO, "HOB(%p) : %x %x\n", Hob, Hob.Header->HobType, Hob= .Header->HobLength)); + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + DEBUG ((DEBUG_INFO, "\t: %x %x %llx %llx\n", + Hob.ResourceDescriptor->ResourceType, + Hob.ResourceDescriptor->ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength)); + + break; + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + DEBUG ((DEBUG_INFO, "\t: %llx %llx %x\n", + Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress, + Hob.MemoryAllocation->AllocDescriptor.MemoryLength, + Hob.MemoryAllocation->AllocDescriptor.MemoryType)); + break; + default: + break; + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } +} + +/** + Transfer the incoming HobList for the TD to the final HobList for Dxe. + The Hobs transferred in this function are ResourceDescriptor hob and + MemoryAllocation hob. + + @param[in] VmmHobList The Hoblist pass the firmware + +**/ +VOID +EFIAPI +TransferTdxHobList ( + VOID + ) +{ + EFI_PEI_HOB_POINTERS Hob; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + EFI_PHYSICAL_ADDRESS PhysicalEnd; + + // + // PcdOvmfSecGhcbBase is used as the TD_HOB in Tdx guest. + // + Hob.Raw =3D (UINT8 *) (UINTN) PcdGet32 (PcdOvmfSecGhcbBase); + while (!END_OF_HOB_LIST (Hob)) { + switch (Hob.Header->HobType) { + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + ResourceAttribute =3D Hob.ResourceDescriptor->ResourceAttribute; + PhysicalEnd =3D Hob.ResourceDescriptor->PhysicalStart + Hob.Resource= Descriptor->ResourceLength; + + // + // We mark each resource that we issue AcceptPage to with EFI_RESOUR= CE_SYSTEM_MEMORY + // + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) && + (PhysicalEnd <=3D BASE_4GB)) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_ENCRYPTED; + } + BuildResourceDescriptorHob ( + Hob.ResourceDescriptor->ResourceType, + ResourceAttribute, + Hob.ResourceDescriptor->PhysicalStart, + Hob.ResourceDescriptor->ResourceLength); + break; + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + BuildMemoryAllocationHob ( + Hob.MemoryAllocation->AllocDescriptor.MemoryBaseAddress, + Hob.MemoryAllocation->AllocDescriptor.MemoryLength, + Hob.MemoryAllocation->AllocDescriptor.MemoryType); + break; + } + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + DEBUG_HOBLIST (GetHobList ()); +} + +/** + + Publish memory regions in Intel TDX guest. + +**/ +VOID +TdxPublishRamRegions ( + VOID + ) +{ + TransferTdxHobList (); + + // + // The memory region defined by PcdOvmfSecGhcbBackupBase is pre-allocate= d by + // host VMM and used as the td mailbox at the beginning of system boot. + // + BuildMemoryAllocationHob ( + PcdGet32 (PcdOvmfSecGhcbBackupBase), + PcdGet32 (PcdOvmfSecGhcbBackupSize), + EfiACPIMemoryNVS + ); +} + +/** + This function check the system status from QEMU via fw_cfg. + If the system status from QEMU is retrieved, its value is set + into PlatformInfoHob. + + @param[in] PlatformInfoHob The data structure of PlatformInfo hob +**/ +VOID +EFIAPI +CheckSystemStatsForOverride ( + IN EFI_HOB_PLATFORM_INFO * PlatformInfoHob + ) +{ + EFI_STATUS Status; + FIRMWARE_CONFIG_ITEM FwCfgItem; + UINTN FwCfgSize; + + // + // check for overrides + // + Status =3D QemuFwCfgFindFile ("etc/system-states", &FwCfgItem, &FwCfgSiz= e); + if (Status !=3D RETURN_SUCCESS || FwCfgSize !=3D sizeof PlatformInfoHob-= >SystemStates) { + DEBUG ((DEBUG_INFO, "ACPI using S3/S4 defaults\n")); + return; + } + + QemuFwCfgSelectItem (FwCfgItem); + QemuFwCfgReadBytes (sizeof (PlatformInfoHob->SystemStates), PlatformInfo= Hob->SystemStates); +} + +/** + At the beginning of system boot, a 4K-aligned, 4K-size memory (Td mailbo= x) is + pre-allocated by host VMM. BSP & APs do the page accept together in that= memory + region. + + After that TDVF is designed to relocate the mailbox to a 4K-aligned, 4K-= size + memory block which is allocated in the ACPI Nvs memory. APs are waken up= and + spin around the relocated mailbox for further command. + + @return UINT64 Address of the relocated mailbox +**/ +UINT64 +EFIAPI +TdxRelocateMailbox ( + VOID + ) +{ + VOID *Address; + VOID *ApLoopFunc =3D NULL; + UINT32 RelocationPages; + MP_RELOCATION_MAP RelocationMap; + MP_WAKEUP_MAILBOX *RelocatedMailBox; + + // + // Get information needed to setup aps running in their + // run loop in allocated acpi reserved memory + // Add another page for mailbox + // + AsmGetRelocationMap (&RelocationMap); + RelocationPages =3D EFI_SIZE_TO_PAGES ((UINT32)RelocationMap.RelocateAp= LoopFuncSize) + 1; + + Address =3D AllocatePagesWithMemoryType (EfiACPIMemoryNVS, RelocationPag= es); + ApLoopFunc =3D (VOID *) ((UINTN) Address + EFI_PAGE_SIZE); + + CopyMem ( + ApLoopFunc, + RelocationMap.RelocateApLoopFuncAddress, + RelocationMap.RelocateApLoopFuncSize + ); + + DEBUG ((DEBUG_INFO, "Ap Relocation: mailbox %p, loop %p\n", + Address, ApLoopFunc)); + + // + // Initialize mailbox + // + RelocatedMailBox =3D (MP_WAKEUP_MAILBOX *)Address; + RelocatedMailBox->Command =3D MpProtectedModeWakeupCommandNoop; + RelocatedMailBox->ApicId =3D MP_CPU_PROTECTED_MODE_MAILBOX_APICID_INVALI= D; + RelocatedMailBox->WakeUpVector =3D 0; + + // + // Wakup APs and have been move to the finalized run loop + // They will spin until guest OS wakes them + // + MpSerializeStart (); + + MpSendWakeupCommand ( + MpProtectedModeWakeupCommandWakeup, + (UINT64)ApLoopFunc, + (UINT64)RelocatedMailBox, + 0, + 0, + 0); + + return (UINT64)RelocatedMailBox; +} + +/** + + This Function checks if TDX is available, if present then it sets + the dynamic PcdTdxIsEnabled and PcdIa32EferChangeAllowed. + + It relocates the td mailbox and create the PlatformInfo Hob which includ= es + the TDX specific information which will be consumed in DXE phase. + + **/ +VOID +IntelTdxInitialize ( + VOID + ) +{ + EFI_HOB_PLATFORM_INFO PlatformInfoHob; + RETURN_STATUS PcdStatus; + + if (!TdxIsEnabled ()) { + return; + } + + PcdStatus =3D PcdSetBoolS (PcdTdxIsEnabled, TRUE); + ASSERT_RETURN_ERROR (PcdStatus); + + PcdStatus =3D PcdSetBoolS (PcdIa32EferChangeAllowed, FALSE); + ASSERT_RETURN_ERROR (PcdStatus); + + ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob)); + PlatformInfoHob.HostBridgePciDevId =3D mHostBridgeDevId; + + PlatformInfoHob.RelocatedMailBox =3D TdxRelocateMailbox (); + + CheckSystemStatsForOverride (&PlatformInfoHob); + + BuildGuidDataHob (&gUefiOvmfPkgTdxPlatformGuid, &PlatformInfoHob, sizeof= (EFI_HOB_PLATFORM_INFO)); +} diff --git a/OvmfPkg/PlatformPei/IntelTdxNull.c b/OvmfPkg/PlatformPei/Intel= TdxNull.c new file mode 100644 index 000000000000..871f213fca48 --- /dev/null +++ b/OvmfPkg/PlatformPei/IntelTdxNull.c @@ -0,0 +1,35 @@ +/** @file + Main SEC phase code. Handles initial TDX Hob List Processing + + Copyright (c) 2008, Intel Corporation. All rights reserved.
+ (C) Copyright 2016 Hewlett Packard Enterprise Development LP
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include + +VOID +TdxPublishRamRegions ( + VOID + ) +{ +} + +VOID +IntelTdxInitialize ( + VOID + ) +{ +} + +VOID +AsmGetRelocationMap ( + OUT MP_RELOCATION_MAP *AddressMap + ) +{ +} diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 2deec128f464..d36cd362f667 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -35,6 +35,8 @@ Module Name: #include #include #include +#include +#include =20 #include "Platform.h" #include "Cmos.h" @@ -484,6 +486,7 @@ AddressWidthInitialization ( ) { UINT64 FirstNonAddress; + UINT64 TdxSharedPageMask; =20 // // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts @@ -511,6 +514,17 @@ AddressWidthInitialization ( if (mPhysMemAddressWidth <=3D 36) { mPhysMemAddressWidth =3D 36; } + + if (TdxIsEnabled ()) { + TdxSharedPageMask =3D TdSharedPageMask (); + if (TdxSharedPageMask =3D=3D (1ULL << 47)) { + mPhysMemAddressWidth =3D 48; + } else { + DEBUG ((DEBUG_ERROR, "Currently only PhysMemAddressWidth =3D 48 is s= upported in TDX.\n")); + ASSERT (FALSE); + } + } + ASSERT (mPhysMemAddressWidth <=3D 48); } =20 @@ -815,7 +829,11 @@ InitializeRamRegions ( VOID ) { - QemuInitializeRam (); + if (TdxIsEnabled ()) { + TdxPublishRamRegions (); + } else { + QemuInitializeRam (); + } =20 if (mS3Supported && mBootMode !=3D BOOT_ON_S3_RESUME) { // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d3a20122a2ea..4be3c4bd1d3c 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -35,6 +35,7 @@ #include #include #include +#include =20 #include "Platform.h" #include "Cmos.h" @@ -742,6 +743,7 @@ InitializePlatform ( =20 InstallClearCacheCallback (); AmdSevInitialize (); + IntelTdxInitialize (); MiscInitialization (); InstallFeatureControlCallback (); =20 diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 8b1d270c2b0b..89121bcb8a41 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -10,6 +10,7 @@ #define _PLATFORM_PEI_H_INCLUDED_ =20 #include +#include =20 VOID AddIoMemoryBaseSizeHob ( @@ -102,6 +103,22 @@ AmdSevInitialize ( VOID ); =20 +VOID +TdxPublishRamRegions ( + VOID + ); + +VOID +AsmGetRelocationMap ( + OUT MP_RELOCATION_MAP *AddressMap + ); + + +VOID +IntelTdxInitialize ( + VOID + ); + extern EFI_BOOT_MODE mBootMode; =20 extern BOOLEAN mS3Supported; diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 89d1f7636870..80f2b3a52ac9 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -34,6 +34,13 @@ Platform.c Platform.h =20 +[Sources.IA32, Sources.EBC] + IntelTdxNull.c + +[Sources.X64] + IntelTdx.c + X64/ApRunLoop.nasm + [Packages] EmbeddedPkg/EmbeddedPkg.dec MdePkg/MdePkg.dec @@ -44,6 +51,7 @@ =20 [Guids] gEfiMemoryTypeInformationGuid + gUefiOvmfPkgTdxPlatformGuid =20 [LibraryClasses] BaseLib @@ -62,6 +70,10 @@ MtrrLib MemEncryptSevLib PcdLib + TdxProbeLib + TdxMailboxLib + TdxLib + MemoryAllocationLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase @@ -106,6 +118,8 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled + gUefiCpuPkgTokenSpaceGuid.PcdTdxIsEnabled + gEfiMdeModulePkgTokenSpaceGuid.PcdIa32EferChangeAllowed =20 [FixedPcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/OvmfPkg/PlatformPei/X64/ApRunLoop.nasm b/OvmfPkg/PlatformPei/X= 64/ApRunLoop.nasm new file mode 100644 index 000000000000..adf4f03c3a9e --- /dev/null +++ b/OvmfPkg/PlatformPei/X64/ApRunLoop.nasm @@ -0,0 +1,83 @@ +;-------------------------------------------------------------------------= ----- ; +; Copyright (c) 2015, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; ApRunLoop.nasm +; +; Abstract: +; +; This is the assembly code for run loop for APs in the guest TD +; +;-------------------------------------------------------------------------= ------ + +%include "TdxCommondefs.inc" + +DEFAULT REL + +SECTION .text + +BITS 64 + +%macro tdcall 0 + db 0x66, 0x0f, 0x01, 0xcc +%endmacro + +; +; Relocated Ap Mailbox loop +; +; @param[in] RBX: Relocated mailbox address +; @param[in] RBP: vCpuId +; +; @return None This routine does not return +; +global ASM_PFX(AsmRelocateApMailBoxLoop) +ASM_PFX(AsmRelocateApMailBoxLoop): +AsmRelocateApMailBoxLoopStart: + + ; + ; TdCall[TDINFO] to get the vCpuId + ; + ;mov rax, 1 + ;tdcall + ; + ; R8 [31:0] NUM_VCPUS + ; [63:32] MAX_VCPUS + ; R9 [31:0] VCPU_INDEX + ; + + mov r8, rbp +MailBoxLoop: + ; Spin until command set + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandNo= op + je MailBoxLoop + ; Determine if this is a broadcast or directly for my apic-id, if not,= ignore + cmp dword [rbx + ApicidOffset], MailboxApicidBroadcast + je MailBoxProcessCommand + cmp dword [rbx + ApicidOffset], r8d + jne MailBoxLoop +MailBoxProcessCommand: + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandWa= keup + je MailBoxWakeUp + cmp dword [rbx + CommandOffset], MpProtectedModeWakeupCommandSl= eep + je MailBoxSleep + ; Don't support this command, so ignore + jmp MailBoxLoop +MailBoxWakeUp: + mov rax, [rbx + WakeupVectorOffset] + jmp rax +MailBoxSleep: + jmp $ +BITS 64 +AsmRelocateApMailBoxLoopEnd: + +;-------------------------------------------------------------------------= ------------ +; AsmGetRelocationMap (&RelocationMap); +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(AsmGetRelocationMap) +ASM_PFX(AsmGetRelocationMap): + lea rax, [ASM_PFX(AsmRelocateApMailBoxLoopStart)] + mov qword [rcx], rax + mov qword [rcx + 8h], AsmRelocateApMailBoxLoopEnd - AsmRelocat= eApMailBoxLoopStart + ret --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#79179): https://edk2.groups.io/g/devel/message/79179 Mute This Topic: https://groups.io/mt/84837923/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-