From nobody Mon May 6 18:09:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78056+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78056+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626933190; cv=none; d=zohomail.com; s=zohoarc; b=EfU71dpE5VrevFbNzSQXBB3eMC61VHoZeDqyWi9kRihbIGrjPL9kBnHshFj3mR/Muj2rYm0OGv/INq3eSloLic3zEakqMRp9h8eRelKOxvD690VvV1VOS/Tf9MaQIXytIjoLJipuHJpwMOqCD51R/Y/OGh3tZw0EVzGBPMj3uvQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626933190; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VKmNwTmz4BhRv4eJG2KMr0EtgkWZA/NyoTrLL1+DpmQ=; b=bbR4MfvwbIYaAzLXPhmCTPiSC02IbRwzWrwBwXDNtOGRHh4uKfPj62ba4XFYVZy1SaUMESg2beiPnFI1hKZmQ57C2d/q6iVmEq4Kh7OK3yWwlRg0wD05GSbLg08hjcGUR/AMc14bTYF30tH0bfcriSuPHuxE9jIxaOzgJ0vUXz8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78056+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 162693319000459.45746191888895; Wed, 21 Jul 2021 22:53:10 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id wXZEYY1788612xwR6yhqXRs2; Wed, 21 Jul 2021 22:53:09 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web09.4239.1626933188573229816 for ; Wed, 21 Jul 2021 22:53:09 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10052"; a="275391623" X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="275391623" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:08 -0700 X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="512374760" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.4.4]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:05 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V2 1/4] OvmfPkg: Add Tdx BFV/CFV PCDs and PcdOvmfImageSizeInKb Date: Thu, 22 Jul 2021 13:52:13 +0800 Message-Id: <594806725a3ded1516d4a7e77b03c77c31d2ab1a.1626931332.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: Ezdo2XtaPcWioTRUnWeQzbmZx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626933189; bh=3CtvyRw/LP7QjkFkIQgvL4tat/kE3PeCK0DOMUNMwok=; h=Cc:Date:From:Reply-To:Subject:To; b=mmh+lvTkA5q4ihfImv+FAY18IrKskhuGxBPekRbRX3UhRya3cgedUcfRwBJ/bLrCbWs rHGje51kJ3pHG3fTHJWUsWIucCHSay95gcAQQlAId3emRphpYIvlCbdsaEGSkE7MRi3FW k+wE2qnI/hPBkDgo7pzJF9/WCP1jQ/X4Ofo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626933191883100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Tdx Virtual Firmware (TDVF) includes one Firmware Volume (FV) known as the Boot Firmware Volume (BFV). The FV format is defined in the UEFI Platform Initialization (PI) spec. BFV includes all TDVF components required during boot. TDVF also include a configuration firmware volume (CFV) that is separated from the BFV. The reason is because the CFV is measured in RTMR, while the BFV is measured in MRTD. In practice BFV is the code part of Ovmf image. CFV is the vars part of Ovmf image (exclude the SPARE part). PcdOvmfImageSizeInKb is added which is used to calculate the offset of TdxMetadata in ResetVectorVtf0.asm. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/OvmfPkg.dec | 13 +++++++++++++ OvmfPkg/OvmfPkgDefines.fdf.inc | 12 +++++++++++- 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 6ae733f6e39f..6d9bb91e9274 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -321,6 +321,19 @@ gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase|0x0|UINT32|0x42 gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretSize|0x0|UINT32|0x43 =20 + ## The base address and size of the TDX Cfv base and size. + gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase|0|UINT32|0x47 + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset|0|UINT32|0x48 + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize|0|UINT32|0x49 + + ## The base address and size of the TDX Bfv base and size. + gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase|0|UINT32|0x4a + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset|0|UINT32|0x4b + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize|0|UINT32|0x4c + + ## Size of the Ovmf image in KB + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb|0|UINT32|0x4d + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgDefines.fdf.inc b/OvmfPkg/OvmfPkgDefines.fdf.inc index 35fd454b97ab..401e491e4cbe 100644 --- a/OvmfPkg/OvmfPkgDefines.fdf.inc +++ b/OvmfPkg/OvmfPkgDefines.fdf.inc @@ -2,13 +2,14 @@ # FDF include file that defines the main macros and sets the dependent PC= Ds. # # Copyright (C) 2014, Red Hat, Inc. -# Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 DEFINE BLOCK_SIZE =3D 0x1000 +DEFINE VARS_OFFSET =3D 0 =20 # # A firmware binary built with FD_SIZE_IN_KB=3D1024, and a firmware binary= built @@ -66,6 +67,7 @@ DEFINE SECFV_OFFSET =3D 0x003CC000 DEFINE SECFV_SIZE =3D 0x34000 !endif =20 +SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb =3D $(FD_SIZE_IN_K= B) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress =3D $(FW_BASE_ADDR= ESS) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize =3D $(FW_SIZE) SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize =3D $(BLOCK_SIZE) @@ -82,6 +84,14 @@ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwW= orkingSize =3D $(BLOCK_SIZ SET gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase =3D gUefi= OvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase + gEfiMdeModulePk= gTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D $(VAR= S_SPARE_SIZE) =20 +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase =3D $(FW_BASE_ADDRESS) +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset =3D $(VARS_OFFSET) +SET gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize =3D $(VARS_LIVE_SIZE) + +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase =3D $(CODE_BASE_ADDRES= S) +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset =3D $(VARS_SIZE) +SET gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize =3D $(CODE_SIZE) + !if $(SMM_REQUIRE) =3D=3D TRUE SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 =3D gUe= fiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase =3D gUe= fiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78056): https://edk2.groups.io/g/devel/message/78056 Mute This Topic: https://groups.io/mt/84373826/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 18:09:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78058+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78058+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626933196; cv=none; d=zohomail.com; s=zohoarc; b=aT0MbtRyIePiogHW9SwWcF/LgTH15LM65PByUNDXHk0+NcM+uE+wiHr7j5UaHmo6rXLzf55deb5wEFp5XmsmYw9LQ+C/Ho5p7tryZSMcQhqnGAGvPofBF7LYBIeF3pHpXSEQzpqRxClQgqoDp7mFrf+fLwD0b8URv7bwoJCb0Mo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626933196; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=yOTlol34dXHFXK9Es8pVC/YeeH9BdlyLSG8nF2ORA20=; b=Zi0z5yyiJfcYrTFVNVzhGTrALygpB3dY4D9NTFM8Kh/esBBcz8xfG5JdFUPmuH9Yrp8sP+T6Z0asXw170Hs8BR2u/5dO+C3TZKEOL2fT3OPg0XdHqwVQ2vV2iEUGok9xFNGT8fryrPaO+zOzfMipQx8FKqy2qwPddRwywfAlcR4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78058+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626933196602392.00949190078404; Wed, 21 Jul 2021 22:53:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id XdqKYY1788612xxqGfOTZyqQ; Wed, 21 Jul 2021 22:53:16 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.4239.1626933190759000499 for ; Wed, 21 Jul 2021 22:53:10 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10052"; a="275391629" X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="275391629" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:10 -0700 X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="512374765" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.4.4]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:08 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V2 2/4] OvmfPkg: Add Tdx metadata Date: Thu, 22 Jul 2021 13:52:14 +0800 Message-Id: <416e37e6481d5ef8279de60b379945c7ce43c7f3.1626931332.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: T3rW6DHTcCeZBWEhLRGKW0Cfx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626933196; bh=uRamr1lXSlEdwufkTkAGIDr+eSb/j6gSOoq3F/vxHuA=; h=Cc:Date:From:Reply-To:Subject:To; b=sKg+dXA2swfKBYtoBKMrh2WTzlnPP2JN/AIaMXxoO5y5uOx90/KN989S/3GIvKGrKg+ XqBibLKIifE2b56ojf1PPIWI/YXXktkp6wj6Dsz4TRyLUPt7EJC089py3XKJLDElAwlWH xU5uFZsFc5k/FtUd+NgWbB1mJ7PrUB5DrOw= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626933198467100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 Tdx Metadata describes the information about the image for VMM use. For example, the base address and length of the TdHob, TdMailbox, etc. Its offset is put in a GUID-ed structure which is appended in the GUID-ed chain from a fixed GPA (0xffffffd0). Below are the items in TdxMetadata: _Bfv: Boot Firmware Volume _Cfv: Configuration Firmware Volume _Stack: Initial stack _Heap: Initial heap _MailBox: TDVF reserves the memory region so each AP can receive the message sent by the guest OS. _TdHob: VMM pass the resource information in TdHob to TDVF. _TdxPageTable: If 5-level page table is supported (GPAW is 52), a top level page directory pointers (1 * 256TB entry) is generated in this page. _OvmfPageTable: Initial page table for standard Ovmf. TDVF indicate above chunk of temporary initialized memory region (_Stack/ _Heap/_MailBox/_TdHob/_TdxPageTables/OvmfPageTable) to support TDVF code finishing the memory initialization. Because the other unaccepted memory cannot be accessed until they're accepted. Since AMD SEV has already defined some SEV specific memory region in MEMFD. SEV and TDX will not run at the same time. So TDX re-use the memory region defined by SEV. - MailBox : PcdOvmfSecGhcbBackupBase|PcdOvmfSecGhcbBackupSize - TdHob : PcdOvmfSecGhcbBase|PcdOvmfSecGhcbSize - TdxPageTable : PcdOvmfSecGhcbPageTableBase|PcdOvmfSecGhcbPageTableSize Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 17 ++++ OvmfPkg/ResetVector/ResetVector.inf | 11 ++- OvmfPkg/ResetVector/ResetVector.nasmb | 47 +++++++++- OvmfPkg/ResetVector/X64/TdxMetadata.asm | 97 ++++++++++++++++++++ 4 files changed, 169 insertions(+), 3 deletions(-) create mode 100644 OvmfPkg/ResetVector/X64/TdxMetadata.asm diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVe= ctor/Ia16/ResetVectorVtf0.asm index 9c0b5853a46f..ac86ce69ebe8 100644 --- a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm +++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm @@ -47,6 +47,23 @@ TIMES (15 - ((guidedStructureEnd - guidedStructureStart = + 15) % 16)) DB 0 ; guidedStructureStart: =20 +%ifdef ARCH_X64 +; +; TDX Metadata offset block +; +; If TdxMetadata.asm is included then we need below block which describes +; the offset of TdxMetadata block in Ovmf image +; +; GUID : e47a6535-984a-4798-865e-4685a7bf8ec2 +; +tdxMetadataOffsetStart: + DD (OVMF_IMAGE_SIZE_IN_KB * 1024 - (fourGigabytes - TdxMetadataGu= id - 16)) + DD tdxMetadataOffsetEnd - tdxMetadataOffsetStart + DB 0x35, 0x65, 0x7a, 0xe4, 0x4a, 0x98, 0x98, 0x47 + DB 0x86, 0x5e, 0x46, 0x85, 0xa7, 0xbf, 0x8e, 0xc2 +tdxMetadataOffsetEnd: + +%endif ; ; SEV Secret block ; diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index dc38f68919cd..fd65c0c9621d 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -1,7 +1,7 @@ ## @file # Reset Vector # -# Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,15 @@ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfImageSizeInKb + gUefiOvmfPkgTokenSpaceGuid.PcdCfvBase + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataOffset + gUefiOvmfPkgTokenSpaceGuid.PcdCfvRawDataSize + gUefiOvmfPkgTokenSpaceGuid.PcdBfvBase + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataOffset + gUefiOvmfPkgTokenSpaceGuid.PcdBfvRawDataSize =20 [FixedPcd] gUefiOvmfPkgTokenSpaceGuid.PcdSevLaunchSecretBase diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 5fbacaed5f9d..b653fe87abd6 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -4,6 +4,7 @@ ; ; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; Copyright (c) 2021, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;-------------------------------------------------------------------------= ----- @@ -67,6 +68,44 @@ %error "This implementation inherently depends on PcdOvmfSecGhcbBase n= ot straddling a 2MB boundary" %endif =20 + ; + ; TDX meta data + ; + %define TDX_METADATA_SECTION_TYPE_BFV 0 + %define TDX_METADATA_SECTION_TYPE_CFV 1 + %define TDX_METADATA_SECTION_TYPE_TD_HOB 2 + %define TDX_METADATA_SECTION_TYPE_TEMP_MEM 3 + %define TDX_METADATA_VERSION 1 + %define TDX_METADATA_ATTRIBUTES_EXTENDMR 0x00000001 + + %define TDX_BFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdBfvRawDataOffset) + %define TDX_BFV_RAW_DATA_SIZE FixedPcdGet32 (PcdBfvRawDataSize) + %define TDX_BFV_MEMORY_BASE FixedPcdGet32 (PcdBfvBase) + %define TDX_BFV_MEMORY_SIZE FixedPcdGet32 (PcdBfvRawDataSize) + + %define TDX_CFV_RAW_DATA_OFFSET FixedPcdGet32 (PcdCfvRawDataOffset) + %define TDX_CFV_RAW_DATA_SIZE FixedPcdGet32 (PcdCfvRawDataSize) + %define TDX_CFV_MEMORY_BASE FixedPcdGet32 (PcdCfvBase), + %define TDX_CFV_MEMORY_SIZE FixedPcdGet32 (PcdCfvRawDataSize), + + %define TDX_HEAP_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecPeiTempRamBas= e) + %define TDX_HEAP_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSiz= e) / 2 + + %define TDX_STACK_MEMORY_BASE (TDX_HEAP_MEMORY_BASE + TDX_HEAP_MEMOR= Y_SIZE) + %define TDX_STACK_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecPeiTempRamSiz= e) / 2 + + %define TDX_HOB_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBase) + %define TDX_HOB_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbSize) + + %define TDX_MAILBOX_MEMORY_BASE FixedPcdGet32 (PcdOvmfSecGhcbBackupBas= e) + %define TDX_MAILBOX_MEMORY_SIZE FixedPcdGet32 (PcdOvmfSecGhcbBackupSiz= e) + + %define OVMF_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecPageTablesBas= e) + %define OVMF_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecPageTablesSiz= e) + + %define TDX_EXTRA_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Base) + %define TDX_EXTRA_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Size) + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) =20 %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) @@ -76,8 +115,11 @@ %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + = 8) %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) = + 16) %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) -%include "Ia32/Flat32ToFlat64.asm" -%include "Ia32/PageTables64.asm" + + %include "X64/TdxMetadata.asm" + + %include "Ia32/Flat32ToFlat64.asm" + %include "Ia32/PageTables64.asm" %endif =20 %include "Ia16/Real16ToFlat32.asm" @@ -88,5 +130,6 @@ %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase) %define SEV_LAUNCH_SECRET_BASE FixedPcdGet32 (PcdSevLaunchSecretBase) %define SEV_LAUNCH_SECRET_SIZE FixedPcdGet32 (PcdSevLaunchSecretSize) + %define OVMF_IMAGE_SIZE_IN_KB FixedPcdGet32 (PcdOvmfImageSizeInKb) %include "Ia16/ResetVectorVtf0.asm" =20 diff --git a/OvmfPkg/ResetVector/X64/TdxMetadata.asm b/OvmfPkg/ResetVector/= X64/TdxMetadata.asm new file mode 100644 index 000000000000..8dba8daa0165 --- /dev/null +++ b/OvmfPkg/ResetVector/X64/TdxMetadata.asm @@ -0,0 +1,97 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Tdx Virtual Firmware metadata +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 64 + +%define TDX_VIRTUAL_FIRMWARE + +ALIGN 16 +TIMES (15 - ((TdxGuidedStructureEnd - TdxGuidedStructureStart + 15) % 16))= DB 0 + +TdxGuidedStructureStart: + +; +; TDVF meta data +; +TdxMetadataGuid: + DB 0xf3, 0xf9, 0xea, 0xe9, 0x8e, 0x16, 0xd5, 0x44 + DB 0xa8, 0xeb, 0x7f, 0x4d, 0x87, 0x38, 0xf6, 0xae + +_Descriptor: + DB 'T','D','V','F' ; Signature + DD TdxGuidedStructureEnd - _Descriptor ; Length + DD TDX_METADATA_VERSION ; Version + DD (TdxGuidedStructureEnd - _Descriptor - 16)/32 ; Number of sections + +_Bfv: + DD TDX_BFV_RAW_DATA_OFFSET + DD TDX_BFV_RAW_DATA_SIZE + DQ TDX_BFV_MEMORY_BASE + DQ TDX_BFV_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_BFV + DD TDX_METADATA_ATTRIBUTES_EXTENDMR + +_Cfv: + DD TDX_CFV_RAW_DATA_OFFSET + DD TDX_CFV_RAW_DATA_SIZE + DQ TDX_CFV_MEMORY_BASE + DQ TDX_CFV_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_CFV + DD 0 + +_Stack: + DD 0 + DD 0 + DQ TDX_STACK_MEMORY_BASE + DQ TDX_STACK_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_Heap: + DD 0 + DD 0 + DQ TDX_HEAP_MEMORY_BASE + DQ TDX_HEAP_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_MailBox: + DD 0 + DD 0 + DQ TDX_MAILBOX_MEMORY_BASE + DQ TDX_MAILBOX_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_TdHob: + DD 0 + DD 0 + DQ TDX_HOB_MEMORY_BASE + DQ TDX_HOB_MEMORY_SIZE + DD TDX_METADATA_SECTION_TYPE_TD_HOB + DD 0 + +_TdxPageTable: + DD 0 + DD 0 + DQ TDX_EXTRA_PAGE_TABLE_BASE + DQ TDX_EXTRA_PAGE_TABLE_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +_OvmfPageTable: + DD 0 + DD 0 + DQ OVMF_PAGE_TABLE_BASE + DQ OVMF_PAGE_TABLE_SIZE + DD TDX_METADATA_SECTION_TYPE_TEMP_MEM + DD 0 + +TdxGuidedStructureEnd: +ALIGN 16 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78058): https://edk2.groups.io/g/devel/message/78058 Mute This Topic: https://groups.io/mt/84373828/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 18:09:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78059+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78059+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626933192; cv=none; d=zohomail.com; s=zohoarc; b=R7fqlJneb0uHvEO8+89ex87oxCaSQbA/yOhtenDRXOzav6CCFRrJb+HOw9aWOCnyT7URaqxYEpuk82KuOfaVoVJgdMCVoiLPX3rXT65YOXLEEcxj5GPgSjV0dq6pNhklHoaQdgvubdzuVEa9/ebFgd5PPaLq0OBrcLq0qGx/WF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626933192; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=es5IP9qHxOjqpPAsYmUtkrRwIZ1Wt/y/crVJ9MHgSwo=; b=IbuEvwGXC40VWZoCFrzaxdCrEZsbFYXvKPnR2jLkoWUozZEEVUUmjfDSzZkrYDEuSH8+E9CCNH9IPsYVuMOVORgmbbsXjOGJ5HORUk3xeZ6Kr4uZZ4pY34mxVw3OurARcprDnLjWP96GJKsRZ4rYEVPqtiTlYN6962quf6qPum8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78059+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626933192927142.52911400317862; Wed, 21 Jul 2021 22:53:12 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ghQUYY1788612xpxH3cGGhW3; Wed, 21 Jul 2021 22:53:12 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.4239.1626933190759000499 for ; Wed, 21 Jul 2021 22:53:12 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10052"; a="275391637" X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="275391637" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:11 -0700 X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="512374772" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.4.4]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:10 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Eric Dong , Ray Ni , Jiewen Yao Subject: [edk2-devel] [PATCH V2 3/4] UefiCpuPkg/ResetVector: Add Main32 entry point in Main.asm Date: Thu, 22 Jul 2021 13:52:15 +0800 Message-Id: <385d5e4bc26eb601a1ee6eeb982d5cde06ceab2a.1626931332.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: cq58gdxJXroolbzabjodx9pqx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626933192; bh=wPMQjzLJPtDcziyYK2QkwzC09NtwCOchKrLu3/z09AU=; h=Cc:Date:From:Reply-To:Subject:To; b=H30BW0bBBuJtiuFMDy7h8dnvMe7Z/qBCUjKZ+NFWagbu6amBgHVuLoYW4yT2EkoAGLr MOyikjjSGVMQC9e4p8nLJv/kPCeHcDCQiKsUoaCwJs0CnIlnw86NvGJwUO0jPtEdlHivs rRPKE5zzguz2qE+Ajq7DUcidu7OPxMp3k3Y= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626933194061100011 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). Main32 entry point is added in UefiCpuPkg/ResetVector/Vtf0/Main.asm so that Main.asm can support the 32-bit protected mode. Init32.asm is the 32-bit initialization code. It is a null stub in UefiCpuPkg. The actual initialization can be implemented in the platform (OvmfPkg/ResetVector/Ia32/Init32.asm is the example.) Cc: Eric Dong Cc: Ray Ni Cc: Jiewen Yao Signed-off-by: Min Xu Reviewed-by: Ray Ni --- UefiCpuPkg/ResetVector/Vtf0/Ia32/Init32.asm | 13 +++++++++++++ UefiCpuPkg/ResetVector/Vtf0/Main.asm | 14 ++++++++++++++ UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/ResetVector/Vtf0/Ia32/Init32.asm diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/Init32.asm b/UefiCpuPkg/Reset= Vector/Vtf0/Ia32/Init32.asm new file mode 100644 index 000000000000..0cdae4a4a84a --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/Init32.asm @@ -0,0 +1,13 @@ +;-------------------------------------------------------------------------= ----- +; @file +; 32-bit initialization code. +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +Init32: + nop + OneTimeCallRet Init32 diff --git a/UefiCpuPkg/ResetVector/Vtf0/Main.asm b/UefiCpuPkg/ResetVector/= Vtf0/Main.asm index 19d08482f831..4920c6937e1b 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Main.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Main.asm @@ -36,6 +36,20 @@ Main16: =20 BITS 32 =20 +%ifdef ARCH_X64 + + jmp SearchBfv + +; +; Entry point of Main32 +; +Main32: + + OneTimeCall Init32 + +%endif + +SearchBfv: ; ; Search for the Boot Firmware Volume (BFV) ; diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVecto= r/Vtf0/Vtf0.nasmb index 493738c79c1c..6493b9863c48 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -51,7 +51,7 @@ %include "Ia32/SearchForSecEntry.asm" =20 %ifdef ARCH_X64 -%include "Ia32/Flat32ToFlat64.asm" +%include "Ia32/Init32.asm" %include "Ia32/PageTables64.asm" %endif =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78059): https://edk2.groups.io/g/devel/message/78059 Mute This Topic: https://groups.io/mt/84373829/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon May 6 18:09:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+78060+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78060+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1626933195; cv=none; d=zohomail.com; s=zohoarc; b=ff0GoEA2UC0QEd47IFtAWwNWKssL8Cu902IJKnkAhm5rCpkSsFgLHnPzfCHKKRigFvSy8uk28jcHGe4fXnmfiiwN3blgutsrCnwS7aQaP6ynajdYyxOwEq/L1puDmOGLDUK1n3u6WvuciFM9ImRwOKODef8m5uJ91j9nTWKc/js= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1626933195; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=zthMGUKgpreUed+Opl7tUPOt8UwL5e4RMoCirXZRrSs=; b=SNkmu9wYMv4KncxPOST/K8cq1H/55+bfFHPnI4W3+rxqEsIughsz02SCTFK12pq079h4JW+0wEl+V3BwdOp0jQylhULc9fjxfZlqhv1YMQbcjQt2lhKKSnXRbsg2oXf+T4NATORie9UKUePFqRgUPQJbrc+eCh39tVE73bnhaCo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+78060+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1626933195179536.7931653667428; Wed, 21 Jul 2021 22:53:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3wwCYY1788612xwuQcMQWnsO; Wed, 21 Jul 2021 22:53:14 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.4239.1626933190759000499 for ; Wed, 21 Jul 2021 22:53:14 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10052"; a="275391652" X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="275391652" X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:14 -0700 X-IronPort-AV: E=Sophos;i="5.84,260,1620716400"; d="scan'208";a="512374785" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.238.4.4]) by fmsmga002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2021 22:53:11 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky Subject: [edk2-devel] [PATCH V2 4/4] OvmfPkg/ResetVector: Update ResetVector to support Tdx Date: Thu, 22 Jul 2021 13:52:16 +0800 Message-Id: <0e28e0d01b2db776c5c00469bac5097a326c3ed9.1626931332.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: 7HHKZYE8Lxt0KtGznTKHGtrix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1626933194; bh=D4xxEtEA6SGXhCfc0iiR8TWEFq3Q72ILndKiGPsM+dM=; h=Cc:Date:From:Reply-To:Subject:To; b=EXMbYiQjIgov59ccuWa0UWNidUBdZZ4YOj4fQg8KFFuxeJFW1tv3ztggPeR6Hcv/lvF dRDzN1KfjBjuqCbRBDAzA7MlPvNZwWo/lR3rC5P8+mGV6r6dfMd14bwIFjzU7J0OF9aYk TyXSoqfvH+KAYB/cHqvZ/j3T4djEFV9gquE= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1626933196257100001 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 In Tdx all CPUs "reset" to run on 32-bit protected mode with flat descriptor (paging disabled). But in Non-Td guest the initial state of CPUs is 16-bit real mode. To resolve this conflict, BITS 16/32 is used in the very beginning of ResetVector. It will check the 32-bit protected mode or 16-bit real mode, then jump to the corresponding entry point. This is done in OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm. ReloadFlat32.asm load the GDT and set the CR0, then jump to Flat-32 mode. InitTdx.asm is called to record the Tdx signature ('TDXG') and other tdx information in a TDX_WORK_AREA which can be used by the other routines in ResetVector. Init32.asm is 32-bit initialization code in OvmfPkg. It puts above ReloadFlat32 and InitTdx together to do the initializaiton for Tdx. After that Tdx jumps to 64-bit long mode by doing following tasks: 1. SetCr3ForPageTables64 For OVMF, some initial page tables is built at: PcdOvmfSecPageTablesBase - (PcdOvmfSecPageTablesBase + 0x6000) This page table supports the 4-level page table. But Tdx support 4-level and 5-level page table based on the CPU GPA widt= h. 48bit is 4-level paging, 52-bit is 5-level paging. If 5-level page table is supported (GPAW is 52), then a top level page directory pointers (1 * 256TB entry) is generated in the TdxPageTable. 2. Set Cr4 Enable PAE. 3. Adjust Cr3 If GPAW is 48, then Cr3 is PT_ADDR (0). If GPAW is 52, then Cr3 is TDX_PT_ADDR (0). Tdx MailBox [0x10, 0x800] is reserved for OS. So we initialize piece of this area ([0x10, 0x20]) to record the Tdx flag ('TDXG') and other Tdx info so t= hat they can be used in the following flow. After all above is successfully done, Tdx jump to SecEntry. Cc: Ard Biesheuvel Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Signed-off-by: Min Xu --- OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 21 ++++++++ OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm | 47 ++++++++++++++++ OvmfPkg/ResetVector/Ia32/Init32.asm | 34 ++++++++++++ OvmfPkg/ResetVector/Ia32/InitTdx.asm | 57 ++++++++++++++++++++ OvmfPkg/ResetVector/Ia32/PageTables64.asm | 41 ++++++++++++++ OvmfPkg/ResetVector/Ia32/ReloadFlat32.asm | 44 +++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 18 +++++++ 7 files changed, 262 insertions(+) create mode 100644 OvmfPkg/ResetVector/Ia32/Init32.asm create mode 100644 OvmfPkg/ResetVector/Ia32/InitTdx.asm create mode 100644 OvmfPkg/ResetVector/Ia32/ReloadFlat32.asm diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVe= ctor/Ia16/ResetVectorVtf0.asm index ac86ce69ebe8..a390ed81d021 100644 --- a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm +++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm @@ -155,10 +155,31 @@ resetVector: ; ; This is where the processor will begin execution ; +; In IA32 we follow the standard reset vector flow. While in X64, Td guest +; may be supported. Td guest requires the startup mode to be 32-bit +; protected mode but the legacy VM startup mode is 16-bit real mode. +; To make NASM generate such shared entry code that behaves correctly in +; both 16-bit and 32-bit mode, more BITS directives are added. +; +%ifdef ARCH_IA32 + nop nop jmp EarlyBspInitReal16 =20 +%else + + smsw ax + test al, 1 + jz .Real +BITS 32 + jmp Main32 +BITS 16 +.Real: + jmp EarlyBspInitReal16 + +%endif + ALIGN 16 =20 fourGigabytes: diff --git a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm b/OvmfPkg/ResetVec= tor/Ia32/Flat32ToFlat64.asm index c6d0d898bcd1..2206ca719593 100644 --- a/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm +++ b/OvmfPkg/ResetVector/Ia32/Flat32ToFlat64.asm @@ -17,6 +17,9 @@ Transition32FlatTo64Flat: =20 OneTimeCall SetCr3ForPageTables64 =20 + cmp dword[TDX_WORK_AREA], 0x47584454 ; 'TDXG' + jz TdxTransition32FlatTo64Flat + mov eax, cr4 bts eax, 5 ; enable PAE mov cr4, eax @@ -65,10 +68,54 @@ EnablePaging: bts eax, 31 ; set PG mov cr0, eax ; enable paging =20 + jmp _jumpTo64Bit + +; +; Tdx Transition from 32Flat to 64Flat +; +TdxTransition32FlatTo64Flat: + + mov eax, cr4 + bts eax, 5 ; enable PAE + + ; + ; byte[TDX_WORK_AREA_PAGELEVEL5] holds the indicator whether 52bit is = supported. + ; if it is the case, need to set LA57 and use 5-level paging + ; + cmp byte[TDX_WORK_AREA_PAGELEVEL5], 0 + jz .set_cr4 + bts eax, 12 +.set_cr4: + mov cr4, eax + mov ebx, cr3 + + ; + ; if la57 is not set, we are ok + ; if using 5-level paging, adjust top-level page directory + ; + bt eax, 12 + jnc .set_cr3 + mov ebx, TDX_PT_ADDR (0) +.set_cr3: + mov cr3, ebx + + mov eax, cr0 + bts eax, 31 ; set PG + mov cr0, eax ; enable paging + +_jumpTo64Bit: jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere) + BITS 64 jumpTo64BitAndLandHere: =20 + ; + ; For Td guest we are done and jump to the end + ; + mov eax, TDX_WORK_AREA + cmp dword [eax], 0x47584454 ; 'TDXG' + jz GoodCompare + ; ; Check if the second step of the SEV-ES mitigation is to be performed. ; diff --git a/OvmfPkg/ResetVector/Ia32/Init32.asm b/OvmfPkg/ResetVector/Ia32= /Init32.asm new file mode 100644 index 000000000000..772adc51e531 --- /dev/null +++ b/OvmfPkg/ResetVector/Ia32/Init32.asm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; @file +; 32-bit initialization for Tdx +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +; +; Modified: EBP +; +; @param[in] EBX [6:0] CPU supported GPA width +; [7:7] 5 level page table support +; @param[in] ECX [31:0] TDINITVP - Untrusted Configuration +; @param[in] EDX [31:0] VCPUID +; @param[in] ESI [31:0] VCPU_Index +; +Init32: + ; + ; Save EBX in EBP because EBX will be changed in ReloadFlat32 + ; + mov ebp, ebx + + OneTimeCall ReloadFlat32 + + ; + ; Init Tdx + ; + OneTimeCall InitTdx + + OneTimeCallRet Init32 diff --git a/OvmfPkg/ResetVector/Ia32/InitTdx.asm b/OvmfPkg/ResetVector/Ia3= 2/InitTdx.asm new file mode 100644 index 000000000000..de8273da6a0c --- /dev/null +++ b/OvmfPkg/ResetVector/Ia32/InitTdx.asm @@ -0,0 +1,57 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Initialize TDX_WORK_AREA to record the Tdx flag ('TDXG') and other Tdx= info +; so that the following codes can use these information. +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 32 + +; +; Modified: EBP +; +InitTdx: + ; + ; In Td guest, BSP/AP shares the same entry point + ; BSP builds up the page table, while APs shouldn't do the same task. + ; Instead, APs just leverage the page table which is built by BSP. + ; APs will wait until the page table is ready. + ; In Td guest, vCPU 0 is treated as the BSP, the others are APs. + ; ESI indicates the vCPU ID. + ; + cmp esi, 0 + je tdBspEntry + +apWait: + cmp byte[TDX_WORK_AREA_PGTBL_READY], 0 + je apWait + jmp doneTdxInit + +tdBspEntry: + ; + ; It is of Tdx Guest + ; Save the Tdx info in TDX_WORK_AREA so that the following code can use + ; these information. + ; + mov dword [TDX_WORK_AREA], 0x47584454 ; 'TDXG' + + ; + ; EBP[6:0] CPU supported GPA width + ; + and ebp, 0x3f + cmp ebp, 52 + jl NotPageLevel5 + mov byte[TDX_WORK_AREA_PAGELEVEL5], 1 + +NotPageLevel5: + ; + ; ECX[31:0] TDINITVP - Untrusted Configuration + ; + mov DWORD[TDX_WORK_AREA_INITVP], ecx + mov DWORD[TDX_WORK_AREA_INFO], ebp + +doneTdxInit: + OneTimeCallRet InitTdx diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index 5fae8986d9da..508df6cf5967 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -218,6 +218,24 @@ SevEsDisabled: ; SetCr3ForPageTables64: =20 + ; + ; Check Td guest + ; + cmp dword[TDX_WORK_AREA], 0x47584454 ; 'TDXG' + jnz CheckSev + + xor edx, edx + + ; + ; In Td guest, BSP builds the page table and set the flag of + ; TDX_WORK_AREA_PGTBL_READY. APs check this flag and then set + ; cr3 directly. + ; + cmp byte[TDX_WORK_AREA_PGTBL_READY], 1 + jz SetCr3 + jmp SevNotActive + +CheckSev: OneTimeCall CheckSevFeatures xor edx, edx test eax, eax @@ -277,6 +295,29 @@ pageTableEntriesLoop: mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop =20 + ; + ; If it is Td guest, TdxExtraPageTable should be initialized as well + ; + cmp dword[TDX_WORK_AREA], 0x47584454 ; 'TDXG' + jnz IsSevEs + + xor eax, eax + mov ecx, 0x400 +tdClearTdxPageTablesMemoryLoop: + mov dword [ecx * 4 + TDX_PT_ADDR (0) - 4], eax + loop tdClearTdxPageTablesMemoryLoop + + xor edx, edx + ; + ; Top level Page Directory Pointers (1 * 256TB entry) + ; + mov dword[TDX_PT_ADDR (0)], PT_ADDR (0) + PAGE_PDP_ATTR + mov dword[TDX_PT_ADDR (4)], edx + + mov byte[TDX_WORK_AREA_PGTBL_READY], 1 + jmp SetCr3 + +IsSevEs: OneTimeCall IsSevEsEnabled test eax, eax jz SetCr3 diff --git a/OvmfPkg/ResetVector/Ia32/ReloadFlat32.asm b/OvmfPkg/ResetVecto= r/Ia32/ReloadFlat32.asm new file mode 100644 index 000000000000..06d44142625a --- /dev/null +++ b/OvmfPkg/ResetVector/Ia32/ReloadFlat32.asm @@ -0,0 +1,44 @@ +;-------------------------------------------------------------------------= ----- +; @file +; Load the GDT and set the CR0/CR4, then jump to Flat 32 protected mode. +; +; Copyright (c) 2021, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +%define SEC_DEFAULT_CR0 0x00000023 +%define SEC_DEFAULT_CR4 0x640 + +BITS 32 + +; +; Modified: EAX, EBX, CR0, CR4, DS, ES, FS, GS, SS +; +ReloadFlat32: + + cli + mov ebx, ADDR_OF(gdtr) + lgdt [ebx] + + mov eax, SEC_DEFAULT_CR0 + mov cr0, eax + + jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpToFlat32BitAndLandHere) +BITS 32 +jumpToFlat32BitAndLandHere: + + mov eax, SEC_DEFAULT_CR4 + mov cr4, eax + + debugShowPostCode POSTCODE_32BIT_MODE + + mov ax, LINEAR_SEL + mov ds, ax + mov es, ax + mov fs, ax + mov gs, ax + mov ss, ax + + OneTimeCallRet ReloadFlat32 + diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index b653fe87abd6..3ec163613477 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -106,6 +106,21 @@ %define TDX_EXTRA_PAGE_TABLE_BASE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Base) %define TDX_EXTRA_PAGE_TABLE_SIZE FixedPcdGet32 (PcdOvmfSecGhcbPageTable= Size) =20 + ; + ; TdMailboxBase [0x10, 0x800] is reserved for OS. + ; Td guest initialize piece of this area (TdMailboxBase [0x10,0x20]) to + ; record the Td guest info so that this information can be used in the + ; following ResetVector flow. + ; + %define TD_MAILBOX_WORKAREA_OFFSET 0x10 + %define TDX_WORK_AREA (TDX_MAILBOX_MEMORY_BASE + TD_MAIL= BOX_WORKAREA_OFFSET) + %define TDX_WORK_AREA_PAGELEVEL5 (TDX_WORK_AREA + 4) + %define TDX_WORK_AREA_PGTBL_READY (TDX_WORK_AREA + 5) + %define TDX_WORK_AREA_INITVP (TDX_WORK_AREA + 8) + %define TDX_WORK_AREA_INFO (TDX_WORK_AREA + 8 + 4) + + %define TDX_PT_ADDR(Offset) (TDX_EXTRA_PAGE_TABLE_BASE + (Offset)) + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) =20 %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) @@ -117,6 +132,9 @@ %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) =20 %include "X64/TdxMetadata.asm" + %include "Ia32/Init32.asm" + %include "Ia32/InitTdx.asm" + %include "Ia32/ReloadFlat32.asm" =20 %include "Ia32/Flat32ToFlat64.asm" %include "Ia32/PageTables64.asm" --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#78060): https://edk2.groups.io/g/devel/message/78060 Mute This Topic: https://groups.io/mt/84373830/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-