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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: QsVhMBzRtqoR9hP8o0JUW3Yrx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829195; bh=8lsIj6lKF2cTF6DYgNn6eupV9CnUOOW0KYT8OWquYeU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VdyEBds2Y7Z07AIJnfeDfzszs7YFxr4i6wK6rYAEEAkDGei5PaabANb5ROqQwFiR4G8 abTFuA+NLM6QWhAty3CnRlKAprdLvaSfjGR1OkV9fIUU3QM49t+B4UQlhrr1p6q7X2qFo d6PyB3WAnCeN9+kjJ/mhXNhiu7YpdOP5Voo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Two new dynamic MdeModulePkg PCDs are needed to support SEV-ES under OVMF: - PcdGhcbBase: UINT64 value that is the base address of the GHCB allocation. - PcdGhcbSize: UINT64 value that is the size, in bytes, of the GHCB allocation (size is dependent on the number of APs). Cc: Jian J Wang Cc: Hao A Wu Reviewed-by: Hao A Wu Signed-off-by: Tom Lendacky --- MdeModulePkg/MdeModulePkg.dec | 9 +++++++++ MdeModulePkg/MdeModulePkg.uni | 8 ++++++++ 2 files changed, 17 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index d7572eedd18c..cb30a7975849 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2063,6 +2063,15 @@ [PcdsDynamic, PcdsDynamicEx] # @Prompt If there is any test key used by the platform. gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed|FALSE|BOOLEAN|0x00030003 =20 + ## This dynamic PCD holds the base address of the Guest-Hypervisor Commu= nication Block (GHCB) pool allocation. + # @Prompt GHCB Pool Base Address + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0|UINT64|0x00030007 + + ## This dynamic PCD holds the total size of the Guest-Hypervisor Communi= cation Block (GHCB) pool allocation. + # The amount of memory allocated for GHCBs is dependent on the number o= f APs. + # @Prompt GHCB Pool Size + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008 + [PcdsDynamicEx] ## This dynamic PCD enables the default variable setting. # Its value is the default store ID value. The default value is zero as= Standard default. diff --git a/MdeModulePkg/MdeModulePkg.uni b/MdeModulePkg/MdeModulePkg.uni index 5235dee561ad..b8c867379a86 100644 --- a/MdeModulePkg/MdeModulePkg.uni +++ b/MdeModulePkg/MdeModulePkg.uni @@ -1303,3 +1303,11 @@ #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdTcgPfpMeasurementRevision_PR= OMPT #language en-US "TCG Platform Firmware Profile revision" =20 #string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdTcgPfpMeasurementRevision_HE= LP #language en-US "Indicates which TCG Platform Firmware Profile revision = the EDKII firmware follows." + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbBase_PROMPT #language en= -US "Guest-Hypervisor Communication Block (GHCB) Pool Base Address" + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbBase_HELP #language en-U= S "Used with SEV-ES support to identify an address range that is not to be = encrypted." + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbSize_PROMPT #language en= -US "Guest-Hypervisor Communication Block (GHCB) Pool Base Size" + +#string STR_gEfiMdeModulePkgTokenSpaceGuid_PcdGhcbSize_HELP #language en-U= S "Used with SEV-ES support to identify the size of the address range that = is not to be encrypted." --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: x1OME8SF4zRGP0ixKaLVWhd0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829202; bh=ZASxpU4KVYA79XIoVUlp2MKGpslscq8EDpNTxFKs+Vw=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=QYFF0WagCyN+vyENG7HHpD4MrevL9D/cIm8TSdGP4dbO3Ahq3gZZkytqfKTJldSngtV ipuuSEtojOWU9YqbKtHZPv0oW8JnWa8+m7+gvb2gEVdcX9lY2ZvkZkon5/4oi5bkFwKjp qmDnjcFTaiwwmZbMB2ilT3nZaZWxoaxE9Qo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A new dynamic UefiCpuPkg PCD is needed to support SEV-ES under OVMF: - PcdSevEsIsEnabled: BOOLEAN value used to indicate if SEV-ES is enabled Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/UefiCpuPkg.dec | 6 ++++++ UefiCpuPkg/UefiCpuPkg.uni | 3 +++ 2 files changed, 9 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 8b2e03d49d07..d52912ddca1f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -373,5 +373,11 @@ [PcdsDynamic, PcdsDynamicEx] # @ValidRange 0x80000001 | 0 - 1 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x600000= 15 =20 + ## This dynamic PCD indicates whether SEV-ES is enabled + # TRUE - SEV-ES is enabled + # FALSE - SEV-ES is not enabled + # @Prompt SEV-ES Status + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016 + [UserExtensions.TianoCore."ExtraFiles"] UefiCpuPkgExtra.uni diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index 1780dfdc126d..f4a0c72f6293 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -278,3 +278,6 @@ =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApStatusCheckIntervalInMicroSe= conds_PROMPT #language en-US "Periodic interval value in microseconds for = AP status check in DXE.\n" #string STR_gUefiCpuPkgTokenSpaceGuid_PcdCpuApStatusCheckIntervalInMicroSe= conds_HELP #language en-US "Periodic interval value in microseconds for = the status check of APs for StartupAllAPs() and StartupThisAP() executed in= non-blocking mode in DXE phase.\n" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsIsEnabled_PROMPT #language = en-US "Specifies whether SEV-ES is enabled" +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsIsEnabled_HELP #language = en-US "Set to TRUE when running as an SEV-ES guest, FALSE otherwise." --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63844): https://edk2.groups.io/g/devel/message/63844 Mute This Topic: https://groups.io/mt/76056468/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 22:24:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63845+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63845+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1596829209387526.7236918119721; Fri, 7 Aug 2020 12:40:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id IN6YYY1788612xoDINqsR8k4; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) by CY4PR12MB1541.namprd12.prod.outlook.com (2603:10b6:910:7::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.18; Fri, 7 Aug 2020 19:40:07 +0000 X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b]) by CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b%5]) with mapi id 15.20.3239.024; Fri, 7 Aug 2020 19:40:07 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io CC: Brijesh Singh , Ard Biesheuvel , Eric Dong , Jordan Justen , Laszlo Ersek , Liming Gao , Michael D Kinney , Ray Ni Subject: [edk2-devel] [PATCH v14 03/46] MdePkg: Add the MSR definition for the GHCB register Date: Fri, 7 Aug 2020 14:38:48 -0500 Message-ID: <372b26f6ac52fd65bf069b51982c76d87ce91831.1596829170.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: SN6PR2101CA0021.namprd21.prod.outlook.com (2603:10b6:805:106::31) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by SN6PR2101CA0021.namprd21.prod.outlook.com (2603:10b6:805:106::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3305.2 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: O0UqbqX15Q9TSJUly1MgIQiHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829209; bh=jjCrzVUel/dSRekpjcafdGmNU8RvsX0rxnREVonjzb0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=jA24ZCUHtadXVXYgHeO8m1FRoZwx1d3juTRBnfzH+lW7oh+De9/p8ddyQmJlh5aIj1o 1UYeyYquxQ93GoekLseCUuDu1Fe8eTMErGwgFfnIZrIRJTQ2Axpurpn8cr88VvyhMevUt XVhaq+Zt2xYvWCuzTAhhBjFw+vFes2qIFZ4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 For SEV-ES, the GHCB page address is stored in the GHCB MSR register (0xc0010130). Define the register and the format used for register during GHCB protocol negotiation. Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Include/Register/Amd/Fam17Msr.h | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Regist= er/Amd/Fam17Msr.h index 6ef45a9b21d3..e4db09c5184c 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -17,6 +17,52 @@ #ifndef __FAM17_MSR_H__ #define __FAM17_MSR_H__ =20 +/** + Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register + +**/ +#define MSR_SEV_ES_GHCB 0xc0010130 + +/** + MSR information returned for #MSR_SEV_ES_GHCB +**/ +typedef union { + struct { + UINT32 Function:12; + UINT32 Reserved1:20; + UINT32 Reserved2:32; + } GhcbInfo; + + struct { + UINT8 Reserved[3]; + UINT8 SevEncryptionBitPos; + UINT16 SevEsProtocolMin; + UINT16 SevEsProtocolMax; + } GhcbProtocol; + + struct { + UINT32 Function:12; + UINT32 ReasonCodeSet:4; + UINT32 ReasonCode:8; + UINT32 Reserved1:8; + UINT32 Reserved2:32; + } GhcbTerminate; + + VOID *Ghcb; + + UINT64 GhcbPhysicalAddress; +} MSR_SEV_ES_GHCB_REGISTER; + +#define GHCB_INFO_SEV_INFO 1 +#define GHCB_INFO_SEV_INFO_GET 2 +#define GHCB_INFO_CPUID_REQUEST 4 +#define GHCB_INFO_CPUID_RESPONSE 5 +#define GHCB_INFO_TERMINATE_REQUEST 256 + +#define GHCB_TERMINATE_GHCB 0 +#define GHCB_TERMINATE_GHCB_GENERAL 0 +#define GHCB_TERMINATE_GHCB_PROTOCOL 1 + /** Secure Encrypted Virtualization (SEV) status register =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: VFHYCaf5D6P6bcBgDVA7Uwwgx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829217; bh=exck8PRq3zsjy+7lvZv450dHHOg83B3DYFgKydwIxcE=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=dbcngx6CNcdbDg6RuMmeH0ZBRJLNRBJTJ9KE59fWzZyXfdHxwGJ5pQY9nmblhGdRPS+ iRmL/YrdxxhpwMjpVATzfVqCfEQU96zbDRoz/ukETcF+68HHcZl5wGbA+6zHJe1LiFZnj +dmIs8pQ9vOr1PKT+ht/vDZg+yRYAc49G6I= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The GHCB is used by an SEV-ES guest for communicating between the guest and the hypervisor. Create the GHCB definition as defined by the GHCB protocol definition. Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Include/Register/Amd/Ghcb.h | 166 +++++++++++++++++++++++++++++ 1 file changed, 166 insertions(+) create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/A= md/Ghcb.h new file mode 100644 index 000000000000..54a80da0f6d7 --- /dev/null +++ b/MdePkg/Include/Register/Amd/Ghcb.h @@ -0,0 +1,166 @@ +/** @file + Guest-Hypervisor Communication Block (GHCB) Definition. + + Provides data types allowing an SEV-ES guest to interact with the hyperv= isor + using the GHCB protocol. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SEV-ES Guest-Hypervisor Communication Block Standardization + +**/ + +#ifndef __GHCB_H__ +#define __GHCB_H__ + +#include +#include +#include + +#define UD_EXCEPTION 6 +#define GP_EXCEPTION 13 +#define VC_EXCEPTION 29 + +#define GHCB_VERSION_MIN 1 +#define GHCB_VERSION_MAX 1 + +#define GHCB_STANDARD_USAGE 0 + +// +// SVM Exit Codes +// +#define SVM_EXIT_DR7_READ 0x27ULL +#define SVM_EXIT_DR7_WRITE 0x37ULL +#define SVM_EXIT_RDTSC 0x6EULL +#define SVM_EXIT_RDPMC 0x6FULL +#define SVM_EXIT_CPUID 0x72ULL +#define SVM_EXIT_INVD 0x76ULL +#define SVM_EXIT_IOIO_PROT 0x7BULL +#define SVM_EXIT_MSR 0x7CULL +#define SVM_EXIT_VMMCALL 0x81ULL +#define SVM_EXIT_RDTSCP 0x87ULL +#define SVM_EXIT_WBINVD 0x89ULL +#define SVM_EXIT_MONITOR 0x8AULL +#define SVM_EXIT_MWAIT 0x8BULL +#define SVM_EXIT_NPF 0x400ULL + +// +// VMG Special Exit Codes +// +#define SVM_EXIT_MMIO_READ 0x80000001ULL +#define SVM_EXIT_MMIO_WRITE 0x80000002ULL +#define SVM_EXIT_NMI_COMPLETE 0x80000003ULL +#define SVM_EXIT_AP_RESET_HOLD 0x80000004ULL +#define SVM_EXIT_AP_JUMP_TABLE 0x80000005ULL +#define SVM_EXIT_UNSUPPORTED 0x8000FFFFULL + +// +// IOIO Exit Information +// +#define IOIO_TYPE_STR BIT2 +#define IOIO_TYPE_IN 1 +#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) +#define IOIO_TYPE_OUT 0 +#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR) + +#define IOIO_REP BIT3 + +#define IOIO_ADDR_64 BIT9 +#define IOIO_ADDR_32 BIT8 +#define IOIO_ADDR_16 BIT7 + +#define IOIO_DATA_32 BIT6 +#define IOIO_DATA_16 BIT5 +#define IOIO_DATA_8 BIT4 +#define IOIO_DATA_MASK (BIT6 | BIT5 | BIT4) +#define IOIO_DATA_OFFSET 4 +#define IOIO_DATA_BYTES(x) (((x) & IOIO_DATA_MASK) >> IOIO_DATA_OFFSET) + +#define IOIO_SEG_ES 0 +#define IOIO_SEG_DS (BIT11 | BIT10) + + +typedef enum { + GhcbCpl =3D 25, + GhcbRflags =3D 46, + GhcbRip, + GhcbRsp =3D 59, + GhcbRax =3D 63, + GhcbRcx =3D 97, + GhcbRdx, + GhcbRbx, + GhcbRbp =3D 101, + GhcbRsi, + GhcbRdi, + GhcbR8, + GhcbR9, + GhcbR10, + GhcbR11, + GhcbR12, + GhcbR13, + GhcbR14, + GhcbR15, + GhcbXCr0 =3D 125, +} GHCB_REGISTER; + +typedef PACKED struct { + UINT8 Reserved1[203]; + UINT8 Cpl; + UINT8 Reserved2[148]; + UINT64 Dr7; + UINT8 Reserved3[144]; + UINT64 Rax; + UINT8 Reserved4[264]; + UINT64 Rcx; + UINT64 Rdx; + UINT64 Rbx; + UINT8 Reserved5[112]; + UINT64 SwExitCode; + UINT64 SwExitInfo1; + UINT64 SwExitInfo2; + UINT64 SwScratch; + UINT8 Reserved6[56]; + UINT64 XCr0; + UINT8 ValidBitmap[16]; + UINT64 X87StateGpa; + UINT8 Reserved7[1016]; +} GHCB_SAVE_AREA; + +typedef PACKED struct { + GHCB_SAVE_AREA SaveArea; + UINT8 SharedBuffer[2032]; + UINT8 Reserved1[10]; + UINT16 ProtocolVersion; + UINT32 GhcbUsage; +} GHCB; + +typedef union { + struct { + UINT32 Lower32Bits; + UINT32 Upper32Bits; + } Elements; + + UINT64 Uint64; +} GHCB_EXIT_INFO; + +typedef union { + struct { + UINT32 Vector:8; + UINT32 Type:3; + UINT32 ErrorCodeValid:1; + UINT32 Rsvd:19; + UINT32 Valid:1; + UINT32 ErrorCode; + } Elements; + + UINT64 Uint64; +} GHCB_EVENT_INJECTION; + +#define GHCB_EVENT_INJECTION_TYPE_INT 0 +#define GHCB_EVENT_INJECTION_TYPE_NMI 2 +#define GHCB_EVENT_INJECTION_TYPE_EXCEPTION 3 +#define GHCB_EVENT_INJECTION_TYPE_SOFT_INT 4 + +#endif --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: vB6mFLdLKZYBXoiczoOPjjwwx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829225; bh=4Ae9goI8KEPQua3HMmL5zrQfOpZUG7INAp5nZhs3QCg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=fX19DPn5c01619yfqFpcMBjJbfvVubkKddmxzQNEG6jWDHRdrGZElxxEapgXSw4a9Ly K/tAOjfO/bCuvQGBR6Xx2TR+WLoVRlKlvO+MbluyfBV6+7y1vwsRarUiGxZTENjKEM2Fl B5+f9SdH11Hz3UPg8NAF3MIIWF1YxPOMeuI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 GHCB pages must be mapped as shared pages, so modify the process of creating identity mapped pagetable entries so that GHCB entries are created without the encryption bit set. The GHCB range consists of two pages per CPU, the first being the GHCB and the second being a per-CPU variable page. Only the GHCB page is mapped as shared. Cc: Jian J Wang Cc: Hao A Wu Cc: Dandan Bi Cc: Liming Gao Acked-by: Hao A Wu Signed-off-by: Tom Lendacky --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 + .../Core/DxeIplPeim/X64/VirtualMemory.h | 12 +++- .../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +- .../Core/DxeIplPeim/X64/DxeLoadFunc.c | 11 +++- .../Core/DxeIplPeim/X64/VirtualMemory.c | 57 +++++++++++++++---- 5 files changed, 70 insertions(+), 16 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 3f1702854660..19b8a4c8aefa 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -115,6 +115,8 @@ [Pcd.IA32,Pcd.X64] gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 2d0493f109e8..6b7c38a441d6 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -201,6 +201,8 @@ EnableExecuteDisableBit ( @param[in, out] PageEntry2M Pointer to 2M page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -208,7 +210,9 @@ Split2MPageTo4K ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry2M, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ); =20 /** @@ -217,6 +221,8 @@ Split2MPageTo4K ( =20 @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 @return The address of 4 level page map. =20 @@ -224,7 +230,9 @@ Split2MPageTo4K ( UINTN CreateIdentityMappingPageTables ( IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbkSize ); =20 =20 diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 6e8ca824d469..284b34818ca7 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -123,7 +123,7 @@ Create4GPageTablesIa32Pae ( // // Need to split this 2M page that covers stack range. // - Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize, 0, 0); } else { // // Fill in the Page Directory entries @@ -282,7 +282,7 @@ HandOffToDxeCore ( // // Create page table and save PageMapLevel4 to CR3 // - PageTables =3D CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZ= E); + PageTables =3D CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZ= E, 0, 0); =20 // // End of PEI phase signal diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/= Core/DxeIplPeim/X64/DxeLoadFunc.c index f465eb1d8ac4..156a477d8467 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c @@ -35,6 +35,8 @@ HandOffToDxeCore ( UINT32 Index; EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi; + VOID *GhcbBase; + UINTN GhcbSize; =20 // // Clear page 0 and mark it as allocated if NULL pointer detection is en= abled. @@ -81,12 +83,19 @@ HandOffToDxeCore ( TopOfStack =3D (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_= SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); TopOfStack =3D ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); =20 + // + // Get the address and size of the GHCB pages + // + GhcbBase =3D (VOID *) PcdGet64 (PcdGhcbBase); + GhcbSize =3D PcdGet64 (PcdGhcbSize); + PageTables =3D 0; if (FeaturePcdGet (PcdDxeIplBuildPageTables)) { // // Create page table and save PageMapLevel4 to CR3 // - PageTables =3D CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS)= (UINTN) BaseOfStack, STACK_SIZE); + PageTables =3D CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS)= (UINTN) BaseOfStack, STACK_SIZE, + (EFI_PHYSICAL_ADDRESS) (= UINTN) GhcbBase, GhcbSize); } else { // // Set NX for stack feature also require PcdDxeIplBuildPageTables be T= RUE diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 516cf908bc88..6831946c54d3 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -181,6 +181,8 @@ EnableExecuteDisableBit ( @param Size Size of the given physical memory. @param StackBase Base address of stack. @param StackSize Size of stack. + @param GhcbBase Base address of GHCB pages. + @param GhcbSize Size of GHCB area. =20 @retval TRUE Page table should be split. @retval FALSE Page table should not be split. @@ -190,7 +192,9 @@ ToSplitPageTable ( IN EFI_PHYSICAL_ADDRESS Address, IN UINTN Size, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { if (IsNullDetectionEnabled () && Address =3D=3D 0) { @@ -209,6 +213,12 @@ ToSplitPageTable ( } } =20 + if (GhcbBase !=3D 0) { + if ((Address < GhcbBase + GhcbSize) && ((Address + Size) > GhcbBase)) { + return TRUE; + } + } + return FALSE; } /** @@ -322,6 +332,8 @@ AllocatePageTableMemory ( @param[in, out] PageEntry2M Pointer to 2M page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -329,7 +341,9 @@ Split2MPageTo4K ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry2M, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { EFI_PHYSICAL_ADDRESS PhysicalAddress4K; @@ -355,7 +369,20 @@ Split2MPageTo4K ( // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; + PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + + // + // The GHCB range consists of two pages per CPU, the GHCB and a + // per-CPU variable page. The GHCB page needs to be mapped as an + // unencrypted page while the per-CPU variable page needs to be + // mapped encrypted. These pages alternate in assignment. + // + if ((GhcbBase =3D=3D 0) + || (PhysicalAddress4K < GhcbBase) + || (PhysicalAddress4K >=3D GhcbBase + GhcbSize) + || (((PhysicalAddress4K - GhcbBase) & SIZE_4KB) !=3D 0)) { + PageTableEntry->Uint64 |=3D AddressEncMask; + } PageTableEntry->Bits.ReadWrite =3D 1; =20 if ((IsNullDetectionEnabled () && PhysicalAddress4K =3D=3D 0) || @@ -383,6 +410,8 @@ Split2MPageTo4K ( @param[in, out] PageEntry1G Pointer to 1G page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -390,7 +419,9 @@ Split1GPageTo2M ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry1G, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { EFI_PHYSICAL_ADDRESS PhysicalAddress2M; @@ -413,11 +444,11 @@ Split1GPageTo2M ( =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { - if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e)) { + if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { // // Need to split this 2M page that covers NULL or stack range. // - Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries @@ -616,6 +647,8 @@ EnablePageTableProtection ( =20 @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB base address. + @param[in] GhcbSize GHCB size. =20 @return The address of 4 level page map. =20 @@ -623,7 +656,9 @@ EnablePageTableProtection ( UINTN CreateIdentityMappingPageTables ( IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { UINT32 RegEax; @@ -809,8 +844,8 @@ CreateIdentityMappingPageTables ( PageDirectory1GEntry =3D (VOID *) PageDirectoryPointerEntry; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { - if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e)) { - Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry,= StackBase, StackSize); + if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { + Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry,= StackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries @@ -840,11 +875,11 @@ CreateIdentityMappingPageTables ( PageDirectoryPointerEntry->Bits.Present =3D 1; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { - if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize)) { + if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize, GhcbBase, GhcbSize)) { // // Need to split this 2M page that covers NULL or stack rang= e. // - Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry,= StackBase, StackSize); + Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry,= StackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: anvf39KGsIWERXSgsZZHBjirx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829233; bh=kE4HkMs0oIX/bJUNbN7DKw3IePvPGge+Px0Q7dv9Nyw=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=iQUkhZrFrEfG+h9QtEzqc172/1mNO5o081BkfB447qCzMb9phvJ4XbVMg2/V+3fqGI9 JfLmNgdyt31/lXH2m+Ch2mPFKMKtwPGDk0N9CIqznVQoyYTt/dF56lZV9eGWeH6HVY/Q2 dLyJ0GqCgwhAnSK2EhgFpdLdtGX9AJ2aEEc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Include/Library/BaseLib.h | 17 +++++++++++++ MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 ++++++++++++++++++++++ MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 +++++++++++++++++++++++++ 4 files changed, 84 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index c740a819cacf..3b93b5db8d24 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -183,6 +183,7 @@ [Sources.Ia32] Ia32/EnableCache.nasm| GCC Ia32/DisableCache.nasm| GCC Ia32/RdRand.nasm + Ia32/XGetBv.nasm =20 Ia32/DivS64x64Remainder.c Ia32/InternalSwitchStack.c | MSFT @@ -315,6 +316,7 @@ [Sources.X64] X64/EnableDisableInterrupts.nasm X64/DisablePaging64.nasm X64/RdRand.nasm + X64/XGetBv.nasm ChkStkGcc.c | GCC =20 [Sources.EBC] diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 8e7b87cbda4e..7edf0051a0a0 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7831,6 +7831,23 @@ AsmLfence ( VOID ); =20 +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 = and + x64. + + @param[in] Index Extended control register index + + @return The current value of the extended control regist= er +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ); + + /** Patch the immediate operand of an IA32 or X64 instruction such that the = byte, word, dword or qword operand is encoded at the end of the instruction's diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/MdePkg/Library/BaseL= ib/Ia32/XGetBv.nasm new file mode 100644 index 000000000000..9f7b03bbff35 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm @@ -0,0 +1,31 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + mov ecx, [esp + 4] + xgetbv + ret diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/MdePkg/Library/BaseLi= b/X64/XGetBv.nasm new file mode 100644 index 000000000000..09f3be8ae0a8 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + xgetbv + shl rdx, 32 + or rax, rdx + ret + --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: UxEvXEqGu3prUNP0VuquiqOWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829241; bh=WmBe8OAq1Mq/GPk+EEK0YMg+Yr6p5q5yEWjYF8TuMtI=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=MWQHwIqPFratgNNQ12MUBJ+5mLcoR/6veT8FHe5/VO8uomEhMZbVO1A18DEPsl3UtHq Ji9ciwRbBKGT+CBPKLDtHKhM7negEd/lnnhHBVj82QQI1dmhBqSaU9s94w3kPJvJm8hhO gW6G0DcmTWV/wLR68Np7bVuiDbVYNr+6pbc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 VMGEXIT is a new instruction used for Hypervisor/Guest communication when running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE) to occur, resulting in a #VMEXIT with an exit code value of 0x403. Since SEV-ES is only supported in X64, provide the necessary X64 support to execute the VMGEXIT instruction, which is coded as "rep vmmcall". For IA32, since "vmmcall" is not supported in NASM 32-bit mode and VMGEXIT should never be called, provide a stub implementation that is identical to CpuBreakpoint(). Cc: Michael D Kinney Cc: Liming Gao Reviewed-by: Liming Gao Signed-off-by: Tom Lendacky Reviewed-by: Laszlo Ersek --- MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Include/Library/BaseLib.h | 14 +++++++++ MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 38 ++++++++++++++++++++++++ MdePkg/Library/BaseLib/X64/VmgExit.nasm | 32 ++++++++++++++++++++ 4 files changed, 86 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3b93b5db8d24..3b85c56c3c03 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -184,6 +184,7 @@ [Sources.Ia32] Ia32/DisableCache.nasm| GCC Ia32/RdRand.nasm Ia32/XGetBv.nasm + Ia32/VmgExit.nasm =20 Ia32/DivS64x64Remainder.c Ia32/InternalSwitchStack.c | MSFT @@ -317,6 +318,7 @@ [Sources.X64] X64/DisablePaging64.nasm X64/RdRand.nasm X64/XGetBv.nasm + X64/VmgExit.nasm ChkStkGcc.c | GCC =20 [Sources.EBC] diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index 7edf0051a0a0..04fb329eaabb 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7848,6 +7848,20 @@ AsmXGetBv ( ); =20 =20 +/** + Executes a VMGEXIT instruction (VMMCALL with a REP prefix) + + Executes a VMGEXIT instruction. This function is only available on IA-32= and + x64. + +**/ +VOID +EFIAPI +AsmVmgExit ( + VOID + ); + + /** Patch the immediate operand of an IA32 or X64 instruction such that the = byte, word, dword or qword operand is encoded at the end of the instruction's diff --git a/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm b/MdePkg/Library/Base= Lib/Ia32/VmgExit.nasm new file mode 100644 index 000000000000..69f7fbf3506a --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm @@ -0,0 +1,38 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; VmgExit.Asm +; +; Abstract: +; +; AsmVmgExit function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; AsmVmgExit ( +; VOID +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmVmgExit) +ASM_PFX(AsmVmgExit): +; +; NASM doesn't support the vmmcall instruction in 32-bit mode and NASM ver= sions +; before 2.12 cannot translate the 64-bit "rep vmmcall" instruction into e= lf32 +; format. Given that VMGEXIT does not make sense on IA32, provide a stub +; implementation that is identical to CpuBreakpoint(). In practice, AsmVmg= Exit() +; should never be called on IA32. +; + int 3 + ret + diff --git a/MdePkg/Library/BaseLib/X64/VmgExit.nasm b/MdePkg/Library/BaseL= ib/X64/VmgExit.nasm new file mode 100644 index 000000000000..26f034593c67 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/VmgExit.nasm @@ -0,0 +1,32 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; VmgExit.Asm +; +; Abstract: +; +; AsmVmgExit function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; AsmVmgExit ( +; VOID +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmVmgExit) +ASM_PFX(AsmVmgExit): + rep vmmcall + ret + --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 9iUaPwZcoA6xhO7T2CqS98mEx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829250; bh=H9xTgcOgCxsiBjSv7qqIE37OWriA7XsFNQjHWE+4Pm0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=fOKW5PZX2cXVgBcgg2aODRuIyxvNSdZcATA4YjXI4qG1lH0l+Rp3aJciPrS6t8hvQAb fdDSn0cggaY2Zceq/+/i5jFhowuGWwvSArvzZNbMXeVRwEKuROZiVF6c3qOykNDcYE6Xk sE5n6KDrvqRlU1sOymaDJ5pER72laHI1RfQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 To support handling #VC exceptions and issuing VMGEXIT instructions, create a library with functions that can be used to perform these #VC/VMGEXIT related operations. This includes functions for: - Handling #VC exceptions - Preparing for and issuing a VMGEXIT - Performing MMIO-related write operations to support flash emulation - Performing AP related boot opeations The base functions in this driver will not do anything and will return an error if a return value is required. It is expected that other packages (like OvmfPkg) will create a version of the library to fully support an SEV-ES guest. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/UefiCpuPkg.dec | 3 + UefiCpuPkg/UefiCpuPkg.dsc | 2 + .../Library/VmgExitLibNull/VmgExitLibNull.inf | 27 ++++ UefiCpuPkg/Include/Library/VmgExitLib.h | 103 +++++++++++++++ .../Library/VmgExitLibNull/VmgExitLibNull.c | 121 ++++++++++++++++++ .../Library/VmgExitLibNull/VmgExitLibNull.uni | 15 +++ 6 files changed, 271 insertions(+) create mode 100644 UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h create mode 100644 UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c create mode 100644 UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.uni diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index d52912ddca1f..17228cb5a84f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -53,6 +53,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## MpInitLib|Include/Library/MpInitLib.h =20 + ## @libraryclass Provides function to support VMGEXIT processing. + VmgExitLib|Include/Library/VmgExitLib.h + [Guids] gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 964720048dd7..b2b6d78a71b0 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -56,6 +56,7 @@ [LibraryClasses] PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.SEC] PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf @@ -143,6 +144,7 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.i= nf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf + UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf UefiCpuPkg/SecCore/SecCore.inf diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf b/UefiCpu= Pkg/Library/VmgExitLibNull/VmgExitLibNull.inf new file mode 100644 index 000000000000..d8770a21c355 --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf @@ -0,0 +1,27 @@ +## @file +# VMGEXIT Support Library. +# +# Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VmgExitLibNull + MODULE_UNI_FILE =3D VmgExitLibNull.uni + FILE_GUID =3D 3cd7368f-ef9b-4a9b-9571-2ed93813677e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VmgExitLib + +[Sources.common] + VmgExitLibNull.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/L= ibrary/VmgExitLib.h new file mode 100644 index 000000000000..45fc27d35e29 --- /dev/null +++ b/UefiCpuPkg/Include/Library/VmgExitLib.h @@ -0,0 +1,103 @@ +/** @file + Public header file for the VMGEXIT Support library class. + + This library class defines some routines used when invoking the VMGEXIT + instruction in support of SEV-ES and to handle #VC exceptions. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __VMG_EXIT_LIB_H__ +#define __VMG_EXIT_LIB_H__ + +#include +#include + + +/** + Perform VMGEXIT. + + Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction a= nd + then handles the return actions. + + @param[in, out] Ghcb A pointer to the GHCB + @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode + field of the GHCB. + @param[in] ExitInfo1 VMGEXIT information to be assigned to the + SwExitInfo1 field of the GHCB. + @param[in] ExitInfo2 VMGEXIT information to be assigned to the + SwExitInfo2 field of the GHCB. + + @retval 0 VMGEXIT succeeded. + @return Exception number to be propagated, VMGEXIT + processing did not succeed. + +**/ +UINT64 +EFIAPI +VmgExit ( + IN OUT GHCB *Ghcb, + IN UINT64 ExitCode, + IN UINT64 ExitInfo1, + IN UINT64 ExitInfo2 + ); + +/** + Perform pre-VMGEXIT initialization/preparation. + + Performs the necessary steps in preparation for invoking VMGEXIT. Must be + called before setting any fields within the GHCB. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgInit ( + IN OUT GHCB *Ghcb + ); + +/** + Perform post-VMGEXIT cleanup. + + Performs the necessary steps to cleanup after invoking VMGEXIT. Must be + called after obtaining needed fields within the GHCB. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgDone ( + IN OUT GHCB *Ghcb + ); + +/** + Handle a #VC exception. + + Performs the necessary processing to handle a #VC exception. + + The base library function returns an error equal to VC_EXCEPTION, + to be propagated to the standard exception handling stack. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VC not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VC handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmgExitHandleVc ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ); + +#endif diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c b/UefiCpuPk= g/Library/VmgExitLibNull/VmgExitLibNull.c new file mode 100644 index 000000000000..bb265e1700d2 --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.c @@ -0,0 +1,121 @@ +/** @file + VMGEXIT Base Support Library. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + Perform VMGEXIT. + + Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction a= nd + then handles the return actions. + + The base library function returns an error in the form of a + GHCB_EVENT_INJECTION representing a GP_EXCEPTION. + + @param[in, out] Ghcb A pointer to the GHCB + @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode + field of the GHCB. + @param[in] ExitInfo1 VMGEXIT information to be assigned to the + SwExitInfo1 field of the GHCB. + @param[in] ExitInfo2 VMGEXIT information to be assigned to the + SwExitInfo2 field of the GHCB. + + @retval 0 VMGEXIT succeeded. + @return Exception number to be propagated, VMGEXIT + processing did not succeed. + +**/ +UINT64 +EFIAPI +VmgExit ( + IN OUT GHCB *Ghcb, + IN UINT64 ExitCode, + IN UINT64 ExitInfo1, + IN UINT64 ExitInfo2 + ) +{ + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D 0; + Event.Elements.Vector =3D GP_EXCEPTION; + Event.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid =3D 1; + + return Event.Uint64; +} + +/** + Perform pre-VMGEXIT initialization/preparation. + + Performs the necessary steps in preparation for invoking VMGEXIT. Must be + called before setting any fields within the GHCB. + + The base library function does nothing. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgInit ( + IN OUT GHCB *Ghcb + ) +{ +} + +/** + Perform post-VMGEXIT cleanup. + + Performs the necessary steps to cleanup after invoking VMGEXIT. Must be + called after obtaining needed fields within the GHCB. + + The base library function does nothing. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgDone ( + IN OUT GHCB *Ghcb + ) +{ +} + +/** + Handle a #VC exception. + + Performs the necessary processing to handle a #VC exception. + + The base library function returns an error equal to VC_EXCEPTION, + to be propagated to the standard exception handling stack. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VC not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VC handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmgExitHandleVc ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + *ExceptionType =3D VC_EXCEPTION; + + return EFI_UNSUPPORTED; +} diff --git a/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.uni b/UefiCpu= Pkg/Library/VmgExitLibNull/VmgExitLibNull.uni new file mode 100644 index 000000000000..8639bc0e8ce9 --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.uni @@ -0,0 +1,15 @@ +// /** @file +// VMGEXIT support library instance. +// +// VMGEXIT support library instance. +// +// Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "VMGEXIT support N= ULL library instance" + +#string STR_MODULE_DESCRIPTION #language en-US "VMGEXIT support N= ULL library instance." + --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 6QbU8bxRuKrj89E12QBnMafVx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829260; bh=96d6EIpxA1PjLNn+OVoHLs8iIUofCT3bbp/EMi9RqDg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Xh1gB5zO9TlI2nzhWlOOCbumrfDd5k8t+gE0P8+11TAq8hXq9V3ykdkyxubO2i/uhrZ S+ouBcwDzzgbt8zt/UYrpG64gZwMWP3hEByM4q0ENctnYoBe0JTnX7F1np0BHFPokwEGP ZtMPOfA+/q7ZKYWW9IZ7SaZKbJ0VjnunUEQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Various CpuExceptionHandlerLib libraries will updated to use the new VmgExitLib library. To prevent any build breakage, update the OvmfPkg DSC files that use a form of the CpuExceptionHandlerLib library to include the VmgExitLib library. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Anthony Perard Cc: Julien Grall Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/OvmfXen.dsc | 1 + 4 files changed, 4 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 9178ffeb71cb..c57bba1ba197 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -229,6 +229,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a665f78f0dc7..22e930b12b9b 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -233,6 +233,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 17f345acf4ee..27f5225fc281 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -233,6 +233,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 782803cb2787..37b63a874067 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -213,6 +213,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.SEC] QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Sjejqxas5GU9gobjtnCGnSV3x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829268; bh=UeiFwCHhlf3qYUWB/dmgb4O8q/cMw3N8wdvuBVndWsU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=eBWKHdg4rsKP1x7X5CPP++CIB0ZPbD8cEdFPKkx7xP/r6qLAayaCdiaP2N8ZWUxZP/0 h4UCdJp07B7j9oho/qXn4kqrJW17N84V5lV2iNryX3hKL6Hy0+884fahqrPbnDEGdXDOR yPhW8ZK8nfWq+5Mr6KHbpdB9MAD+rClEGnQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Various CpuExceptionHandlerLib libraries will updated to use the new VmgExitLib library. To prevent any build breakage, update the UefiPayloadPkg DSC files that use a form of the CpuExceptionHandlerLib library to include the VmgExitLib library. Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You Reviewed-by: Guo Dong Reviewed-by: Maurice Ma Signed-off-by: Tom Lendacky --- UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 2 ++ UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 2 ++ 2 files changed, 4 insertions(+) diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay= loadPkgIa32.dsc index 9a9ca3060e47..460da1c504dc 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc @@ -237,6 +237,7 @@ [LibraryClasses.common.DXE_CORE] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -249,6 +250,7 @@ [LibraryClasses.common.DXE_DRIVER] !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index a768a8702c66..942bc9076634 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -238,6 +238,7 @@ [LibraryClasses.common.DXE_CORE] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -250,6 +251,7 @@ [LibraryClasses.common.DXE_DRIVER] !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 4VTB65TEsrcpLJ4GdFUUJEgnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829275; bh=FPAHPeEMXtRrwZh/8N9XETThDB4NQdKwxP4eZHNq9U4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=aMxz1xMf6u7TapvCMgYPjA31s47l6jyrs63NWCXThmKCoNaChxnJe5IavtPtE+bJmYk DuEvsZOKaxLMviOLv+H7cdWoiEbIghHpBo0ipw7/lWkHit/O8BgSaH8pjdTYFdgjucrfn 8fjoeC8iaXtRgZNeBMi4018imTuaZX0fQOw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Add base support to handle #VC exceptions. Update the common exception handlers to invoke the VmgExitHandleVc () function of the VmgExitLib library when a #VC is encountered. A non-zero return code will propagate to the targeted exception handler. Under SEV-ES, a DR7 read or write intercept generates a #VC exception. To avoid exception recursion, a #VC exception will not try to read and push the actual debug registers into the EFI_SYSTEM_CONTEXT_X64 struct and instead push zeroes. The #VC exception handler does not make use of the debug registers from the saved context and the exception processing exit code does not attempt to restore the debug register values. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- .../DxeCpuExceptionHandlerLib.inf | 1 + .../PeiCpuExceptionHandlerLib.inf | 1 + .../SecPeiCpuExceptionHandlerLib.inf | 1 + .../SmmCpuExceptionHandlerLib.inf | 1 + .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 1 + .../CpuExceptionCommon.c | 10 +++++++++- .../PeiDxeSmmCpuException.c | 20 ++++++++++++++++++- .../SecPeiCpuException.c | 19 ++++++++++++++++++ .../X64/ExceptionHandlerAsm.nasm | 17 ++++++++++++++++ .../X64/Xcode5ExceptionHandlerAsm.nasm | 17 ++++++++++++++++ 10 files changed, 86 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index 61e2ec30b089..07b34c92a892 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -57,3 +57,4 @@ [LibraryClasses] PeCoffGetEntryPointLib MemoryAllocationLib DebugLib + VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index 093374944df6..feae7b3e06de 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -52,6 +52,7 @@ [LibraryClasses] HobLib MemoryAllocationLib SynchronizationLib + VmgExitLib =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 6d25cafe2ca3..967cb61ba6d9 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -48,3 +48,4 @@ [LibraryClasses] PrintLib LocalApicLib PeCoffGetEntryPointLib + VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 2ffbbccc302f..4cdb11c04ea0 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -51,4 +51,5 @@ [LibraryClasses] LocalApicLib PeCoffGetEntryPointLib DebugLib + VmgExitLib =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExcep= tionHandlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPei= CpuExceptionHandlerLib.inf index 7e21beaab6f2..743c2aa76684 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExceptionHan= dlerLib.inf @@ -53,3 +53,4 @@ [LibraryClasses] PrintLib LocalApicLib PeCoffGetEntryPointLib + VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 8adbd43fefb4..c9003b10e552 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -14,7 +14,7 @@ // // 1 means an error code will be pushed, otherwise 0 // -CONST UINT32 mErrorCodeFlag =3D 0x00227d00; +CONST UINT32 mErrorCodeFlag =3D 0x20227d00; =20 // // Define the maximum message length @@ -45,6 +45,14 @@ CONST CHAR8 *mExceptionNameStr[] =3D { "#XM - SIMD floating-point", "#VE - Virtualization", "#CP - Control Protection" + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "Reserved", + "#VC - VMM Communication", }; =20 #define EXCEPTION_KNOWN_NAME_NUM (sizeof (mExceptionNameStr) / sizeof (CH= AR8 *)) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuExceptio= n.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 6a2670d55918..892d349d4b37 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -6,8 +6,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 -#include "CpuExceptionCommon.h" #include +#include +#include "CpuExceptionCommon.h" =20 /** Internal worker function for common exception handler. @@ -27,6 +28,23 @@ CommonExceptionHandlerWorker ( RESERVED_VECTORS_DATA *ReservedVectors; EFI_CPU_INTERRUPT_HANDLER *ExternalInterruptHandler; =20 + if (ExceptionType =3D=3D VC_EXCEPTION) { + EFI_STATUS Status; + // + // #VC needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface. + // + // Handle the #VC: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmgExitHandleVc (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + ExceptionHandlerContext =3D (EXCEPTION_HANDLER_CONTEXT *) (UINTN) (Syst= emContext.SystemContextIa32); ReservedVectors =3D ExceptionHandlerData->ReservedVectors; ExternalInterruptHandler =3D ExceptionHandlerData->ExternalInterruptHand= ler; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index d4ae153c5742..01b5a2f1f4fc 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -7,6 +7,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 #include +#include #include "CpuExceptionCommon.h" =20 CONST UINTN mDoFarReturnFlag =3D 0; @@ -24,6 +25,24 @@ CommonExceptionHandler ( IN EFI_SYSTEM_CONTEXT SystemContext ) { + if (ExceptionType =3D=3D VC_EXCEPTION) { + EFI_STATUS Status; + // + // #VC needs to be handled immediately upon enabling exception handling + // and therefore can't use the RegisterCpuInterruptHandler() interface + // (which isn't supported under Sec and Pei anyway). + // + // Handle the #VC: + // On EFI_SUCCESS - Exception has been handled, return + // On other - ExceptionType contains (possibly new) exception + // value + // + Status =3D VmgExitHandleVc (&ExceptionType, SystemContext); + if (!EFI_ERROR (Status)) { + return; + } + } + // // Initialize the serial port before dumping. // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs= m.nasm index 3814f9de3703..2a5545ecfd41 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; =20 +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -224,6 +226,9 @@ HasErrorCode: push rax =20 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -236,7 +241,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish =20 +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid excep= tion recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionH= andlerAsm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5Except= ionHandlerAsm.nasm index 19198f273137..26cae56cc5cf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/Xcode5ExceptionHandlerA= sm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; =20 +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -225,6 +227,9 @@ HasErrorCode: push rax =20 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -237,7 +242,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish =20 +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid excep= tion recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: tXx24TTzqTeYuQRDolrNEc3kx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829283; bh=aQxIxdBMB+R1wbrzO5+Z2+aGGxDdKCU7p2a1Y9LcCjk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=cDOEPuY/jkYReqUi1uTSjQ5CTQH3EAxVsQfzyi2UsdJWwJO+FPWHzGUGj92koPmelRv rvy2N8jFSxsb2DIvCXCc6+dD3x9nNP30UEasChXulrzvTj/neL5JJa69p+m8jWMBIUQkg 3ZUB2bCKcR0ojnhKfF6w24ccisWal/cRl4o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky The base VmgExitLib library provides a default limited interface. As it does not provide full support, create an OVMF version of this library to begin the process of providing full support of SEV-ES within OVMF. SEV-ES support is only provided for X64 builds, so only OvmfPkgX64.dsc is updated to make use of the OvmfPkg version of the library. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgX64.dsc | 2 +- OvmfPkg/Library/VmgExitLib/VmgExitLib.inf | 36 ++++ OvmfPkg/Library/VmgExitLib/VmgExitLib.c | 159 ++++++++++++++++++ OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 81 +++++++++ 4 files changed, 277 insertions(+), 1 deletion(-) create mode 100644 OvmfPkg/Library/VmgExitLib/VmgExitLib.inf create mode 100644 OvmfPkg/Library/VmgExitLib/VmgExitLib.c create mode 100644 OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 27f5225fc281..60be5eae3d2b 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -233,7 +233,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf - VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf + VmgExitLib|OvmfPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf b/OvmfPkg/Library/Vm= gExitLib/VmgExitLib.inf new file mode 100644 index 000000000000..d003ac63173e --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/VmgExitLib.inf @@ -0,0 +1,36 @@ +## @file +# VMGEXIT Support Library. +# +# Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VmgExitLib + FILE_GUID =3D 0e923c25-13cd-430b-8714-ffe85652a97b + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VmgExitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D X64 +# + +[Sources.common] + VmgExitLib.c + VmgExitVcHandler.c + +[Packages] + MdePkg/MdePkg.dec + OvmfPkg/OvmfPkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + BaseMemoryLib + DebugLib + diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitLib.c b/OvmfPkg/Library/VmgE= xitLib/VmgExitLib.c new file mode 100644 index 000000000000..53040cc6f649 --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/VmgExitLib.c @@ -0,0 +1,159 @@ +/** @file + VMGEXIT Support Library. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Check for VMGEXIT error + + Check if the hypervisor has returned an error after completion of the VM= GEXIT + by examining the SwExitInfo1 field of the GHCB. + + @param[in] Ghcb A pointer to the GHCB + + @retval 0 VMGEXIT succeeded. + @return Exception number to be propagated, VMGEXIT proces= sing + did not succeed. + +**/ +STATIC +UINT64 +VmgExitErrorCheck ( + IN GHCB *Ghcb + ) +{ + GHCB_EVENT_INJECTION Event; + GHCB_EXIT_INFO ExitInfo; + UINT64 Status; + + ExitInfo.Uint64 =3D Ghcb->SaveArea.SwExitInfo1; + ASSERT ((ExitInfo.Elements.Lower32Bits =3D=3D 0) || + (ExitInfo.Elements.Lower32Bits =3D=3D 1)); + + Status =3D 0; + if (ExitInfo.Elements.Lower32Bits =3D=3D 0) { + return Status; + } + + if (ExitInfo.Elements.Lower32Bits =3D=3D 1) { + ASSERT (Ghcb->SaveArea.SwExitInfo2 !=3D 0); + + // + // Check that the return event is valid + // + Event.Uint64 =3D Ghcb->SaveArea.SwExitInfo2; + if (Event.Elements.Valid && + Event.Elements.Type =3D=3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION) { + switch (Event.Elements.Vector) { + case GP_EXCEPTION: + case UD_EXCEPTION: + // + // Use returned event as return code + // + Status =3D Event.Uint64; + } + } + } + + if (Status =3D=3D 0) { + GHCB_EVENT_INJECTION GpEvent; + + GpEvent.Uint64 =3D 0; + GpEvent.Elements.Vector =3D GP_EXCEPTION; + GpEvent.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + GpEvent.Elements.Valid =3D 1; + + Status =3D GpEvent.Uint64; + } + + return Status; +} + +/** + Perform VMGEXIT. + + Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction a= nd + then handles the return actions. + + @param[in, out] Ghcb A pointer to the GHCB + @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode + field of the GHCB. + @param[in] ExitInfo1 VMGEXIT information to be assigned to the + SwExitInfo1 field of the GHCB. + @param[in] ExitInfo2 VMGEXIT information to be assigned to the + SwExitInfo2 field of the GHCB. + + @retval 0 VMGEXIT succeeded. + @return Exception number to be propagated, VMGEXIT + processing did not succeed. + +**/ +UINT64 +EFIAPI +VmgExit ( + IN OUT GHCB *Ghcb, + IN UINT64 ExitCode, + IN UINT64 ExitInfo1, + IN UINT64 ExitInfo2 + ) +{ + Ghcb->SaveArea.SwExitCode =3D ExitCode; + Ghcb->SaveArea.SwExitInfo1 =3D ExitInfo1; + Ghcb->SaveArea.SwExitInfo2 =3D ExitInfo2; + + // + // Guest memory is used for the guest-hypervisor communication, so fence + // the invocation of the VMGEXIT instruction to ensure GHCB accesses are + // synchronized properly. + // + MemoryFence (); + AsmVmgExit (); + MemoryFence (); + + return VmgExitErrorCheck (Ghcb); +} + +/** + Perform pre-VMGEXIT initialization/preparation. + + Performs the necessary steps in preparation for invoking VMGEXIT. Must be + called before setting any fields within the GHCB. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgInit ( + IN OUT GHCB *Ghcb + ) +{ + SetMem (&Ghcb->SaveArea, sizeof (Ghcb->SaveArea), 0); +} + +/** + Perform post-VMGEXIT cleanup. + + Performs the necessary steps to cleanup after invoking VMGEXIT. Must be + called after obtaining needed fields within the GHCB. + + @param[in, out] Ghcb A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgDone ( + IN OUT GHCB *Ghcb + ) +{ +} + diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c new file mode 100644 index 000000000000..b6a955ed8088 --- /dev/null +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -0,0 +1,81 @@ +/** @file + X64 #VC Exception Handler functon. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + Handle a #VC exception. + + Performs the necessary processing to handle a #VC exception. + + @param[in, out] ExceptionType Pointer to an EFI_EXCEPTION_TYPE to be s= et + as value to use on error. + @param[in, out] SystemContext Pointer to EFI_SYSTEM_CONTEXT + + @retval EFI_SUCCESS Exception handled + @retval EFI_UNSUPPORTED #VC not supported, (new) exception value= to + propagate provided + @retval EFI_PROTOCOL_ERROR #VC handling failed, (new) exception val= ue to + propagate provided + +**/ +EFI_STATUS +EFIAPI +VmgExitHandleVc ( + IN OUT EFI_EXCEPTION_TYPE *ExceptionType, + IN OUT EFI_SYSTEM_CONTEXT SystemContext + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + EFI_SYSTEM_CONTEXT_X64 *Regs; + GHCB *Ghcb; + UINT64 ExitCode, Status; + EFI_STATUS VcRet; + + VcRet =3D EFI_SUCCESS; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + ASSERT (Msr.GhcbInfo.Function =3D=3D 0); + ASSERT (Msr.Ghcb !=3D 0); + + Regs =3D SystemContext.SystemContextX64; + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + + ExitCode =3D Regs->ExceptionData; + switch (ExitCode) { + default: + Status =3D VmgExit (Ghcb, SVM_EXIT_UNSUPPORTED, ExitCode, 0); + if (Status =3D=3D 0) { + Regs->ExceptionData =3D 0; + *ExceptionType =3D GP_EXCEPTION; + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D Status; + if (Event.Elements.ErrorCodeValid !=3D 0) { + Regs->ExceptionData =3D Event.Elements.ErrorCode; + } else { + Regs->ExceptionData =3D 0; + } + + *ExceptionType =3D Event.Elements.Vector; + } + + VcRet =3D EFI_PROTOCOL_ERROR; + } + + VmgDone (Ghcb); + + return VcRet; +} --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: jj4qHKMUaPqfkCMajXEj2Lsnx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829291; bh=et4PSbFgiuQBlmfViSd5l9hHXMERZxAlGI+XESWw8So=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=PaA/LAfZboIBvTg9/lV5RS5lc3NIfbfGtrNpP5rxDEcEC5KmhAhnkS+YRhXP24A6Yvm +0ibKzKwDHxN72+81fHxvXOemXzItDvUhFT+f92YtASCgNt6c7fccqDGehg/BkEZtMfp/ Dr/9ov1eaT3TbvVDjKW8+Idhg7nhbg8Huko= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a IOIO_PROT NAE event. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXITINFO1 value in the GHCB. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../IndustryStandard/InstructionParsing.h | 83 +++ OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 560 +++++++++++++++++- 2 files changed, 629 insertions(+), 14 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/InstructionParsing.h diff --git a/OvmfPkg/Include/IndustryStandard/InstructionParsing.h b/OvmfPk= g/Include/IndustryStandard/InstructionParsing.h new file mode 100644 index 000000000000..149ff328e06c --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/InstructionParsing.h @@ -0,0 +1,83 @@ +/** @file + Instruction parsing support definitions. + + Copyright (C) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __INSTRUCTION_PARSING_H__ +#define __INSTRUCTION_PARSING_H__ + +#include +#include + +// +// Instruction REX prefix definition +// +typedef union { + struct { + UINT8 BitB:1; + UINT8 BitX:1; + UINT8 BitR:1; + UINT8 BitW:1; + UINT8 Rex:4; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_REX_PREFIX; + +// +// Instruction ModRM definition +// +typedef union { + struct { + UINT8 Rm:3; + UINT8 Reg:3; + UINT8 Mod:2; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_MODRM; + +// +// Instruction SIB definition +// +typedef union { + struct { + UINT8 Base:3; + UINT8 Index:3; + UINT8 Scale:2; + } Bits; + + UINT8 Uint8; +} INSTRUCTION_SIB; + +// +// Legacy Instruction Prefixes +// +#define OVERRIDE_SEGMENT_CS 0x2E +#define OVERRIDE_SEGMENT_DS 0x3E +#define OVERRIDE_SEGMENT_ES 0x26 +#define OVERRIDE_SEGMENT_SS 0x36 +#define OVERRIDE_SEGMENT_FS 0x64 +#define OVERRIDE_SEGMENT_GS 0x65 +#define OVERRIDE_OPERAND_SIZE 0x66 +#define OVERRIDE_ADDRESS_SIZE 0x67 +#define LOCK_PREFIX 0xF0 +#define REPNZ_PREFIX 0xF2 +#define REPZ_PREFIX 0xF3 + +// +// REX Prefixes +// +#define REX_PREFIX_START 0x40 +#define REX_PREFIX_STOP 0x4F +#define REX_64BIT_OPERAND_SIZE_MASK 0x08 + +// +// Two-byte Opcode Flag +// +#define TWO_BYTE_OPCODE_ESCAPE 0x0F + +#endif diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index b6a955ed8088..04e8b8aebf7d 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -11,6 +11,529 @@ #include #include #include +#include + +// +// Instruction execution mode definition +// +typedef enum { + LongMode64Bit =3D 0, + LongModeCompat32Bit, + LongModeCompat16Bit, +} SEV_ES_INSTRUCTION_MODE; + +// +// Instruction size definition (for operand and address) +// +typedef enum { + Size8Bits =3D 0, + Size16Bits, + Size32Bits, + Size64Bits, +} SEV_ES_INSTRUCTION_SIZE; + +// +// Intruction segment definition +// +typedef enum { + SegmentEs =3D 0, + SegmentCs, + SegmentSs, + SegmentDs, + SegmentFs, + SegmentGs, +} SEV_ES_INSTRUCTION_SEGMENT; + +// +// Instruction rep function definition +// +typedef enum { + RepNone =3D 0, + RepZ, + RepNZ, +} SEV_ES_INSTRUCTION_REP; + +typedef struct { + UINT8 Rm; + UINT8 Reg; + UINT8 Mod; +} SEV_ES_INSTRUCTION_MODRM_EXT; + +typedef struct { + UINT8 Base; + UINT8 Index; + UINT8 Scale; +} SEV_ES_INSTRUCTION_SIB_EXT; + +// +// Instruction opcode definition +// +typedef struct { + SEV_ES_INSTRUCTION_MODRM_EXT ModRm; + + SEV_ES_INSTRUCTION_SIB_EXT Sib; + + UINTN RegData; + UINTN RmData; +} SEV_ES_INSTRUCTION_OPCODE_EXT; + +// +// Instruction parsing context definition +// +typedef struct { + GHCB *Ghcb; + + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE DataSize; + SEV_ES_INSTRUCTION_SIZE AddrSize; + BOOLEAN SegmentSpecified; + SEV_ES_INSTRUCTION_SEGMENT Segment; + SEV_ES_INSTRUCTION_REP RepMode; + + UINT8 *Begin; + UINT8 *End; + + UINT8 *Prefixes; + UINT8 *OpCodes; + UINT8 *Displacement; + UINT8 *Immediate; + + INSTRUCTION_REX_PREFIX RexPrefix; + + BOOLEAN ModRmPresent; + INSTRUCTION_MODRM ModRm; + + BOOLEAN SibPresent; + INSTRUCTION_SIB Sib; + + UINTN PrefixSize; + UINTN OpCodeSize; + UINTN DisplacementSize; + UINTN ImmediateSize; + + SEV_ES_INSTRUCTION_OPCODE_EXT Ext; +} SEV_ES_INSTRUCTION_DATA; + +// +// Non-automatic Exit function prototype +// +typedef +UINT64 +(*NAE_EXIT) ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ); + + +/** + Checks the GHCB to determine if the specified register has been marked v= alid. + + The ValidBitmap area represents the areas of the GHCB that have been mar= ked + valid. Return an indication of whether the area of the GHCB that holds t= he + specified register has been marked valid. + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication Block + @param[in] Reg Offset in the GHCB of the register to check + + @retval TRUE Register has been marked vald in the GHCB + @retval FALSE Register has not been marked valid in the GHCB + +**/ +STATIC +BOOLEAN +GhcbIsRegValid ( + IN GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex =3D Reg / 8; + RegBit =3D Reg & 0x07; + + return ((Ghcb->SaveArea.ValidBitmap[RegIndex] & (1 << RegBit)) !=3D 0); +} + +/** + Marks a register as valid in the GHCB. + + The ValidBitmap area represents the areas of the GHCB that have been mar= ked + valid. Set the area of the GHCB that holds the specified register as val= id. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communication Bl= ock + @param[in] Reg Offset in the GHCB of the register to mark valid + +**/ +STATIC +VOID +GhcbSetRegValid ( + IN OUT GHCB *Ghcb, + IN GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex; + UINT32 RegBit; + + RegIndex =3D Reg / 8; + RegBit =3D Reg & 0x07; + + Ghcb->SaveArea.ValidBitmap[RegIndex] |=3D (1 << RegBit); +} + +/** + Decode instruction prefixes. + + Parse the instruction data to track the instruction prefixes that have + been used. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + +**/ +STATIC +VOID +DecodePrefixes ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE ModeDataSize; + SEV_ES_INSTRUCTION_SIZE ModeAddrSize; + UINT8 *Byte; + + // + // Always in 64-bit mode + // + Mode =3D LongMode64Bit; + ModeDataSize =3D Size32Bits; + ModeAddrSize =3D Size64Bits; + + InstructionData->Mode =3D Mode; + InstructionData->DataSize =3D ModeDataSize; + InstructionData->AddrSize =3D ModeAddrSize; + + InstructionData->Prefixes =3D InstructionData->Begin; + + Byte =3D InstructionData->Prefixes; + for ( ; ; Byte++, InstructionData->PrefixSize++) { + // + // Check the 0x40 to 0x4F range using an if statement here since some + // compilers don't like the "case 0x40 ... 0x4F:" syntax. This avoids + // 16 case statements below. + // + if ((*Byte >=3D REX_PREFIX_START) && (*Byte <=3D REX_PREFIX_STOP)) { + InstructionData->RexPrefix.Uint8 =3D *Byte; + if ((*Byte & REX_64BIT_OPERAND_SIZE_MASK) !=3D 0) { + InstructionData->DataSize =3D Size64Bits; + } + continue; + } + + switch (*Byte) { + case OVERRIDE_SEGMENT_CS: + case OVERRIDE_SEGMENT_DS: + case OVERRIDE_SEGMENT_ES: + case OVERRIDE_SEGMENT_SS: + if (Mode !=3D LongMode64Bit) { + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D (*Byte >> 3) & 3; + } + break; + + case OVERRIDE_SEGMENT_FS: + case OVERRIDE_SEGMENT_GS: + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D *Byte & 7; + break; + + case OVERRIDE_OPERAND_SIZE: + if (InstructionData->RexPrefix.Uint8 =3D=3D 0) { + InstructionData->DataSize =3D + (Mode =3D=3D LongMode64Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + } + break; + + case OVERRIDE_ADDRESS_SIZE: + InstructionData->AddrSize =3D + (Mode =3D=3D LongMode64Bit) ? Size32Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + break; + + case LOCK_PREFIX: + break; + + case REPZ_PREFIX: + InstructionData->RepMode =3D RepZ; + break; + + case REPNZ_PREFIX: + InstructionData->RepMode =3D RepNZ; + break; + + default: + InstructionData->OpCodes =3D Byte; + InstructionData->OpCodeSize =3D (*Byte =3D=3D TWO_BYTE_OPCODE_ESCAPE= ) ? 2 : 1; + + InstructionData->End =3D Byte + InstructionData->OpCodeSize; + InstructionData->Displacement =3D InstructionData->End; + InstructionData->Immediate =3D InstructionData->End; + return; + } + } +} + +/** + Determine instruction length + + Return the total length of the parsed instruction. + + @param[in] InstructionData Instruction parsing context + + @return Length of parsed instruction + +**/ +STATIC +UINT64 +InstructionLength ( + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return (UINT64) (InstructionData->End - InstructionData->Begin); +} + +/** + Initialize the instruction parsing context. + + Initialize the instruction parsing context, which includes decoding the + instruction prefixes. + + @param[in, out] InstructionData Instruction parsing context + @param[in] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in] Regs x64 processor context + +**/ +STATIC +VOID +InitInstructionData ( + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData, + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs + ) +{ + SetMem (InstructionData, sizeof (*InstructionData), 0); + InstructionData->Ghcb =3D Ghcb; + InstructionData->Begin =3D (UINT8 *) Regs->Rip; + InstructionData->End =3D (UINT8 *) Regs->Rip; + + DecodePrefixes (Regs, InstructionData); +} + +/** + Report an unsupported event to the hypervisor + + Use the VMGEXIT support to report an unsupported event to the hypervisor. + + @param[in] Ghcb Pointer to the Guest-Hypervisor Communication + Block + @param[in] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @return New exception value to propagate + +**/ +STATIC +UINT64 +UnsupportedExit ( + IN GHCB *Ghcb, + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SVM_EXIT_UNSUPPORTED, Regs->ExceptionData, 0); + if (Status =3D=3D 0) { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D 0; + Event.Elements.Vector =3D GP_EXCEPTION; + Event.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid =3D 1; + + Status =3D Event.Uint64; + } + + return Status; +} + +/** + Build the IOIO event information. + + The IOIO event information identifies the type of IO operation to be per= formed + by the hypervisor. Build this information based on the instruction data. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + + @return IOIO event information value + +**/ +STATIC +UINT64 +IoioExitInfo ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo; + + ExitInfo =3D 0; + + switch (*(InstructionData->OpCodes)) { + // + // IN immediate opcodes + // + case 0xE4: + case 0xE5: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16); + break; + + // + // OUT immediate opcodes + // + case 0xE6: + case 0xE7: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16) | IOIO_TYPE_OU= T; + break; + + // + // IN register opcodes + // + case 0xEC: + case 0xED: + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + // + // OUT register opcodes + // + case 0xEE: + case 0xEF: + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + default: + return 0; + } + + switch (*(InstructionData->OpCodes)) { + // + // Single-byte opcodes + // + case 0xE4: + case 0xE6: + case 0xEC: + case 0xEE: + ExitInfo |=3D IOIO_DATA_8; + break; + + // + // Length determined by instruction parsing + // + default: + ExitInfo |=3D (InstructionData->DataSize =3D=3D Size16Bits) ? IOIO_DAT= A_16 + : IOIO_DATA_32; + } + + switch (InstructionData->AddrSize) { + case Size16Bits: + ExitInfo |=3D IOIO_ADDR_16; + break; + + case Size32Bits: + ExitInfo |=3D IOIO_ADDR_32; + break; + + case Size64Bits: + ExitInfo |=3D IOIO_ADDR_64; + break; + + default: + break; + } + + if (InstructionData->RepMode !=3D 0) { + ExitInfo |=3D IOIO_REP; + } + + return ExitInfo; +} + +/** + Handle an IOIO event. + + Use the VMGEXIT instruction to handle an IOIO event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +IoioExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 =3D IoioExitInfo (Regs, InstructionData); + if (ExitInfo1 =3D=3D 0) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + Ghcb->SaveArea.Rax =3D 0; + } else { + CopyMem (&Ghcb->SaveArea.Rax, &Regs->Rax, IOIO_DATA_BYTES (ExitInfo1)); + } + GhcbSetRegValid (Ghcb, GhcbRax); + + Status =3D VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, 0); + if (Status !=3D 0) { + return Status; + } + + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + CopyMem (&Regs->Rax, &Ghcb->SaveArea.Rax, IOIO_DATA_BYTES (ExitInfo1)); + } + + return 0; +} =20 /** Handle a #VC exception. @@ -38,6 +561,8 @@ VmgExitHandleVc ( MSR_SEV_ES_GHCB_REGISTER Msr; EFI_SYSTEM_CONTEXT_X64 *Regs; GHCB *Ghcb; + NAE_EXIT NaeExit; + SEV_ES_INSTRUCTION_DATA InstructionData; UINT64 ExitCode, Status; EFI_STATUS VcRet; =20 @@ -54,24 +579,31 @@ VmgExitHandleVc ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_IOIO_PROT: + NaeExit =3D IoioExit; + break; + default: - Status =3D VmgExit (Ghcb, SVM_EXIT_UNSUPPORTED, ExitCode, 0); - if (Status =3D=3D 0) { - Regs->ExceptionData =3D 0; - *ExceptionType =3D GP_EXCEPTION; + NaeExit =3D UnsupportedExit; + } + + InitInstructionData (&InstructionData, Ghcb, Regs); + + Status =3D NaeExit (Ghcb, Regs, &InstructionData); + if (Status =3D=3D 0) { + Regs->Rip +=3D InstructionLength (&InstructionData); + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D Status; + if (Event.Elements.ErrorCodeValid !=3D 0) { + Regs->ExceptionData =3D Event.Elements.ErrorCode; } else { - GHCB_EVENT_INJECTION Event; - - Event.Uint64 =3D Status; - if (Event.Elements.ErrorCodeValid !=3D 0) { - Regs->ExceptionData =3D Event.Elements.ErrorCode; - } else { - Regs->ExceptionData =3D 0; - } - - *ExceptionType =3D Event.Elements.Vector; + Regs->ExceptionData =3D 0; } =20 + *ExceptionType =3D Event.Elements.Vector; + VcRet =3D EFI_PROTOCOL_ERROR; } =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: fltzSCguFjEIQRgIYNgdKn32x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829300; bh=nQ0elLKn/NWZvLP4CTGv6OVUFLhyS0vjnxi5v+kxZRc=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=oeSMxMV+DVc8ZxncitosEB8Y4He1VqEcIFZBPmiGipvSPfACnFhTbLpyMMKVHatKSsU 40VzvwLXacfFQZ+LE/f7pZSbzjfjNT3WWd0MWQ8dqSxP84l4qtgJcMTz17MVVRMY4bANH jRirf0Vdr/zTe7u1lqiW7K6fmafe29Xl6PA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Add support to the #VC exception handler to handle string IO. This requires expanding the IO instruction parsing to recognize string based IO instructions as well as preparing an un-encrypted buffer to be used to transfer (either to or from the guest) the string contents for the IO operation. The SW_EXITINFO2 and SW_SCRATCH fields of the GHCB are set appropriately for the operation. Multiple VMGEXIT invocations may be needed to complete the string IO operation. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 90 ++++++++++++++++--- 1 file changed, 76 insertions(+), 14 deletions(-) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 04e8b8aebf7d..b6ac3552894f 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -397,6 +397,26 @@ IoioExitInfo ( ExitInfo =3D 0; =20 switch (*(InstructionData->OpCodes)) { + // + // INS opcodes + // + case 0x6C: + case 0x6D: + ExitInfo |=3D IOIO_TYPE_INS; + ExitInfo |=3D IOIO_SEG_ES; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + // + // OUTS opcodes + // + case 0x6E: + case 0x6F: + ExitInfo |=3D IOIO_TYPE_OUTS; + ExitInfo |=3D IOIO_SEG_DS; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + // // IN immediate opcodes // @@ -445,6 +465,8 @@ IoioExitInfo ( // // Single-byte opcodes // + case 0x6C: + case 0x6E: case 0xE4: case 0xE6: case 0xEC: @@ -506,30 +528,70 @@ IoioExit ( IN SEV_ES_INSTRUCTION_DATA *InstructionData ) { - UINT64 ExitInfo1, Status; + UINT64 ExitInfo1, ExitInfo2, Status; + BOOLEAN IsString; =20 ExitInfo1 =3D IoioExitInfo (Regs, InstructionData); if (ExitInfo1 =3D=3D 0) { return UnsupportedExit (Ghcb, Regs, InstructionData); } =20 - if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { - Ghcb->SaveArea.Rax =3D 0; + IsString =3D ((ExitInfo1 & IOIO_TYPE_STR) !=3D 0) ? TRUE : FALSE; + if (IsString) { + UINTN IoBytes, VmgExitBytes; + UINTN GhcbCount, OpCount; + + Status =3D 0; + + IoBytes =3D IOIO_DATA_BYTES (ExitInfo1); + GhcbCount =3D sizeof (Ghcb->SharedBuffer) / IoBytes; + + OpCount =3D ((ExitInfo1 & IOIO_REP) !=3D 0) ? Regs->Rcx : 1; + while (OpCount) { + ExitInfo2 =3D MIN (OpCount, GhcbCount); + VmgExitBytes =3D ExitInfo2 * IoBytes; + + if ((ExitInfo1 & IOIO_TYPE_IN) =3D=3D 0) { + CopyMem (Ghcb->SharedBuffer, (VOID *) Regs->Rsi, VmgExitBytes); + Regs->Rsi +=3D VmgExitBytes; + } + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + CopyMem ((VOID *) Regs->Rdi, Ghcb->SharedBuffer, VmgExitBytes); + Regs->Rdi +=3D VmgExitBytes; + } + + if ((ExitInfo1 & IOIO_REP) !=3D 0) { + Regs->Rcx -=3D ExitInfo2; + } + + OpCount -=3D ExitInfo2; + } } else { - CopyMem (&Ghcb->SaveArea.Rax, &Regs->Rax, IOIO_DATA_BYTES (ExitInfo1)); - } - GhcbSetRegValid (Ghcb, GhcbRax); + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + Ghcb->SaveArea.Rax =3D 0; + } else { + CopyMem (&Ghcb->SaveArea.Rax, &Regs->Rax, IOIO_DATA_BYTES (ExitInfo1= )); + } + GhcbSetRegValid (Ghcb, GhcbRax); =20 - Status =3D VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, 0); - if (Status !=3D 0) { - return Status; - } + Status =3D VmgExit (Ghcb, SVM_EXIT_IOIO_PROT, ExitInfo1, 0); + if (Status !=3D 0) { + return Status; + } =20 - if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { - if (!GhcbIsRegValid (Ghcb, GhcbRax)) { - return UnsupportedExit (Ghcb, Regs, InstructionData); + if ((ExitInfo1 & IOIO_TYPE_IN) !=3D 0) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + CopyMem (&Regs->Rax, &Ghcb->SaveArea.Rax, IOIO_DATA_BYTES (ExitInfo1= )); } - CopyMem (&Regs->Rax, &Ghcb->SaveArea.Rax, IOIO_DATA_BYTES (ExitInfo1)); } =20 return 0; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: ISnG9W7cPkgJ8AAthNtfD1fox1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829307; bh=mXF3A+rIZ3SXh5nad2KUAE620D67lczc1T6xeZ6zwc4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=MQ0Rl0VVZXWEMpG8jwZqHH1XsGRLhV5UWjWpiMdpr8P7zLqVzNlP28Ypa7/uT7y3x01 TNvnjZ0bCy5KtBGKgPBVVh/v/2y0dtwAtv4jscIc2ETfIfF+mMIYZP1GlydgBPzhwR+ah dDA8w3K++ynhPLkkB31jDWWM9lzhAlz2MsQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d (CPUID_EXTENDED_STATE) requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index b6ac3552894f..1c9c272a250e 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -11,6 +11,7 @@ #include #include #include +#include #include =20 // @@ -597,6 +598,61 @@ IoioExit ( return 0; } =20 +/** + Handle a CPUID event. + + Use the VMGEXIT instruction to handle a CPUID event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +CpuidExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax =3D=3D CPUID_EXTENDED_STATE) { + IA32_CR4 Cr4; + + Cr4.UintN =3D AsmReadCr4 (); + Ghcb->SaveArea.XCr0 =3D (Cr4.Bits.OSXSAVE =3D=3D 1) ? AsmXGetBv (0) : = 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status =3D VmgExit (Ghcb, SVM_EXIT_CPUID, 0, 0); + if (Status !=3D 0) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rbx =3D Ghcb->SaveArea.Rbx; + Regs->Rcx =3D Ghcb->SaveArea.Rcx; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + /** Handle a #VC exception. =20 @@ -641,6 +697,10 @@ VmgExitHandleVc ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_CPUID: + NaeExit =3D CpuidExit; + break; + case SVM_EXIT_IOIO_PROT: NaeExit =3D IoioExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 84R2oJ0uXSYmzcmlNR5M0F8Zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829317; bh=yf+92cJXdJX0XtwEnheXe7QwKEP5GX30dFQOXBhVU9g=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=jEFgFXeoISUeMf+MFCu/q9v5ZWWaHgRY+3DgR6RbKgo+7DT4vYdkPik6y0GzanEIHRe Lmrq7TVzRBUAXENbA1x2dPUXeGZ8embFqv7addD24dRG88mzFf3xeCUqcPIC3wukWH2KO ZR15S1DSyF2wJjyzmu5ugMg+GkYUBNUuBkc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support an MSR_PROT NAE event. Parse the instruction that generated the #VC exception to determine whether it is RDMSR or WRMSR, setting the required register register values in the GHCB and creating the proper SW_EXIT_INFO1 value in the GHCB. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 1c9c272a250e..dbedd4e9f95d 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -374,6 +374,67 @@ UnsupportedExit ( return Status; } =20 +/** + Handle an MSR event. + + Use the VMGEXIT instruction to handle either a RDMSR or WRMSR event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +MsrExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 =3D 0; + + switch (*(InstructionData->OpCodes + 1)) { + case 0x30: // WRMSR + ExitInfo1 =3D 1; + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rdx =3D Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + // + // fall through + // + case 0x32: // RDMSR + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + break; + default: + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + Status =3D VmgExit (Ghcb, SVM_EXIT_MSR, ExitInfo1, 0); + if (Status !=3D 0) { + return Status; + } + + if (ExitInfo1 =3D=3D 0) { + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + } + + return 0; +} + /** Build the IOIO event information. =20 @@ -705,6 +766,10 @@ VmgExitHandleVc ( NaeExit =3D IoioExit; break; =20 + case SVM_EXIT_MSR: + NaeExit =3D MsrExit; + break; + default: NaeExit =3D UnsupportedExit; } --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: rFDtjBkP90LPrLFa6FHHXfxxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829324; bh=Iqjn5RttyJ/xkud3HzJWZzCJGiIfgpwiauV5CfTkuSI=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=PLBDBnCywWOlSJZ4XTwf/oEBNfNxRUVdLOn8dvi9hCebIJEeQ5asnoU09eRXqKqVkE7 QlRG4faKSqsswL7QggzmUarwzvJVrxQKxLhxqjq09mGnA1d4JYgLyncRu0whSgjV3LROJ 3xtgf8tJbCQ1WgpgafHEhOFbEyv7gzyRsGE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a NPF intercept for an NPT entry with a reserved bit set generates a #VC exception. This condition is assumed to be an MMIO access. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a NPF NAE event for MMIO. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXIT_INFO1, SW_EXITINFO2 and SW_SCRATCH values in the GHCB. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 486 ++++++++++++++++++ 1 file changed, 486 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index dbedd4e9f95d..0e502ac14819 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -183,6 +183,281 @@ GhcbSetRegValid ( Ghcb->SaveArea.ValidBitmap[RegIndex] |=3D (1 << RegBit); } =20 +/** + Return a pointer to the contents of the specified register. + + Based upon the input register, return a pointer to the registers contents + in the x86 processor context. + + @param[in] Regs x64 processor context + @param[in] Register Register to obtain pointer for + + @return Pointer to the contents of the requested register + +**/ +STATIC +UINT64 * +GetRegisterPointer ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN UINT8 Register + ) +{ + UINT64 *Reg; + + switch (Register) { + case 0: + Reg =3D &Regs->Rax; + break; + case 1: + Reg =3D &Regs->Rcx; + break; + case 2: + Reg =3D &Regs->Rdx; + break; + case 3: + Reg =3D &Regs->Rbx; + break; + case 4: + Reg =3D &Regs->Rsp; + break; + case 5: + Reg =3D &Regs->Rbp; + break; + case 6: + Reg =3D &Regs->Rsi; + break; + case 7: + Reg =3D &Regs->Rdi; + break; + case 8: + Reg =3D &Regs->R8; + break; + case 9: + Reg =3D &Regs->R9; + break; + case 10: + Reg =3D &Regs->R10; + break; + case 11: + Reg =3D &Regs->R11; + break; + case 12: + Reg =3D &Regs->R12; + break; + case 13: + Reg =3D &Regs->R13; + break; + case 14: + Reg =3D &Regs->R14; + break; + case 15: + Reg =3D &Regs->R15; + break; + default: + Reg =3D NULL; + } + ASSERT (Reg !=3D NULL); + + return Reg; +} + +/** + Update the instruction parsing context for displacement bytes. + + @param[in, out] InstructionData Instruction parsing context + @param[in] Size The instruction displacement size + +**/ +STATIC +VOID +UpdateForDisplacement ( + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData, + IN UINTN Size + ) +{ + InstructionData->DisplacementSize =3D Size; + InstructionData->Immediate +=3D Size; + InstructionData->End +=3D Size; +} + +/** + Determine if an instruction address if RIP relative. + + Examine the instruction parsing context to determine if the address offs= et + is relative to the instruction pointer. + + @param[in] InstructionData Instruction parsing context + + @retval TRUE Instruction addressing is RIP relative + @retval FALSE Instruction addressing is not RIP relative + +**/ +STATIC +BOOLEAN +IsRipRelative ( + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + + Ext =3D &InstructionData->Ext; + + return ((InstructionData->Mode =3D=3D LongMode64Bit) && + (Ext->ModRm.Mod =3D=3D 0) && + (Ext->ModRm.Rm =3D=3D 5) && + (InstructionData->SibPresent =3D=3D FALSE)); +} + +/** + Return the effective address of a memory operand. + + Examine the instruction parsing context to obtain the effective memory + address of a memory operand. + + @param[in] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @return The memory operand effective address + +**/ +STATIC +UINT64 +GetEffectiveMemoryAddress ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + UINT64 EffectiveAddress; + + Ext =3D &InstructionData->Ext; + EffectiveAddress =3D 0; + + if (IsRipRelative (InstructionData)) { + // + // RIP-relative displacement is a 32-bit signed value + // + INT32 RipRelative; + + RipRelative =3D *(INT32 *) InstructionData->Displacement; + + UpdateForDisplacement (InstructionData, 4); + + // + // Negative displacement is handled by standard UINT64 wrap-around. + // + return Regs->Rip + (UINT64) RipRelative; + } + + switch (Ext->ModRm.Mod) { + case 1: + UpdateForDisplacement (InstructionData, 1); + EffectiveAddress +=3D (UINT64) (*(INT8 *) (InstructionData->Displaceme= nt)); + break; + case 2: + switch (InstructionData->AddrSize) { + case Size16Bits: + UpdateForDisplacement (InstructionData, 2); + EffectiveAddress +=3D (UINT64) (*(INT16 *) (InstructionData->Displac= ement)); + break; + default: + UpdateForDisplacement (InstructionData, 4); + EffectiveAddress +=3D (UINT64) (*(INT32 *) (InstructionData->Displac= ement)); + break; + } + break; + } + + if (InstructionData->SibPresent) { + INT64 Displacement; + + if (Ext->Sib.Index !=3D 4) { + CopyMem ( + &Displacement, + GetRegisterPointer (Regs, Ext->Sib.Index), + sizeof (Displacement) + ); + Displacement *=3D (INT64)(1 << Ext->Sib.Scale); + + // + // Negative displacement is handled by standard UINT64 wrap-around. + // + EffectiveAddress +=3D (UINT64) Displacement; + } + + if ((Ext->Sib.Base !=3D 5) || Ext->ModRm.Mod) { + EffectiveAddress +=3D *GetRegisterPointer (Regs, Ext->Sib.Base); + } else { + UpdateForDisplacement (InstructionData, 4); + EffectiveAddress +=3D (UINT64) (*(INT32 *) (InstructionData->Displac= ement)); + } + } else { + EffectiveAddress +=3D *GetRegisterPointer (Regs, Ext->ModRm.Rm); + } + + return EffectiveAddress; +} + +/** + Decode a ModRM byte. + + Examine the instruction parsing context to decode a ModRM byte and the S= IB + byte, if present. + + @param[in] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + +**/ +STATIC +VOID +DecodeModRm ( + IN EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + INSTRUCTION_REX_PREFIX *RexPrefix; + INSTRUCTION_MODRM *ModRm; + INSTRUCTION_SIB *Sib; + + RexPrefix =3D &InstructionData->RexPrefix; + Ext =3D &InstructionData->Ext; + ModRm =3D &InstructionData->ModRm; + Sib =3D &InstructionData->Sib; + + InstructionData->ModRmPresent =3D TRUE; + ModRm->Uint8 =3D *(InstructionData->End); + + InstructionData->Displacement++; + InstructionData->Immediate++; + InstructionData->End++; + + Ext->ModRm.Mod =3D ModRm->Bits.Mod; + Ext->ModRm.Reg =3D (RexPrefix->Bits.BitR << 3) | ModRm->Bits.Reg; + Ext->ModRm.Rm =3D (RexPrefix->Bits.BitB << 3) | ModRm->Bits.Rm; + + Ext->RegData =3D *GetRegisterPointer (Regs, Ext->ModRm.Reg); + + if (Ext->ModRm.Mod =3D=3D 3) { + Ext->RmData =3D *GetRegisterPointer (Regs, Ext->ModRm.Rm); + } else { + if (ModRm->Bits.Rm =3D=3D 4) { + InstructionData->SibPresent =3D TRUE; + Sib->Uint8 =3D *(InstructionData->End); + + InstructionData->Displacement++; + InstructionData->Immediate++; + InstructionData->End++; + + Ext->Sib.Scale =3D Sib->Bits.Scale; + Ext->Sib.Index =3D (RexPrefix->Bits.BitX << 3) | Sib->Bits.Index; + Ext->Sib.Base =3D (RexPrefix->Bits.BitB << 3) | Sib->Bits.Base; + } + + Ext->RmData =3D GetEffectiveMemoryAddress (Regs, InstructionData); + } +} + /** Decode instruction prefixes. =20 @@ -374,6 +649,213 @@ UnsupportedExit ( return Status; } =20 +/** + Handle an MMIO event. + + Use the VMGEXIT instruction to handle either an MMIO read or an MMIO wri= te. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in, out] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +MmioExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN OUT SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, ExitInfo2, Status; + UINTN Bytes; + UINT64 *Register; + UINT8 OpCode, SignByte; + + Bytes =3D 0; + + OpCode =3D *(InstructionData->OpCodes); + if (OpCode =3D=3D TWO_BYTE_OPCODE_ESCAPE) { + OpCode =3D *(InstructionData->OpCodes + 1); + } + + switch (OpCode) { + // + // MMIO write (MOV reg/memX, regX) + // + case 0x88: + Bytes =3D 1; + // + // fall through + // + case 0x89: + DecodeModRm (Regs, InstructionData); + Bytes =3D ((Bytes !=3D 0) ? Bytes : + (InstructionData->DataSize =3D=3D Size16Bits) ? 2 : + (InstructionData->DataSize =3D=3D Size32Bits) ? 4 : + (InstructionData->DataSize =3D=3D Size64Bits) ? 8 : + 0); + + if (InstructionData->Ext.ModRm.Mod =3D=3D 3) { + // + // NPF on two register operands??? + // + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + CopyMem (Ghcb->SharedBuffer, &InstructionData->Ext.RegData, Bytes); + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + break; + + // + // MMIO write (MOV reg/memX, immX) + // + case 0xC6: + Bytes =3D 1; + // + // fall through + // + case 0xC7: + DecodeModRm (Regs, InstructionData); + Bytes =3D ((Bytes !=3D 0) ? Bytes : + (InstructionData->DataSize =3D=3D Size16Bits) ? 2 : + (InstructionData->DataSize =3D=3D Size32Bits) ? 4 : + 0); + + InstructionData->ImmediateSize =3D Bytes; + InstructionData->End +=3D Bytes; + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + CopyMem (Ghcb->SharedBuffer, InstructionData->Immediate, Bytes); + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + break; + + // + // MMIO read (MOV regX, reg/memX) + // + case 0x8A: + Bytes =3D 1; + // + // fall through + // + case 0x8B: + DecodeModRm (Regs, InstructionData); + Bytes =3D ((Bytes !=3D 0) ? Bytes : + (InstructionData->DataSize =3D=3D Size16Bits) ? 2 : + (InstructionData->DataSize =3D=3D Size32Bits) ? 4 : + (InstructionData->DataSize =3D=3D Size64Bits) ? 8 : + 0); + if (InstructionData->Ext.ModRm.Mod =3D=3D 3) { + // + // NPF on two register operands??? + // + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + + Register =3D GetRegisterPointer (Regs, InstructionData->Ext.ModRm.Reg); + if (Bytes =3D=3D 4) { + // + // Zero-extend for 32-bit operation + // + *Register =3D 0; + } + CopyMem (Register, Ghcb->SharedBuffer, Bytes); + break; + + // + // MMIO read w/ zero-extension ((MOVZX regX, reg/memX) + // + case 0xB6: + Bytes =3D 1; + // + // fall through + // + case 0xB7: + Bytes =3D (Bytes !=3D 0) ? Bytes : 2; + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + + Register =3D GetRegisterPointer (Regs, InstructionData->Ext.ModRm.Reg); + SetMem (Register, InstructionData->DataSize, 0); + CopyMem (Register, Ghcb->SharedBuffer, Bytes); + break; + + // + // MMIO read w/ sign-extension (MOVSX regX, reg/memX) + // + case 0xBE: + Bytes =3D 1; + // + // fall through + // + case 0xBF: + Bytes =3D (Bytes !=3D 0) ? Bytes : 2; + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SVM_EXIT_MMIO_READ, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + + if (Bytes =3D=3D 1) { + UINT8 *Data =3D (UINT8 *) Ghcb->SharedBuffer; + + SignByte =3D ((*Data & BIT7) !=3D 0) ? 0xFF : 0x00; + } else { + UINT16 *Data =3D (UINT16 *) Ghcb->SharedBuffer; + + SignByte =3D ((*Data & BIT15) !=3D 0) ? 0xFF : 0x00; + } + + Register =3D GetRegisterPointer (Regs, InstructionData->Ext.ModRm.Reg); + SetMem (Register, InstructionData->DataSize, SignByte); + CopyMem (Register, Ghcb->SharedBuffer, Bytes); + break; + + default: + Status =3D GP_EXCEPTION; + ASSERT (FALSE); + } + + return Status; +} + /** Handle an MSR event. =20 @@ -770,6 +1252,10 @@ VmgExitHandleVc ( NaeExit =3D MsrExit; break; =20 + case SVM_EXIT_NPF: + NaeExit =3D MmioExit; + break; + default: NaeExit =3D UnsupportedExit; } --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: fUTclR1O3KuUedZtzVnWwmx0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829332; bh=yLheDVmEYwTad2aLi0Z+O2ZVvvtRiyhG4ZHj7pGnz3g=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=HddszZLFEVfW/2yTADcUPeMWt/Am6xb3cU8ocFYnU/yfQ00eKm0LwFcPHGl2VipUS7Y 8m59Yq8om1qBpztIY4JeNWpPySDi2DlieqqwXK3zWClH1bnJJtSp+eNMgOiO9WYSujkyS RNSkCnNq0gaGAFjDVTbHAibOKz2dRPW2Vos= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a WBINVD intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 0e502ac14819..bf07f960e380 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -856,6 +856,31 @@ MmioExit ( return Status; } =20 +/** + Handle a WBINVD event. + + Use the VMGEXIT instruction to handle a WBINVD event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +WbinvdExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return VmgExit (Ghcb, SVM_EXIT_WBINVD, 0, 0); +} + /** Handle an MSR event. =20 @@ -1252,6 +1277,10 @@ VmgExitHandleVc ( NaeExit =3D MsrExit; break; =20 + case SVM_EXIT_WBINVD: + NaeExit =3D WbinvdExit; + break; + case SVM_EXIT_NPF: NaeExit =3D MmioExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: bk4mNbOkVgfmHWAf54Dw7pTUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829340; bh=hea+BIHJ0tIHZ6XrrH69ImZtA14oEm1NN8yqDFooB7Q=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=aZwyo9Ww1suzSgQ8WTBj7Rh35BYfdLGz4D5wgzHfTQ0q1eI4zMDq5S68T0PzDJJZWb5 i4xwfOZu4sABZsGeRn+no7ufqXzM0Nxx84lQ4VPgqTD65f7BBdwEv+tfRpfcV/Evov1Ge 9QbLzaH5eqq6+6CKKs3masWGq+QbbBxfgNI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index bf07f960e380..65af57046063 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -1221,6 +1221,45 @@ CpuidExit ( return 0; } =20 +/** + Handle a RDTSC event. + + Use the VMGEXIT instruction to handle a RDTSC event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +RdtscExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SVM_EXIT_RDTSC, 0, 0); + if (Status !=3D 0) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + /** Handle a #VC exception. =20 @@ -1265,6 +1304,10 @@ VmgExitHandleVc ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_RDTSC: + NaeExit =3D RdtscExit; + break; + case SVM_EXIT_CPUID: NaeExit =3D CpuidExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: lDYfzwbZTUi9bBkSEHL5srosx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829348; bh=4w0rZipRZB3yKPXx0+1AfnVHHVdZpswMiqXfUrmi/nk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=nWfkSbI3LVwgfFThGN3Aqn4Qum8Ike1NaQFiZRoGg3g6Lksxk8vVs61uOIDyzaxcLiC mj6bBii2I6IfM5eD6hyRYWMPQXWZJxlQvzPJX71QwW8I2daFASbmBr7rvaNoxbiWdu+71 mgW2i4wBS5Fy2PlycfpDFo7p+X+67IEzzBs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDPMC intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 65af57046063..b19bd3ee8906 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -1221,6 +1221,48 @@ CpuidExit ( return 0; } =20 +/** + Handle a RDPMC event. + + Use the VMGEXIT instruction to handle a RDPMC event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +RdpmcExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + + Status =3D VmgExit (Ghcb, SVM_EXIT_RDPMC, 0, 0); + if (Status !=3D 0) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + /** Handle a RDTSC event. =20 @@ -1308,6 +1350,10 @@ VmgExitHandleVc ( NaeExit =3D RdtscExit; break; =20 + case SVM_EXIT_RDPMC: + NaeExit =3D RdpmcExit; + break; + case SVM_EXIT_CPUID: NaeExit =3D CpuidExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: E5vqSy5KvB6vJXFnJgsgzB5Bx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829357; bh=XnV06cCKiitkYlzePtlIxV8REMYo0lQS5zZM4AGZVlU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=IcQjeGQiIhY9RnHEdaZxt35ZAyciT6bHn/ONNZO3sXmeLzX8XdI8k1uvLMgRAVO4op5 hR24IUhJBo8oV2TPpa3TeVZDYYhWuPZNuupfPOXQUxtRaf4ImJtOITs0BeyrVXIMmwXvs gcGgn25PK9QoDqH/ZKs7KccJ78Rbfn7tKCQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a INVD intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index b19bd3ee8906..af5264095b98 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -1166,6 +1166,31 @@ IoioExit ( return 0; } =20 +/** + Handle a INVD event. + + Use the VMGEXIT instruction to handle a INVD event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +InvdExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return VmgExit (Ghcb, SVM_EXIT_INVD, 0, 0); +} + /** Handle a CPUID event. =20 @@ -1358,6 +1383,10 @@ VmgExitHandleVc ( NaeExit =3D CpuidExit; break; =20 + case SVM_EXIT_INVD: + NaeExit =3D InvdExit; + break; + case SVM_EXIT_IOIO_PROT: NaeExit =3D IoioExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 7hryzQEYGxbZtZjqg2RWvC5bx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829364; bh=5vNQMNgQivwAAgwqqrCjOYIlPep/1vEXYa3dtaBPXas=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=FUsX/ZuenGbksfnAwpfKX1kD2WU7u47SVkp3qeTEaPh4E4ABvIserOspqmUPRaLNFju nKCN5iCQZ25Rp9XrJoYrOo+V+i+GbVUjRmK6NKholtxRNNyEFpHrErvHNzSZng83e+Qmx u5q3l0N7gSTEEr90kmuttTKU8tw7CmgHh0c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index af5264095b98..54134f37e614 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -881,6 +881,50 @@ WbinvdExit ( return VmgExit (Ghcb, SVM_EXIT_WBINVD, 0, 0); } =20 +/** + Handle a VMMCALL event. + + Use the VMGEXIT instruction to handle a VMMCALL event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +VmmCallExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Cpl =3D (UINT8) (Regs->Cs & 0x3); + GhcbSetRegValid (Ghcb, GhcbCpl); + + Status =3D VmgExit (Ghcb, SVM_EXIT_VMMCALL, 0, 0); + if (Status !=3D 0) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + + return 0; +} + /** Handle an MSR event. =20 @@ -1395,6 +1439,10 @@ VmgExitHandleVc ( NaeExit =3D MsrExit; break; =20 + case SVM_EXIT_VMMCALL: + NaeExit =3D VmmCallExit; + break; + case SVM_EXIT_WBINVD: NaeExit =3D WbinvdExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: J27b4VH85jkzgG2asTsb1zmJx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829375; bh=WK7ggEZdvfjJCIniFvFLVXFMXkwo7ld+lgdbSug3VSA=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=JbauPj/ASsRqGDxsVHb18sU3a6EZ3gNeVwtru2LVTAfm6NpQe2HcJ7pv90oHN9SYfEa 5GMigmHKjBZ6LtU5Lmbg82Q/fZHspXehKy7MJq0cstgD3tzz0KF2bjtq2jV0sMTH+EvLH vOkMpDXAFVhNTCj2HT1JHujpehrh824ZdEI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDTSCP intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index 54134f37e614..a1cf792d4d0b 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -881,6 +881,49 @@ WbinvdExit ( return VmgExit (Ghcb, SVM_EXIT_WBINVD, 0, 0); } =20 +/** + Handle a RDTSCP event. + + Use the VMGEXIT instruction to handle a RDTSCP event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +RdtscpExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Status =3D VmgExit (Ghcb, SVM_EXIT_RDTSCP, 0, 0); + if (Status !=3D 0) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rcx =3D Ghcb->SaveArea.Rcx; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + /** Handle a VMMCALL event. =20 @@ -1443,6 +1486,10 @@ VmgExitHandleVc ( NaeExit =3D VmmCallExit; break; =20 + case SVM_EXIT_RDTSCP: + NaeExit =3D RdtscpExit; + break; + case SVM_EXIT_WBINVD: NaeExit =3D WbinvdExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Aznmh1Sdas48tkUnuFd3rLo4x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829381; bh=gGXX2UwKOkr0vQnirUmGqEPjbsdT9DFG/QKV8Mkw6w0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=fLBQN31M0Jd0XmBSEWizDsfdL3UTS5R+l6YvoliUtR3fq0xhj88Z5scUJhuHI02iwJr Bie7c3it9tQAOwraBgfR35FgEYtod6xiGltNMojHm1qF1NQJHMRzfm2bR/u+ttKCuuPTz a/v4zjpKt55e+ajTSdUAhAEsp/SNDXNYQiA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MONITOR/MONITORX intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 38 +++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index a1cf792d4d0b..fe08b1e0ff49 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -856,6 +856,40 @@ MmioExit ( return Status; } =20 +/** + Handle a MONITOR event. + + Use the VMGEXIT instruction to handle a MONITOR event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +MonitorExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; // Identity mapped, so VA =3D PA + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + Ghcb->SaveArea.Rdx =3D Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + + return VmgExit (Ghcb, SVM_EXIT_MONITOR, 0, 0); +} + /** Handle a WBINVD event. =20 @@ -1494,6 +1528,10 @@ VmgExitHandleVc ( NaeExit =3D WbinvdExit; break; =20 + case SVM_EXIT_MONITOR: + NaeExit =3D MonitorExit; + break; + case SVM_EXIT_NPF: NaeExit =3D MmioExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: KYoqyceTZAs8let3JkZpMVO0x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829389; bh=9W7Njdg6JXTv+ZDDNjGGpX45bJpQyuAnNDpL/nGl81Q=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=L+jhbU5WDeOow+Zxii7x57YAYi31lcluYAXELBHHqNPv+1w1XmYL5H0WauCRe2kqSVK 8wnPJfEburejg+BjC9FZ0s7Hez1dVa0wGazm4sl/Wghd+e6AmPwrkRjFiooAMtsJ/AcQf Ul1ppVcq/o68VJI6+i2B71osUw8PblrAxiU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MWAIT/MWAITX intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index fe08b1e0ff49..e70e0ef82f68 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -856,6 +856,38 @@ MmioExit ( return Status; } =20 +/** + Handle a MWAIT event. + + Use the VMGEXIT instruction to handle a MWAIT event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +MwaitExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + + return VmgExit (Ghcb, SVM_EXIT_MWAIT, 0, 0); +} + /** Handle a MONITOR event. =20 @@ -1532,6 +1564,10 @@ VmgExitHandleVc ( NaeExit =3D MonitorExit; break; =20 + case SVM_EXIT_MWAIT: + NaeExit =3D MwaitExit; + break; + case SVM_EXIT_NPF: NaeExit =3D MmioExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 7j8BMFw4srCLUR4Wf6mUEUHWx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829397; bh=KdhhZ1vvtNywxyjKf7bD7p9Ujo1hPEP5cnJWDw3yaY4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=rfxvMtf1Od3q7o53njOafVSArx4e+2EANJ6Ppzr7dnZou+U3C8smx7sWwj9/B2GZ3C7 pfTH80pJftZVGfOSqMzXzKN0Hh1OyUin8e+xI555CCUr2j7+RAe6YPJQODmXy+fM0Q7NF M5wZ9fcpPVdVUWHqfw1V8CT6Uu5YPfQ/Cno= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a DR7 read or write intercept generates a #VC exception. The #VC handler must provide special support to the guest for this. On a DR7 write, the #VC handler must cache the value and issue a VMGEXIT to notify the hypervisor of the write. However, the #VC handler must not actually set the value of the DR7 register. On a DR7 read, the #VC handler must return the cached value of the DR7 register to the guest. VMGEXIT is not invoked for a DR7 register read. The caching of the DR7 values will make use of the per-CPU data pages that are allocated along with the GHCB pages. The per-CPU page for a vCPU is the page that immediately follows the vCPU's GHCB page. Since each GHCB page is unique for a vCPU, the page that follows becomes unique for that vCPU. The SEC phase will reserves an area of memory for a single GHCB and per-CPU page for use by the BSP. After transitioning to the PEI phase, new GHCB and per-CPU pages are allocated for the BSP and all APs. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c | 114 ++++++++++++++++++ 1 file changed, 114 insertions(+) diff --git a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c b/OvmfPkg/Librar= y/VmgExitLib/VmgExitVcHandler.c index e70e0ef82f68..c57c8c4ba203 100644 --- a/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c +++ b/OvmfPkg/Library/VmgExitLib/VmgExitVcHandler.c @@ -126,6 +126,14 @@ UINT64 SEV_ES_INSTRUCTION_DATA *InstructionData ); =20 +// +// Per-CPU data mapping structure +// +typedef struct { + BOOLEAN Dr7Cached; + UINT64 Dr7; +} SEV_ES_PER_CPU_DATA; + =20 /** Checks the GHCB to determine if the specified register has been marked v= alid. @@ -1480,6 +1488,104 @@ RdtscExit ( return 0; } =20 +/** + Handle a DR7 register write event. + + Use the VMGEXIT instruction to handle a DR7 write event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + @return New exception value to propagate + +**/ +STATIC +UINT64 +Dr7WriteExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + SEV_ES_PER_CPU_DATA *SevEsData; + UINT64 *Register; + UINT64 Status; + + Ext =3D &InstructionData->Ext; + SevEsData =3D (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + + DecodeModRm (Regs, InstructionData); + + // + // MOV DRn always treats MOD =3D=3D 3 no matter how encoded + // + Register =3D GetRegisterPointer (Regs, Ext->ModRm.Rm); + + // + // Using a value of 0 for ExitInfo1 means RAX holds the value + // + Ghcb->SaveArea.Rax =3D *Register; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status =3D VmgExit (Ghcb, SVM_EXIT_DR7_WRITE, 0, 0); + if (Status !=3D 0) { + return Status; + } + + SevEsData->Dr7 =3D *Register; + SevEsData->Dr7Cached =3D TRUE; + + return 0; +} + +/** + Handle a DR7 register read event. + + Use the VMGEXIT instruction to handle a DR7 read event. + + @param[in, out] Ghcb Pointer to the Guest-Hypervisor Communi= cation + Block + @param[in, out] Regs x64 processor context + @param[in] InstructionData Instruction parsing context + + @retval 0 Event handled successfully + +**/ +STATIC +UINT64 +Dr7ReadExit ( + IN OUT GHCB *Ghcb, + IN OUT EFI_SYSTEM_CONTEXT_X64 *Regs, + IN SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext; + SEV_ES_PER_CPU_DATA *SevEsData; + UINT64 *Register; + + Ext =3D &InstructionData->Ext; + SevEsData =3D (SEV_ES_PER_CPU_DATA *) (Ghcb + 1); + + DecodeModRm (Regs, InstructionData); + + // + // MOV DRn always treats MOD =3D=3D 3 no matter how encoded + // + Register =3D GetRegisterPointer (Regs, Ext->ModRm.Rm); + + // + // If there is a cached valued for DR7, return that. Otherwise return the + // DR7 standard reset value of 0x400 (no debug breakpoints set). + // + *Register =3D (SevEsData->Dr7Cached) ? SevEsData->Dr7 : 0x400; + + return 0; +} + /** Handle a #VC exception. =20 @@ -1524,6 +1630,14 @@ VmgExitHandleVc ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SVM_EXIT_DR7_READ: + NaeExit =3D Dr7ReadExit; + break; + + case SVM_EXIT_DR7_WRITE: + NaeExit =3D Dr7WriteExit; + break; + case SVM_EXIT_RDTSC: NaeExit =3D RdtscExit; break; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Kl3eujr7w2BphbqzQM27zPAHx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829405; bh=iuX20JfpO7+0raLKw8ojoAYwRvUWida3/ZUlGXno+VQ=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=iohiBdNGa2ZxARbc6JBUcySakzbmeGpPr6k8KZjmZv2cfX4y1t973cbqIXP2mj3ErTI oeal6xbhJnIZQfg1uAOEfqU5aJc4rCcdxZrAXvrLlXZlGwWtfSv+z5/lT6AMdBHWSWYD3 47SCHXpkolc22GVQUJSPsJwWcd/8xsBU5fQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Create a function that can be used to determine if the VM is running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Include/Library/MemEncryptSevLib.h | 12 +++ .../MemEncryptSevLibInternal.c | 75 ++++++++++++------- 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index 64dd6977b0f8..a50a0de9c870 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -13,6 +13,18 @@ =20 #include =20 +/** + Returns a boolean to indicate whether SEV-ES is enabled + + @retval TRUE SEV-ES is enabled + @retval FALSE SEV-ES is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevEsIsEnabled ( + VOID + ); + /** Returns a boolean to indicate whether SEV is enabled =20 diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index 96a66e373f11..3301c5c2862f 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -20,19 +20,17 @@ #include =20 STATIC BOOLEAN mSevStatus =3D FALSE; +STATIC BOOLEAN mSevEsStatus =3D FALSE; STATIC BOOLEAN mSevStatusChecked =3D FALSE; =20 /** + Reads and sets the status of SEV features =20 - Returns a boolean to indicate whether SEV is enabled - - @retval TRUE SEV is enabled - @retval FALSE SEV is not enabled **/ STATIC -BOOLEAN +VOID EFIAPI -InternalMemEncryptSevIsEnabled ( +InternalMemEncryptSevStatus ( VOID ) { @@ -56,32 +54,55 @@ InternalMemEncryptSevIsEnabled ( // Msr.Uint32 =3D AsmReadMsr32 (MSR_SEV_STATUS); if (Msr.Bits.SevBit) { - return TRUE; + mSevStatus =3D TRUE; + } + + // + // Check MSR_0xC0010131 Bit 1 (Sev-Es Enabled) + // + if (Msr.Bits.SevEsBit) { + mSevEsStatus =3D TRUE; } } } =20 - return FALSE; -} - -/** - Returns a boolean to indicate whether SEV is enabled - - @retval TRUE SEV is enabled - @retval FALSE SEV is not enabled -**/ -BOOLEAN -EFIAPI -MemEncryptSevIsEnabled ( - VOID - ) -{ - if (mSevStatusChecked) { - return mSevStatus; - } - - mSevStatus =3D InternalMemEncryptSevIsEnabled(); mSevStatusChecked =3D TRUE; +} + +/** + Returns a boolean to indicate whether SEV-ES is enabled + + @retval TRUE SEV-ES is enabled + @retval FALSE SEV-ES is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevEsIsEnabled ( + VOID + ) +{ + if (!mSevStatusChecked) { + InternalMemEncryptSevStatus (); + } + + return mSevEsStatus; +} + +/** + Returns a boolean to indicate whether SEV is enabled + + @retval TRUE SEV is enabled + @retval FALSE SEV is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevIsEnabled ( + VOID + ) +{ + if (!mSevStatusChecked) { + InternalMemEncryptSevStatus (); + } =20 return mSevStatus; } --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: CtpBIzqg2gq23X42aWpgQ3iSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829414; bh=3LJPRAikNdfIzcQiHOU7bajKFjO8YrMHIK2K4cRtmrA=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=F6t1IwwYsj4flofcoAdWGbCgXcQ9Ypr15jRR7FlcBHdi+u2pC1NnBgMxXjkUaXkSXLl Vs/bgWqo8GsC/p8shx1Hwz1woeA0AFvJTD1cZnr8WMEUIORrgMBqw0mjqwrh71ClRW2wu VpKKtqGNbX9F6Sw7YZA0JlEPvyk6WeFzsS8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 When SEV-ES is enabled, then SEV is also enabled. Add support to the SEV initialization function to also check for SEV-ES being enabled, and if enabled, set the SEV-ES enabled PCD (PcdSevEsIsEnabled). Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 3 +++ OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++ OvmfPkg/OvmfPkgX64.dsc | 3 +++ OvmfPkg/PlatformPei/PlatformPei.inf | 1 + OvmfPkg/PlatformPei/AmdSev.c | 26 ++++++++++++++++++++++++++ 5 files changed, 36 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index c57bba1ba197..f84f23f250ef 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -607,6 +607,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 22e930b12b9b..a66abccf8266 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -619,6 +619,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 60be5eae3d2b..2a8975fd3d29 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -617,6 +617,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index ff397b3ee9d7..00feb96c9308 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -103,6 +103,7 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled =20 [FixedPcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index e484f4b311fe..4dc5340caa7a 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -21,6 +21,27 @@ =20 #include "Platform.h" =20 +/** + + Initialize SEV-ES support if running as an SEV-ES guest. + + **/ +STATIC +VOID +AmdSevEsInitialize ( + VOID + ) +{ + RETURN_STATUS PcdStatus; + + if (!MemEncryptSevEsIsEnabled ()) { + return; + } + + PcdStatus =3D PcdSetBoolS (PcdSevEsIsEnabled, TRUE); + ASSERT_RETURN_ERROR (PcdStatus); +} + /** =20 Function checks if SEV support is available, if present then it sets @@ -103,4 +124,9 @@ AmdSevInitialize ( ); } } + + // + // Check and perform SEV-ES initialization if required. + // + AmdSevEsInitialize (); } --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) by CY4PR12MB1798.namprd12.prod.outlook.com (2603:10b6:903:11a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19; Fri, 7 Aug 2020 19:43:40 +0000 X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b]) by CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b%5]) with mapi id 15.20.3239.024; Fri, 7 Aug 2020 19:43:40 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io CC: Brijesh Singh , Ard Biesheuvel , Eric Dong , Jordan Justen , Laszlo Ersek , Liming Gao , Michael D Kinney , Ray Ni Subject: [edk2-devel] [PATCH v14 29/46] OvmfPkg: Create a GHCB page for use during Sec phase Date: Fri, 7 Aug 2020 14:39:14 -0500 Message-ID: <5e2171228c13f2530b59b0ed3a6e6b15cb3c3490.1596829170.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: SN4PR0201CA0036.namprd02.prod.outlook.com (2603:10b6:803:2e::22) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by SN4PR0201CA0036.namprd02.prod.outlook.com (2603:10b6:803:2e::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: pysqdjytZfcMcDmL2OC2PNuZx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829422; bh=k5YwcJZTd1jjCLI/fq3hiSNqBNxWfxxIzVHcz4BY/yk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=T8+eUF3yEOjVNEWFYWz/tanpp+oJiN5gpbZv6cVDMjrtEINzNn5oWLeAgH8jZjSMIpM qbzfEpJB9qU87ZU7sWhG1HkFMyBHQewSO5v5pu2nAF9yucYjWc2CiNgswp6E9O/TEaG09 Ig/xOkhnWu14QqzoQn4rgXhpcKnZY9zbWS4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A GHCB page is needed during the Sec phase, so this new page must be created. Since the #VC exception handler routines assume that a per-CPU variable area is immediately after the GHCB, this per-CPU variable area must also be created. Since the GHCB must be marked as an un-encrypted, or shared, page, an additional pagetable page is required to break down the 2MB region where the GHCB page lives into 4K pagetable entries. Create a new entry in the OVMF memory layout for the new page table page and for the SEC GHCB and per-CPU variable pages. After breaking down the 2MB page, update the GHCB page table entry to remove the encryption mask. The GHCB page will be used by the SEC #VC exception handler. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB in order to perform the requested function. Four new fixed PCDs are needed to support the SEC GHCB page: - PcdOvmfSecGhcbBase UINT32 value that is the base address of the GHCB used during the SEC phase. - PcdOvmfSecGhcbSize UINT32 value that is the size, in bytes, of the GHCB area used during the SEC phase. - PcdOvmfSecGhcbPageTableBase UINT32 value that is address of a page table page used to break down the 2MB page into 512 4K pages. - PcdOvmfSecGhcbPageTableSize UINT32 value that is the size, in bytes, of the page table page. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkg.dec | 9 +++ OvmfPkg/OvmfPkgX64.fdf | 6 ++ OvmfPkg/ResetVector/ResetVector.inf | 5 ++ OvmfPkg/ResetVector/Ia32/PageTables64.asm | 76 +++++++++++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 17 +++++ 5 files changed, 113 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 55bb8ea91a00..6abde4fd9351 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -294,6 +294,15 @@ [PcdsFixedAtBuild] ## Number of page frames to use for storing grant table entries. gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33 =20 + ## Specify the extra page table needed to mark the GHCB as unencrypted. + # The value should be a multiple of 4KB for each. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x3e + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x3f + + ## The base address of the SEC GHCB page used by SEV-ES. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x40 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x41 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index 83ff6aef2e8c..edb03b5464d4 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -76,6 +76,12 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize =20 +0x008000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecGhcbPageTableSize + +0x009000|0x002000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|gUefiOvmfPkgTokenSpaceGuid.P= cdOvmfSecGhcbSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index b0ddfa5832a2..483fd90fe785 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -26,6 +26,7 @@ [Sources] [Packages] OvmfPkg/OvmfPkg.dec MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [BuildOptions] @@ -33,5 +34,9 @@ [BuildOptions] *_*_X64_NASMB_FLAGS =3D -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ =20 [Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index abad009f20f5..9f86ddf6f08f 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -21,6 +21,11 @@ BITS 32 %define PAGE_2M_MBO 0x080 %define PAGE_2M_PAT 0x01000 =20 +%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \ + PAGE_DIRTY + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ @@ -75,6 +80,37 @@ NoSev: SevExit: OneTimeCallRet CheckSevFeature =20 +; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feat= ure +; is enabled. +; +; Modified: EAX, EBX, ECX +; +; If SEV-ES is enabled then EAX will be non-zero. +; If SEV-ES is disabled then EAX will be zero. +; +CheckSevEsFeature: + xor eax, eax + + ; SEV-ES can't be enabled if SEV isn't, so first check the encryption + ; mask. + test edx, edx + jz NoSevEs + + ; Save current value of encryption mask + mov ebx, edx + + ; Check if SEV-ES is enabled + ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) + mov ecx, 0xc0010131 + rdmsr + and eax, 2 + + ; Restore encryption mask + mov edx, ebx + +NoSevEs: + OneTimeCallRet CheckSevEsFeature + ; ; Modified: EAX, EBX, ECX, EDX ; @@ -139,6 +175,46 @@ pageTableEntriesLoop: mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop =20 + OneTimeCall CheckSevEsFeature + test eax, eax + jz SetCr3 + + ; + ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted. + ; This requires the 2MB page for this range be broken down into 512 4KB + ; pages. All will be marked encrypted, except for the GHCB. + ; + mov ecx, (GHCB_BASE >> 21) + mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR + mov [ecx * 8 + PT_ADDR (0x2000)], eax + + ; + ; Page Table Entries (512 * 4KB entries =3D> 2MB) + ; + mov ecx, 512 +pageTableEntries4kLoop: + mov eax, ecx + dec eax + shl eax, 12 + add eax, GHCB_BASE & 0xFFE0_0000 + add eax, PAGE_4K_PDE_ATTR + mov [ecx * 8 + GHCB_PT_ADDR - 8], eax + mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx + loop pageTableEntries4kLoop + + ; + ; Clear the encryption bit from the GHCB entry + ; + mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12 + mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0 + + mov ecx, GHCB_SIZE / 4 + xor eax, eax +clearGhcbMemoryLoop: + mov dword[ecx * 4 + GHCB_BASE - 4], eax + loop clearGhcbMemoryLoop + +SetCr3: ; ; Set CR3 now that the paging structures are available ; diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 75cfe16654b1..bfb77e439105 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -53,8 +53,25 @@ %error "This implementation inherently depends on PcdOvmfSecPageTables= Size" %endif =20 + %if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) !=3D 0x1000) + %error "This implementation inherently depends on PcdOvmfSecGhcbPageTa= bleSize" + %endif + + %if (FixedPcdGet32 (PcdOvmfSecGhcbSize) !=3D 0x2000) + %error "This implementation inherently depends on PcdOvmfSecGhcbSize" + %endif + + %if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) !=3D \ + ((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhc= bSize) - 1) >> 21)) + %error "This implementation inherently depends on PcdOvmfSecGhcbBase n= ot straddling a 2MB boundary" + %endif + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) %include "Ia32/Flat32ToFlat64.asm" + + %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) + %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) + %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) %include "Ia32/PageTables64.asm" %endif =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 7Oaq1rvm0GgpjfHyxRwUKY70x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829432; bh=OtJ17tEoL8ynXnonXa550Vl61AF2bWpnRcPCd2LVrP4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Rr2moQDoH5ujIFbrcpJwO8gcbUmevXiYJ3sNkHCH4BdSJTUIkCQjP6lfgQiicGmMClB Yq6iZYF1uOC8p67WKw/S/ZMwWHB4J/gSwA0V48E5fcKGJV63hb27t8BI6jBUAVcXUBIlE WHYFX+Mb71alCwYjWq1XRd5/X6c6XlWnwM0= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Protect the memory used by an SEV-ES guest when S3 is supported. This includes the page table used to break down the 2MB page that contains the GHCB so that it can be marked un-encrypted, as well as the GHCB area. Regarding the lifecycle of the GHCB-related memory areas: PcdOvmfSecGhcbPageTableBase PcdOvmfSecGhcbBase (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the GHCB-related areas are initialized during the SEC phase [OvmfPkg/ResetVector/Ia32/PageTables64.asm]. (b) how it is protected from memory allocations during DXE If S3 and SEV-ES are enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with an AcpiNVS memory allocation HOB, in PEI. If S3 is disabled, then these ranges are not protected. DXE's own page tables are first built while still in PEI (see HandOffToDxeCore() [MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c]). Those tables are located in permanent PEI memory. After CR3 is switched over to them (which occurs before jumping to the DXE core entry point), we don't have to preserve PcdOvmfSecGhcbPageTableBase. PEI switches to GHCB pages in permanent PEI memory and DXE will use these PEI GHCB pages, so we don't have to preserve PcdOvmfSecGhcbBase. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Anthony Perard Cc: Julien Grall Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/PlatformPei.inf | 4 ++++ OvmfPkg/PlatformPei/MemDetect.c | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 00feb96c9308..a54d10ba90d5 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -75,6 +75,10 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 3b46ea431ade..6b5fee166b5d 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -27,6 +27,7 @@ Module Name: #include #include #include +#include #include #include #include @@ -866,6 +867,28 @@ InitializeRamRegions ( (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize), EfiACPIMemoryNVS ); + + if (MemEncryptSevEsIsEnabled ()) { + // + // If SEV-ES is enabled, reserve the GHCB-related memory area. This + // includes the extra page table used to break down the 2MB page + // mapping into 4KB page entries where the GHCB resides and the + // GHCB area itself. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableBas= e), + (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableSize), + EfiACPIMemoryNVS + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBase), + (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbSize), + EfiACPIMemoryNVS + ); + } #endif } =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Q840fAQSx0iPvsxsKTEMQIFPx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829440; bh=gSnuQcOEWbUeEweYXvdxfqqU5kK0YEtTHzqU+3EvZAk=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=BwncDODaB0YqwSjKD0eQ3BggOkk0w1Qu/yUtRtnBmS4s7rQLbw/gGxtmNhNJF6h4GTF EShPZD4B+RyIHCHDpM8E6QwvrNG5pANVwdM/t8mV4y/3jrZPXkNOsVl3wDwTFU56+bTQO BIip3OgOF1P4MgnWjcLCtlPQJAFs5krHXbk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Allocate memory for the GHCB pages and the per-CPU variable pages during SEV initialization for use during Pei and Dxe phases. The GHCB page(s) must be shared pages, so clear the encryption mask from the current page table entries. Upon successful allocation, set the GHCB PCDs (PcdGhcbBase and PcdGhcbSize). The per-CPU variable page needs to be unique per AP. Using the page after the GHCB ensures that it is unique per AP. Only the GHCB page is marked as shared, keeping the per-CPU variable page encyrpted. The same logic is used in DXE using CreateIdentityMappingPageTables() before switching to the DXE pagetables. The GHCB pages (one per vCPU) will be used by the PEI and DXE #VC exception handlers. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB associated with the vCPU in order to perform the requested function. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 2 ++ OvmfPkg/OvmfPkgIa32X64.dsc | 2 ++ OvmfPkg/OvmfPkgX64.dsc | 2 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 2 ++ OvmfPkg/PlatformPei/AmdSev.c | 45 ++++++++++++++++++++++++++++- 5 files changed, 52 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index f84f23f250ef..133a9a93c071 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -608,6 +608,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index a66abccf8266..338c38db29b5 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -620,6 +620,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 2a8975fd3d29..b80710fbdca4 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -618,6 +618,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index a54d10ba90d5..4742e1bdf42b 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -102,6 +102,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 4dc5340caa7a..4fd4534cabea 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -10,12 +10,15 @@ // The package level header files this module uses // #include +#include #include #include #include +#include #include #include #include +#include #include #include =20 @@ -32,7 +35,10 @@ AmdSevEsInitialize ( VOID ) { - RETURN_STATUS PcdStatus; + VOID *GhcbBase; + PHYSICAL_ADDRESS GhcbBasePa; + UINTN GhcbPageCount, PageCount; + RETURN_STATUS PcdStatus, DecryptStatus; =20 if (!MemEncryptSevEsIsEnabled ()) { return; @@ -40,6 +46,43 @@ AmdSevEsInitialize ( =20 PcdStatus =3D PcdSetBoolS (PcdSevEsIsEnabled, TRUE); ASSERT_RETURN_ERROR (PcdStatus); + + // + // Allocate GHCB and per-CPU variable pages. + // + GhcbPageCount =3D mMaxCpuCount * 2; + GhcbBase =3D AllocatePages (GhcbPageCount); + ASSERT (GhcbBase !=3D NULL); + + GhcbBasePa =3D (PHYSICAL_ADDRESS)(UINTN) GhcbBase; + + // + // Each vCPU gets two consecutive pages, the first is the GHCB and the + // second is the per-CPU variable page. Loop through the allocation and + // only clear the encryption mask for the GHCB pages. + // + for (PageCount =3D 0; PageCount < GhcbPageCount; PageCount +=3D 2) { + DecryptStatus =3D MemEncryptSevClearPageEncMask ( + 0, + GhcbBasePa + EFI_PAGES_TO_SIZE (PageCount), + 1, + TRUE + ); + ASSERT_RETURN_ERROR (DecryptStatus); + } + + ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount)); + + PcdStatus =3D PcdSet64S (PcdGhcbBase, GhcbBasePa); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount)); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG ((DEBUG_INFO, + "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n", + (UINT64)GhcbPageCount, GhcbBase)); + + AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); } =20 /** --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: whNCUeP0r7KeLNGnHMLBRQAix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829448; bh=3XmHiiWiV6//gFKW+RhYqeeb4i+lpllGNkM4Y/mjU7w=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=RrhOKexYaSA4QwG3UFFSf3uaWZzSAwK7FhRs9dU3OuEJ+l6pBlbumdRlwYiU7uxd/2K SN/d2RFY+7tb+JJ6RhBEivYY0dzdmG7EvnZgjd/UdrqgBmTLj64eXTvWHPh6KM1gaJPX2 9W29FKzLC7Ewk6RQqX0GmD+zOLSr6Yx0T+E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The SEV support will clear the C-bit from non-RAM areas. The early GDT lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT will be read as un-encrypted even though it is encrypted. This will result in a failure to be able to handle the exception. Move the GDT into RAM so it can be accessed without error when running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/AmdSev.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 4fd4534cabea..a2b38c591236 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -39,6 +39,8 @@ AmdSevEsInitialize ( PHYSICAL_ADDRESS GhcbBasePa; UINTN GhcbPageCount, PageCount; RETURN_STATUS PcdStatus, DecryptStatus; + IA32_DESCRIPTOR Gdtr; + VOID *Gdt; =20 if (!MemEncryptSevEsIsEnabled ()) { return; @@ -83,6 +85,22 @@ AmdSevEsInitialize ( (UINT64)GhcbPageCount, GhcbBase)); =20 AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); + + // + // The SEV support will clear the C-bit from non-RAM areas. The early G= DT + // lives in a non-RAM area, so when an exception occurs (like a #VC) the= GDT + // will be read as un-encrypted even though it was created before the C-= bit + // was cleared (encrypted). This will result in a failure to be able to + // handle the exception. + // + AsmReadGdtr (&Gdtr); + + Gdt =3D AllocatePages (EFI_SIZE_TO_PAGES ((UINTN) Gdtr.Limit + 1)); + ASSERT (Gdt !=3D NULL); + + CopyMem (Gdt, (VOID *) Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN) Gdt; + AsmWriteGdtr (&Gdtr); } =20 /** --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63874): https://edk2.groups.io/g/devel/message/63874 Mute This Topic: https://groups.io/mt/76056573/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 22:24:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63875+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63875+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1596829456536584.4082381699388; Fri, 7 Aug 2020 12:44:16 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id YTJVYY1788612xFuFfgu7SZB; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) by CY4PR12MB1798.namprd12.prod.outlook.com (2603:10b6:903:11a::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19; Fri, 7 Aug 2020 19:44:13 +0000 X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b]) by CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b%5]) with mapi id 15.20.3239.024; Fri, 7 Aug 2020 19:44:13 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io CC: Brijesh Singh , Ard Biesheuvel , Eric Dong , Jordan Justen , Laszlo Ersek , Liming Gao , Michael D Kinney , Ray Ni Subject: [edk2-devel] [PATCH v14 33/46] UefiCpuPkg: Create an SEV-ES workarea PCD Date: Fri, 7 Aug 2020 14:39:18 -0500 Message-ID: <26aea09a30e0463b18e54ae9ed900fa70f2d10ea.1596829170.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: SN4PR0201CA0023.namprd02.prod.outlook.com (2603:10b6:803:2b::33) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by SN4PR0201CA0023.namprd02.prod.outlook.com (2603:10b6:803:2b::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.18 via Frontend Transport; Fri, 7 Aug 2020 19:44:13 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 1eaa33f5-0e7f-4964-1d6e-08d83b0a433f X-MS-TrafficTypeDiagnostic: CY4PR12MB1798: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4714; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: szB28nHYovGlmh3e//9UM9alBDk5xn/rVppoHUKnYFbM8S2FFDz44VzgruiMRYV1XdHNrYjt1AP66zEp6Xs6dmtEVA9q8dajHl2x9JsqmLTDlAYc2FUt95oXaPXal1sLN6KKN1F42AC8VCxKXptISIvfDwDwJwANkHY3GY/H/ILxJwI1ZQsRDug64sJu1P/oYqxJX76tiMSZhkgCMRtgTmwiEwk/lPac3/gr6/S/kyngJHKSiVNyMxWpJWMMd1+VUtwqxyb8Tk6JXOe1KVDi70G2n6mzB7wBe+/PAlMBaaYt0vqpEwaQ/AV7g1ERer/4wyDm/0II2VXW/cCKVjKHrdTZxZC2lGsChOMqZQpDbUH1Nl1zAJ1TPtsJT2lpDjbQQzvS7pWi2j76QinG01xeOaB19LUdcNIea4rDEKn5Zxj0SI8SeGpHAq7+FKMRgA/7aZcD/CZ+hKEBxJVi+ZJdyw== X-MS-Exchange-AntiSpam-MessageData: 6XcSgMT/O2jh5ADAFso9davG3YZAUcsd2dGI00JX1+baFlvqNMoPTjMVDk6o4xTpcmAmu2/VrdDWmUSVPLZHzTj/xmn0ie6sZxQNAxqC9aXxbDbEo1rTiCCfeoc8LtB2i9I5NVy7+OczET0vGDQGtCGLI6rZaW1PX8mcieJ1Uf+ZL4cj/UGTLI2vSz05OHTpbr73UtT3NOADf/gBKaNHnScu7t7AsbpMS1KNb3NF95csPJ1kKSuu4rv+22HqKhk1yZ1yADZ7/UrUOoDMdDA2TfUQo/zhjt4LAb2ycCM/fr1oZCOOKq0SEZMEwl68MGG/hiWabklYy0zlpg98Jm/fYVSuLQMOdNnhAUZ+xTSz+wZT8gwvNr0DyIR5byEb2WCKqOlrBI8CdxaGp5+w8z1JYBwnSLs7keQmrj6cbLzFbW9fS2z5We7jpdRcY16+Nu479ntOp44uGOuntv9qEr3Hmj2AqId1JYndHuQPmOEh/OHgYHZWeQnC/XjbMuaNXR6kdYaXtay7krD3Xs8tOrd8NYA2KmDM28q8T5cHlw37Trkf9DmPWQPlPvdjXWemceeCJXy5D9YtICu17bdCgct0qP2zTEBgm+ANvEHGB7AUZf9JmYTsMJ/EAGxa3+0nJ2egy27TmNIhTfHb0yMk4g74qA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1eaa33f5-0e7f-4964-1d6e-08d83b0a433f X-MS-Exchange-CrossTenant-AuthSource: CY4PR12MB1352.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2020 19:44:13.8545 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 2QrL84B8MsXU1/JTtTHpM83h8HtOjMg53OndYWj8pZYr/8eJWYG6aJba1vNUSieJWqMsYuvSAAnMXga+uFcppQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1798 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: OjXX7jA0j3x8hQYb5UHtP8gSx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829456; bh=so0zgsFtlyqD8uybswd6/Jq/6OTP5xLxvSZ03WWh3Jo=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=PA3OVB3S3ApRmVq+C1+JODx5HM3/trza1ODjmtnSrO1m9iZHcHEyWRUG4QxMyw9W7ef cCRkkmQYaqU3UPvmidF3NsIO0FTHYX6nMSJjJgv+Yx4k7z7sVdb3ob7fGBQywdFe3K2Zc rvJc14L9TwS8Vwbw3yMdJIDsO9u5DIQBBxQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Create an SEV-ES workarea PCD. This PCD will be used for BSP communication during SEC and for AP startup during PEI and DXE phases, the latter is the reason for creating it in the UefiCpuPkg. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ UefiCpuPkg/UefiCpuPkg.uni | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 17228cb5a84f..d83c084467b3 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -164,6 +164,14 @@ [PcdsFixedAtBuild] # @Prompt Specify the count of pre allocated SMM MP tokens per chunk. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x3000= 2002 =20 + ## Area of memory where the SEV-ES work area block lives. + # @Prompt Configure the SEV-ES work area base + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005 + + ## Size of teh area of memory where the SEV-ES work area block lives. + # @Prompt Configure the SEV-ES work area base + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is the CPU Local APIC base address, which aligns the addre= ss on a 4-KByte boundary. # @Prompt Configure base address of CPU Local APIC diff --git a/UefiCpuPkg/UefiCpuPkg.uni b/UefiCpuPkg/UefiCpuPkg.uni index f4a0c72f6293..219c1963bf08 100644 --- a/UefiCpuPkg/UefiCpuPkg.uni +++ b/UefiCpuPkg/UefiCpuPkg.uni @@ -281,3 +281,11 @@ =20 #string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsIsEnabled_PROMPT #language = en-US "Specifies whether SEV-ES is enabled" #string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsIsEnabled_HELP #language = en-US "Set to TRUE when running as an SEV-ES guest, FALSE otherwise." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsWorkAreaBase_PROMPT #langua= ge en-US "Specify the address of the SEV-ES work area" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsWorkAreaBase_HELP #langua= ge en-US "Specifies the address of the work area used by an SEV-ES guest." + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsWorkAreaSize_PROMPT #langua= ge en-US "Specify the size of the SEV-ES work area" + +#string STR_gUefiCpuPkgTokenSpaceGuid_PcdSevEsWorkAreaSize_HELP #langua= ge en-US "Specifies the size of the work area used by an SEV-ES guest." --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: r9rDRZuMpC1GyTr2MMttCv2zx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829464; bh=WxkSQ3K7Im17PwWtUmJTMlbSmYtga5sczUL6Bc/mvuU=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=ASELtD/v06H+hy091gtPieEBcXskUpjw9v01pevaaW9HVdwmjrFiZ1y6LB6JH2VQFqx 4LaTUpKVSqb9RaFmM6khc8vQ8+ko/3cuamDcriY/fU6RvbunsX51p+MDHTNy7cxVGKikV qU5J5CyLKoCFgZAz2B39VPgSvutHmy350yo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Reserve a fixed area of memory for SEV-ES use and set a fixed PCD, PcdSevEsWorkAreaBase, to this value. This area will be used by SEV-ES support for two purposes: 1. Communicating the SEV-ES status during BSP boot to SEC: Using a byte of memory from the page, the BSP reset vector code can communicate the SEV-ES status to SEC for use before exception handling can be enabled in SEC. After SEC, this field is no longer valid and the standard way of determine if SEV-ES is active should be used. 2. Establishing an area of memory for AP boot support: A hypervisor is not allowed to update an SEV-ES guest's register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead an SEV-ES AP must be re-directed from within the guest to the actual requested staring location as specified in the INIT-SIPI-SIPI sequence. Use this memory for reset vector code that can be programmed to have the AP jump to the desired RIP location after starting the AP. This is required for only the very first AP reset. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgX64.fdf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index edb03b5464d4..8da59037e5f0 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -82,6 +82,9 @@ [FD.MEMFD] 0x009000|0x002000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|gUefiOvmfPkgTokenSpaceGuid.P= cdOvmfSecGhcbSize =20 +0x00B000|0x001000 +gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|gUefiCpuPkgTokenSpaceGuid.P= cdSevEsWorkAreaSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: kzw2xOHYGmfMavdNmqapfBXDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829473; bh=fQecM+oVZbv7BJlUOnjsK3ywar4iA5i/P76Z331YIOs=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=xQGTZcX1bw/D2Rfklkl8p9F1ztN/RmHcGeGO1nL778q0yPg+JmCQmWprwhQjEX6swFs tZDZc77O7GsZSvihfWdn+fvoztGnTNJ+6PgUfYnWA1LALI/CO/mb0i76n130I+I557J/+ qgrW+ivuM/wRkJM3VravPM9l+EP8/Fh05qY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Protect the SEV-ES work area memory used by an SEV-ES guest. Regarding the lifecycle of the SEV-ES memory area: PcdSevEsWorkArea (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the SEV-ES area is initialized during the SEC phase [OvmfPkg/ResetVector/Ia32/PageTables64.asm]. (b) how it is protected from memory allocations during DXE If SEV-ES is enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with either an AcpiNVS (S3 enabled) or BootServicesData (S3 disabled) memory allocation HOB, in PEI. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Anthony Perard Cc: Julien Grall Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/PlatformPei.inf | 2 ++ OvmfPkg/PlatformPei/MemDetect.c | 20 ++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 4742e1bdf42b..c53be2f4925c 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -118,6 +118,8 @@ [FixedPcd] gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize =20 [FeaturePcd] gUefiOvmfPkgTokenSpaceGuid.PcdCsmEnable diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 6b5fee166b5d..ffbbef891a11 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -940,5 +940,25 @@ InitializeRamRegions ( ); } } + +#ifdef MDE_CPU_X64 + if (MemEncryptSevEsIsEnabled ()) { + // + // If SEV-ES is enabled, reserve the SEV-ES work area. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + // If S3 is unsupported, then various drivers might still write to t= he + // work area. We ought to prevent DXE from serving allocation reques= ts + // such that they would overlap the work area. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN) FixedPcdGet32 (PcdSevEsWorkAreaBase), + (UINT64)(UINTN) FixedPcdGet32 (PcdSevEsWorkAreaSize), + mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData + ); + } +#endif } } --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: K87OKNc8ZKOTu2lPTI2SbV2Ix1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829482; bh=X2alM+OdVfcpSk1yz0qaeySltxYNLvqtSXz/orhoeyQ=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=sj9PVl09ahUP6h02GSSeQVl1tYyTn3JD7OSd2oetzti8PtCA9ybxedIO6acN+9o7fXh 7JRRAkQnASg0Xa0MRKetMyeVqtfxkEZSQfzWf9Sqe6tKITN+2cdT3dbmHc8K9ZdH79tQi Cbmz8JYewirgr81JqrBKmgEDxC+2c4WgTAc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 During BSP startup, the reset vector code will issue a CPUID instruction while in 32-bit mode. When running as an SEV-ES guest, this will trigger a #VC exception. Add exception handling support to the early reset vector code to catch these exceptions. Also, since the guest is in 32-bit mode at this point, writes to the GHCB will be encrypted and thus not able to be read by the hypervisor, so use the GHCB CPUID request/response protocol to obtain the requested CPUID function values and provide these to the guest. The exception handling support is active during the SEV check and uses the OVMF temporary RAM space for a stack. After the SEV check is complete, the exception handling support is removed and the stack pointer cleared. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/ResetVector/ResetVector.inf | 3 + OvmfPkg/ResetVector/Ia32/PageTables64.asm | 275 +++++++++++++++++++++- OvmfPkg/ResetVector/ResetVector.nasmb | 2 + 3 files changed, 277 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index 483fd90fe785..a53ae6c194ae 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -34,9 +34,12 @@ [BuildOptions] *_*_X64_NASMB_FLAGS =3D -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ =20 [Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index 9f86ddf6f08f..7c72128a84d6 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -36,13 +36,58 @@ BITS 32 PAGE_READ_WRITE + \ PAGE_PRESENT) =20 +; +; SEV-ES #VC exception handler support +; +; #VC handler local variable locations +; +%define VC_CPUID_RESULT_EAX 0 +%define VC_CPUID_RESULT_EBX 4 +%define VC_CPUID_RESULT_ECX 8 +%define VC_CPUID_RESULT_EDX 12 +%define VC_GHCB_MSR_EDX 16 +%define VC_GHCB_MSR_EAX 20 +%define VC_CPUID_REQUEST_REGISTER 24 +%define VC_CPUID_FUNCTION 28 + +; #VC handler total local variable size +; +%define VC_VARIABLE_SIZE 32 + +; #VC handler GHCB CPUID request/response protocol values +; +%define GHCB_CPUID_REQUEST 4 +%define GHCB_CPUID_RESPONSE 5 +%define GHCB_CPUID_REGISTER_SHIFT 30 +%define CPUID_INSN_LEN 2 + + ; Check if Secure Encrypted Virtualization (SEV) feature is enabled ; -; If SEV is enabled then EAX will be at least 32 +; Modified: EAX, EBX, ECX, EDX, ESP +; +; If SEV is enabled then EAX will be at least 32. ; If SEV is disabled then EAX will be zero. ; CheckSevFeature: + ; Set the first byte of the workarea to zero to communicate to the SEC + ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID + ; instruction will trigger a #VC exception where the first byte of the + ; workarea will be set to one. + mov byte[SEV_ES_WORK_AREA], 0 + + ; + ; Set up exception handlers to check for SEV-ES + ; Load temporary RAM stack based on PCDs (see SevEsIdtVmmComm for + ; stack usage) + ; Establish exception handlers + ; + mov esp, SEV_ES_VC_TOP_OF_STACK + mov eax, ADDR_OF(Idtr) + lidt [cs:eax] + ; Check if we have a valid (0x8000_001F) CPUID leaf + ; CPUID raises a #VC exception if running as an SEV-ES guest mov eax, 0x80000000 cpuid =20 @@ -53,8 +98,8 @@ CheckSevFeature: jl NoSev =20 ; Check for memory encryption feature: - ; CPUID Fn8000_001F[EAX] - Bit 1 - ; + ; CPUID Fn8000_001F[EAX] - Bit 1 + ; CPUID raises a #VC exception if running as an SEV-ES guest mov eax, 0x8000001f cpuid bt eax, 1 @@ -78,6 +123,15 @@ NoSev: xor eax, eax =20 SevExit: + ; + ; Clear exception handlers and stack + ; + push eax + mov eax, ADDR_OF(IdtrClear) + lidt [cs:eax] + pop eax + mov esp, 0 + OneTimeCallRet CheckSevFeature =20 ; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feat= ure @@ -222,3 +276,218 @@ SetCr3: mov cr3, eax =20 OneTimeCallRet SetCr3ForPageTables64 + +; +; Start of #VC exception handling routines +; + +SevEsIdtNotCpuid: + ; + ; Use VMGEXIT to request termination. + ; 1 - #VC was not for CPUID + ; + mov eax, 1 + jmp SevEsIdtTerminate + +SevEsIdtNoCpuidResponse: + ; + ; Use VMGEXIT to request termination. + ; 2 - GHCB_CPUID_RESPONSE not received + ; + mov eax, 2 + +SevEsIdtTerminate: + ; + ; Use VMGEXIT to request termination. At this point the reason code is + ; located in EAX, so shift it left 16 bits to the proper location. + ; + ; EAX[11:0] =3D> 0x100 - request termination + ; EAX[15:12] =3D> 0x1 - OVMF + ; EAX[23:16] =3D> 0xXX - REASON CODE + ; + shl eax, 16 + or eax, 0x1100 + xor edx, edx + mov ecx, 0xc0010130 + wrmsr + ; + ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-b= it + ; mode, so work around this by temporarily switching to 64-bit mode. + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; We shouldn't come back from the VMGEXIT, but if we do, just loop. + ; +SevEsIdtHlt: + hlt + jmp SevEsIdtHlt + iret + + ; + ; Total stack usage for the #VC handler is 44 bytes: + ; - 12 bytes for the exception IRET (after popping error code) + ; - 32 bytes for the local variables. + ; +SevEsIdtVmmComm: + ; + ; If we're here, then we are an SEV-ES guest and this + ; was triggered by a CPUID instruction + ; + ; Set the first byte of the workarea to one to communicate to the SEC + ; phase that SEV-ES is enabled. + mov byte[SEV_ES_WORK_AREA], 1 + + pop ecx ; Error code + cmp ecx, 0x72 ; Be sure it was CPUID + jne SevEsIdtNotCpuid + + ; Set up local variable room on the stack + ; CPUID function : + 28 + ; CPUID request register : + 24 + ; GHCB MSR (EAX) : + 20 + ; GHCB MSR (EDX) : + 16 + ; CPUID result (EDX) : + 12 + ; CPUID result (ECX) : + 8 + ; CPUID result (EBX) : + 4 + ; CPUID result (EAX) : + 0 + sub esp, VC_VARIABLE_SIZE + + ; Save the CPUID function being requested + mov [esp + VC_CPUID_FUNCTION], eax + + ; The GHCB CPUID protocol uses the following mapping to request + ; a specific register: + ; 0 =3D> EAX, 1 =3D> EBX, 2 =3D> ECX, 3 =3D> EDX + ; + ; Set EAX as the first register to request. This will also be used as a + ; loop variable to request all register values (EAX to EDX). + xor eax, eax + mov [esp + VC_CPUID_REQUEST_REGISTER], eax + + ; Save current GHCB MSR value + mov ecx, 0xc0010130 + rdmsr + mov [esp + VC_GHCB_MSR_EAX], eax + mov [esp + VC_GHCB_MSR_EDX], edx + +NextReg: + ; + ; Setup GHCB MSR + ; GHCB_MSR[63:32] =3D CPUID function + ; GHCB_MSR[31:30] =3D CPUID register + ; GHCB_MSR[11:0] =3D CPUID request protocol + ; + mov eax, [esp + VC_CPUID_REQUEST_REGISTER] + cmp eax, 4 + jge VmmDone + + shl eax, GHCB_CPUID_REGISTER_SHIFT + or eax, GHCB_CPUID_REQUEST + mov edx, [esp + VC_CPUID_FUNCTION] + mov ecx, 0xc0010130 + wrmsr + + ; + ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-b= it + ; mode, so work around this by temporarily switching to 64-bit mode. + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Read GHCB MSR + ; GHCB_MSR[63:32] =3D CPUID register value + ; GHCB_MSR[31:30] =3D CPUID register + ; GHCB_MSR[11:0] =3D CPUID response protocol + ; + mov ecx, 0xc0010130 + rdmsr + mov ecx, eax + and ecx, 0xfff + cmp ecx, GHCB_CPUID_RESPONSE + jne SevEsIdtNoCpuidResponse + + ; Save returned value + shr eax, GHCB_CPUID_REGISTER_SHIFT + mov [esp + eax * 4], edx + + ; Next register + inc word [esp + VC_CPUID_REQUEST_REGISTER] + + jmp NextReg + +VmmDone: + ; + ; At this point we have all CPUID register values. Restore the GHCB MS= R, + ; set the return register values and return. + ; + mov eax, [esp + VC_GHCB_MSR_EAX] + mov edx, [esp + VC_GHCB_MSR_EDX] + mov ecx, 0xc0010130 + wrmsr + + mov eax, [esp + VC_CPUID_RESULT_EAX] + mov ebx, [esp + VC_CPUID_RESULT_EBX] + mov ecx, [esp + VC_CPUID_RESULT_ECX] + mov edx, [esp + VC_CPUID_RESULT_EDX] + + add esp, VC_VARIABLE_SIZE + + ; Update the EIP value to skip over the now handled CPUID instruction + ; (the CPUID instruction has a length of 2) + add word [esp], CPUID_INSN_LEN + iret + +ALIGN 2 + +Idtr: + dw IDT_END - IDT_BASE - 1 ; Limit + dd ADDR_OF(IDT_BASE) ; Base + +IdtrClear: + dw 0 ; Limit + dd 0 ; Base + +ALIGN 16 + +; +; The Interrupt Descriptor Table (IDT) +; This will be used to determine if SEV-ES is enabled. Upon execution +; of the CPUID instruction, a VMM Communication Exception will occur. +; This will tell us if SEV-ES is enabled. We can use the current value +; of the GHCB MSR to determine the SEV attributes. +; +IDT_BASE: +; +; Vectors 0 - 28 (No handlers) +; +%rep 29 + dw 0 ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw 0 ; Offset high bits 31..16 +%endrep +; +; Vector 29 (VMM Communication Exception) +; + dw (ADDR_OF(SevEsIdtVmmComm) & 0xffff) ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw (ADDR_OF(SevEsIdtVmmComm) >> 16) ; Offset high bits 31..16 +; +; Vectors 30 - 31 (No handlers) +; +%rep 2 + dw 0 ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw 0 ; Offset high bits 31..16 +%endrep +IDT_END: diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index bfb77e439105..762661115d50 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -72,6 +72,8 @@ %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) + %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase)) + %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) %include "Ia32/PageTables64.asm" %endif =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: mpBO7X3qMUlW8oYPoCKR4Yzxx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829489; bh=shMe0bbMl+DsPnRN57Yirlr6e8P7eut3sq4maJXImLE=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=VSCT8SXqYSOOKvfp3jxx6f+w+hiSXAI9gprutVgxkx7qoTFFdy1yr26mXTV99/JyHQP vhjzGVZlgZdiGCU09R3pg4MyxX+q51iwrIQ6zqmKGpYw6Fk360/NcXlyFgd61AKo1uZqU lZ+XzyKO0TacNy8KFVy8w4rPWg2g1NAB6pk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 An SEV-ES guest will generate a #VC exception when it encounters a non-automatic exit (NAE) event. It is expected that the #VC exception handler will communicate with the hypervisor using the GHCB to handle the NAE event. NAE events can occur during the Sec phase, so initialize exception handling early in the OVMF Sec support. Before establishing the exception handling, validate that the supported version of the SEV-ES protocol in OVMF is supported by the hypervisor. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Sec/SecMain.inf | 4 + OvmfPkg/Sec/SecMain.c | 181 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 172 insertions(+), 13 deletions(-) diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 63ba4cb555fb..7f78dcee2772 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -50,15 +50,19 @@ [LibraryClasses] PeCoffExtraActionLib ExtractGuidedSectionLib LocalApicLib + CpuExceptionHandlerLib =20 [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED =20 [Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index 6dea6e771a29..c2a35463dce4 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include =20 #include =20 @@ -34,6 +37,10 @@ typedef struct _SEC_IDT_TABLE { IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT]; } SEC_IDT_TABLE; =20 +typedef struct _SEC_SEV_ES_WORK_AREA { + UINT8 SevEsEnabled; +} SEC_SEV_ES_WORK_AREA; + VOID EFIAPI SecStartupPhase2 ( @@ -712,6 +719,120 @@ FindAndReportEntryPoints ( return; } =20 +/** + Handle an SEV-ES/GHCB protocol check failure. + + Notify the hypervisor using the VMGEXIT instruction that the SEV-ES guest + wishes to be terminated. + + @param[in] ReasonCode Reason code to provide to the hypervisor for the + termination request. + +**/ +STATIC +VOID +SevEsProtocolFailure ( + IN UINT8 ReasonCode + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + + // + // Use the GHCB MSR Protocol to request termination by the hypervisor + // + Msr.GhcbPhysicalAddress =3D 0; + Msr.GhcbTerminate.Function =3D GHCB_INFO_TERMINATE_REQUEST; + Msr.GhcbTerminate.ReasonCodeSet =3D GHCB_TERMINATE_GHCB; + Msr.GhcbTerminate.ReasonCode =3D ReasonCode; + AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + AsmVmgExit (); + + ASSERT (FALSE); + CpuDeadLoop (); +} + +/** + Validate the SEV-ES/GHCB protocol level. + + Verify that the level of SEV-ES/GHCB protocol supported by the hypervisor + and the guest intersect. If they don't intersect, request termination. + +**/ +STATIC +VOID +SevEsProtocolCheck ( + VOID + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + + // + // Use the GHCB MSR Protocol to obtain the GHCB SEV-ES Information for + // protocol checking + // + Msr.GhcbPhysicalAddress =3D 0; + Msr.GhcbInfo.Function =3D GHCB_INFO_SEV_INFO_GET; + AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + AsmVmgExit (); + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + + if (Msr.GhcbInfo.Function !=3D GHCB_INFO_SEV_INFO) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_GENERAL); + } + + if (Msr.GhcbProtocol.SevEsProtocolMin > Msr.GhcbProtocol.SevEsProtocolMa= x) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_PROTOCOL); + } + + if ((Msr.GhcbProtocol.SevEsProtocolMin > GHCB_VERSION_MAX) || + (Msr.GhcbProtocol.SevEsProtocolMax < GHCB_VERSION_MIN)) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_PROTOCOL); + } + + // + // SEV-ES protocol checking succeeded, set the initial GHCB address + // + Msr.GhcbPhysicalAddress =3D FixedPcdGet32 (PcdOvmfSecGhcbBase); + AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + Ghcb =3D Msr.Ghcb; + SetMem (Ghcb, sizeof (*Ghcb), 0); + + // + // Set the version to the maximum that can be supported + // + Ghcb->ProtocolVersion =3D MIN (Msr.GhcbProtocol.SevEsProtocolMax, GHCB_V= ERSION_MAX); + Ghcb->GhcbUsage =3D GHCB_STANDARD_USAGE; +} + +/** + Determine if SEV-ES is active. + + During early booting, SEV-ES support code will set a flag to indicate th= at + SEV-ES is enabled. Return the value of this flag as an indicator that SE= V-ES + is enabled. + + @retval TRUE SEV-ES is enabled + @retval FALSE SEV-ES is not enabled + +**/ +STATIC +BOOLEAN +SevEsIsEnabled ( + VOID + ) +{ + SEC_SEV_ES_WORK_AREA *SevEsWorkArea; + + SevEsWorkArea =3D (SEC_SEV_ES_WORK_AREA *) FixedPcdGet32 (PcdSevEsWorkAr= eaBase); + + return ((SevEsWorkArea !=3D NULL) && (SevEsWorkArea->SevEsEnabled !=3D 0= )); +} + VOID EFIAPI SecCoreStartupWithStack ( @@ -737,8 +858,55 @@ SecCoreStartupWithStack ( Table[Index] =3D 0; } =20 + // + // Initialize IDT - Since this is before library constructors are called, + // we use a loop rather than CopyMem. + // + IdtTableInStack.PeiService =3D NULL; + for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { + UINT8 *Src, *Dst; + UINTN Byte; + + Src =3D (UINT8 *) &mIdtEntryTemplate; + Dst =3D (UINT8 *) &IdtTableInStack.IdtTable[Index]; + for (Byte =3D 0; Byte < sizeof (mIdtEntryTemplate); Byte++) { + Dst[Byte] =3D Src[Byte]; + } + } + + IdtDescriptor.Base =3D (UINTN)&IdtTableInStack.IdtTable; + IdtDescriptor.Limit =3D (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1); + + if (SevEsIsEnabled ()) { + SevEsProtocolCheck (); + + // + // For SEV-ES guests, the exception handler is needed before calling + // ProcessLibraryConstructorList() because some of the library constru= ctors + // perform some functions that result in #VC exceptions being generate= d. + // + // Due to this code executing before library constructors, *all* libra= ry + // API calls are theoretically interface contract violations. However, + // because this is SEC (executing in flash), those constructors cannot + // write variables with static storage duration anyway. Furthermore, o= nly + // a small, restricted set of APIs, such as AsmWriteIdtr() and + // InitializeCpuExceptionHandlers(), are called, where we require that= the + // underlying library not require constructors to have been invoked and + // that the library instance not trigger any #VC exceptions. + // + AsmWriteIdtr (&IdtDescriptor); + InitializeCpuExceptionHandlers (NULL); + } + ProcessLibraryConstructorList (NULL, NULL); =20 + if (!SevEsIsEnabled ()) { + // + // For non SEV-ES guests, just load the IDTR. + // + AsmWriteIdtr (&IdtDescriptor); + } + DEBUG ((DEBUG_INFO, "SecCoreStartupWithStack(0x%x, 0x%x)\n", (UINT32)(UINTN)BootFv, @@ -751,19 +919,6 @@ SecCoreStartupWithStack ( // InitializeFloatingPointUnits (); =20 - // - // Initialize IDT - // - IdtTableInStack.PeiService =3D NULL; - for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { - CopyMem (&IdtTableInStack.IdtTable[Index], &mIdtEntryTemplate, sizeof = (mIdtEntryTemplate)); - } - - IdtDescriptor.Base =3D (UINTN)&IdtTableInStack.IdtTable; - IdtDescriptor.Limit =3D (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1); - - AsmWriteIdtr (&IdtDescriptor); - #if defined (MDE_CPU_X64) // // ASSERT that the Page Tables were set by the reset vector code to --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: KXTaVQtrBDCj9D5RRL1Im1xIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829497; bh=C8YaaFjJZZaXVDL1p9c7GNFV2Y2SV249NNzODoANIb4=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=joBD1KXpCzjqWYb/rTxW/Kuv4gCiElHbCAHGDHRbLdP/9ojdaNNRUJXyCG82FB9QYuH tnBT+uCX98Ce1F3x6I62wg9DOrubwJHCYEl8xMo3vI6aRp1I0jI4fjLfxrY9qnKKNEsJT eaMrTXmSc5MeQOUA8BPjxTx6n7VHcOzRbwc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Currently, the OVMF code relies on the hypervisor to enable the cache support on the processor in order to improve the boot speed. However, with SEV-ES, the hypervisor is not allowed to change the CR0 register to enable caching. Update the OVMF Sec support to enable caching in order to improve the boot speed when running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Sec/SecMain.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index c2a35463dce4..271a06348ed8 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -905,6 +905,13 @@ SecCoreStartupWithStack ( // For non SEV-ES guests, just load the IDTR. // AsmWriteIdtr (&IdtDescriptor); + } else { + // + // Under SEV-ES, the hypervisor can't modify CR0 and so can't enable + // caching in order to speed up the boot. Enable caching early for + // an SEV-ES guest. + // + AsmEnableCache (); } =20 DEBUG ((DEBUG_INFO, --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#63880): https://edk2.groups.io/g/devel/message/63880 Mute This Topic: https://groups.io/mt/76056590/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Mon Nov 25 22:24:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+63881+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+63881+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1596829505948390.2362237263925; Fri, 7 Aug 2020 12:45:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id ZUz3YY1788612xQD77VvyLq4; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: gPNHkxrro3OlcWs3U6feHVesx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596829505; bh=XohkpoSAKonrGqIAuVKxpIZZ1Vdt44M+Qsm3fQ4d/jM=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=cSz5T1VPcoa1rwaAkY/Tfhoof1/lGZc+/duzmUKPEIcSz8a5eE1PCnmTpnW3DYNrRe0 iRRe8hS4DVLd5ynLDGq2gb5rZvMgWkPvA8/gcbXFrTqjfnpVKYpBL8JC+4Evi1ZhD0fL8 EkXCZIu1Lsg5Fls+WNdg5qEBJWWer+bga4k= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The flash detection routine will attempt to determine how the flash device behaves (e.g. ROM, RAM, Flash). But when SEV-ES is enabled and the flash device behaves as a ROM device (meaning it is marked read-only by the hypervisor), this check may result in an infinite nested page fault because of the attempted write. Since the instruction cannot be emulated when SEV-ES is enabled, the RIP is never advanced, resulting in repeated nested page faults. When SEV-ES is enabled, exit the flash detection early and assume that the FD behaves as Flash. This will result in QemuFlashWrite() being called to store EFI variables, which will also result in an infinite nested page fault when the write is performed. In this case, update QemuFlashWrite() to use the VMGEXIT MMIO write support to have the hypervisor perform the write without having to emulate the instruction. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../FvbServicesRuntimeDxe.inf | 2 + .../QemuFlash.h | 13 ++++++ .../QemuFlash.c | 23 +++++++++-- .../QemuFlashDxe.c | 40 +++++++++++++++++++ .../QemuFlashSmm.c | 16 ++++++++ 5 files changed, 91 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.i= nf b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf index 72cabba4357d..8bb2325157ea 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf @@ -38,6 +38,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] @@ -52,6 +53,7 @@ [LibraryClasses] UefiBootServicesTableLib UefiDriverEntryPoint UefiRuntimeLib + VmgExitLib =20 [Guids] gEfiEventVirtualAddressChangeGuid # ALWAYS_CONSUMED diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h b/OvmfPkg/Q= emuFlashFvbServicesRuntimeDxe/QemuFlash.h index f1afabcbe6ae..219d0d6e83cf 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h @@ -89,5 +89,18 @@ QemuFlashBeforeProbe ( IN UINTN FdBlockCount ); =20 +/** + Write to QEMU Flash + + @param[in] Ptr Pointer to the location to write. + @param[in] Value The value to write. + +**/ +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ); + #endif =20 diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c b/OvmfPkg/Q= emuFlashFvbServicesRuntimeDxe/QemuFlash.c index 1b0d6c053f1a..0d29bf701aca 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include =20 #include "QemuFlash.h" @@ -80,6 +81,21 @@ QemuFlashDetected ( =20 DEBUG ((DEBUG_INFO, "QEMU Flash: Attempting flash detection at %p\n", Pt= r)); =20 + if (MemEncryptSevEsIsEnabled ()) { + // + // When SEV-ES is enabled, the check below can result in an infinite + // loop with respect to a nested page fault. When the memslot is mapped + // read-only, the nested page table entry is read-only. The check below + // will cause a nested page fault that cannot be emulated, causing + // the instruction to retried over and over. For SEV-ES, acknowledge t= hat + // the FD appears as ROM and not as FLASH, but report FLASH anyway bec= ause + // FLASH behavior can be simulated using VMGEXIT. + // + DEBUG ((DEBUG_INFO, + "QEMU Flash: SEV-ES enabled, assuming FD behaves as FLASH\n")); + return TRUE; + } + OriginalUint8 =3D *Ptr; *Ptr =3D CLEAR_STATUS_CMD; ProbeUint8 =3D *Ptr; @@ -181,8 +197,9 @@ QemuFlashWrite ( // Ptr =3D QemuFlashPtr (Lba, Offset); for (Loop =3D 0; Loop < *NumBytes; Loop++) { - *Ptr =3D WRITE_BYTE_CMD; - *Ptr =3D Buffer[Loop]; + QemuFlashPtrWrite (Ptr, WRITE_BYTE_CMD); + QemuFlashPtrWrite (Ptr, Buffer[Loop]); + Ptr++; } =20 @@ -190,7 +207,7 @@ QemuFlashWrite ( // Restore flash to read mode // if (*NumBytes > 0) { - *(Ptr - 1) =3D READ_ARRAY_CMD; + QemuFlashPtrWrite (Ptr - 1, READ_ARRAY_CMD); } =20 return EFI_SUCCESS; diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c b/OvmfPk= g/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c index 5aabe9d7b59c..565383ee26d2 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c @@ -10,6 +10,9 @@ **/ =20 #include +#include +#include +#include =20 #include "QemuFlash.h" =20 @@ -32,3 +35,40 @@ QemuFlashBeforeProbe ( // Do nothing // } + +/** + Write to QEMU Flash + + @param[in] Ptr Pointer to the location to write. + @param[in] Value The value to write. + +**/ +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ) +{ + if (MemEncryptSevEsIsEnabled ()) { + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + // + // Writing to flash is emulated by the hypervisor through the use of w= rite + // protection. This won't work for an SEV-ES guest because the write w= on't + // be recognized as a true MMIO write, which would result in the requi= red + // #VC exception. Instead, use the the VMGEXIT MMIO write support dire= ctly + // to perform the update. + // + VmgInit (Ghcb); + Ghcb->SharedBuffer[0] =3D Value; + Ghcb->SaveArea.SwScratch =3D (UINT64) (UINTN) Ghcb->SharedBuffer; + VmgExit (Ghcb, SVM_EXIT_MMIO_WRITE, (UINT64) (UINTN) Ptr, 1); + VmgDone (Ghcb); + } else { + *Ptr =3D Value; + } +} diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c b/OvmfPk= g/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c index 7eb426e03855..7eb80bfeffae 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c @@ -46,3 +46,19 @@ QemuFlashBeforeProbe ( ); ASSERT_EFI_ERROR (Status); } + +/** + Write to QEMU Flash + + @param[in] Ptr Pointer to the location to write. + @param[in] Value The value to write. + +**/ +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ) +{ + *Ptr =3D Value; +} --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: P6kmdBBmsqSAcEjwJvo92kjOx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837253; bh=Sh7MDFDthQ/x+vFRwfyvi92KcJ12CpFy7//W/LIS8+M=; h=Content-Type:Date:From:Reply-To:Subject:To; b=YDv3q+V2j0+Aq4pA/P0KO5Qi//Rn2I+iW1Ndeg+ywEqIe9HQLh8L4FMlXAMZMPXkV4J 7tdfcxijBu7Qw4M24evGTn/XpjO5LqH+OBaNQ633W39G4GLauXjBuVE+YOxka8IecpBuQ T9J0UKGnHs2Ox6I5Zlik+geesMtTYJE6zNo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 3a0210b2f172..1c94487cbee8 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY Spare4; + GDT_ENTRY SysCode16; GDT_ENTRY LinearData64; GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 64efadeba601..a1ab543f2da5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate =3D { 0x0, }, // - // SPARE4_SEL + // SYS_CODE16_SEL // { - 0x0, // limit 15:0 + 0x0FFFF, // limit 15:0 0x0, // base 15:0 0x0, // base 23:16 - 0x0, // type - 0x0, // limit 19:16, flags + 0x09A, // present, ring 0, code, execute/read + 0x08F, // page-granular, 16-bit 0x0, // base 31:24 }, // diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuP= kg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24 %endif =20 +; linear code segment descriptor +LINEAR_CODE16_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIM= IT(0xf) + DB 0 ; base 31:24 + GDT_END: =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: TdwWxIp1VDtIGwGEPtoo9nJpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837265; bh=aKa1Qu3W/ROgcnbiAIQIu4mE3YoBhrwg5tL1cFj+Wgo=; h=Content-Type:Date:From:Reply-To:Subject:To; b=SxHLpsJq56KJe9w1Dp5olWuibkahdvPgKXrf+1hETMRj4UBqHD0q1NSBr6ZojJUQw36 UOPbN5thVcgHBl9ZNYWqiIWx4iRtjJg3Rrh0oYAnfFMtoo4rUMd2jCEsQ4k0LLp7tqYad JwRveSQyhIXAlbnuzcIHHUaPx+gMG2U27SM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 When starting APs in an SMP configuration, the AP needs to know if it is running as an SEV-ES guest in order to assign a GHCB page. Add a field to the CPU_MP_DATA structure that will indicate if SEV-ES is enabled. This new field is set during MP library initialization with the PCD value PcdSevEsIsEnabled. This flag can then be used to determine if SEV-ES is enabled. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 2 ++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 1 + 4 files changed, 5 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 9907f4157b09..583276595619 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -71,4 +71,5 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## = CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## = SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## = CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## = CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## = CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 89ee9a79d8c5..4b3d39fbf36c 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -61,6 +61,7 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES =20 [Ppis] gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index a8ca03efb8e3..5b46c295b6b2 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -276,6 +276,8 @@ struct _CPU_MP_DATA { // driver. // BOOLEAN WakeUpByInitSipiSipi; + + BOOLEAN SevEsIsEnabled; }; =20 extern EFI_GUID mCpuInitMpLibHobGuid; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 9b0660a5d4ea..2a3fbeef35f7 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1704,6 +1704,7 @@ MpInitLibInitialize ( CpuMpData->CpuData =3D (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); InitializeSpinLock(&CpuMpData->MpLock); + CpuMpData->SevEsIsEnabled =3D PcdGetBool (PcdSevEsIsEnabled); =20 // // Make sure no memory usage outside of the allocated buffer. --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: mTQyWMkhWk8oIbxbTxzJVCuDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837268; bh=5SWNRmedAt3q+oODuvQnAiHo8+hWBr/QnJPG+b5dFmM=; h=Content-Type:Date:From:Reply-To:Subject:To; b=hyucNFnOL8nCg53LqZeSqZ/J9RNbU4qy1wU9wPgj8SolCQAB3ZDW0IlTLWL7T/loC/0 JsJJozdMzyPWsGJjgzMEZp2BpKjR6aMxP27gJYMkf0Vw6yS2Y2hSGjmNbD0X29M2m37zq fzYvLSJA7MK/Imgq3XwADAcdutnGcKNx+Bk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This sequence is intercepted by the hypervisor, which sets the AP's registers to the values requested by the sequence. At that point, the hypervisor can start the AP, which will then begin execution at the appropriate location. Under SEV-ES, AP booting presents some challenges since the hypervisor is not allowed to alter the AP's register state. In this situation, we have to distinguish between the AP's first boot and AP's subsequent boots. First boot: Once the AP's register state has been defined (which is before the guest is first booted) it cannot be altered. Should the hypervisor attempt to alter the register state, the change would be detected by the hardware and the VMRUN instruction would fail. Given this, the first boot for the AP is required to begin execution with this initial register state, which is typically the reset vector. This prevents the BSP from directing the AP startup location through the INIT-SIPI-SIPI sequence. To work around this, the firmware will provide a build time reserved area that can be used as the initial IP value. The hypervisor can extract this location value by checking for the SEV-ES reset block GUID that must be located 48-bytes from the end of the firmware. The format of the SEV-ES reset block area is: 0x00 - 0x01 - SEV-ES Reset IP 0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16] 0x04 - 0x05 - Size of the SEV-ES reset block 0x06 - 0x15 - SEV-ES Reset Block GUID (00f771de-1a7e-4fcb-890e-68c77e2fb44e) The total size is 22 bytes. Any expansion to this block must be done by adding new values before existing values. The hypervisor will use the IP and CS values obtained from the SEV-ES reset block to set as the AP's initial values. The CS Segment Base represents the upper 16 bits of the CS segment base and must be left shifted by 16 bits to form the complete CS segment base value. Before booting the AP for the first time, the BSP must initialize the SEV-ES reset area. This consists of programming a FAR JMP instruction to the contents of a memory location that is also located in the SEV-ES reset area. The BSP must program the IP and CS values for the FAR JMP based on values drived from the INIT-SIPI-SIPI sequence. Subsequent boots: Again, the hypervisor cannot alter the AP register state, so a method is required to take the AP out of halt state and redirect it to the desired IP location. If it is determined that the AP is running in an SEV-ES guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence is recognized, the hypervisor will resume the AP. At this point the AP must transition from the current 64-bit long mode down to 16-bit real mode and begin executing at the derived location from the INIT-SIPI-SIPI sequence. Another change is around the area of obtaining the (x2)APIC ID during AP startup. During AP startup, the AP can't take a #VC exception before the AP has established a stack. However, the AP stack is set by using the (x2)APIC ID, which is obtained through CPUID instructions. A CPUID instruction will cause a #VC, so a different method must be used. The GHCB protocol supports a method to obtain CPUID information from the hypervisor through the GHCB MSR. This method does not require a stack, so it is used to obtain the necessary CPUID information to determine the (x2)APIC ID. The new 16-bit protected mode GDT entry is used in order to transition from 64-bit long mode down to 16-bit real mode. A new assembler routine is created that takes the AP from 64-bit long mode to 16-bit real mode. This is located under 1MB in memory and transitions from 64-bit long mode to 32-bit compatibility mode to 16-bit protected mode and finally 16-bit real mode. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 3 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 3 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 60 ++++ UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 70 +++- UefiCpuPkg/Library/MpInitLib/MpLib.c | 336 +++++++++++++++++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 19 + UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +- UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 2 +- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 15 + UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 4 +- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 239 +++++++++++++ 11 files changed, 738 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 583276595619..1771575c69c1 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -52,6 +52,7 @@ [LibraryClasses] DebugAgentLib SynchronizationLib PcdLib + VmgExitLib =20 [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES @@ -72,4 +73,6 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## = SOMETIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApStatusCheckIntervalInMicroSeconds ## = CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## = CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## = SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## = CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## = CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 4b3d39fbf36c..34abf25d43cd 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -51,6 +51,7 @@ [LibraryClasses] SynchronizationLib PeiServicesLib PcdLib + VmgExitLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONS= UMES @@ -62,6 +63,8 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOME= TIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONS= UMES =20 [Ppis] gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 5b46c295b6b2..b1a9d99cb3eb 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -173,6 +173,11 @@ typedef struct { UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; UINTN ModeTransitionOffset; + UINTN SwitchToRealSize; + UINTN SwitchToRealOffset; + UINTN SwitchToRealNoNxOffset; + UINTN SwitchToRealPM16ModeOffset; + UINTN SwitchToRealPM16ModeSize; } MP_ASSEMBLY_ADDRESS_MAP; =20 typedef struct _CPU_MP_DATA CPU_MP_DATA; @@ -211,6 +216,8 @@ typedef struct { // Enable5LevelPaging indicates whether 5-level paging is enabled in lon= g mode. // BOOLEAN Enable5LevelPaging; + BOOLEAN SevEsIsEnabled; + UINTN GhcbBase; } MP_CPU_EXCHANGE_INFO; =20 #pragma pack() @@ -257,6 +264,7 @@ struct _CPU_MP_DATA { UINT8 ApLoopMode; UINT8 ApTargetCState; UINT16 PmCodeSegment; + UINT16 Pm16CodeSegment; CPU_AP_DATA *CpuData; volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo; =20 @@ -278,8 +286,47 @@ struct _CPU_MP_DATA { BOOLEAN WakeUpByInitSipiSipi; =20 BOOLEAN SevEsIsEnabled; + UINTN SevEsAPBuffer; + UINTN SevEsAPResetStackStart; + CPU_MP_DATA *NewCpuMpData; + + UINT64 GhcbBase; }; =20 +#define AP_RESET_STACK_SIZE 64 + +#pragma pack(1) + +typedef struct { + UINT8 InsnBuffer[8]; + UINT16 Rip; + UINT16 Segment; +} SEV_ES_AP_JMP_FAR; + +#pragma pack() + +/** + Assembly code to move an AP from long mode to real mode. + + Move an AP from long mode to real mode in preparation to invoking + the reset vector. This is used for SEV-ES guests where a hypervisor + is not allowed to set the CS and RIP to point to the reset vector. + + @param[in] BufferStart The reset vector target. + @param[in] Code16 16-bit protected mode code segment value. + @param[in] Code32 32-bit protected mode code segment value. + @param[in] StackStart The start of a stack to be used for transitioni= ng + from long mode to real mode. +**/ +typedef +VOID +(EFIAPI AP_RESET) ( + IN UINTN BufferStart, + IN UINT16 Code16, + IN UINT16 Code32, + IN UINTN StackStart + ); + extern EFI_GUID mCpuInitMpLibHobGuid; =20 /** @@ -385,6 +432,19 @@ GetModeTransitionBuffer ( IN UINTN BufferSize ); =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @return Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ); + /** This function will be called by BSP to wakeup AP. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 8ccddf8e9f9c..9115ff9e3e30 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -144,6 +146,39 @@ GetModeTransitionBuffer ( return (UINTN)StartAddress; } =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @return Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS StartAddress; + + // + // Allocate 1 page for AP jump table page + // + StartAddress =3D BASE_4GB - 1; + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + 1, + &StartAddress + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory =3D %lx\n", (UINTN) StartAddress= )); + + return (UINTN) StartAddress; +} + /** Checks APs status and updates APs status if needed. =20 @@ -218,6 +253,38 @@ CheckApsStatus ( } } =20 +/** + Get Protected mode code segment with 16-bit default addressing + from current GDT table. + + @return Protected mode 16-bit code segment value. +**/ +UINT16 +GetProtectedMode16CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 0) { + break; + } + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + /** Get Protected mode code segment from current GDT table. =20 @@ -238,7 +305,7 @@ GetProtectedModeCS ( GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; for (Index =3D 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L =3D=3D 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 1) { break; } } @@ -300,6 +367,7 @@ MpInitChangeApLoopCallback ( =20 CpuMpData =3D GetCpuMpData (); CpuMpData->PmCodeSegment =3D GetProtectedModeCS (); + CpuMpData->Pm16CodeSegment =3D GetProtectedMode16CS (); CpuMpData->ApLoopMode =3D PcdGet8 (PcdCpuApLoopMode); mNumberToFinish =3D CpuMpData->CpuCount - 1; WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 2a3fbeef35f7..90416c81b616 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -9,6 +9,9 @@ **/ =20 #include "MpLib.h" +#include +#include +#include =20 EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GUID; =20 @@ -291,6 +294,14 @@ GetApLoopMode ( // ApLoopMode =3D ApInHltLoop; } + + if (PcdGetBool (PcdSevEsIsEnabled)) { + // + // For SEV-ES, force AP in Hlt-loop mode in order to use the GHCB + // protocol for starting APs + // + ApLoopMode =3D ApInHltLoop; + } } =20 if (ApLoopMode !=3D ApInMwaitLoop) { @@ -587,6 +598,112 @@ InitializeApData ( SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); } =20 +/** + Get Protected mode code segment with 16-bit default addressing + from current GDT table. + + @return Protected mode 16-bit code segment value. +**/ +STATIC +UINT16 +GetProtectedMode16CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0 && + GdtEntry->Bits.DB =3D=3D 0 && + GdtEntry->Bits.Type > 8) { + break; + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + +/** + Get Protected mode code segment with 32-bit default addressing + from current GDT table. + + @return Protected mode 32-bit code segment value. +**/ +STATIC +UINT16 +GetProtectedMode32CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0 && + GdtEntry->Bits.DB =3D=3D 1 && + GdtEntry->Bits.Type > 8) { + break; + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + +/** + Reset an AP when in SEV-ES mode. + + If successful, this function never returns. + + @param[in] Ghcb Pointer to the GHCB + @param[in] CpuMpData Pointer to CPU MP Data + +**/ +STATIC +VOID +MpInitLibSevEsAPReset ( + IN GHCB *Ghcb, + IN CPU_MP_DATA *CpuMpData + ) +{ + UINT16 Code16, Code32; + AP_RESET *APResetFn; + UINTN BufferStart; + UINTN StackStart; + + Code16 =3D GetProtectedMode16CS (); + Code32 =3D GetProtectedMode32CS (); + + if (CpuMpData->WakeupBufferHigh !=3D 0) { + APResetFn =3D (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->A= ddressMap.SwitchToRealNoNxOffset); + } else { + APResetFn =3D (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart = + CpuMpData->AddressMap.SwitchToRealOffset); + } + + BufferStart =3D CpuMpData->MpCpuExchangeInfo->BufferStart; + StackStart =3D CpuMpData->SevEsAPResetStackStart - + (AP_RESET_STACK_SIZE * GetApicId ()); + + // + // This call never returns. + // + APResetFn (BufferStart, Code16, Code32, StackStart); +} + /** This function will be called from AP reset code if BSP uses WakeUpAP. =20 @@ -648,7 +765,14 @@ ApWakeupFunction ( InitializeApData (CpuMpData, ProcessorNumber, BistData, ApTopOfStack= ); ApStartupSignalBuffer =3D CpuMpData->CpuData[ProcessorNumber].Startu= pApSignal; =20 - InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->NumA= psExecuting); + // + // Delay decrementing the APs executing count when SEV-ES is enabled + // to allow the APs to issue an AP_RESET_HOLD before the BSP possibly + // performs another INIT-SIPI-SIPI sequence. + // + if (!CpuMpData->SevEsIsEnabled) { + InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeInfo->Nu= mApsExecuting); + } } else { // // Execute AP function if AP is ready @@ -755,7 +879,52 @@ ApWakeupFunction ( // while (TRUE) { DisableInterrupts (); - CpuSleep (); + if (CpuMpData->SevEsIsEnabled) { + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + UINT64 Status; + BOOLEAN DoDecrement; + + if (CpuMpData->InitFlag =3D=3D ApInitConfig) { + DoDecrement =3D TRUE; + } + + while (TRUE) { + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + + if (DoDecrement) { + DoDecrement =3D FALSE; + + // + // Perform the delayed decrement just before issuing the fir= st + // VMGEXIT with AP_RESET_HOLD. + // + InterlockedDecrement ((UINT32 *) &CpuMpData->MpCpuExchangeIn= fo->NumApsExecuting); + } + + Status =3D VmgExit (Ghcb, SVM_EXIT_AP_RESET_HOLD, 0, 0); + if ((Status =3D=3D 0) && (Ghcb->SaveArea.SwExitInfo2 !=3D 0)) { + VmgDone (Ghcb); + break; + } + + VmgDone (Ghcb); + } + + // + // Awakened in a new phase? Use the new CpuMpData + // + if (CpuMpData->NewCpuMpData !=3D NULL) { + CpuMpData =3D CpuMpData->NewCpuMpData; + } + + MpInitLibSevEsAPReset (Ghcb, CpuMpData); + } else { + CpuSleep (); + } CpuPause (); } } @@ -868,6 +1037,9 @@ FillExchangeInfoData ( ExchangeInfo->Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); DEBUG ((DEBUG_INFO, "%a: 5-Level Paging =3D %d\n", gEfiCallerBaseName, E= xchangeInfo->Enable5LevelPaging)); =20 + ExchangeInfo->SevEsIsEnabled =3D CpuMpData->SevEsIsEnabled; + ExchangeInfo->GhcbBase =3D (UINTN) CpuMpData->GhcbBase; + // // Get the BSP's data of GDT and IDT // @@ -894,8 +1066,9 @@ FillExchangeInfoData ( // EfiBootServicesCode to avoid page fault if NX memory protection is en= abled. // if (CpuMpData->WakeupBufferHigh !=3D 0) { - Size =3D CpuMpData->AddressMap.RendezvousFunnelSize - - CpuMpData->AddressMap.ModeTransitionOffset; + Size =3D CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize - + CpuMpData->AddressMap.ModeTransitionOffset; CopyMem ( (VOID *)CpuMpData->WakeupBufferHigh, CpuMpData->AddressMap.RendezvousFunnelAddress + @@ -948,7 +1121,8 @@ BackupAndPrepareWakeupBuffer( CopyMem ( (VOID *) CpuMpData->WakeupBuffer, (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress, - CpuMpData->AddressMap.RendezvousFunnelSize + CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize ); } =20 @@ -969,6 +1143,44 @@ RestoreWakeupBuffer( ); } =20 +/** + Calculate the size of the reset stack. + + @return Total amount of memory required for stacks +**/ +STATIC +UINTN +GetApResetStackSize ( + VOID + ) +{ + return AP_RESET_STACK_SIZE * PcdGet32(PcdCpuMaxLogicalProcessorNumber); +} + +/** + Calculate the size of the reset vector. + + @param[in] AddressMap The pointer to Address Map structure. + + @return Total amount of memory required for the AP reset= area +**/ +STATIC +UINTN +GetApResetVectorSize ( + IN MP_ASSEMBLY_ADDRESS_MAP *AddressMap + ) +{ + UINTN Size; + + Size =3D ALIGN_VALUE (AddressMap->RendezvousFunnelSize + + AddressMap->SwitchToRealSize + + sizeof (MP_CPU_EXCHANGE_INFO), + CPU_STACK_ALIGNMENT); + Size +=3D GetApResetStackSize (); + + return Size; +} + /** Allocate reset vector buffer. =20 @@ -982,16 +1194,22 @@ AllocateResetVector ( UINTN ApResetVectorSize; =20 if (CpuMpData->WakeupBuffer =3D=3D (UINTN) -1) { - ApResetVectorSize =3D CpuMpData->AddressMap.RendezvousFunnelSize + - sizeof (MP_CPU_EXCHANGE_INFO); + ApResetVectorSize =3D GetApResetVectorSize (&CpuMpData->AddressMap); =20 CpuMpData->WakeupBuffer =3D GetWakeupBuffer (ApResetVectorSize); CpuMpData->MpCpuExchangeInfo =3D (MP_CPU_EXCHANGE_INFO *) (UINTN) - (CpuMpData->WakeupBuffer + CpuMpData->AddressMap.Rende= zvousFunnelSize); + (CpuMpData->WakeupBuffer + + CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize); CpuMpData->WakeupBufferHigh =3D GetModeTransitionBuffer ( - CpuMpData->AddressMap.RendezvousFunnel= Size - + CpuMpData->AddressMap.RendezvousFunnel= Size + + CpuMpData->AddressMap.SwitchToRealSize= - CpuMpData->AddressMap.ModeTransitionOf= fset ); + // + // The reset stack starts at the end of the buffer. + // + CpuMpData->SevEsAPResetStackStart =3D CpuMpData->WakeupBuffer + ApRese= tVectorSize; } BackupAndPrepareWakeupBuffer (CpuMpData); } @@ -1006,7 +1224,80 @@ FreeResetVector ( IN CPU_MP_DATA *CpuMpData ) { - RestoreWakeupBuffer (CpuMpData); + // + // If SEV-ES is enabled, the reset area is needed for AP parking and + // and AP startup in the OS, so the reset area is reserved. Do not + // perform the restore as this will overwrite memory which has data + // needed by SEV-ES. + // + if (!CpuMpData->SevEsIsEnabled) { + RestoreWakeupBuffer (CpuMpData); + } +} + +/** + Allocate the SEV-ES AP jump table buffer. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +AllocateSevEsAPMemory ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + if (CpuMpData->SevEsAPBuffer =3D=3D (UINTN) -1) { + CpuMpData->SevEsAPBuffer =3D + CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0; + } +} + +/** + Program the SEV-ES AP jump table buffer. + + @param[in] SipiVector The SIPI vector used for the AP Reset +**/ +VOID +SetSevEsJumpTable ( + IN UINTN SipiVector + ) +{ + SEV_ES_AP_JMP_FAR *JmpFar; + UINT32 Offset, InsnByte; + UINT8 LoNib, HiNib; + + JmpFar =3D (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBase); + ASSERT (JmpFar !=3D NULL); + + // + // Obtain the address of the Segment/Rip location in the workarea. + // This will be set to a value derived from the SIPI vector and will + // be the memory address used for the far jump below. + // + Offset =3D FixedPcdGet32 (PcdSevEsWorkAreaBase); + Offset +=3D sizeof (JmpFar->InsnBuffer); + LoNib =3D (UINT8) Offset; + HiNib =3D (UINT8) (Offset >> 8); + + // + // Program the workarea (which is the initial AP boot address) with + // far jump to the SIPI vector (where XX and YY represent the + // address of where the SIPI vector is stored. + // + // JMP FAR [CS:XXYY] =3D> 2E FF 2E YY XX + // + InsnByte =3D 0; + JmpFar->InsnBuffer[InsnByte++] =3D 0x2E; // CS override prefix + JmpFar->InsnBuffer[InsnByte++] =3D 0xFF; // JMP (FAR) + JmpFar->InsnBuffer[InsnByte++] =3D 0x2E; // ModRM (JMP memory location) + JmpFar->InsnBuffer[InsnByte++] =3D LoNib; // YY offset ... + JmpFar->InsnBuffer[InsnByte++] =3D HiNib; // XX offset ... + + // + // Program the Segment/Rip based on the SIPI vector (always at least + // 16-byte aligned, so Rip is set to 0). + // + JmpFar->Rip =3D 0; + JmpFar->Segment =3D (UINT16) (SipiVector >> 4); } =20 /** @@ -1043,6 +1334,7 @@ WakeUpAP ( CpuMpData->InitFlag !=3D ApInitDone) { ResetVectorRequired =3D TRUE; AllocateResetVector (CpuMpData); + AllocateSevEsAPMemory (CpuMpData); FillExchangeInfoData (CpuMpData); SaveLocalApicTimerSetting (CpuMpData); } @@ -1079,6 +1371,15 @@ WakeUpAP ( } } if (ResetVectorRequired) { + // + // For SEV-ES, the initial AP boot address will be defined by + // PcdSevEsWorkAreaBase. The Segment/Rip must be the jump address + // from the original INIT-SIPI-SIPI. + // + if (CpuMpData->SevEsIsEnabled) { + SetSevEsJumpTable (ExchangeInfo->BufferStart); + } + // // Wakeup all APs // @@ -1170,6 +1471,16 @@ WakeUpAP ( *(UINT32 *) CpuData->StartupApSignal =3D WAKEUP_AP_SIGNAL; if (ResetVectorRequired) { CpuInfoInHob =3D (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob; + + // + // For SEV-ES, the initial AP boot address will be defined by + // PcdSevEsWorkAreaBase. The Segment/Rip must be the jump address + // from the original INIT-SIPI-SIPI. + // + if (CpuMpData->SevEsIsEnabled) { + SetSevEsJumpTable (ExchangeInfo->BufferStart); + } + SendInitSipiSipi ( CpuInfoInHob[ProcessorNumber].ApicId, (UINT32) ExchangeInfo->BufferStart @@ -1646,7 +1957,7 @@ MpInitLibInitialize ( ASSERT (MaxLogicalProcessorNumber !=3D 0); =20 AsmGetAddressMap (&AddressMap); - ApResetVectorSize =3D AddressMap.RendezvousFunnelSize + sizeof (MP_CPU_E= XCHANGE_INFO); + ApResetVectorSize =3D GetApResetVectorSize (&AddressMap); ApStackSize =3D PcdGet32(PcdCpuApStackSize); ApLoopMode =3D GetApLoopMode (&MonitorFilterSize); =20 @@ -1705,6 +2016,8 @@ MpInitLibInitialize ( CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); InitializeSpinLock(&CpuMpData->MpLock); CpuMpData->SevEsIsEnabled =3D PcdGetBool (PcdSevEsIsEnabled); + CpuMpData->SevEsAPBuffer =3D (UINTN) -1; + CpuMpData->GhcbBase =3D PcdGet64 (PcdGhcbBase); =20 // // Make sure no memory usage outside of the allocated buffer. @@ -1763,6 +2076,7 @@ MpInitLibInitialize ( // APs have been wakeup before, just get the CPU Information // from HOB // + OldCpuMpData->NewCpuMpData =3D CpuMpData; CpuMpData->CpuCount =3D OldCpuMpData->CpuCount; CpuMpData->BspNumber =3D OldCpuMpData->BspNumber; CpuMpData->CpuInfoInHob =3D OldCpuMpData->CpuInfoInHob; diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index a548fed23fa7..3989bd6a7a9f 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -280,6 +280,25 @@ GetModeTransitionBuffer ( return 0; } =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @return Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ) +{ + // + // PEI phase doesn't need to do such transition. So simply return 0. + // + return 0; +} + /** Checks APs status and updates APs status if needed. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSm= mCpuDxeSmm/X64/SmmFuncsArch.c index 6298571e29b2..28f8e8e133e5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -121,7 +121,7 @@ GetProtectedModeCS ( GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; for (Index =3D 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L =3D=3D 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 1) { break; } } diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc b/UefiCpuPkg/Libra= ry/MpInitLib/Ia32/MpEqu.inc index efb1bc2bf7cb..4f5a7c859a56 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc @@ -19,7 +19,7 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1 CPU_SWITCH_STATE_LOADED equ 2 =20 -LockLocation equ (RendezvousFunnelProcEnd - Rendez= vousFunnelProcStart) +LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart) StackStartAddressLocation equ LockLocation + 04h StackSizeLocation equ LockLocation + 08h ApProcedureLocation equ LockLocation + 0Ch diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index b74046b76af3..309d53bf3b37 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -215,6 +215,16 @@ CProcedureInvoke: jmp $ ; Never reach here RendezvousFunnelProcEnd: =20 +;-------------------------------------------------------------------------= ------------ +;SwitchToRealProc procedure follows. +;NOT USED IN 32 BIT MODE. +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(SwitchToRealProc) +ASM_PFX(SwitchToRealProc): +SwitchToRealProcStart: + jmp $ ; Never reach here +SwitchToRealProcEnd: + ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); ;-------------------------------------------------------------------------= ------------ @@ -263,6 +273,11 @@ ASM_PFX(AsmGetAddressMap): mov dword [ebx + 0Ch], AsmRelocateApLoopStart mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start mov dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart + mov dword [ebx + 18h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize + mov dword [ebx + 1Ch], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset + mov dword [ebx + 20h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset + mov dword [ebx + 24h], 0 = ; SwitchToRealPM16ModeOffset + mov dword [ebx + 28h], 0 = ; SwitchToRealPM16ModeSize =20 popad ret diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc index 58ef369342a7..c92daaaffd6b 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -19,7 +19,7 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1 CPU_SWITCH_STATE_LOADED equ 2 =20 -LockLocation equ (RendezvousFunnelProcEnd - Rendez= vousFunnelProcStart) +LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart) StackStartAddressLocation equ LockLocation + 08h StackSizeLocation equ LockLocation + 10h ApProcedureLocation equ LockLocation + 18h @@ -41,3 +41,5 @@ ModeTransitionSegmentLocation equ LockLocation + 9= 8h ModeHighMemoryLocation equ LockLocation + 9Ah ModeHighSegmentLocation equ LockLocation + 9Eh Enable5LevelPagingLocation equ LockLocation + 0A0h +SevEsIsEnabledLocation equ LockLocation + 0A1h +GhcbBaseLocation equ LockLocation + 0A2h diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 87f2523e856f..6956b408d004 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -184,9 +184,97 @@ Releaselock: add edi, StackStartAddressLocation add rax, qword [edi] mov rsp, rax + + lea edi, [esi + SevEsIsEnabledLocation] + cmp byte [edi], 1 ; SevEsIsEnabled + jne CProcedureInvoke + + ; + ; program GHCB + ; Each page after the GHCB is a per-CPU page, so the calculation pro= grams + ; a GHCB to be every 8KB. + ; + mov eax, SIZE_4KB + shl eax, 1 ; EAX =3D SIZE_4K * 2 + mov ecx, ebx + mul ecx ; EAX =3D SIZE_4K * 2 * C= puNumber + mov edi, esi + add edi, GhcbBaseLocation + add rax, qword [edi] + mov rdx, rax + shr rdx, 32 + mov rcx, 0xc0010130 + wrmsr jmp CProcedureInvoke =20 GetApicId: + lea edi, [esi + SevEsIsEnabledLocation] + cmp byte [edi], 1 ; SevEsIsEnabled + jne DoCpuid + + ; + ; Since we don't have a stack yet, we can't take a #VC + ; exception. Use the GHCB protocol to perform the CPUID + ; calls. + ; + mov rcx, 0xc0010130 + rdmsr + shl rdx, 32 + or rax, rdx + mov rdi, rax ; RDI now holds the original GHCB GPA + + mov rdx, 0 ; CPUID function 0 + mov rax, 0 ; RAX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + cmp edx, 0bh + jb NoX2ApicSevEs ; CPUID level below CPUID_EXTENDED_TOP= OLOGY + + mov rdx, 0bh ; CPUID function 0x0b + mov rax, 040000000h ; RBX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + test edx, 0ffffh + jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero + + mov rdx, 0bh ; CPUID function 0x0b + mov rax, 0c0000000h ; RDX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + + ; Processor is x2APIC capable; 32-bit x2APIC ID is now in EDX + jmp RestoreGhcb + +NoX2ApicSevEs: + ; Processor is not x2APIC capable, so get 8-bit APIC ID + mov rdx, 1 ; CPUID function 1 + mov rax, 040000000h ; RBX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + shr edx, 24 + +RestoreGhcb: + mov rbx, rdx ; Save x2APIC/APIC ID + + mov rdx, rdi ; RDI holds the saved GHCB GPA + shr rdx, 32 + mov eax, edi + wrmsr + + mov rdx, rbx + + ; x2APIC ID or APIC ID is in EDX + jmp GetProcessorNumber + +DoCpuid: mov eax, 0 cpuid cmp eax, 0bh @@ -253,12 +341,158 @@ CProcedureInvoke: =20 RendezvousFunnelProcEnd: =20 +;-------------------------------------------------------------------------= ------------ +;SwitchToRealProc procedure follows. +;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENC= E THIS PROC +;IS IN MACHINE CODE. +; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINT= N StackStart) +; rcx - Buffer Start +; rdx - Code16 Selector Offset +; r8 - Code32 Selector Offset +; r9 - Stack Start +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(SwitchToRealProc) +ASM_PFX(SwitchToRealProc): +SwitchToRealProcStart: +BITS 64 + cli + + ; + ; Get RDX reset value before changing stacks since the + ; new stack won't be able to accomodate a #VC exception. + ; + push rax + push rbx + push rcx + push rdx + + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for = RDX + + pop rdx + pop rcx + pop rbx + pop rax + + ; + ; Establish stack below 1MB + ; + mov rsp, r9 + + ; + ; Push ultimate Reset Vector onto the stack + ; + mov rax, rcx + shr rax, 4 + push word 0x0002 ; RFLAGS + push ax ; CS + push word 0x0000 ; RIP + push word 0x0000 ; For alignment, will be discar= ded + + ; + ; Get address of "16-bit operand size" label + ; + lea rbx, [PM16Mode] + + ; + ; Push addresses used to change to compatibility mode + ; + lea rax, [CompatMode] + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + +BITS 32 +CompatMode: + ; + ; Set up stack to prepare for exiting protected mode + ; + push edx ; Code16 CS + push ebx ; PM16Mode label address + + ; + ; Disable paging + ; + mov eax, cr0 ; Read CR0 + btr eax, 31 ; Set PG=3D0 + mov cr0, eax ; Write CR0 + + ; + ; Disable long mode + ; + mov ecx, 0c0000080h ; EFER MSR number + rdmsr ; Read EFER + btr eax, 8 ; Set LME=3D0 + wrmsr ; Write EFER + + ; + ; Disable PAE + ; + mov eax, cr4 ; Read CR4 + btr eax, 5 ; Set PAE=3D0 + mov cr4, eax ; Write CR4 + + mov edx, esi ; Restore RDX reset value + + ; + ; Switch to 16-bit operand size + ; + retf + +BITS 16 + ; + ; At entry to this label + ; - RDX will have its reset value + ; - On the top of the stack + ; - Alignment data (two bytes) to be discarded + ; - IP for Real Mode (two bytes) + ; - CS for Real Mode (two bytes) + ; +PM16Mode: + mov eax, cr0 ; Read CR0 + btr eax, 0 ; Set PE=3D0 + mov cr0, eax ; Write CR0 + + pop ax ; Discard alignment data + + ; + ; Clear registers (except RDX and RSP) before going into 16-bit mode + ; + xor eax, eax + xor ebx, ebx + xor ecx, ecx + xor esi, esi + xor edi, edi + xor ebp, ebp + + iret + +SwitchToRealProcEnd: + ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmRelocateApLoop) ASM_PFX(AsmRelocateApLoop): AsmRelocateApLoopStart: +BITS 64 cli ; Disable interrupt before switching to 3= 2-bit mode mov rax, [rsp + 40] ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- @@ -324,6 +558,11 @@ ASM_PFX(AsmGetAddressMap): mov qword [rcx + 18h], rax mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart + mov qword [rcx + 30h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize + mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset + mov qword [rcx + 40h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset + mov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart = ; SwitchToRealPM16ModeOffset + mov qword [rcx + 50h], SwitchToRealProcEnd - PM16Mode = ; SwitchToRealPM16ModeSize ret =20 ;-------------------------------------------------------------------------= ------------ --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: N6JSVZCWnaQObPUxepoAhLQlx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837275; bh=Arivw4cUbO7Sy/r3N6hTUEWgewHnMnwynfRq23rm2YQ=; h=Content-Type:Date:From:Reply-To:Subject:To; b=PFhx/2g/CuWstfsLX0EuD4FuEjnyiJ2fEEfzkWwtEnCFQ/v2+BlUd1AcFZ0g4xZOZpG S3FWr54pVjSwZII2fX6aHivvULdUCxDDBetLbxsNg2Y+Vog46N0d+Bm2fdFX1KFh3IJmc mkqTzG7laxt7RzR4Y4WyYwqSqOCXD+oHc3U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A hypervisor is not allowed to update an SEV-ES guest's register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead an SEV-ES AP must be re-directed from within the guest to the actual requested staring location as specified in the INIT-SIPI-SIPI sequence. Use the SEV-ES work area for the reset vector code that contains support to jump to the desired RIP location after having been started. This is required for only the very first AP reset. This new OVMF source file, ResetVectorVtf0.asm, is used in place of the original file through the use of the include path order set in OvmfPkg/ResetVector/ResetVector.inf under "[BuildOptions]". Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 100 +++++++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 1 + 2 files changed, 101 insertions(+) create mode 100644 OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVe= ctor/Ia16/ResetVectorVtf0.asm new file mode 100644 index 000000000000..980e0138e7fe --- /dev/null +++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,100 @@ +;-------------------------------------------------------------------------= ----- +; @file +; First code executed by processor after resetting. +; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm +; +; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 16 + +ALIGN 16 + +; +; Pad the image size to 4k when page tables are in VTF0 +; +; If the VTF0 image has page tables built in, then we need to make +; sure the end of VTF0 is 4k above where the page tables end. +; +; This is required so the page tables will be 4k aligned when VTF0 is +; located just below 0x100000000 (4GB) in the firmware device. +; +%ifdef ALIGN_TOP_TO_4K_FOR_PAGING + TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0 +%endif + +; +; SEV-ES Processor Reset support +; +; sevEsResetBlock: +; For the initial boot of an AP under SEV-ES, the "reset" RIP must be +; programmed to the RAM area defined by SEV_ES_AP_RESET_IP. A known offs= et +; and GUID will be used to locate this block in the firmware and extract +; the build time RIP value. The GUID must always be 48 bytes from the +; end of the firmware. +; +; 0xffffffca (-0x36) - IP value +; 0xffffffcc (-0x34) - CS segment base [31:16] +; 0xffffffce (-0x32) - Size of the SEV-ES reset block +; 0xffffffd0 (-0x30) - SEV-ES reset block GUID +; (00f771de-1a7e-4fcb-890e-68c77e2fb44e) +; +; A hypervisor reads the CS segement base and IP value. The CS segment b= ase +; value represents the high order 16-bits of the CS segment base, so the +; hypervisor must left shift the value of the CS segement base by 16 bit= s to +; form the full CS segment base for the CS segment register. It would th= en +; program the EIP register with the IP value as read. +; + +TIMES (32 - (sevEsResetBlockEnd - sevEsResetBlockStart)) DB 0 + +sevEsResetBlockStart: + DD SEV_ES_AP_RESET_IP + DW sevEsResetBlockEnd - sevEsResetBlockStart + DB 0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F + DB 0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E +sevEsResetBlockEnd: + +ALIGN 16 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + nop + nop + jmp EarlyBspInitReal16 + +ALIGN 16 + +fourGigabytes: + diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 762661115d50..4913b379a993 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -82,5 +82,6 @@ =20 %include "Main.asm" =20 + %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase) %include "Ia16/ResetVectorVtf0.asm" =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) by CY4PR12MB1717.namprd12.prod.outlook.com (2603:10b6:903:11f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.20; Fri, 7 Aug 2020 21:54:41 +0000 X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b]) by CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b%5]) with mapi id 15.20.3239.024; Fri, 7 Aug 2020 21:54:41 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v14 44/46] OvmfPkg: Move the GHCB allocations into reserved memory Date: Fri, 7 Aug 2020 16:53:57 -0500 Message-ID: <1f7624e2bdaa880ceff2b49ba73bea955b36e1db.1596829170.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM6PR18CA0026.namprd18.prod.outlook.com (2603:10b6:5:15b::39) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM6PR18CA0026.namprd18.prod.outlook.com (2603:10b6:5:15b::39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: GOBiU0GhTOt7Chahb9qX9MPGx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837287; bh=U65IH6ZmXjbYI0nF/MgI8/igreRDNabLxljAM4Q3nUg=; h=Content-Type:Date:From:Reply-To:Subject:To; b=oUe0gTAwF/Jkyg6goTIuunl07d9RNOs80s3R1lMVeqpUMF+e58CzU5XmlTqSf+RYfqO SbXLs3gOdfC1K5cvoo5ussgXikuOxnO0V9d/QSnNKhVTAA5E83RUw2kp3B0gVS1RT7+UK hlNdTtt7yQahr0d4njgCA//JeoQ6x3H7stk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 After having transitioned from UEFI to the OS, the OS will need to boot the APs. For an SEV-ES guest, the APs will have been parked by UEFI using GHCB pages allocated by UEFI. The hypervisor will write to the GHCB SW_EXITINFO2 field of the GHCB when the AP is booted. As a result, the GHCB pages must be marked reserved so that the OS does not attempt to use them and experience memory corruption because of the hypervisor write. Change the GHCB allocation from the default boot services memory to reserved memory. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/AmdSev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index a2b38c591236..4a515a484720 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -51,9 +51,11 @@ AmdSevEsInitialize ( =20 // // Allocate GHCB and per-CPU variable pages. + // Since the pages must survive across the UEFI to OS transition + // make them reserved. // GhcbPageCount =3D mMaxCpuCount * 2; - GhcbBase =3D AllocatePages (GhcbPageCount); + GhcbBase =3D AllocateReservedPages (GhcbPageCount); ASSERT (GhcbBase !=3D NULL); =20 GhcbBasePa =3D (PHYSICAL_ADDRESS)(UINTN) GhcbBase; --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) by CY4PR12MB1717.namprd12.prod.outlook.com (2603:10b6:903:11f::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.20; Fri, 7 Aug 2020 21:54:49 +0000 X-Received: from CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b]) by CY4PR12MB1352.namprd12.prod.outlook.com ([fe80::9181:78bf:bf0:702b%5]) with mapi id 15.20.3239.024; Fri, 7 Aug 2020 21:54:49 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v14 45/46] UefiCpuPkg/MpInitLib: Prepare SEV-ES guest APs for OS use Date: Fri, 7 Aug 2020 16:53:58 -0500 Message-ID: In-Reply-To: References: X-ClientProxiedBy: DM5PR1401CA0012.namprd14.prod.outlook.com (2603:10b6:4:4a::22) To CY4PR12MB1352.namprd12.prod.outlook.com (2603:10b6:903:3a::13) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR1401CA0012.namprd14.prod.outlook.com (2603:10b6:4:4a::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3261.19 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Wpk55OYbJDWrtbWRWN3AiQVMx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837291; bh=BTOUKpTKYa+hAPKnoi9/sxYSkl6btX5AoWwOAwQ1qcw=; h=Content-Type:Date:From:Reply-To:Subject:To; b=w/YWOcg7fHoyViUzedwdyA4kgGEbNiog1v1cvGCXqEh/OkqdyNAOImQontKkgKfMvyR OV0DTVtH0gq+eLkBhX4jwUcbAAD2D7a/jUl+LGhPHnTlGisaRw089Bfg5JCHKN142pxSW YKtgtCSqZ52i3bGVDoQGbwmtErN2Xp7iOek= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Before UEFI transfers control to the OS, it must park the AP. This is done using the AsmRelocateApLoop function to transition into 32-bit non-paging mode. For an SEV-ES guest, a few additional things must be done: - AsmRelocateApLoop must be updated to support SEV-ES. This means performing a VMGEXIT AP Reset Hold instead of an MWAIT or HLT loop. - Since the AP must transition to real mode, a small routine is copied to the WakeupBuffer area. Since the WakeupBuffer will be used by the AP during OS booting, it must be placed in reserved memory. Additionally, the AP stack must be located where it can be accessed in real mode. - Once the AP is in real mode it will transfer control to the destination specified by the OS in the SEV-ES AP Jump Table. The SEV-ES AP Jump Table address is saved by the hypervisor for the OS using the GHCB VMGEXIT AP Jump Table exit code. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Reviewed-by: Eric Dong Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 8 +- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 54 +++++++- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 5 +- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 130 ++++++++++++++++-- 4 files changed, 179 insertions(+), 18 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index b1a9d99cb3eb..02652eaae126 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -293,7 +293,8 @@ struct _CPU_MP_DATA { UINT64 GhcbBase; }; =20 -#define AP_RESET_STACK_SIZE 64 +#define AP_SAFE_STACK_SIZE 128 +#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE =20 #pragma pack(1) =20 @@ -350,7 +351,10 @@ VOID IN UINTN ApTargetCState, IN UINTN PmCodeSegment, IN UINTN TopOfApStack, - IN UINTN NumberToFinish + IN UINTN NumberToFinish, + IN UINTN Pm16CodeSegment, + IN UINTN SevEsAPJumpTable, + IN UINTN WakeupBuffer ); =20 /** diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 9115ff9e3e30..2c00d72ddefe 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include =20 @@ -85,6 +86,13 @@ GetWakeupBuffer ( { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS StartAddress; + EFI_MEMORY_TYPE MemoryType; + + if (PcdGetBool (PcdSevEsIsEnabled)) { + MemoryType =3D EfiReservedMemoryType; + } else { + MemoryType =3D EfiBootServicesData; + } =20 // // Try to allocate buffer below 1M for waking vector. @@ -97,7 +105,7 @@ GetWakeupBuffer ( StartAddress =3D 0x88000; Status =3D gBS->AllocatePages ( AllocateMaxAddress, - EfiBootServicesData, + MemoryType, EFI_SIZE_TO_PAGES (WakeupBufferSize), &StartAddress ); @@ -159,8 +167,10 @@ GetSevEsAPMemory ( VOID ) { - EFI_STATUS Status; - EFI_PHYSICAL_ADDRESS StartAddress; + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS StartAddress; + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; =20 // // Allocate 1 page for AP jump table page @@ -176,6 +186,16 @@ GetSevEsAPMemory ( =20 DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory =3D %lx\n", (UINTN) StartAddress= )); =20 + // + // Save the SevEsAPMemory as the AP jump table. + // + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + VmgExit (Ghcb, SVM_EXIT_AP_JUMP_TABLE, 0, (UINT64) (UINTN) StartAddress); + VmgDone (Ghcb); + return (UINTN) StartAddress; } =20 @@ -330,17 +350,26 @@ RelocateApLoop ( BOOLEAN MwaitSupport; ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); + if (CpuMpData->SevEsIsEnabled) { + StackStart =3D CpuMpData->SevEsAPResetStackStart; + } else { + StackStart =3D mReservedTopOfApStack; + } AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoop= Func; AsmRelocateApLoopFunc ( MwaitSupport, CpuMpData->ApTargetCState, CpuMpData->PmCodeSegment, - mReservedTopOfApStack - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN) &mNumberToFinish + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN) &mNumberToFinish, + CpuMpData->Pm16CodeSegment, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer ); // // It should never reach here @@ -374,6 +403,21 @@ MpInitChangeApLoopCallback ( while (mNumberToFinish > 0) { CpuPause (); } + + if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer !=3D (UINTN) -= 1)) { + // + // There are APs present. Re-use reserved memory area below 1MB from + // WakeupBuffer as the area to be used for transitioning to 16-bit mode + // in support of booting of the AP by an OS. + // + CopyMem ( + (VOID *) CpuMpData->WakeupBuffer, + (VOID *) (CpuMpData->AddressMap.RendezvousFunnelAddress + + CpuMpData->AddressMap.SwitchToRealPM16ModeOffset), + CpuMpData->AddressMap.SwitchToRealPM16ModeSize + ); + } + DEBUG ((DEBUG_INFO, "%a() done!\n", __FUNCTION__)); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index 309d53bf3b37..7e81d24aa60f 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -226,7 +226,10 @@ SwitchToRealProcStart: SwitchToRealProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); +; +; The last three parameters (Pm16CodeSegment, SevEsAPJumpTable and Wakeup= Buffer) are +; specific to SEV-ES support and are not applicable on IA32. ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmRelocateApLoop) ASM_PFX(AsmRelocateApLoop): diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 6956b408d004..5d30f35b201c 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -465,6 +465,10 @@ BITS 16 ; - IP for Real Mode (two bytes) ; - CS for Real Mode (two bytes) ; + ; This label is also used with AsmRelocateApLoop. During MP finalizati= on, + ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start= of + ; the WakeupBuffer, allowing a parked AP to be booted by an OS. + ; PM16Mode: mov eax, cr0 ; Read CR0 btr eax, 0 ; Set PE=3D0 @@ -487,32 +491,96 @@ PM16Mode: SwitchToRealProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish, Pm16CodeSegment, SevEsAPJumpTable, WakeupBuffer); ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmRelocateApLoop) ASM_PFX(AsmRelocateApLoop): AsmRelocateApLoopStart: BITS 64 + cmp qword [rsp + 56], 0 ; SevEsAPJumpTable + je NoSevEs + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + + pop rdx + pop rcx + +NoSevEs: cli ; Disable interrupt before switching to 3= 2-bit mode mov rax, [rsp + 40] ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- - mov rsp, r9 - push rcx - push rdx =20 - lea rsi, [PmEntry] ; rsi <- The start address of transition = code + mov r10, [rsp + 48] ; Pm16CodeSegment + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, r9 ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r10 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntry] ; rax <- The start address of transition = code =20 push r8 - push rsi - DB 0x48 - retf + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + BITS 32 PmEntry: mov eax, cr0 btr eax, 31 ; Clear CR0.PG mov cr0, eax ; Disable paging and caches =20 - mov ebx, edx ; Save EntryPoint to rbx, for rdmsr will = overwrite rdx mov ecx, 0xc0000080 rdmsr and ah, ~ 1 ; Clear LME @@ -525,6 +593,8 @@ PmEntry: add esp, 4 pop ecx, add esp, 4 + +MwaitCheck: cmp cl, 1 ; Check mwait-monitor support jnz HltLoop mov ebx, edx ; Save C-State to ebx @@ -538,10 +608,50 @@ MwaitLoop: shl eax, 4 mwait jmp MwaitLoop + HltLoop: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHlt + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHlt: cli hlt - jmp HltLoop + jmp DoHlt + BITS 64 AsmRelocateApLoopEnd: =20 --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: uhBUULHZBrMPULHZYho111pkx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1596837299; bh=L+RfaEoaBLvXhbWRHzkFgPdFwdW8n/OSAvho2SLFVU0=; h=Content-Type:Date:From:Reply-To:Subject:To; b=iWGCD5md2yDAPjvhxpHbZ8rlTerftVee9Hf6/WyJapp8eN82mQZkKUUKPPigrn7Twtm 9wBPMy3CoM//P14ZVv8wtGuxczsAXUUyeFfR7C50p/e88FtVSPplNDzsZhC+VQxQeg2as DvSLoWJGWcSep5Ap+D25iCk008aXyfawMuY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Tom Lendacky Register reviewers for the SEV-related files in OvmfPkg. Cc: Andrew Fish Cc: Laszlo Ersek Cc: Leif Lindholm Cc: Michael D Kinney Cc: Brijesh Singh Acked-by: Brijesh Singh Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- Maintainers.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Maintainers.txt b/Maintainers.txt index 4c163496b1b0..f673ddd2b38c 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -441,6 +441,16 @@ F: OvmfPkg/PvScsiDxe/ R: Liran Alon R: Nikita Leshenko =20 +OvmfPkg: SEV-related modules +F: OvmfPkg/AmdSevDxe/ +F: OvmfPkg/Include/Library/MemEncryptSevLib.h +F: OvmfPkg/IoMmuDxe/AmdSevIoMmu.* +F: OvmfPkg/Library/BaseMemEncryptSevLib/ +F: OvmfPkg/Library/VmgExitLib/ +F: OvmfPkg/PlatformPei/AmdSev.c +R: Tom Lendacky +R: Brijesh Singh + OvmfPkg: TCG- and TPM2-related modules F: OvmfPkg/Include/IndustryStandard/QemuTpm.h F: OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c --=20 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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