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Mon, 2 Mar 2020 23:07:30 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh , Jian J Wang , Hao A Wu Subject: [edk2-devel] [PATCH v5 01/42] MdePkg: Create PCDs to be used in support of SEV-ES Date: Mon, 2 Mar 2020 17:06:32 -0600 Message-Id: <13141b1fb978236858e5b17faf162ca682952827.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:07:29 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 2b4a1040-05ee-4707-c65e-08d7befe7b5c X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8273; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55241+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: Ud5THnQm7oBuNlf78mz/AcOjGgqSAeq1NApRsKQCYHwQKKKl+Gs+cGhDNIctWVVhfGpXoUkwCx9xftiy9e+Mj4BRkAdqGYEAE+Q+s2vGghPArdMpqMAiWyvLA28CFmpTU2gKYmv3r93qCvd3Kgb57ItPa0eL8838yQC7ZviIfDXJlX24BYXtiozASGAY4wQ3Ns1EcSsGDycuOl6qu+qkjInN4YwxCeMmfveNuxvcrtTOvk0Gv0e1wNF99zJfxigen9uJhlS1TVnlHxtlJNe5aOdlxhG5ogIez4X9caLrlohfylu8GOkZVX2XQkwM643TIf/PxqIbSrRgqWQ7PegdMq5ac69rzCFaIcRJkEvOBn5P6V5B8smhnnRBN9oVDvkXcWM3BGG1zZpdAU4nL7/hsphDOkV8vsd3Z61bDOuFk9WkpiWS0+ZdYzkVjA4FT1VzydGm871yrpcGCaC8NJzhv7cROJrU4SuM3tuorW8X9PSyyttHqJS387iLAYT/w9rPzxgyfvmkNwIK/hX7UrMEaw== X-MS-Exchange-AntiSpam-MessageData: lVYjhDRJ5PlyETiCpBmA5c9MuX/eLa0wByCSOC6Ij3IGFlUV1Urik+2Kp4PDl/9Jhy5N4OENET3dDf23EP3LE7gMLv+FLJjJii1BErv1ipd6Atz1qTcNYg40WKEOWeopWpbhdqkmFTToT6CsTXx7Zg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2b4a1040-05ee-4707-c65e-08d7befe7b5c X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:30.2229 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hyMA75PVrhcJT05lLBsnkfOngOvAQgS1jSIfVQuhQDw3Fw4P/StfSdiqExZ58OlqGZVu5ISbYF5WZtYn3Gb7Sg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: hhVNBw4htI7xta7tpXzNzi1Ix1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190451; bh=zXoHAP2A6+KDeYONnYiqPXwnBM+xmLVBMAp2+GPA6XM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=miWxYGsCwOGhJJj2Ko2luW5tCLT0LD77IXHWfAA0SwVQcNhpRtuqthxLLbwt3P8fTj8 3FaKbSvzIozF/URhxwPmPz5KMCOZnz2v2InGsE0VrorNMojhgXPKFIA71T0FCk8P4374q GUUM1o88Z7ufs+0tUWmy1jepASJA+5PKdBA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Three new dynamic PCDs are needed to support SEV-ES under OVMF: - PcdSevEsIsEnabled: BOOLEAN value used to indicate if SEV-ES is enabled - PcdGhcbBase: UINT64 value that is the base address of the GHCB allocation. - PcdGhcbSize: UINT64 value that is the size, in bytes, of the GHCB allocation (size is dependent on the number of APs). Cc: Jian J Wang Cc: Hao A Wu Signed-off-by: Tom Lendacky --- MdeModulePkg/MdeModulePkg.dec | 9 +++++++++ UefiCpuPkg/UefiCpuPkg.dec | 6 ++++++ 2 files changed, 15 insertions(+) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 91a3c608231c..c144b23233db 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -2071,6 +2071,15 @@ [PcdsDynamic, PcdsDynamicEx] # @Prompt If there is any test key used by the platform. gEfiMdeModulePkgTokenSpaceGuid.PcdTestKeyUsed|FALSE|BOOLEAN|0x00030003 =20 + ## This dynamic PCD holds the base address of the GHCB pool allocation. + # @Prompt GHCB Pool Base Address + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0|UINT64|0x00030007 + + ## This dynamic PCD holds the total size of the GHCB pool allocation. + # The amount of memory allocated for GHCBs is dependent on the number o= f APs. + # @Prompt GHCB Pool Size + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0|UINT64|0x00030008 + [PcdsDynamicEx] ## This dynamic PCD enables the default variable setting. # Its value is the default store ID value. The default value is zero as= Standard default. diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index e91dc68cbeb2..2f30bf89615f 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -364,5 +364,11 @@ [PcdsDynamic, PcdsDynamicEx] # @ValidRange 0x80000001 | 0 - 1 gUefiCpuPkgTokenSpaceGuid.PcdCpuProcTraceOutputScheme|0x0|UINT8|0x600000= 15 =20 + ## This dynamic PCD indicates whether SEV-ES is enabled + # TRUE - SEV-ES is enabled + # FALSE - SEV-ES is not enabled + # @Prompt SEV-ES Status + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|FALSE|BOOLEAN|0x60000016 + [UserExtensions.TianoCore."ExtraFiles"] UefiCpuPkgExtra.uni --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55241): https://edk2.groups.io/g/devel/message/55241 Mute This Topic: https://groups.io/mt/71687789/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55242+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190453974810.7405923400939; Mon, 2 Mar 2020 15:07:33 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id kEmrYY1788612xIjo7uj0Qpa; Mon, 02 Mar 2020 15:07:33 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com [40.107.220.55]) by mx.groups.io with SMTP id smtpd.web09.716.1583190452495300133 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:31 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:31 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 02/42] MdePkg: Add the MSR definition for the GHCB register Date: Mon, 2 Mar 2020 17:06:33 -0600 Message-Id: <104a19634a77f60fa3e67cce321d4d722c4119fe.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:07:30 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 1e80d7db-d243-414f-0f7b-08d7befe7c1f X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4941; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55242+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: U50YUCvh4O9yOpN7fDRtJX2ZskryuAPnQYzOYMnsDLUJh0VkjgF9YRBtMK7wOZr/RVZJE5bzV1TGx0wLED476BsJyIc/rYC853ry0rIc87uPVV9zYSTV25X4DB/6q66YP5Ym0PfIJNSMKAZkDU26rxW8mdof2jFBPKg4G46dfgx+nN45bfWx0Qk4jg87b6YKAP2NTCNhWJ4UVlzgDKEY+oerOst0IDUzirCIAnSi4WpWRiZ1eG3fNujkW7wJN2q9DpOukYc7Lf7rERTRl68eWGFpWvSJhAwLha6JS8yz7zO+R8hE2l+divwZXEfFXgsSTclN+VZxUpgcc8kEK8q7f0Wz+z2LhGBYe3wpFYsuZz1B0Zbkhl8StvwQvBxjruluP49dvMB02ktPFpat9Gx+JopHOH/bV0fMZI0+09xtxyNg2hYw745XWZBcpzZsCw5ukGwCjcSjpIETdNTf09L6ucHqAciPkV2SALeHXc5Oihv8nIEZI/axolsSNaTiphreQz9CgENieauxYmHFWHP4rw== X-MS-Exchange-AntiSpam-MessageData: 5UrqDmAaWw1cfxo8z2YpvFj4GD1gX6otokVvwhJXNYNDWLSHrbKs27tXxsaoHoHxx4hd/xoSPRBaQhkNti6MEbDZgGSctAc7ubXiajW9IPblgYOczA6w83TxgIL8noqg91QLbRt62FpXP31YtUFUug== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1e80d7db-d243-414f-0f7b-08d7befe7c1f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:31.2953 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZQG6d9ZxrZ2Ex5vB4sr6sbOZn6tENLwlDB71/4MgIfGHCIeXyy4SBgCZjtVph6QZYkLx733CptB0aZJvYBtrsA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: H2bhVJEaD4RtrEHj5tIxBDp7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190453; bh=17oNeUjiH3Si3OhVnqUfGtLgavBY5bIhkhQ8OP8Aobw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Ld78/C1iibrQ8RapahmVkJhu3y+PjJe/h/Pgqu8ZQffUD4BtKVXUZ9NsVC3LMRT/dCk o4bMvAE1VOxDHGzbOzftgi/cz8pYZjA7Nu+7t0xd3U92XABusMS6srsl1n7GA7UOUNrTJ OVko/9weCa/0fIKvfHzmxqLtoPnNQnLjihg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 For SEV-ES, the GHCB page address is stored in the GHCB MSR register (0xc0010130). Define the register and the format used for register during GHCB protocol negotiation. Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Include/Register/Amd/Fam17Msr.h | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/MdePkg/Include/Register/Amd/Fam17Msr.h b/MdePkg/Include/Regist= er/Amd/Fam17Msr.h index 6ef45a9b21d3..466a3143599c 100644 --- a/MdePkg/Include/Register/Amd/Fam17Msr.h +++ b/MdePkg/Include/Register/Amd/Fam17Msr.h @@ -17,6 +17,48 @@ #ifndef __FAM17_MSR_H__ #define __FAM17_MSR_H__ =20 +/** + Secure Encrypted Virtualization - Encrypted State (SEV-ES) GHCB register + +**/ +#define MSR_SEV_ES_GHCB 0xc0010130 + +/** + MSR information returned for #MSR_SEV_ES_GHCB +**/ +typedef union { + struct { + UINT64 Function:12; + } GhcbInfo; + + struct { + UINT8 Reserved[3]; + UINT8 SevEncryptionBitPos; + UINT16 SevEsProtocolMin; + UINT16 SevEsProtocolMax; + } GhcbProtocol; + + struct { + UINT64 Function:12; + UINT64 ReasonCodeSet:4; + UINT64 ReasonCode:8; + } GhcbTerminate; + + VOID *Ghcb; + + UINT64 GhcbPhysicalAddress; +} MSR_SEV_ES_GHCB_REGISTER; + +#define GHCB_INFO_SEV_INFO 1 +#define GHCB_INFO_SEV_INFO_GET 2 +#define GHCB_INFO_CPUID_REQUEST 4 +#define GHCB_INFO_CPUID_RESPONSE 5 +#define GHCB_INFO_TERMINATE_REQUEST 256 + +#define GHCB_TERMINATE_GHCB 0 +#define GHCB_TERMINATE_GHCB_GENERAL 0 +#define GHCB_TERMINATE_GHCB_PROTOCOL 1 + /** Secure Encrypted Virtualization (SEV) status register =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:07:31 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 85f175c2-fe8f-4912-3382-08d7befe7cc6 X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:8882; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55243+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: jSOtRMq1YeYGjPbwgqQ1SsXhvTVVCAIiLSUzd2yodXF11xsdj5FCLoNr0BMtoREgkyDqKOC0DXvPpaELIc1WkgR9GU91YTU9ErRQ23HlWBI/kzpvD/ELEEu0ZqKBUP+8uOwppI0IvmSYT07VI0AZ70UndkYyoCLtBmtaP0h9Uv368DccAq4zeG5PQ7Uue0hrI0DnpPoXFOpQbW30QHaxpVaPqCKhQrvWnkP5US0KdLGj0fOcy+JLh9Am9JkMLKtmkAuBr6kzj1hdVtg82q9F/ts6wFq2tCyrjoKMJrw+OLlgpaJuRqUDTItwEoVQ7leX47ofNdCSnAbafcQxTqr4CSn/8gQzB/wddcZbJy07FzIUkc/mAjYtbBzuoQpbT4mxmhOYeoymzE6U6k3lG4ms5lWpCvaKOHsSn3flWhEm3x+i6anJ7K/NVp5eHJTb4+1youv53FqG8cZZSltP23T0e5Y/amyya4mNYgjPZA/5qFNXC7EE/m8DZqckNAas4fr15I+aTsPkv5z7EDkf4hJNew== X-MS-Exchange-AntiSpam-MessageData: T4DiZXLahEtjOUqrwsVE68QvrhwFyHfM1sAn6vbAi/ycs9fpktkrFYPcl5z1R0RAVL5at76HkqSeKAGFerwGH57FKrU1qS35qjDvBayisi+oCVHAgxG03M9sksqusdfFtC7ucXG4T7qUeSUqm+9yVg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 85f175c2-fe8f-4912-3382-08d7befe7cc6 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:32.2128 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Mt9mOacvLmlOlF5FhwwDYSHUAFlFksukJTsPOTQL9VZeYT95aayLWk01vNWs/8kcspJf/ECQI9irTCD7iIeN9Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: W7j4nCQJbLpLKc0GwiCqzl7Sx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190453; bh=178hvZZfpS+7cMbjRW0MKNTdLIrwQrlKdUS0JrZogkc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=JnzQTtR8yWCpfTO6mWdqlqFHPuBd0Y/oVJQC6GGPam2OE8K+lLctP5iK4l0t3wPHoV2 p26yUjzm6bXd9AxMAigdTZyceB0hHY7HGDRDC5vr5iVzH582ECZrwdm+5QtNq2kvzcbAa +J70FMZRJIvpWBEFALkTTOzg7HB09+7JcVk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The GHCB is used by an SEV-ES guest for communicating between the guest and the hypervisor. Create the GHCB definition as defined by the GHCB protocol definition. Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Include/Register/Amd/Ghcb.h | 136 +++++++++++++++++++++++++++++ 1 file changed, 136 insertions(+) create mode 100644 MdePkg/Include/Register/Amd/Ghcb.h diff --git a/MdePkg/Include/Register/Amd/Ghcb.h b/MdePkg/Include/Register/A= md/Ghcb.h new file mode 100644 index 000000000000..ffad7efd82d9 --- /dev/null +++ b/MdePkg/Include/Register/Amd/Ghcb.h @@ -0,0 +1,136 @@ +/** @file + Guest-Hypervisor Communication Block (GHCB) Definition. + + Provides data types allowing an SEV-ES guest to interact with the hyperv= isor + using the GHCB protocol. + + Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Specification Reference: + SEV-ES Guest-Hypervisor Communication Block Standardization + +**/ + +#ifndef __GHCB_H__ +#define __GHCB_H__ + +#include +#include + +#define UD_EXCEPTION 6 +#define GP_EXCEPTION 13 + +#define GHCB_VERSION_MIN 1 +#define GHCB_VERSION_MAX 1 + +#define GHCB_STANDARD_USAGE 0 + +typedef enum { + SvmExitDr7Read =3D 0x27, + SvmExitDr7Write =3D 0x37, + SvmExitRdtsc =3D 0x6E, + SvmExitRdpmc, + SvmExitCpuid =3D 0x72, + SvmExitInvd =3D 0x76, + SvmExitIoioProt =3D 0x7B, + SvmExitMsr, + SvmExitVmmCall =3D 0x81, + SvmExitRdtscp =3D 0x87, + SvmExitWbinvd =3D 0x89, + SvmExitMonitor, + SvmExitMwait, + SvmExitNpf =3D 0x400, + + // VMG special exits + SvmExitMmioRead =3D 0x80000001, + SvmExitMmioWrite, + SvmExitNmiComplete, + SvmExitApResetHold, + SvmExitApJumpTable, + + SvmExitUnsupported =3D 0x8000FFFF, +} SVM_EXITCODE; + +typedef enum { + GhcbCpl =3D 25, + GhcbRflags =3D 46, + GhcbRip, + GhcbRsp =3D 59, + GhcbRax =3D 63, + GhcbRcx =3D 97, + GhcbRdx, + GhcbRbx, + GhcbRbp =3D 101, + GhcbRsi, + GhcbRdi, + GhcbR8, + GhcbR9, + GhcbR10, + GhcbR11, + GhcbR12, + GhcbR13, + GhcbR14, + GhcbR15, + GhcbXCr0 =3D 125, +} GHCB_REGISTER; + +typedef struct { + UINT8 Reserved1[203]; + UINT8 Cpl; + UINT8 Reserved2[148]; + UINT64 Dr7; + UINT8 Reserved3[144]; + UINT64 Rax; + UINT8 Reserved4[264]; + UINT64 Rcx; + UINT64 Rdx; + UINT64 Rbx; + UINT8 Reserved5[112]; + UINT64 SwExitCode; + UINT64 SwExitInfo1; + UINT64 SwExitInfo2; + UINT64 SwScratch; + UINT8 Reserved6[56]; + UINT64 XCr0; + UINT8 ValidBitmap[16]; + UINT64 X87StateGpa; + UINT8 Reserved7[1016]; +} __attribute__ ((__packed__)) GHCB_SAVE_AREA; + +typedef struct { + GHCB_SAVE_AREA SaveArea; + UINT8 SharedBuffer[2032]; + UINT8 Reserved1[10]; + UINT16 ProtocolVersion; + UINT32 GhcbUsage; +} __attribute__ ((__packed__)) __attribute__ ((aligned(SIZE_4KB))) GHCB; + +typedef union { + struct { + UINT32 Lower32Bits; + UINT32 Upper32Bits; + } Elements; + + UINT64 Uint64; +} GHCB_EXIT_INFO; + +typedef union { + struct { + UINT32 Vector:8; + UINT32 Type:3; + UINT32 ErrorCodeValid:1; + UINT32 Rsvd:19; + UINT32 Valid:1; + UINT32 ErrorCode; + } Elements; + + UINT64 Uint64; +} GHCB_EVENT_INJECTION; + +#define GHCB_EVENT_INJECTION_TYPE_INT 0 +#define GHCB_EVENT_INJECTION_TYPE_NMI 2 +#define GHCB_EVENT_INJECTION_TYPE_EXCEPTION 3 +#define GHCB_EVENT_INJECTION_TYPE_SOFT_INT 4 + +#endif --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: HZkGMw3kVYgiPejrgwpII1N9x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190454; bh=Vcu2KGf9lQNhlV2nmTyIf5u5lWpvY7YSbuC11ET1/bw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=Y5Pm7qIm41rfhkCogc8EUEZzUqGB++mHvGyxJuJewJOcZL+8iWP56WiRTlaac7YR+qJ eedIgD1kTFqzd5DJrGgG/wBs2gxTJ0i0lwEwI2jOzEOm+HJAkv9XV/zBKVXgSsujvuzu+ itu9jPSwOImMRq4RYDs8ZHzsZ/GbPaEACuk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 GHCB pages must be mapped as shared pages, so modify the process of creating identity mapped pagetable entries so that GHCB entries are created without the encryption bit set. Cc: Jian J Wang Cc: Hao A Wu Cc: Dandan Bi Cc: Liming Gao Signed-off-by: Tom Lendacky --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 2 + .../Core/DxeIplPeim/X64/VirtualMemory.h | 12 ++++- .../Core/DxeIplPeim/Ia32/DxeLoadFunc.c | 4 +- .../Core/DxeIplPeim/X64/DxeLoadFunc.c | 11 ++++- .../Core/DxeIplPeim/X64/VirtualMemory.c | 49 ++++++++++++++----- 5 files changed, 62 insertions(+), 16 deletions(-) diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 98bc17fc9d1f..5e6b78e295e6 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -111,6 +111,8 @@ [Pcd.IA32,Pcd.X64] gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##= CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##= SOMETIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##= CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##= CONSUMES =20 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64] gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack ## SOMETIM= ES_CONSUMES diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.h index 2d0493f109e8..6b7c38a441d6 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h @@ -201,6 +201,8 @@ EnableExecuteDisableBit ( @param[in, out] PageEntry2M Pointer to 2M page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -208,7 +210,9 @@ Split2MPageTo4K ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry2M, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ); =20 /** @@ -217,6 +221,8 @@ Split2MPageTo4K ( =20 @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 @return The address of 4 level page map. =20 @@ -224,7 +230,9 @@ Split2MPageTo4K ( UINTN CreateIdentityMappingPageTables ( IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbkSize ); =20 =20 diff --git a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c b/MdeModulePkg= /Core/DxeIplPeim/Ia32/DxeLoadFunc.c index 6e8ca824d469..284b34818ca7 100644 --- a/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c @@ -123,7 +123,7 @@ Create4GPageTablesIa32Pae ( // // Need to split this 2M page that covers stack range. // - Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + Split2MPageTo4K (PhysicalAddress, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize, 0, 0); } else { // // Fill in the Page Directory entries @@ -282,7 +282,7 @@ HandOffToDxeCore ( // // Create page table and save PageMapLevel4 to CR3 // - PageTables =3D CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZ= E); + PageTables =3D CreateIdentityMappingPageTables (BaseOfStack, STACK_SIZ= E, 0, 0); =20 // // End of PEI phase signal diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c b/MdeModulePkg/= Core/DxeIplPeim/X64/DxeLoadFunc.c index f465eb1d8ac4..156a477d8467 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c @@ -35,6 +35,8 @@ HandOffToDxeCore ( UINT32 Index; EFI_VECTOR_HANDOFF_INFO *VectorInfo; EFI_PEI_VECTOR_HANDOFF_INFO_PPI *VectorHandoffInfoPpi; + VOID *GhcbBase; + UINTN GhcbSize; =20 // // Clear page 0 and mark it as allocated if NULL pointer detection is en= abled. @@ -81,12 +83,19 @@ HandOffToDxeCore ( TopOfStack =3D (VOID *) ((UINTN) BaseOfStack + EFI_SIZE_TO_PAGES (STACK_= SIZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT); TopOfStack =3D ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT); =20 + // + // Get the address and size of the GHCB pages + // + GhcbBase =3D (VOID *) PcdGet64 (PcdGhcbBase); + GhcbSize =3D PcdGet64 (PcdGhcbSize); + PageTables =3D 0; if (FeaturePcdGet (PcdDxeIplBuildPageTables)) { // // Create page table and save PageMapLevel4 to CR3 // - PageTables =3D CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS)= (UINTN) BaseOfStack, STACK_SIZE); + PageTables =3D CreateIdentityMappingPageTables ((EFI_PHYSICAL_ADDRESS)= (UINTN) BaseOfStack, STACK_SIZE, + (EFI_PHYSICAL_ADDRESS) (= UINTN) GhcbBase, GhcbSize); } else { // // Set NX for stack feature also require PcdDxeIplBuildPageTables be T= RUE diff --git a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c b/MdeModulePk= g/Core/DxeIplPeim/X64/VirtualMemory.c index 516cf908bc88..32a81d1f3c21 100644 --- a/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c +++ b/MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c @@ -181,6 +181,8 @@ EnableExecuteDisableBit ( @param Size Size of the given physical memory. @param StackBase Base address of stack. @param StackSize Size of stack. + @param GhcbBase Base address of GHCB pages. + @param GhcbSize Size of GHCB area. =20 @retval TRUE Page table should be split. @retval FALSE Page table should not be split. @@ -190,7 +192,9 @@ ToSplitPageTable ( IN EFI_PHYSICAL_ADDRESS Address, IN UINTN Size, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { if (IsNullDetectionEnabled () && Address =3D=3D 0) { @@ -209,6 +213,12 @@ ToSplitPageTable ( } } =20 + if (GhcbBase) { + if ((Address < GhcbBase + GhcbSize) && ((Address + Size) > GhcbBase)) { + return TRUE; + } + } + return FALSE; } /** @@ -322,6 +332,8 @@ AllocatePageTableMemory ( @param[in, out] PageEntry2M Pointer to 2M page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -329,7 +341,9 @@ Split2MPageTo4K ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry2M, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { EFI_PHYSICAL_ADDRESS PhysicalAddress4K; @@ -355,7 +369,12 @@ Split2MPageTo4K ( // // Fill in the Page Table entries // - PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K | AddressEncMask; + PageTableEntry->Uint64 =3D (UINT64) PhysicalAddress4K; + if (!GhcbBase + || (PhysicalAddress4K < GhcbBase) + || (PhysicalAddress4K >=3D GhcbBase + GhcbSize)) { + PageTableEntry->Uint64 |=3D AddressEncMask; + } PageTableEntry->Bits.ReadWrite =3D 1; =20 if ((IsNullDetectionEnabled () && PhysicalAddress4K =3D=3D 0) || @@ -383,6 +402,8 @@ Split2MPageTo4K ( @param[in, out] PageEntry1G Pointer to 1G page entry. @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB page area base address. + @param[in] GhcbSize GHCB page area size. =20 **/ VOID @@ -390,7 +411,9 @@ Split1GPageTo2M ( IN EFI_PHYSICAL_ADDRESS PhysicalAddress, IN OUT UINT64 *PageEntry1G, IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { EFI_PHYSICAL_ADDRESS PhysicalAddress2M; @@ -413,11 +436,11 @@ Split1GPageTo2M ( =20 PhysicalAddress2M =3D PhysicalAddress; for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntries < 51= 2; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += =3D SIZE_2MB) { - if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e)) { + if (ToSplitPageTable (PhysicalAddress2M, SIZE_2MB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { // // Need to split this 2M page that covers NULL or stack range. // - Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize); + Split2MPageTo4K (PhysicalAddress2M, (UINT64 *) PageDirectoryEntry, S= tackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries @@ -616,6 +639,8 @@ EnablePageTableProtection ( =20 @param[in] StackBase Stack base address. @param[in] StackSize Stack size. + @param[in] GhcbBase GHCB base address. + @param[in] GhcbSize GHCB size. =20 @return The address of 4 level page map. =20 @@ -623,7 +648,9 @@ EnablePageTableProtection ( UINTN CreateIdentityMappingPageTables ( IN EFI_PHYSICAL_ADDRESS StackBase, - IN UINTN StackSize + IN UINTN StackSize, + IN EFI_PHYSICAL_ADDRESS GhcbBase, + IN UINTN GhcbSize ) { UINT32 RegEax; @@ -809,8 +836,8 @@ CreateIdentityMappingPageTables ( PageDirectory1GEntry =3D (VOID *) PageDirectoryPointerEntry; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntrie= s < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress= +=3D SIZE_1GB) { - if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e)) { - Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry,= StackBase, StackSize); + if (ToSplitPageTable (PageAddress, SIZE_1GB, StackBase, StackSiz= e, GhcbBase, GhcbSize)) { + Split1GPageTo2M (PageAddress, (UINT64 *) PageDirectory1GEntry,= StackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries @@ -840,11 +867,11 @@ CreateIdentityMappingPageTables ( PageDirectoryPointerEntry->Bits.Present =3D 1; =20 for (IndexOfPageDirectoryEntries =3D 0; IndexOfPageDirectoryEntr= ies < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress= +=3D SIZE_2MB) { - if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize)) { + if (ToSplitPageTable (PageAddress, SIZE_2MB, StackBase, StackS= ize, GhcbBase, GhcbSize)) { // // Need to split this 2M page that covers NULL or stack rang= e. // - Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry,= StackBase, StackSize); + Split2MPageTo4K (PageAddress, (UINT64 *) PageDirectoryEntry,= StackBase, StackSize, GhcbBase, GhcbSize); } else { // // Fill in the Page Directory entries --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: BZ6hv6XFGA6MRMYjWoGvJ6XTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190455; bh=69ymvdHfNxkhBHi2Kwa4rTjchffGSFA6mi3hJ6GT01Q=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=htQtBrIRZBdfXhik9+z8Xy0JApiJWQFfzZg8dWAOVOgRj9fI6tQZ8myCz0dy+ctujpF qFB3L/UNw+EmhUQrG8MAKD448bnscNgl3M9bhQmF4XsmaS8MkyZKOffPJ33T/V7DKaXBw YHD2AG1o6M4uJJcaFnuUoxMZ1Wuo43r0F2A= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID instruction requires the current value of the XCR0 register. In order to retrieve that value, the XGETBV instruction needs to be executed. Provide the necessary support to execute the XGETBV instruction. Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Include/Library/BaseLib.h | 17 +++++++++++++ MdePkg/Library/BaseLib/Ia32/GccInline.c | 28 ++++++++++++++++++++ MdePkg/Library/BaseLib/X64/GccInline.c | 30 ++++++++++++++++++++++ MdePkg/Library/BaseLib/Ia32/XGetBv.nasm | 31 ++++++++++++++++++++++ MdePkg/Library/BaseLib/X64/XGetBv.nasm | 34 +++++++++++++++++++++++++ 6 files changed, 142 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/XGetBv.nasm create mode 100644 MdePkg/Library/BaseLib/X64/XGetBv.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 3586beb0ab5c..d7a1dd017e95 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -152,6 +152,7 @@ [Sources.Ia32] Ia32/ARShiftU64.c | MSFT Ia32/EnableCache.c | MSFT Ia32/DisableCache.c | MSFT + Ia32/XGetBv.nasm | MSFT =20 =20 Ia32/GccInline.c | GCC @@ -286,6 +287,7 @@ [Sources.X64] X64/ReadCr2.nasm| MSFT X64/ReadCr0.nasm| MSFT X64/ReadEflags.nasm| MSFT + X64/XGetBv.nasm | MSFT =20 =20 X64/Non-existing.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index ecadff8b235e..d0cbb52ed8f9 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7889,6 +7889,23 @@ AsmLfence ( VOID ); =20 +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 = and + x64. + + @param[in] Index Extended control register index + + @retval The current value of the extended control regist= er +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ); + + /** Patch the immediate operand of an IA32 or X64 instruction such that the = byte, word, dword or qword operand is encoded at the end of the instruction's diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseL= ib/Ia32/GccInline.c index 5287200f8754..591f0bb0e097 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -1763,3 +1763,31 @@ AsmFlushCacheLine ( } =20 =20 +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 = and + x64. + + @param[in] Index Extended control register index + + @retval The current value of the extended control regist= er +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ) +{ + UINT64 Data; + + __asm__ __volatile__ ( + "xgetbv" + : "=3DA" (Data) + : "c" (Index) + ); + + return Data; +} + + diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLi= b/X64/GccInline.c index 154ce1f57e92..3eed1205adb2 100644 --- a/MdePkg/Library/BaseLib/X64/GccInline.c +++ b/MdePkg/Library/BaseLib/X64/GccInline.c @@ -1798,3 +1798,33 @@ AsmFlushCacheLine ( } =20 =20 +/** + Executes a XGETBV instruction + + Executes a XGETBV instruction. This function is only available on IA-32 = and + x64. + + @param[in] Index Extended control register index + + @retval The current value of the extended control regist= er +**/ +UINT64 +EFIAPI +AsmXGetBv ( + IN UINT32 Index + ) +{ + UINT32 LowData; + UINT32 HighData; + + __asm__ __volatile__ ( + "xgetbv" + : "=3Da" (LowData), + "=3Dd" (HighData) + : "c" (Index) + ); + + return (((UINT64)HighData) << 32) | LowData; +} + + diff --git a/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm b/MdePkg/Library/BaseL= ib/Ia32/XGetBv.nasm new file mode 100644 index 000000000000..b6dee38af029 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/XGetBv.nasm @@ -0,0 +1,31 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + mov ecx, [esp + 4] + xgetbv + ret diff --git a/MdePkg/Library/BaseLib/X64/XGetBv.nasm b/MdePkg/Library/BaseLi= b/X64/XGetBv.nasm new file mode 100644 index 000000000000..f3aec43e6813 --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/XGetBv.nasm @@ -0,0 +1,34 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; XGetBv.Asm +; +; Abstract: +; +; AsmXgetBv function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; UINT64 +; EFIAPI +; AsmXGetBv ( +; IN UINT32 Index +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmXGetBv) +ASM_PFX(AsmXGetBv): + xgetbv + shl rdx, 32 + or rax, rdx + ret + --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: KJSeKvU18YBsDsydP1JGfSImx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190456; bh=HI9d9g6InUelkC/eRCat/tYUOaBfMNy0pd4ByQCRNmU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=NAL8z69qZaXMCJozesNCQWA8XpN5y1B1sWUkovuNl8vFAkLT/StU2H3jBh2smRZm3yZ NE3Y89nF6Chn9LFoTpdaEwDaYrC8OTS0YYQpAEahuLbIqqYrwMGfsyKpbVPLVXkT75zY9 e4DfVZEZTM96O+lbI/tjeB62QBu3MswB9MY= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 VMGEXIT is a new instruction used for Hypervisor/Guest communication when running as an SEV-ES guest. A VMGEXIT will cause an automatic exit (AE) to occur, resulting in a #VMEXIT with an exit code value of 0x403. Provide the necessary support to execute the VMGEXIT instruction, which is "rep; vmmcall". Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Tom Lendacky --- MdePkg/Library/BaseLib/BaseLib.inf | 2 ++ MdePkg/Include/Library/BaseLib.h | 14 +++++++++ MdePkg/Library/BaseLib/Ia32/GccInline.c | 17 +++++++++++ MdePkg/Library/BaseLib/X64/GccInline.c | 17 +++++++++++ MdePkg/Library/BaseLib/Ia32/VmgExit.nasm | 37 ++++++++++++++++++++++++ MdePkg/Library/BaseLib/X64/VmgExit.nasm | 32 ++++++++++++++++++++ 6 files changed, 119 insertions(+) create mode 100644 MdePkg/Library/BaseLib/Ia32/VmgExit.nasm create mode 100644 MdePkg/Library/BaseLib/X64/VmgExit.nasm diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index d7a1dd017e95..62a09197b8a8 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -153,6 +153,7 @@ [Sources.Ia32] Ia32/EnableCache.c | MSFT Ia32/DisableCache.c | MSFT Ia32/XGetBv.nasm | MSFT + Ia32/VmgExit.nasm | MSFT =20 =20 Ia32/GccInline.c | GCC @@ -288,6 +289,7 @@ [Sources.X64] X64/ReadCr0.nasm| MSFT X64/ReadEflags.nasm| MSFT X64/XGetBv.nasm | MSFT + X64/VmgExit.nasm | MSFT =20 =20 X64/Non-existing.c diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index d0cbb52ed8f9..99fff8af5a3c 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -7906,6 +7906,20 @@ AsmXGetBv ( ); =20 =20 +/** + Executes a VMGEXIT instruction (VMMCALL with a REP prefix) + + Executes a VMGEXIT instruction. This function is only available on IA-32= and + x64. + +**/ +VOID +EFIAPI +AsmVmgExit ( + VOID + ); + + /** Patch the immediate operand of an IA32 or X64 instruction such that the = byte, word, dword or qword operand is encoded at the end of the instruction's diff --git a/MdePkg/Library/BaseLib/Ia32/GccInline.c b/MdePkg/Library/BaseL= ib/Ia32/GccInline.c index 591f0bb0e097..ee8c62c79c93 100644 --- a/MdePkg/Library/BaseLib/Ia32/GccInline.c +++ b/MdePkg/Library/BaseLib/Ia32/GccInline.c @@ -1791,3 +1791,20 @@ AsmXGetBv ( } =20 =20 +/** + Executes a VMGEXIT instruction. + + Executes a VMGEXIT instruction. This function is only available on IA-32= and + X64. + +**/ +VOID +EFIAPI +AsmVmgExit ( + VOID + ) +{ + __asm__ __volatile__ ("rep; vmmcall":::"memory"); +} + + diff --git a/MdePkg/Library/BaseLib/X64/GccInline.c b/MdePkg/Library/BaseLi= b/X64/GccInline.c index 3eed1205adb2..277974eff9ee 100644 --- a/MdePkg/Library/BaseLib/X64/GccInline.c +++ b/MdePkg/Library/BaseLib/X64/GccInline.c @@ -1828,3 +1828,20 @@ AsmXGetBv ( } =20 =20 +/** + Executes a VMGEXIT instruction. + + Executes a VMGEXIT instruction. This function is only available on IA-32= and + X64. + +**/ +VOID +EFIAPI +AsmVmgExit ( + VOID + ) +{ + __asm__ __volatile__ ("rep; vmmcall":::"memory"); +} + + diff --git a/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm b/MdePkg/Library/Base= Lib/Ia32/VmgExit.nasm new file mode 100644 index 000000000000..cdf727825400 --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/VmgExit.nasm @@ -0,0 +1,37 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; VmgExit.Asm +; +; Abstract: +; +; AsmVmgExit function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; AsmVmgExit ( +; VOID +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmVmgExit) +ASM_PFX(AsmVmgExit): +; +; NASM doesn't support the vmmcall instruction in 32-bit mode, so work aro= und +; this by temporarily switching to 64-bit mode. +; +BITS 64 + rep vmmcall +BITS 32 + ret + diff --git a/MdePkg/Library/BaseLib/X64/VmgExit.nasm b/MdePkg/Library/BaseL= ib/X64/VmgExit.nasm new file mode 100644 index 000000000000..6537a97b273c --- /dev/null +++ b/MdePkg/Library/BaseLib/X64/VmgExit.nasm @@ -0,0 +1,32 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; VmgExit.Asm +; +; Abstract: +; +; AsmVmgExit function +; +; Notes: +; +;-------------------------------------------------------------------------= ----- + + DEFAULT REL + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; AsmVmgExit ( +; VOID +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(AsmVmgExit) +ASM_PFX(AsmVmgExit): + rep vmmcall + ret + --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: TaTNS9wmlrIsW5bJIK8B97kYx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190457; bh=j6y/I5ESQMlPUtES8EiO44pfdwKYeIWlOL6NRZ77+/o=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=dFYcfeObiDoM5hNYQHlFqXqt5ZRQ9s3yq9XHvDfcmRRyfe8Z4RXk8j1hnBX8PJrko8P IPQwXfp/MiZysxZX9qHkzZ9IYP1EQReo2X7a3nbGFE+8OcqB0vB32v2+Cxwo2UuTuRSPk Qvp5r7rxjlrxrr486gZ7tltVNgyiyYJl7UE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 To support issuing a VMGEXIT instruction, create a library that can be used to perform GHCB and VMGEXIT related operations and to issue the actual VMGEXIT instruction when using the GHCB. Additionally, two VMGEXIT / MMIO related functions are created to support flash emulation. Flash emulation currently is done by marking the flash area as read-only and taking a nested page fault to perform the emulation of the instruction. However, emulation cannot be performed because there is no instruction decode assist support when SEV-ES is enabled. Provide routines to initiate an MMIO request to perform actual writes to flash. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Acked-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/UefiCpuPkg.dec | 3 + UefiCpuPkg/UefiCpuPkg.dsc | 2 + UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf | 33 +++ UefiCpuPkg/Include/Library/VmgExitLib.h | 111 +++++++++ UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c | 243 +++++++++++++++++++ UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni | 15 ++ 6 files changed, 407 insertions(+) create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf create mode 100644 UefiCpuPkg/Include/Library/VmgExitLib.h create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c create mode 100644 UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 2f30bf89615f..795d1c8dedba 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -53,6 +53,9 @@ [LibraryClasses.IA32, LibraryClasses.X64] ## MpInitLib|Include/Library/MpInitLib.h =20 + ## @libraryclass Provides function to support VMGEXIT processing. + VmgExitLib|Include/Library/VmgExitLib.h + [Guids] gUefiCpuPkgTokenSpaceGuid =3D { 0xac05bf33, 0x995a, 0x4ed4, { 0xaa,= 0xb8, 0xef, 0x7a, 0xe8, 0xf, 0x5c, 0xb0 }} gMsegSmramGuid =3D { 0x5802bce4, 0xeeee, 0x4e33, { 0xa1,= 0x30, 0xeb, 0xad, 0x27, 0xf0, 0xe4, 0x39 }} diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index d28cb5cccb52..997840452218 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -56,6 +56,7 @@ [LibraryClasses] PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem= entLibNull.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] PlatformSecLib|UefiCpuPkg/Library/PlatformSecLibNull/PlatformSecLibNull.= inf @@ -136,6 +137,7 @@ [Components.IA32, Components.X64] UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/SmmCpuPlatformHookLibNull.i= nf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.inf UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLibStm.inf + UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf UefiCpuPkg/SecCore/SecCore.inf diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf b/UefiCpuPkg/Libr= ary/VmgExitLib/VmgExitLib.inf new file mode 100644 index 000000000000..6acfa779e75a --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf @@ -0,0 +1,33 @@ +## @file +# VMGEXIT Support Library. +# +# Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D VmgExitLib + MODULE_UNI_FILE =3D VmgExitLib.uni + FILE_GUID =3D 3cd7368f-ef9b-4a9b-9571-2ed93813677e + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D VmgExitLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +[Sources] + VmgExitLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + diff --git a/UefiCpuPkg/Include/Library/VmgExitLib.h b/UefiCpuPkg/Include/L= ibrary/VmgExitLib.h new file mode 100644 index 000000000000..602b213f1f63 --- /dev/null +++ b/UefiCpuPkg/Include/Library/VmgExitLib.h @@ -0,0 +1,111 @@ +/** @file + Public header file for the VMGEXIT Support library class. + + This library class defines some routines used when invoking the VMGEXIT + instruction in support of SEV-ES. + + Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __VMG_EXIT_LIB_H__ +#define __VMG_EXIT_LIB_H__ + +#include + + +/** + Perform VMGEXIT. + + Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction a= nd + then handles the return actions. + + @param[in] GHCB A pointer to the GHCB + @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode fie= ld of + the GHCB. + @param[in] ExitInfo1 VMGEXIT information to be assigned to the SwExitI= nfo1 + field of the GHCB. + @param[in] ExitInfo2 VMGEXIT information to be assigned to the SwExitI= nfo2 + field of the GHCB. + + @retval 0 VMGEXIT succeeded. + @retval Others VMGEXIT processing did not succeed. Exception number to + be issued. + +**/ +UINTN +EFIAPI +VmgExit ( + GHCB *Ghcb, + UINT64 ExitCode, + UINT64 ExitInfo1, + UINT64 ExitInfo2 + ); + +/** + Perform pre-VMGEXIT initialization/preparation. + + Performs the necessary steps in preparation for invoking VMGEXIT. + + @param[in] GHCB A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgInit ( + GHCB *Ghcb + ); + +/** + Perform post-VMGEXIT cleanup. + + Performs the necessary steps to cleanup after invoking VMGEXIT. + + @param[in] GHCB A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgDone ( + GHCB *Ghcb + ); + +#define VMGMMIO_READ False +#define VMGMMIO_WRITE True + +/** + Perform MMIO write of a buffer to a non-MMIO marked range. + + Performs an MMIO write without taking a #VC. This is useful + for Flash devices, which are marked read-only. + + @param[in] UINT8 A pointer to the destination buffer + @param[in] UINTN The immediate value to write + @param[in] UINTN Number of bytes to write + +**/ +VOID +EFIAPI +VmgMmioWrite ( + UINT8 *Dest, + UINT8 *Src, + UINTN Bytes + ); + +/** + Issue the GHCB set AP Jump Table VMGEXIT. + + Performs a VMGEXIT using the GHCB AP Jump Table exit code to save the + AP Jump Table address with the hypervisor for retrieval at a later time. + + @param[in] EFI_PHYSICAL_ADDRESS Physical address of the AP Jump Table + +**/ +UINTN +EFIAPI +VmgExitSetAPJumpTable ( + EFI_PHYSICAL_ADDRESS Address + ); + +#endif diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c b/UefiCpuPkg/Librar= y/VmgExitLib/VmgExitLib.c new file mode 100644 index 000000000000..6afff51ad06b --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.c @@ -0,0 +1,243 @@ +/** @file + VMGEXIT Support Library. + + Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +STATIC +UINT64 +VmgExitErrorCheck ( + GHCB *Ghcb + ) +{ + GHCB_EVENT_INJECTION Event; + GHCB_EXIT_INFO ExitInfo; + UINT64 Status; + + ExitInfo.Uint64 =3D Ghcb->SaveArea.SwExitInfo1; + ASSERT ((ExitInfo.Elements.Lower32Bits =3D=3D 0) || + (ExitInfo.Elements.Lower32Bits =3D=3D 1)); + + Status =3D 0; + if (ExitInfo.Elements.Lower32Bits =3D=3D 0) { + return Status; + } + + if (ExitInfo.Elements.Lower32Bits =3D=3D 1) { + ASSERT (Ghcb->SaveArea.SwExitInfo2 !=3D 0); + + // Check that the return event is valid + Event.Uint64 =3D Ghcb->SaveArea.SwExitInfo2; + if (Event.Elements.Valid && + Event.Elements.Type =3D=3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION) { + switch (Event.Elements.Vector) { + case GP_EXCEPTION: + case UD_EXCEPTION: + // Use returned event as return code + Status =3D Event.Uint64; + } + } + } + + if (Status =3D=3D 0) { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D 0; + Event.Elements.Vector =3D GP_EXCEPTION; + Event.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid =3D 1; + + Status =3D Event.Uint64; + } + + return Status; +} + +/** + Perform VMGEXIT. + + Sets the necessary fields of the GHCB, invokes the VMGEXIT instruction a= nd + then handles the return actions. + + @param[in] GHCB A pointer to the GHCB + @param[in] ExitCode VMGEXIT code to be assigned to the SwExitCode fie= ld of + the GHCB. + @param[in] ExitInfo1 VMGEXIT information to be assigned to the SwExitI= nfo1 + field of the GHCB. + @param[in] ExitInfo2 VMGEXIT information to be assigned to the SwExitI= nfo2 + field of the GHCB. + + @retval 0 VMGEXIT succeeded. + @retval Others VMGEXIT processing did not succeed. Exception number to + be issued. + +**/ +UINT64 +EFIAPI +VmgExit ( + GHCB *Ghcb, + UINT64 ExitCode, + UINT64 ExitInfo1, + UINT64 ExitInfo2 + ) +{ + Ghcb->SaveArea.SwExitCode =3D ExitCode; + Ghcb->SaveArea.SwExitInfo1 =3D ExitInfo1; + Ghcb->SaveArea.SwExitInfo2 =3D ExitInfo2; + + // + // Guest memory is used for the guest-hypervisor communication, so fence + // the invocation of the VMGEXIT instruction to ensure GHCB accesses are + // synchronized properly. + // + MemoryFence (); + AsmVmgExit (); + MemoryFence (); + + return VmgExitErrorCheck (Ghcb); +} + +/** + Perform pre-VMGEXIT initialization/preparation. + + Performs the necessary steps in preparation for invoking VMGEXIT. + + @param[in] GHCB A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgInit ( + GHCB *Ghcb + ) +{ + SetMem (&Ghcb->SaveArea, sizeof (Ghcb->SaveArea), 0); +} + +/** + Perform post-VMGEXIT cleanup. + + Performs the necessary steps to cleanup after invoking VMGEXIT. + + @param[in] GHCB A pointer to the GHCB + +**/ +VOID +EFIAPI +VmgDone ( + GHCB *Ghcb + ) +{ +} + +STATIC +UINTN +EFIAPI +VmgMmio ( + UINT8 *MmioAddress, + UINT8 *Buffer, + UINTN Bytes, + BOOLEAN Write + ) +{ + UINT64 MmioOp, ExitInfo1, ExitInfo2, Status; + GHCB *Ghcb; + MSR_SEV_ES_GHCB_REGISTER Msr; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + + if (Write) { + MmioOp =3D SvmExitMmioWrite; + } else { + MmioOp =3D SvmExitMmioRead; + } + + ExitInfo1 =3D (UINT64) (UINTN) MmioAddress; + ExitInfo2 =3D Bytes; + + if (Write) { + CopyMem (Ghcb->SharedBuffer, Buffer, Bytes); + } + + Ghcb->SaveArea.SwScratch =3D (UINT64) (UINTN) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, MmioOp, ExitInfo1, ExitInfo2); + if (Status !=3D 0) { + return Status; + } + + if (!Write) { + CopyMem (Buffer, Ghcb->SharedBuffer, Bytes); + } + + VmgDone (Ghcb); + + return 0; +} + +/** + Perform MMIO write of a buffer to a non-MMIO marked range. + + Performs an MMIO write without taking a #VC. This is useful + for Flash devices, which are marked read-only. + + @param[in] UINT8 A pointer to the destination buffer + @param[in] UINTN The immediate value to write + @param[in] UINTN Number of bytes to write + +**/ +VOID +EFIAPI +VmgMmioWrite ( + UINT8 *Dest, + UINT8 *Src, + UINTN Bytes + ) +{ + VmgMmio (Dest, Src, Bytes, TRUE); +} + +/** + Issue the GHCB set AP Jump Table VMGEXIT. + + Performs a VMGEXIT using the GHCB AP Jump Table exit code to save the + AP Jump Table address with the hypervisor for retrieval at a later time. + + @param[in] EFI_PHYSICAL_ADDRESS Physical address of the AP Jump Table + +**/ +UINTN +EFIAPI +VmgExitSetAPJumpTable ( + EFI_PHYSICAL_ADDRESS Address + ) +{ + UINT64 ExitInfo1, ExitInfo2, Status; + GHCB *Ghcb; + MSR_SEV_ES_GHCB_REGISTER Msr; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + + ExitInfo1 =3D 0; + ExitInfo2 =3D (UINT64) (UINTN) Address; + + Status =3D VmgExit (Ghcb, SvmExitApJumpTable, ExitInfo1, ExitInfo2); + + VmgDone (Ghcb); + + return Status; +} + diff --git a/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni b/UefiCpuPkg/Libr= ary/VmgExitLib/VmgExitLib.uni new file mode 100644 index 000000000000..e8656aae4726 --- /dev/null +++ b/UefiCpuPkg/Library/VmgExitLib/VmgExitLib.uni @@ -0,0 +1,15 @@ +// /** @file +// VMGEXIT support library instance. +// +// VMGEXIT support library instance. +// +// Copyright (c) 2019, Advanced Micro Devices, Inc. All rights reserved. +// SPDX-License-Identifier: BSD-2-Clause-Patent +// +// **/ + + +#string STR_MODULE_ABSTRACT #language en-US "VMGEXIT Support L= ibrary." + +#string STR_MODULE_DESCRIPTION #language en-US "VMGEXIT Support L= ibrary." + --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: XpkWdTz0kAFzoI8KXuo4j9rXx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190458; bh=YVdW7cbg/oheAaeKh6ta03WWrHMVX5npFujceYaKXQ4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ZWan4yt3IJXixXnBlJ5Uv4RL1ZfiMYuEpK2w37p3R3QEoqLvaUMkjMH0+GORGZ3Fmbl gKYYyHwAaUvk6FqZhkxkJ81xI3hgsY/Oeb4LZYnWBtYv+MbcjGcVyliAVIWLF2zp1H0ph F51HJ7NDF7wVoDv81BbTe8Y1f3MhGbXpZkU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Various CpuExceptionHandlerLib libraries will updated to use the new VmgExitLib library. To prevent any build breakage, update the OvmfPkg DSC files that use a form of the CpuExceptionHandlerLib library to include the VmgExitLib library. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Signed-off-by: Tom Lendacky Reviewed-by: Laszlo Ersek --- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/OvmfXen.dsc | 1 + 4 files changed, 4 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 19728f20b34e..c842404287dc 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -217,6 +217,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 3c0c229e3a72..c082617be9d8 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -222,6 +222,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index f6c1d8d228c6..d3a96e5a7be6 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -222,6 +222,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] TimerLib|OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.inf diff --git a/OvmfPkg/OvmfXen.dsc b/OvmfPkg/OvmfXen.dsc index 5751ff1f0352..b86129dd092a 100644 --- a/OvmfPkg/OvmfXen.dsc +++ b/OvmfPkg/OvmfXen.dsc @@ -204,6 +204,7 @@ [LibraryClasses] =20 [LibraryClasses.common] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.SEC] QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgSecLib.inf --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55248): https://edk2.groups.io/g/devel/message/55248 Mute This Topic: https://groups.io/mt/71687798/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55249+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190460235618.0635700946624; Mon, 2 Mar 2020 15:07:40 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 1GxKYY1788612xVV3QbJ90WI; Mon, 02 Mar 2020 15:07:39 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com [40.107.220.48]) by mx.groups.io with SMTP id smtpd.web09.720.1583190458696058256 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:37 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:37 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 09/42] UefiPayloadPkg: Prepare UefiPayloadPkg to use the VmgExitLib library Date: Mon, 2 Mar 2020 17:06:40 -0600 Message-Id: <462f2f48d90ad32710daacc8108d5275d87454d1.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: nOAAaZ4GwS0tBazojDl22gG1x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190459; bh=FJdr/IUHPJiQz/NxS9+rK76KZsaO96wYKwEnJV/Jwh4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=KeyFWiUMDenOGTVbEOXTUNbaGwXEWGTcZX1f/v2HPY+aaXDJdzWImsI+LtxlXLJO4ye 8X9qLLKufdziD1caS7kxTN5Ft9zZkndiclBfG9tu/Um4Pr2Wkyj5n5n+KFqW90uWmCJfn us+wgOgLL0ROruVY0U1LSNVVdIUEwX3oBWI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Various CpuExceptionHandlerLib libraries will updated to use the new VmgExitLib library. To prevent any build breakage, update the UefiPayloadPkg DSC files that use a form of the CpuExceptionHandlerLib library to include the VmgExitLib library. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Signed-off-by: Tom Lendacky Reviewed-by: Guo Dong --- UefiPayloadPkg/UefiPayloadPkgIa32.dsc | 2 ++ UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc | 2 ++ 2 files changed, 4 insertions(+) diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc b/UefiPayloadPkg/UefiPay= loadPkgIa32.dsc index d52945442e0e..c2f7217c964e 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32.dsc @@ -233,6 +233,7 @@ [LibraryClasses.common.DXE_CORE] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -244,6 +245,7 @@ [LibraryClasses.common.DXE_DRIVER] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] diff --git a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc b/UefiPayloadPkg/Uefi= PayloadPkgIa32X64.dsc index 0736cd995476..b7cfeeff9b49 100644 --- a/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc +++ b/UefiPayloadPkg/UefiPayloadPkgIa32X64.dsc @@ -234,6 +234,7 @@ [LibraryClasses.common.DXE_CORE] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.DXE_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf @@ -245,6 +246,7 @@ [LibraryClasses.common.DXE_DRIVER] DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf !endif CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuE= xceptionHandlerLib.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf =20 [LibraryClasses.common.DXE_RUNTIME_DRIVER] --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:07:37 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: a99facc7-b420-424a-1e18-08d7befe80a0 X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4502; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55250+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: qqWx/deFas7BGn5hiXY7Uiyvwjr2yNcDu1eSkBZVYnF9sGKYR7kkCjNx4bB3tnwZa0Rpqw5+24yc0Jgb70RUb3456qcwyHu9EpMAXc0cFbEI/kXPF49mFynhcNJepkaapAGbdTy/kHkujnoVF3ErclIu2lr7+45s9Pw5usvAolKAzFQZtxj0V3O8/rMQWr9bgRFBLZCE8zZLYyuYPk4GwycgXsjR7p06UrPhziGoDSWJNMDvwzcFc3ckZAXIFEA3ycwQIYmYhtljDpJDmELpqSPzqwpUpqLivNHOs5qX50YhO2fpbMPVpwz5v1zqAIRxGVuXUUMKaymwTCnRZ+t5kiCUmKIsTXXu/pvBvZg1AOIRbb99t0kh/WHHy6Xrua+rqytMulaAHI+7M6COcd6F+0jptFo2lqWeJjCw0ip2PsnI3v3kPA9Fwor9Bkbwz4DtGR/3maRPVWRWLKPwjcwq1RclD9gR3pkxmrygRc+q0KMRzxyVETYAHzFU/3xv+gwSvMqxGmOxce57ot/xLJFkFA== X-MS-Exchange-AntiSpam-MessageData: jAffJbJqxTgJxCkMExcjkPyHbevpA+CKKM7pXcIMMEfNYObEDgEPGAaE62Nph9NTqJmDF2aJvwUq0LVZwUqq/aD5/1xfKHbnTA6iwitFQJePCCqq1Q75OBRuKDg2rCBH9QU3t6jQRWJdsj8cheGtVw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a99facc7-b420-424a-1e18-08d7befe80a0 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:38.7530 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: rRwFixNdgdRl1ckW/OARpiil90XT8gVGCQp9BkxuHf8+z3g+KlORcwt9/2cuf4Ba7aHFvG799eg0zT78oS3//g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: QEjurBMj3BaHqjYJWFcvNadXx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190460; bh=zPrTJpnrL9QY9GsA3x6EZCD6Yl4gndRmVHx7m8vjRmM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=etBodoeEt4XFdAk1RwG+euPYKUdQ9TpO1O4gSfEYw5HfUwt9+F6AaVVdqmXkwHgjNrs 31Gb/rhnQgcuir9WOpf1ZkWdPcRAEUeGSdE82n15zDKBVapZRuFG8ERCGLK3gJDLoVd84 3FsPh3kvHf5T08j0X5JhnXQq4Essl2EwMX8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Add base support to handle #VC exceptions. This includes a stub routine to invoke when a #VC exception occurs and special checks in the common exception handlers to invoke the #VC exception handler routine. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Jordan Justen Cc: Ard Biesheuvel Cc: Maurice Ma Cc: Guo Dong Cc: Benjamin You Signed-off-by: Tom Lendacky --- .../DxeCpuExceptionHandlerLib.inf | 5 ++ .../PeiCpuExceptionHandlerLib.inf | 5 ++ .../SecPeiCpuExceptionHandlerLib.inf | 5 ++ .../SmmCpuExceptionHandlerLib.inf | 5 ++ .../CpuExceptionHandlerLib/AMDSevVcCommon.h | 26 ++++++++++ .../CpuExceptionCommon.h | 2 + .../CpuExceptionHandlerLib/AMDSevVcHandler.c | 29 +++++++++++ .../CpuExceptionCommon.c | 2 +- .../Ia32/ArchAMDSevVcHandler.c | 24 +++++++++ .../PeiDxeSmmCpuException.c | 16 ++++++ .../SecPeiCpuException.c | 16 ++++++ .../X64/ArchAMDSevVcHandler.c | 50 +++++++++++++++++++ 12 files changed, 184 insertions(+), 1 deletion(-) create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommo= n.h create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcHandl= er.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchAMDS= evVcHandler.c create mode 100644 UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSe= vVcHandler.c diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandle= rLib.inf index e41383573043..4d79c4910b18 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/DxeCpuExceptionHandlerLib.i= nf @@ -26,17 +26,21 @@ [Sources.Ia32] Ia32/ExceptionTssEntryAsm.nasm Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h + Ia32/ArchAMDSevVcHandler.c =20 [Sources.X64] X64/ExceptionHandlerAsm.nasm X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h + X64/ArchAMDSevVcHandler.c =20 [Sources.common] CpuExceptionCommon.h CpuExceptionCommon.c PeiDxeSmmCpuException.c DxeException.c + AMDSevVcHandler.c + AMDSevVcCommon.h =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard @@ -57,3 +61,4 @@ [LibraryClasses] PeCoffGetEntryPointLib MemoryAllocationLib DebugLib + VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandle= rLib.inf index f31423ac0f91..e8445e47eaa3 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.i= nf @@ -26,17 +26,21 @@ [Sources.Ia32] Ia32/ExceptionTssEntryAsm.nasm Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h + Ia32/ArchAMDSevVcHandler.c =20 [Sources.X64] X64/ExceptionHandlerAsm.nasm X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h + X64/ArchAMDSevVcHandler.c =20 [Sources.common] CpuExceptionCommon.h CpuExceptionCommon.c PeiCpuException.c PeiDxeSmmCpuException.c + AMDSevVcHandler.c + AMDSevVcCommon.h =20 [Packages] MdePkg/MdePkg.dec @@ -52,6 +56,7 @@ [LibraryClasses] HobLib MemoryAllocationLib SynchronizationLib + VmgExitLib =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard # CONSUMES diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHa= ndlerLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException= HandlerLib.inf index 6d25cafe2ca3..a15bf71b4052 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuExceptionHandlerLi= b.inf @@ -26,16 +26,20 @@ [Sources.Ia32] Ia32/ExceptionTssEntryAsm.nasm Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h + Ia32/ArchAMDSevVcHandler.c =20 [Sources.X64] X64/ExceptionHandlerAsm.nasm X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h + X64/ArchAMDSevVcHandler.c =20 [Sources.common] CpuExceptionCommon.h CpuExceptionCommon.c SecPeiCpuException.c + AMDSevVcHandler.c + AMDSevVcCommon.h =20 [Packages] MdePkg/MdePkg.dec @@ -48,3 +52,4 @@ [LibraryClasses] PrintLib LocalApicLib PeCoffGetEntryPointLib + VmgExitLib diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandl= erLib.inf b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandle= rLib.inf index 66c7f59e3c91..190d7dfcd42a 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SmmCpuExceptionHandlerLib.i= nf @@ -26,17 +26,21 @@ [Sources.Ia32] Ia32/ExceptionTssEntryAsm.nasm Ia32/ArchExceptionHandler.c Ia32/ArchInterruptDefs.h + Ia32/ArchAMDSevVcHandler.c =20 [Sources.X64] X64/ExceptionHandlerAsm.nasm X64/ArchExceptionHandler.c X64/ArchInterruptDefs.h + X64/ArchAMDSevVcHandler.c =20 [Sources.common] CpuExceptionCommon.h CpuExceptionCommon.c PeiDxeSmmCpuException.c SmmException.c + AMDSevVcHandler.c + AMDSevVcCommon.h =20 [Packages] MdePkg/MdePkg.dec @@ -51,4 +55,5 @@ [LibraryClasses] LocalApicLib PeCoffGetEntryPointLib DebugLib + VmgExitLib =20 diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h b/U= efiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h new file mode 100644 index 000000000000..bdfe716bd8a3 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcCommon.h @@ -0,0 +1,26 @@ +/** @file + Common header file for SEV-ES #VC Exception Handler Support. + + Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _AMD_SEV_VC_COMMON_H_ +#define _AMD_SEV_VC_COMMON_H_ + +#include +#include + +UINTN +DoVcException( + EFI_SYSTEM_CONTEXT Context + ); + +UINTN +DoVcCommon( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT Context + ); + +#endif diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h index 805dd9cbb4ff..0f274e7ea328 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h @@ -24,6 +24,8 @@ #define CPU_INTERRUPT_NUM 256 #define HOOKAFTER_STUB_SIZE 16 =20 +#define VC_EXCEPTION 29 + // // Exception Error Code of Page-Fault Exception // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcHandler.c b/= UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcHandler.c new file mode 100644 index 000000000000..e079a3558714 --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/AMDSevVcHandler.c @@ -0,0 +1,29 @@ +/** @file + SEV-ES #VC Exception Handler functon. + + Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "CpuExceptionCommon.h" +#include "AMDSevVcCommon.h" + +UINTN +DoVcException ( + EFI_SYSTEM_CONTEXT Context + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + ASSERT(Msr.GhcbInfo.Function =3D=3D 0); + ASSERT(Msr.Ghcb !=3D 0); + + Ghcb =3D Msr.Ghcb; + + return DoVcCommon (Ghcb, Context); +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c index 8adbd43fefb4..39e4dd9e9417 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.c @@ -14,7 +14,7 @@ // // 1 means an error code will be pushed, otherwise 0 // -CONST UINT32 mErrorCodeFlag =3D 0x00227d00; +CONST UINT32 mErrorCodeFlag =3D 0x20227d00; =20 // // Define the maximum message length diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchAMDSevVcHan= dler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchAMDSevVcHandler= .c new file mode 100644 index 000000000000..bb00316e5cfb --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchAMDSevVcHandler.c @@ -0,0 +1,24 @@ +/** @file + IA32 SEV-ES #VC Exception Handler functons. + + Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include "AMDSevVcCommon.h" + +UINTN +DoVcCommon ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT Context + ) +{ + EFI_SYSTEM_CONTEXT_IA32 *Regs =3D Context.SystemContextIa32; + + Regs->ExceptionData =3D 0; + + return GP_EXCEPTION; +} diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuExceptio= n.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c index 6a2670d55918..4a60c3b6ae6e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiDxeSmmCpuException.c @@ -7,6 +7,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent **/ =20 #include "CpuExceptionCommon.h" +#include "AMDSevVcCommon.h" #include =20 /** @@ -86,6 +87,21 @@ CommonExceptionHandlerWorker ( break; } =20 + if (ExceptionType =3D=3D VC_EXCEPTION) { + UINTN Status; + // + // #VC must be handled for an SEV-ES guest + // + Status =3D DoVcException(SystemContext); + if (Status) { + // Exception not handled - Status contains the desired exception now + ExceptionType =3D Status; + } else { + // Exception handled + return; + } + } + if (ExternalInterruptHandler !=3D NULL && ExternalInterruptHandler[ExceptionType] !=3D NULL) { (ExternalInterruptHandler[ExceptionType]) (ExceptionType, SystemContex= t); diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c= b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c index 20148db74cf8..998a90ba61a6 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/SecPeiCpuException.c @@ -8,6 +8,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include #include "CpuExceptionCommon.h" +#include "AMDSevVcCommon.h" =20 CONST UINTN mDoFarReturnFlag =3D 0; =20 @@ -24,6 +25,21 @@ CommonExceptionHandler ( IN EFI_SYSTEM_CONTEXT SystemContext ) { + if (ExceptionType =3D=3D VC_EXCEPTION) { + UINTN Status; + // + // #VC must be handled for an SEV-ES guest + // + Status =3D DoVcException(SystemContext); + if (Status) { + // Exception not handled - Status contains the desired exception now + ExceptionType =3D Status; + } else { + // Exception handled + return; + } + } + // // Initialize the serial port before dumping. // diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c new file mode 100644 index 000000000000..7cbf89d9b1aa --- /dev/null +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -0,0 +1,50 @@ +/** @file + X64 SEV-ES #VC Exception Handler functons. + + Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include "AMDSevVcCommon.h" + +UINTN +DoVcCommon ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT Context + ) +{ + EFI_SYSTEM_CONTEXT_X64 *Regs =3D Context.SystemContextX64; + UINT64 Status; + UINTN ExitCode, VcRet; + + VmgInit (Ghcb); + + ExitCode =3D Regs->ExceptionData; + switch (ExitCode) { + default: + Status =3D VmgExit (Ghcb, SvmExitUnsupported, ExitCode, 0); + if (Status =3D=3D 0) { + Regs->ExceptionData =3D 0; + VcRet =3D GP_EXCEPTION; + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D Status; + if (Event.Elements.ErrorCodeValid) { + Regs->ExceptionData =3D Event.Elements.ErrorCode; + } else { + Regs->ExceptionData =3D 0; + } + + VcRet =3D Event.Elements.Vector; + } + } + + VmgDone (Ghcb); + + return VcRet; +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: iyJnoefQLt4nKw6Y8j0GFwRQx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190461; bh=v4C/G8ySKMGReH9nZzpgKV3Wzl5+9ZIkCe9FnVHO0vM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=EC5vGD9/DbTC+Q+7fCLfswTWzBfN+idWkNL1iNcDHwS1oya4iQJqegzn9XKGVbHAs1c 3ARGOLmJ4v24tXvhFBtN43WE13Go1J+QlvkqcIkb37x5ZSh63jmSpEn+j6dNvZOE+fkmo 7JFbCVzRQ7dkQboE2M1Snbm4nsLd6SDBtzs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a IOIO_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a IOIO_PROT NAE event. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXITINFO1 value in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 463 +++++++++++++++++- 1 file changed, 449 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 7cbf89d9b1aa..eb7b776859c1 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -11,6 +11,431 @@ #include #include "AMDSevVcCommon.h" =20 +typedef enum { + LongMode64Bit =3D 0, + LongModeCompat32Bit, + LongModeCompat16Bit, +} SEV_ES_INSTRUCTION_MODE; + +typedef enum { + Size8Bits =3D 0, + Size16Bits, + Size32Bits, + Size64Bits, +} SEV_ES_INSTRUCTION_SIZE; + +typedef enum { + SegmentEs =3D 0, + SegmentCs, + SegmentSs, + SegmentDs, + SegmentFs, + SegmentGs, +} SEV_ES_INSTRUCTION_SEGMENT; + +typedef enum { + RepNone =3D 0, + RepZ, + RepNZ, +} SEV_ES_INSTRUCTION_REP; + +typedef union { + struct { + UINT8 B:1; + UINT8 X:1; + UINT8 R:1; + UINT8 W:1; + UINT8 REX:4; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_REX_PREFIX; + +typedef union { + struct { + UINT8 Rm:3; + UINT8 Reg:3; + UINT8 Mod:2; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_MODRM; + +typedef union { + struct { + UINT8 Base:3; + UINT8 Index:3; + UINT8 Scale:2; + } Bits; + + UINT8 Uint8; +} SEV_ES_INSTRUCTION_SIB; + +typedef struct { + struct { + UINT8 Rm; + UINT8 Reg; + UINT8 Mod; + } ModRm; + + struct { + UINT8 Base; + UINT8 Index; + UINT8 Scale; + } Sib; + + UINTN RegData; + UINTN RmData; +} SEV_ES_INSTRUCTION_OPCODE_EXT; + +typedef struct { + GHCB *Ghcb; + + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE DataSize; + SEV_ES_INSTRUCTION_SIZE AddrSize; + BOOLEAN SegmentSpecified; + SEV_ES_INSTRUCTION_SEGMENT Segment; + SEV_ES_INSTRUCTION_REP RepMode; + + UINT8 *Begin; + UINT8 *End; + + UINT8 *Prefixes; + UINT8 *OpCodes; + UINT8 *Displacement; + UINT8 *Immediate; + + SEV_ES_INSTRUCTION_REX_PREFIX RexPrefix; + + BOOLEAN ModRmPresent; + SEV_ES_INSTRUCTION_MODRM ModRm; + + BOOLEAN SibPresent; + SEV_ES_INSTRUCTION_SIB Sib; + + UINT8 PrefixSize; + UINT8 OpCodeSize; + UINT8 DisplacementSize; + UINT8 ImmediateSize; + + SEV_ES_INSTRUCTION_OPCODE_EXT Ext; +} SEV_ES_INSTRUCTION_DATA; + +typedef +UINT64 +(*NAE_EXIT) ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ); + + +STATIC +BOOLEAN +GhcbIsRegValid ( + GHCB *Ghcb, + GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex =3D Reg / 8; + UINT32 RegBit =3D Reg & 0x07; + + return (Ghcb->SaveArea.ValidBitmap[RegIndex] & (1 << RegBit)); +} + +STATIC +VOID +GhcbSetRegValid ( + GHCB *Ghcb, + GHCB_REGISTER Reg + ) +{ + UINT32 RegIndex =3D Reg / 8; + UINT32 RegBit =3D Reg & 0x07; + + Ghcb->SaveArea.ValidBitmap[RegIndex] |=3D (1 << RegBit); +} + +STATIC +VOID +DecodePrefixes ( + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_MODE Mode; + SEV_ES_INSTRUCTION_SIZE ModeDataSize; + SEV_ES_INSTRUCTION_SIZE ModeAddrSize; + UINT8 *Byte; + + /*TODO: Determine current mode - 64-bit for now */ + Mode =3D LongMode64Bit; + ModeDataSize =3D Size32Bits; + ModeAddrSize =3D Size64Bits; + + InstructionData->Mode =3D Mode; + InstructionData->DataSize =3D ModeDataSize; + InstructionData->AddrSize =3D ModeAddrSize; + + InstructionData->Prefixes =3D InstructionData->Begin; + + Byte =3D InstructionData->Prefixes; + for ( ; ; Byte++, InstructionData->PrefixSize++) { + switch (*Byte) { + case 0x26: + case 0x2E: + case 0x36: + case 0x3E: + if (Mode !=3D LongMode64Bit) { + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D (*Byte >> 3) & 3; + } + break; + + case 0x40 ... 0x4F: + InstructionData->RexPrefix.Uint8 =3D *Byte; + if (*Byte & 0x08) + InstructionData->DataSize =3D Size64Bits; + break; + + case 0x64: + InstructionData->SegmentSpecified =3D TRUE; + InstructionData->Segment =3D *Byte & 7; + break; + + case 0x66: + if (!InstructionData->RexPrefix.Uint8) { + InstructionData->DataSize =3D + (Mode =3D=3D LongMode64Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + } + break; + + case 0x67: + InstructionData->AddrSize =3D + (Mode =3D=3D LongMode64Bit) ? Size32Bits : + (Mode =3D=3D LongModeCompat32Bit) ? Size16Bits : + (Mode =3D=3D LongModeCompat16Bit) ? Size32Bits : 0; + break; + + case 0xF0: + break; + + case 0xF2: + InstructionData->RepMode =3D RepZ; + break; + + case 0xF3: + InstructionData->RepMode =3D RepNZ; + break; + + default: + InstructionData->OpCodes =3D Byte; + InstructionData->OpCodeSize =3D (*Byte =3D=3D 0x0F) ? 2 : 1; + + InstructionData->End =3D Byte + InstructionData->OpCodeSize; + InstructionData->Displacement =3D InstructionData->End; + InstructionData->Immediate =3D InstructionData->End; + return; + } + } +} + +UINT64 +InstructionLength ( + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + return (UINT64) (InstructionData->End - InstructionData->Begin); +} + +STATIC +VOID +InitInstructionData ( + SEV_ES_INSTRUCTION_DATA *InstructionData, + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs + ) +{ + SetMem (InstructionData, sizeof (*InstructionData), 0); + InstructionData->Ghcb =3D Ghcb; + InstructionData->Begin =3D (UINT8 *) Regs->Rip; + InstructionData->End =3D (UINT8 *) Regs->Rip; + + DecodePrefixes (Regs, InstructionData); +} + +STATIC +UINT64 +UnsupportedExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SvmExitUnsupported, Regs->ExceptionData, 0); + if (Status =3D=3D 0) { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D 0; + Event.Elements.Vector =3D GP_EXCEPTION; + Event.Elements.Type =3D GHCB_EVENT_INJECTION_TYPE_EXCEPTION; + Event.Elements.Valid =3D 1; + + Status =3D Event.Uint64; + } + + return Status; +} + +#define IOIO_TYPE_STR (1 << 2) +#define IOIO_TYPE_IN 1 +#define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) +#define IOIO_TYPE_OUT 0 +#define IOIO_TYPE_OUTS (IOIO_TYPE_OUT | IOIO_TYPE_STR) + +#define IOIO_REP (1 << 3) + +#define IOIO_ADDR_64 (1 << 9) +#define IOIO_ADDR_32 (1 << 8) +#define IOIO_ADDR_16 (1 << 7) + +#define IOIO_DATA_32 (1 << 6) +#define IOIO_DATA_16 (1 << 5) +#define IOIO_DATA_8 (1 << 4) + +#define IOIO_SEG_ES (0 << 10) +#define IOIO_SEG_DS (3 << 10) + +STATIC +UINT64 +IoioExitInfo ( + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo =3D 0; + + switch (*(InstructionData->OpCodes)) { + // IN immediate opcodes + case 0xE4: + case 0xE5: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16); + break; + + // OUT immediate opcodes + case 0xE6: + case 0xE7: + InstructionData->ImmediateSize =3D 1; + InstructionData->End++; + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((*(InstructionData->OpCodes + 1)) << 16) | IOIO_TYPE_OU= T; + break; + + // IN register opcodes + case 0xEC: + case 0xED: + ExitInfo |=3D IOIO_TYPE_IN; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + // OUT register opcodes + case 0xEE: + case 0xEF: + ExitInfo |=3D IOIO_TYPE_OUT; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + default: + return 0; + } + + switch (*(InstructionData->OpCodes)) { + case 0xE4: + case 0xE6: + case 0xEC: + case 0xEE: + // Single-byte opcodes + ExitInfo |=3D IOIO_DATA_8; + break; + + default: + // Length determined by instruction parsing + ExitInfo |=3D (InstructionData->DataSize =3D=3D Size16Bits) ? IOIO_DAT= A_16 + : IOIO_DATA_32; + } + + switch (InstructionData->AddrSize) { + case Size16Bits: + ExitInfo |=3D IOIO_ADDR_16; + break; + + case Size32Bits: + ExitInfo |=3D IOIO_ADDR_32; + break; + + case Size64Bits: + ExitInfo |=3D IOIO_ADDR_64; + break; + + default: + break; + } + + if (InstructionData->RepMode) { + ExitInfo |=3D IOIO_REP; + } + + return ExitInfo; +} + +STATIC +UINT64 +IoioExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 =3D IoioExitInfo (Regs, InstructionData); + if (!ExitInfo1) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + if (!(ExitInfo1 & IOIO_TYPE_IN)) { + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + } + + //FIXME: This is likely needed for the merging cases (size<32 bits) + // Pass in zero and perform merge here (only for non-string) + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status =3D VmgExit (Ghcb, SvmExitIoioProt, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (ExitInfo1 & IOIO_TYPE_IN) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + } + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -18,6 +443,8 @@ DoVcCommon ( ) { EFI_SYSTEM_CONTEXT_X64 *Regs =3D Context.SystemContextX64; + SEV_ES_INSTRUCTION_DATA InstructionData; + NAE_EXIT NaeExit; UINT64 Status; UINTN ExitCode, VcRet; =20 @@ -25,23 +452,31 @@ DoVcCommon ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SvmExitIoioProt: + NaeExit =3D IoioExit; + break; + default: - Status =3D VmgExit (Ghcb, SvmExitUnsupported, ExitCode, 0); - if (Status =3D=3D 0) { - Regs->ExceptionData =3D 0; - VcRet =3D GP_EXCEPTION; + NaeExit =3D UnsupportedExit; + } + + InitInstructionData (&InstructionData, Ghcb, Regs); + + Status =3D NaeExit (Ghcb, Regs, &InstructionData); + if (Status =3D=3D 0) { + Regs->Rip +=3D InstructionLength(&InstructionData); + VcRet =3D 0; + } else { + GHCB_EVENT_INJECTION Event; + + Event.Uint64 =3D Status; + if (Event.Elements.ErrorCodeValid) { + Regs->ExceptionData =3D Event.Elements.ErrorCode; } else { - GHCB_EVENT_INJECTION Event; - - Event.Uint64 =3D Status; - if (Event.Elements.ErrorCodeValid) { - Regs->ExceptionData =3D Event.Elements.ErrorCode; - } else { - Regs->ExceptionData =3D 0; - } - - VcRet =3D Event.Elements.Vector; + Regs->ExceptionData =3D 0; } + + VcRet =3D Event.Elements.Vector; } =20 VmgDone (Ghcb); --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:07:40 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 33380975-18a7-4e9c-0387-08d7befe81dd X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55252+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: jUihZbk6W3TJzhbYOUw6Ajzpih44/dOg5HFGYiI/PazXNSGrKacQhsrkozRDSHQbomVHhsO8knMXXo2uppTUZt00q8zG9TXs65tMrQt6asWuxOs44J4l4d/UAlIsqLZuDILZRPIWyR29AxGqZYiaXWeoLeDfPC+K8wJ/0+YBX268+64Dt4QxYEf74fKCrHLw/JlGxOF5SCnXebn8/f0owI1qj64DsXpLaeq76p8RirDtB2jeRWpSQa9PPn8HIf6Ix/gN0nGsNXLNYd7UBs8UAzidR8JmhYygtpstxecFUg6VmjhRVRSLgsOexY24uNWxuIxPLUxow/eE7zPhtqnoIIBp0xet7Y0e6VbwJTibzcUdqqXR5x+wbqL1c9e/QvxhFwRJIj1QzoqtONgSVLDBiMqHxtjyWUp420PJq0m9/YCIYz1LsVPwKVpFgL19vIydy4nO2vng5LQqAgeGeYz18d+Ta5TcZRH2VOdWw983fMVBzgUfkzXOQ7pO1jmeOK8+mZAWNlLh9pqGqmV1ugw+GA== X-MS-Exchange-AntiSpam-MessageData: /0sQSEj0pJUz2ojyeQQHiclrPIid/YITSRlFB3g2pKuCyPt0j1l+LARwEqIdyRA3Z0O9fTPQtInbmM0vhmEsjitrgfNZlQtWDhvmNQRCkKRqdXF3gRV761fcyMQGaKJmeGE5nhDBbKFdmvTTdA/0QQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 33380975-18a7-4e9c-0387-08d7befe81dd X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:40.8588 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8Qh621sons/ZaT14OL13soLrCv9JBAmW4kMrZGYv/zzHMVu9gJlQzeP+l3XxsmUzK6GVxIC17VpvvRxFfcbuUw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: bcGid8MHa7bDnm9bPO1WoZ1Ux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190462; bh=dQP86edu4EVZsHT9h7pcla6Wew5hxcaF7AMBFIq4/5k=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=GZMvA+wwqPJRMZgEs3p3nGA3R9jrLfqhN3W34JXDwmYVysfVz86EaHly9PHf5gqSNvO GYgPp62s+IfK3T0oTpE3zbiYc03gPgPkd4GIyv2lpYwIjr0ed9gF7Z/eqA4azaVjXdoFl A4MEnvP3Oz0fowtfXzBEzAAHfi5cI57Hhkw= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Add support to the #VC exception handler to handle string IO. This requires expanding the IO instruction parsing to recognize string based IO instructions as well as preparing an un-encrypted buffer to be used to transfer (either to or from the guest) the string contents for the IO operation. The SW_EXITINFO2 and SW_SCRATCH fields of the GHCB are set appropriately for the operation. Multiple VMGEXIT invocations may be needed to complete the string IO operation. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 78 ++++++++++++++++--- 1 file changed, 68 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index eb7b776859c1..28adf0d5e9c4 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -321,6 +321,22 @@ IoioExitInfo ( UINT64 ExitInfo =3D 0; =20 switch (*(InstructionData->OpCodes)) { + // INS opcodes + case 0x6C: + case 0x6D: + ExitInfo |=3D IOIO_TYPE_INS; + ExitInfo |=3D IOIO_SEG_ES; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + + // OUTS opcodes + case 0x6E: + case 0x6F: + ExitInfo |=3D IOIO_TYPE_OUTS; + ExitInfo |=3D IOIO_SEG_DS; + ExitInfo |=3D ((Regs->Rdx & 0xffff) << 16); + break; + // IN immediate opcodes case 0xE4: case 0xE5: @@ -358,6 +374,8 @@ IoioExitInfo ( } =20 switch (*(InstructionData->OpCodes)) { + case 0x6C: + case 0x6E: case 0xE4: case 0xE6: case 0xEC: @@ -404,7 +422,8 @@ IoioExit ( SEV_ES_INSTRUCTION_DATA *InstructionData ) { - UINT64 ExitInfo1, Status; + UINT64 ExitInfo1, ExitInfo2, Status; + BOOLEAN String; =20 ExitInfo1 =3D IoioExitInfo (Regs, InstructionData); if (!ExitInfo1) { @@ -421,16 +440,55 @@ IoioExit ( Ghcb->SaveArea.Rax =3D Regs->Rax; GhcbSetRegValid (Ghcb, GhcbRax); =20 - Status =3D VmgExit (Ghcb, SvmExitIoioProt, ExitInfo1, 0); - if (Status) { - return Status; - } - - if (ExitInfo1 & IOIO_TYPE_IN) { - if (!GhcbIsRegValid (Ghcb, GhcbRax)) { - return UnsupportedExit (Ghcb, Regs, InstructionData); + String =3D (ExitInfo1 & IOIO_TYPE_STR) ? TRUE : FALSE; + if (String) { + UINTN IoBytes, VmgExitBytes; + UINTN GhcbCount, OpCount; + + Status =3D 0; + + IoBytes =3D (ExitInfo1 >> 4) & 0x7; + GhcbCount =3D sizeof (Ghcb->SharedBuffer) / IoBytes; + + OpCount =3D (ExitInfo1 & IOIO_REP) ? Regs->Rcx : 1; + while (OpCount) { + ExitInfo2 =3D MIN (OpCount, GhcbCount); + VmgExitBytes =3D ExitInfo2 * IoBytes; + + if (!(ExitInfo1 & IOIO_TYPE_IN)) { + CopyMem (Ghcb->SharedBuffer, (VOID *) Regs->Rsi, VmgExitBytes); + Regs->Rsi +=3D VmgExitBytes; + } + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SvmExitIoioProt, ExitInfo1, ExitInfo2); + if (Status) { + return Status; + } + + if (ExitInfo1 & IOIO_TYPE_IN) { + CopyMem ((VOID *) Regs->Rdi, Ghcb->SharedBuffer, VmgExitBytes); + Regs->Rdi +=3D VmgExitBytes; + } + + if (ExitInfo1 & IOIO_REP) { + Regs->Rcx -=3D ExitInfo2; + } + + OpCount -=3D ExitInfo2; + } + } else { + Status =3D VmgExit (Ghcb, SvmExitIoioProt, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (ExitInfo1 & IOIO_TYPE_IN) { + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; } - Regs->Rax =3D Ghcb->SaveArea.Rax; } =20 return 0; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:07:41 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 5efb061a-f71d-4142-0ab3-08d7befe826e X-MS-TrafficTypeDiagnostic: DM6PR12MB4041:|DM6PR12MB4041: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:6108; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55253+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 45gPSor06NJ7wfzgfIPXmJUAT7HV9MCl6IW+dbB6Pa6bU0vNAJpnWPWRe4D3t6iYdZkv0ELSWcnFul73+2qkqA5TtABYn+Skb4jc48f4patwPIz7ew8xeXAJD4vTIxcptGLu5AsnfYl8wllkJYab1bGvhdsi/mJE/mkRRPndP4IcGsefCzIwzPiUdnQEXlsTU5qVaWUB7FL0tkrs2uQRWQvQZbK0/rdt9cL28NPx2RuT8/1HWNiGkjPxnPCYkGjIqTKADmJ93xD4ZYFnVH9QRnk9/2NzFWE78PKrRRrxK6c+DklQqhW/1rD97r+jfqY098oC6uwBEKWitBpV4Upt3evHGoU72ESIe397jsnIbvCZWBpE+mJKPdj7kCCLnOenlY4EGY5AXv0HXOcUklNBHVB63MNSrAO38sm2b6e/mnJ53t2fChDIk9pFL8kVFOUp5J7M5Azp6kKwivV+pDPkWEc6UXh+XQ/fRI1SSGU5xt48Zq7iz77TRKAhKUSY3IFDJoZd32qZv470BcxHW2aGBA== X-MS-Exchange-AntiSpam-MessageData: S3bxwi7weB5WL7l+HDlri/xdcqZg0y1524UuDvShwkFerdx/yjXTy+qWhSL+efd4f3u8p1YUL8Hs/EkbvmLN6bG4CUc45mbDsABpovcbhUXETneH4pQtCCBSZcnHOLsZlyAWpfJT6FRSFzHY8Vqrvg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5efb061a-f71d-4142-0ab3-08d7befe826e X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:41.8753 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: EalA+7IkXMon59rmptTaSObRmgqItcvrXt5EN8B1+KmwDXBq7v1r1mchXlyMtz+gWxoXS5jVfzt/Mxhy+RK2HA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4041 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: vAbEzmieJKSD2tH9euC5TBAWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190463; bh=+6AHXxXUjtYGwIPp8JTLmfPjEKLdfshtFxLNOnV00Nk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=ZBcTlzU3hHxDoIb7y3Ii2hKK8q5Oa3gG6bkw2aiqbITcwjEciC5H49ShKqfRQzUs/pe YrHNyWXRGLstM0i1Pst9J5duGGZj7DdXW/ZOXMqXiLBIxgfIcp7lzDL8UVYHOFZF+qt9S uCCDTbEThMhMWCD0pji0uBSBlelKdMgM1rg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a CPUID intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a CPUID NAE event. Additionally, CPUID 0x0000_000d requires XCR0 to be supplied in the GHCB, so add support to issue the XGETBV instruction. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 28adf0d5e9c4..970ee8752253 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -11,6 +11,8 @@ #include #include "AMDSevVcCommon.h" =20 +#define CR4_OSXSAVE (1 << 18) + typedef enum { LongMode64Bit =3D 0, LongModeCompat32Bit, @@ -494,6 +496,44 @@ IoioExit ( return 0; } =20 +STATIC +UINT64 +CpuidExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + if (Regs->Rax =3D=3D 0x0000000d) { + Ghcb->SaveArea.XCr0 =3D (AsmReadCr4 () & CR4_OSXSAVE) ? AsmXGetBv (0) = : 1; + GhcbSetRegValid (Ghcb, GhcbXCr0); + } + + Status =3D VmgExit (Ghcb, SvmExitCpuid, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRbx) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rbx =3D Ghcb->SaveArea.Rbx; + Regs->Rcx =3D Ghcb->SaveArea.Rcx; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -510,6 +550,10 @@ DoVcCommon ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SvmExitCpuid: + NaeExit =3D CpuidExit; + break; + case SvmExitIoioProt: NaeExit =3D IoioExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: YCKwzY0iWZydosyiGMpU7Xnzx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190464; bh=br51grfJE84tm9FXrabEGw6OEmzBEtwijzpVgOp0VUY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=D9XmqujLcw9AMgkfnQs2DnNUCa4PXQF7coUH5iE7LF6hah9DkJrAiTLvdiXr0HoFOCx BPFkGu8BDFwRDspC5m5R/YpZvE7WEtTzJTTVNAQwm7l5YMYODA2hqnmeiA0V0B4fjrnrr gWhoPAkNNt/Lj9LkELFohlWaYoTKhbBXzqQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MSR_PROT intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support an MSR_PROT NAE event. Parse the instruction that generated the #VC exception to determine whether it is RDMSR or WRMSR, setting the required register register values in the GHCB and creating the proper SW_EXIT_INFO1 value in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 970ee8752253..6f91cfff5fc8 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -294,6 +294,51 @@ UnsupportedExit ( return Status; } =20 +STATIC +UINT64 +MsrExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, Status; + + ExitInfo1 =3D 0; + + switch (*(InstructionData->OpCodes + 1)) { + case 0x30: // WRMSR + ExitInfo1 =3D 1; + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rdx =3D Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + /* Fallthrough */ + case 0x32: // RDMSR + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + break; + default: + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + Status =3D VmgExit (Ghcb, SvmExitMsr, ExitInfo1, 0); + if (Status) { + return Status; + } + + if (!ExitInfo1) { + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + } + + return 0; +} + #define IOIO_TYPE_STR (1 << 2) #define IOIO_TYPE_IN 1 #define IOIO_TYPE_INS (IOIO_TYPE_IN | IOIO_TYPE_STR) @@ -558,6 +603,10 @@ DoVcCommon ( NaeExit =3D IoioExit; break; =20 + case SvmExitMsr: + NaeExit =3D MsrExit; + break; + default: NaeExit =3D UnsupportedExit; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55254): https://edk2.groups.io/g/devel/message/55254 Mute This Topic: https://groups.io/mt/71687806/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55255+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190466372599.7345943200909; Mon, 2 Mar 2020 15:07:46 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id TpYjYY1788612xniLzIHIjP1; Mon, 02 Mar 2020 15:07:45 -0800 X-Received: from NAM10-DM6-obe.outbound.protection.outlook.com (NAM10-DM6-obe.outbound.protection.outlook.com [40.107.93.89]) by mx.groups.io with SMTP id smtpd.web09.722.1583190464708073620 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:43 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:43 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 15/42] UefiCpuPkg/CpuExceptionHandler: Add support for NPF NAE events (MMIO) Date: Mon, 2 Mar 2020 17:06:46 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: ZtD4qLsaljrcy6OWmcRFITnNx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190465; bh=eqjnd7MsnTopbSIOZ6dIEPHMJ0S1Ly66ZMZneecBsJ8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=lEG0cgLFuT27s6vclpqDBWNx+OGwFe2MwFHXrMjvpiA5aru68iRm5mx8Z2jiNrbvCiy kc52QWMNLQGkc7JWSi3SVboZ+z123lLTlC7b9cPXsEOjctylWx4JeRS38mC4EtOAAkm4Z RRxXv4A0Bcjg09uqGU5W4tIIPqZT7uhZYTo= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a NPF intercept for an NPT entry with a reserved bit set generates a #VC exception. This condition is assumed to be an MMIO access. VMGEXIT must be used to allow the hypervisor to handle this intercept. Add support to construct the required GHCB values to support a NPF NAE event for MMIO. Parse the instruction that generated the #VC exception, setting the required register values in the GHCB and creating the proper SW_EXIT_INFO1, SW_EXITINFO2 and SW_SCRATCH values in the GHCB. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 305 +++++++++++++++++- 1 file changed, 303 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 6f91cfff5fc8..92b15dbd146e 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -86,8 +86,8 @@ typedef struct { UINT8 Scale; } Sib; =20 - UINTN RegData; - UINTN RmData; + INTN RegData; + INTN RmData; } SEV_ES_INSTRUCTION_OPCODE_EXT; =20 typedef struct { @@ -159,6 +159,198 @@ GhcbSetRegValid ( Ghcb->SaveArea.ValidBitmap[RegIndex] |=3D (1 << RegBit); } =20 +STATIC +INT64 * +GetRegisterPointer ( + EFI_SYSTEM_CONTEXT_X64 *Regs, + UINT8 Register + ) +{ + UINT64 *Reg; + + switch (Register) { + case 0: + Reg =3D &Regs->Rax; + break; + case 1: + Reg =3D &Regs->Rcx; + break; + case 2: + Reg =3D &Regs->Rdx; + break; + case 3: + Reg =3D &Regs->Rbx; + break; + case 4: + Reg =3D &Regs->Rsp; + break; + case 5: + Reg =3D &Regs->Rbp; + break; + case 6: + Reg =3D &Regs->Rsi; + break; + case 7: + Reg =3D &Regs->Rdi; + break; + case 8: + Reg =3D &Regs->R8; + break; + case 9: + Reg =3D &Regs->R9; + break; + case 10: + Reg =3D &Regs->R10; + break; + case 11: + Reg =3D &Regs->R11; + break; + case 12: + Reg =3D &Regs->R12; + break; + case 13: + Reg =3D &Regs->R13; + break; + case 14: + Reg =3D &Regs->R14; + break; + case 15: + Reg =3D &Regs->R15; + break; + default: + Reg =3D NULL; + } + ASSERT (Reg !=3D NULL); + + return (INT64 *) Reg; +} + +STATIC +VOID +UpdateForDisplacement ( + SEV_ES_INSTRUCTION_DATA *InstructionData, + UINTN Size + ) +{ + InstructionData->DisplacementSize =3D Size; + InstructionData->Immediate +=3D Size; + InstructionData->End +=3D Size; +} + +STATIC +BOOLEAN +IsRipRelative ( + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext =3D &InstructionData->Ext; + + return ((InstructionData =3D=3D LongMode64Bit) && + (Ext->ModRm.Mod =3D=3D 0) && + (Ext->ModRm.Rm =3D=3D 5) && + (InstructionData->SibPresent =3D=3D FALSE)); +} + +STATIC +UINTN +GetEffectiveMemoryAddress ( + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext =3D &InstructionData->Ext; + INTN EffectiveAddress =3D 0; + + if (IsRipRelative (InstructionData)) { + /* RIP-relative displacement is a 32-bit signed value */ + INT32 RipRelative =3D *(INT32 *) InstructionData->Displacement; + + UpdateForDisplacement (InstructionData, 4); + return (UINTN) ((INTN) Regs->Rip + RipRelative); + } + + switch (Ext->ModRm.Mod) { + case 1: + UpdateForDisplacement (InstructionData, 1); + EffectiveAddress +=3D (INT8) (*(INT8 *) (InstructionData->Displacement= )); + break; + case 2: + switch (InstructionData->AddrSize) { + case Size16Bits: + UpdateForDisplacement (InstructionData, 2); + EffectiveAddress +=3D (INT16) (*(INT16 *) (InstructionData->Displace= ment)); + break; + default: + UpdateForDisplacement (InstructionData, 4); + EffectiveAddress +=3D (INT32) (*(INT32 *) (InstructionData->Displace= ment)); + break; + } + break; + } + + if (InstructionData->SibPresent) { + if (Ext->Sib.Index !=3D 4) { + EffectiveAddress +=3D (*GetRegisterPointer (Regs, Ext->Sib.Index) <<= Ext->Sib.Scale); + } + + if ((Ext->Sib.Base !=3D 5) || Ext->ModRm.Mod) { + EffectiveAddress +=3D *GetRegisterPointer (Regs, Ext->Sib.Base); + } else { + UpdateForDisplacement (InstructionData, 4); + EffectiveAddress +=3D (INT32) (*(INT32 *) (InstructionData->Displace= ment)); + } + } else { + EffectiveAddress +=3D *GetRegisterPointer (Regs, Ext->ModRm.Rm); + } + + return (UINTN) EffectiveAddress; +} + +STATIC +VOID +DecodeModRm ( + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_REX_PREFIX *RexPrefix =3D &InstructionData->RexPrefi= x; + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext =3D &InstructionData->Ext; + SEV_ES_INSTRUCTION_MODRM *ModRm =3D &InstructionData->ModRm; + SEV_ES_INSTRUCTION_SIB *Sib =3D &InstructionData->Sib; + + InstructionData->ModRmPresent =3D TRUE; + ModRm->Uint8 =3D *(InstructionData->End); + + InstructionData->Displacement++; + InstructionData->Immediate++; + InstructionData->End++; + + Ext->ModRm.Mod =3D ModRm->Bits.Mod; + Ext->ModRm.Reg =3D (RexPrefix->Bits.R << 3) | ModRm->Bits.Reg; + Ext->ModRm.Rm =3D (RexPrefix->Bits.B << 3) | ModRm->Bits.Rm; + + Ext->RegData =3D *GetRegisterPointer (Regs, Ext->ModRm.Reg); + + if (Ext->ModRm.Mod =3D=3D 3) { + Ext->RmData =3D *GetRegisterPointer (Regs, Ext->ModRm.Rm); + } else { + if (ModRm->Bits.Rm =3D=3D 4) { + InstructionData->SibPresent =3D TRUE; + Sib->Uint8 =3D *(InstructionData->End); + + InstructionData->Displacement++; + InstructionData->Immediate++; + InstructionData->End++; + + Ext->Sib.Scale =3D Sib->Bits.Scale; + Ext->Sib.Index =3D (RexPrefix->Bits.X << 3) | Sib->Bits.Index; + Ext->Sib.Base =3D (RexPrefix->Bits.B << 3) | Sib->Bits.Base; + } + + Ext->RmData =3D GetEffectiveMemoryAddress (Regs, InstructionData); + } +} + STATIC VOID DecodePrefixes ( @@ -294,6 +486,111 @@ UnsupportedExit ( return Status; } =20 +STATIC +UINT64 +MmioExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 ExitInfo1, ExitInfo2, Status; + UINTN Bytes; + INTN *Register; + + Bytes =3D 0; + + switch (*(InstructionData->OpCodes)) { + /* MMIO write */ + case 0x88: + Bytes =3D 1; + case 0x89: + DecodeModRm (Regs, InstructionData); + Bytes =3D (Bytes) ? Bytes + : (InstructionData->DataSize =3D=3D Size16Bits) ? 2 + : (InstructionData->DataSize =3D=3D Size32Bits) ? 4 + : (InstructionData->DataSize =3D=3D Size64Bits) ? 8 + : 0; + + if (InstructionData->Ext.ModRm.Mod =3D=3D 3) { + /* NPF on two register operands??? */ + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + CopyMem (Ghcb->SharedBuffer, &InstructionData->Ext.RegData, Bytes); + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SvmExitMmioWrite, ExitInfo1, ExitInfo2); + if (Status) { + return Status; + } + break; + + case 0xC6: + Bytes =3D 1; + case 0xC7: + DecodeModRm (Regs, InstructionData); + Bytes =3D (Bytes) ? Bytes + : (InstructionData->DataSize =3D=3D Size16Bits) ? 2 + : (InstructionData->DataSize =3D=3D Size32Bits) ? 4 + : 0; + + InstructionData->ImmediateSize =3D Bytes; + InstructionData->End +=3D Bytes; + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + CopyMem (Ghcb->SharedBuffer, InstructionData->Immediate, Bytes); + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SvmExitMmioWrite, ExitInfo1, ExitInfo2); + if (Status) { + return Status; + } + break; + + /* MMIO read */ + case 0x8A: + Bytes =3D 1; + case 0x8B: + DecodeModRm (Regs, InstructionData); + Bytes =3D (Bytes) ? Bytes + : (InstructionData->DataSize =3D=3D Size16Bits) ? 2 + : (InstructionData->DataSize =3D=3D Size32Bits) ? 4 + : (InstructionData->DataSize =3D=3D Size64Bits) ? 8 + : 0; + if (InstructionData->Ext.ModRm.Mod =3D=3D 3) { + /* NPF on two register operands??? */ + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + + ExitInfo1 =3D InstructionData->Ext.RmData; + ExitInfo2 =3D Bytes; + + Ghcb->SaveArea.SwScratch =3D (UINT64) Ghcb->SharedBuffer; + Status =3D VmgExit (Ghcb, SvmExitMmioRead, ExitInfo1, ExitInfo2); + if (Status) { + return Status; + } + + Register =3D GetRegisterPointer (Regs, InstructionData->Ext.ModRm.Reg); + if (Bytes =3D=3D 4) { + /* Zero-extend for 32-bit operation */ + *Register =3D 0; + } + CopyMem (Register, Ghcb->SharedBuffer, Bytes); + break; + + default: + Status =3D GP_EXCEPTION; + ASSERT (0); + } + + return Status; +} + STATIC UINT64 MsrExit ( @@ -607,6 +904,10 @@ DoVcCommon ( NaeExit =3D MsrExit; break; =20 + case SvmExitNpf: + NaeExit =3D MmioExit; + break; + default: NaeExit =3D UnsupportedExit; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 26V4uR4zra5pta9iJNBvidS8x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190465; bh=4akbB1LoZtM5XZ2R4AvHF1Fkg9a+tetPp/2T0d22GXk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=IgL14IhLm7OfknHXlcU2dF49vIKsVzvY4cZ+QZzNdf8+hmxbm65+UFeklX4+b07XUIV cqiAIJvbPxecbicKm9TeSvR1SU0La03m37XrwfiuTPeaI0l5QQWeyOMrjrOiFvE2iplTV c3MZquBTpdhbO2nHkdcpAvQA+3nma3tEwKM= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a WBINVD intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 92b15dbd146e..1096403261db 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -591,6 +591,24 @@ MmioExit ( return Status; } =20 +STATIC +UINT64 +WbinvdExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SvmExitWbinvd, 0, 0); + if (Status) { + return Status; + } + + return 0; +} + STATIC UINT64 MsrExit ( @@ -904,6 +922,10 @@ DoVcCommon ( NaeExit =3D MsrExit; break; =20 + case SvmExitWbinvd: + NaeExit =3D WbinvdExit; + break; + case SvmExitNpf: NaeExit =3D MmioExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:45 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:45 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 17/42] UefiCpuPkg/CpuExceptionHandler: Add support for RDTSC NAE events Date: Mon, 2 Mar 2020 17:06:48 -0600 Message-Id: <7624fa11bc1774adb70f2528f6cfeda439feeb58.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Jne7j5LwJTtFIbjyLtnthecsx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190466; bh=wJGXst0Rkbn36pg7FW5pwaBBYF14w2O5mx69hxFUpl4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=IgCAzixj87K3e4AJh9K0lRX2jgbaDDgU5jUHD51bgS3OEfmKgL9VCV6DfxeD1Y5TC6+ EI9y1+uIAN/Qk2fQzmesef+eZn921X3ZnOM0OD3XzB/aLHUc09LINgC2egbBttMXWLewB FR9n1xJoviv4/cnGqB2hcCTn4nZVwgDh8vk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDTSC intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 1096403261db..82f42d905068 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -894,6 +894,31 @@ CpuidExit ( return 0; } =20 +STATIC +UINT64 +RdtscExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SvmExitRdtsc, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -910,6 +935,10 @@ DoVcCommon ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SvmExitRdtsc: + NaeExit =3D RdtscExit; + break; + case SvmExitCpuid: NaeExit =3D CpuidExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Q4XDQynjEiPC6LMEm6faHaGax1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190467; bh=RZRv3VRdnuBcbHbbK0FtmYSQic1yItZ/g3RV6Or76AU=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=vSJxKVOFpc25D99GySFRnCZOXxdGMdD0UOMAJg47s1OazFsoYJ3vqcfWK3KurHHboM7 GaHxMimMrInyzj2mMkxH060wBNr0x/yW9zmRUZJkykBhXFoSQceR9MhHzhyrzSGes3PUm zDsFTIRpV31xD7guitd6/ZIGL/a6xBUZvBk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDPMC intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 82f42d905068..595ef0fa066b 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -894,6 +894,34 @@ CpuidExit ( return 0; } =20 +STATIC +UINT64 +RdpmcExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + + Status =3D VmgExit (Ghcb, SvmExitRdpmc, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + STATIC UINT64 RdtscExit ( @@ -939,6 +967,10 @@ DoVcCommon ( NaeExit =3D RdtscExit; break; =20 + case SvmExitRdpmc: + NaeExit =3D RdpmcExit; + break; + case SvmExitCpuid: NaeExit =3D CpuidExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: UEpoSnJ6oUdmKKiAtdXn5Z86x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190468; bh=Q0JdanqYA3xPN/3hUUW0fMbH0mSVoEf+VI2Pu/LIc2A=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=nArN1881tllpGsEw12ivWucplSBgLT+Zx0bcSfFyiK8KlYnYL0g2S2tDUEYZIdbtRt8 EC2LY5Mj9vzqiLj/hxn2k/ONTdoVifR6ybYdqwf+q+zwVDcfSWLpGZaJsXA8yWP2giVc0 AMAYvnaVF5u1Ry9KNUBeC/XObzNUwgJyfp8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a INVD intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 595ef0fa066b..a0dd5e2adcc9 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -856,6 +856,24 @@ IoioExit ( return 0; } =20 +STATIC +UINT64 +InvdExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + Status =3D VmgExit (Ghcb, SvmExitInvd, 0, 0); + if (Status) { + return Status; + } + + return 0; +} + STATIC UINT64 CpuidExit ( @@ -975,6 +993,10 @@ DoVcCommon ( NaeExit =3D CpuidExit; break; =20 + case SvmExitInvd: + NaeExit =3D InvdExit; + break; + case SvmExitIoioProt: NaeExit =3D IoioExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: cby7O2HdyNFkibPZYy1Jh83Yx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190469; bh=VXT24r4vEov6c5mmQvVDCno1XrJIQFmaNe0e5Vkf8Gw=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=XgruL8F4MsdmWDKBd5Zh1aOCzvRuagJy5XtiZJ8plsWwv+hzfN0sHVzOtqgblSpPWUp cjjaFyg9arsZASR1UYDfQErJhDP+SVWNNCmAI1reJrurEsoHKZmm+Eq99wM+rX4fGxnId gmxS5YaIBdG7/n+fmbhO9IO4NqtYkT05F+c= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a VMMCALL intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index a0dd5e2adcc9..354d027f08f3 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -609,6 +609,36 @@ WbinvdExit ( return 0; } =20 +STATIC +UINT64 +VmmCallExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Cpl =3D (UINT8) (Regs->Cs & 0x3); + GhcbSetRegValid (Ghcb, GhcbCpl); + + Status =3D VmgExit (Ghcb, SvmExitVmmCall, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + + return 0; +} + STATIC UINT64 MsrExit ( @@ -1005,6 +1035,10 @@ DoVcCommon ( NaeExit =3D MsrExit; break; =20 + case SvmExitVmmCall: + NaeExit =3D VmmCallExit; + break; + case SvmExitWbinvd: NaeExit =3D WbinvdExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4041.namprd12.prod.outlook.com (2603:10b6:5:210::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.15; Mon, 2 Mar 2020 23:07:48 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:48 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 21/42] UefiCpuPkg/CpuExceptionHandler: Add support for RDTSCP NAE events Date: Mon, 2 Mar 2020 17:06:52 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 6i1IJ7QVnVk4W0vkbrEWFsenx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190470; bh=LeHmdcsrRbvncrDv0PNP51vsfaWDCJS4xwKSTOJ3d6U=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=mASW++vmbuCu7QDZ8cJTghz5febClZlEqst7VCukPghaTueqhtXsTrOVv52RCFdhEm8 a4VcdeAoQMvaVYscM8HSDbPgquO3/tDBu+2z+Dh3uuKKAMo7K0hgkm8Tv6vCT1cF9pbbB juJinVkL2fmIJzJvrhYeb6TabKDPcLK494o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a RDTSCP intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 354d027f08f3..0a27ade69310 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -609,6 +609,35 @@ WbinvdExit ( return 0; } =20 +STATIC +UINT64 +RdtscpExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Status =3D VmgExit (Ghcb, SvmExitRdtscp, 0, 0); + if (Status) { + return Status; + } + + if (!GhcbIsRegValid (Ghcb, GhcbRax) || + !GhcbIsRegValid (Ghcb, GhcbRcx) || + !GhcbIsRegValid (Ghcb, GhcbRdx)) { + return UnsupportedExit (Ghcb, Regs, InstructionData); + } + Regs->Rax =3D Ghcb->SaveArea.Rax; + Regs->Rcx =3D Ghcb->SaveArea.Rcx; + Regs->Rdx =3D Ghcb->SaveArea.Rdx; + + return 0; +} + STATIC UINT64 VmmCallExit ( @@ -1039,6 +1068,10 @@ DoVcCommon ( NaeExit =3D VmmCallExit; break; =20 + case SvmExitRdtscp: + NaeExit =3D RdtscpExit; + break; + case SvmExitWbinvd: NaeExit =3D WbinvdExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55261): https://edk2.groups.io/g/devel/message/55261 Mute This Topic: https://groups.io/mt/71687815/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55265+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190478007996.3594249392531; Mon, 2 Mar 2020 15:07:58 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id LxbLYY1788612x6SMXDuAzCj; Mon, 02 Mar 2020 15:07:57 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.694.1583190475799820802 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 3QTK3pJaPH3i2gCRDHf9SsIGx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190477; bh=gLDHjvQUjHc/dF2d9/aQWuZMLBAXasy3Mqog5TezKBE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=a0j/uelUcDGl4p4VkoG273TmJPbkhOo836uNoNLoOWvqR0dbEOiyPtB1zNkM82rgwBy 9KrdNBBgKKVBSZ3NXMvjVSryXeldlXXMm0T/QFmyfLkqBRp9yVM6BoQa/iXSRv6U1tQXl D5hoQAZeU11XFFnCdHmoJRLllHhpPA1FENc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MONITOR/MONITORX intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 0a27ade69310..784229c5ca8d 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -591,6 +591,33 @@ MmioExit ( return Status; } =20 +STATIC +UINT64 +MonitorExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; // Identity mapped, so VA =3D PA + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + Ghcb->SaveArea.Rdx =3D Regs->Rdx; + GhcbSetRegValid (Ghcb, GhcbRdx); + + Status =3D VmgExit (Ghcb, SvmExitMonitor, 0, 0); + if (Status) { + return Status; + } + + return 0; +} + STATIC UINT64 WbinvdExit ( @@ -1076,6 +1103,10 @@ DoVcCommon ( NaeExit =3D WbinvdExit; break; =20 + case SvmExitMonitor: + NaeExit =3D MonitorExit; + break; + case SvmExitNpf: NaeExit =3D MmioExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:07:50 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:50 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 23/42] UefiCpuPkg/CpuExceptionHandler: Add support for MWAIT/MWAITX NAE events Date: Mon, 2 Mar 2020 17:06:54 -0600 Message-Id: <39e5528af8aeeab437941691c1bc85d9b0ade353.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: MRjzlyo5GNRvs5LujtjzVbK5x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190476; bh=MIe50KX1FyhrRVXyJLEODuSUn3Bbqo8pniFqf02pOtk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=GsFqIjFGJ3XvQ++9WJfT+h9Rdf/9KkO0JkqD1AzWneJjxzJY9LLmuBTaBdg3+clrhti bRmZpnMnYqQpaUoCfgZU5RpCoxbkH8J+HWcVOEG4Iq0L/cxHBIqtHLhcaj7q3ljMHzgHR a0tW+pGcwYmFeUK+ksW3y1/U1ps5E5KN54o= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a MWAIT/MWAITX intercept generates a #VC exception. VMGEXIT must be used to allow the hypervisor to handle this intercept. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index 784229c5ca8d..c35cfabd4069 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -591,6 +591,31 @@ MmioExit ( return Status; } =20 +STATIC +UINT64 +MwaitExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + Ghcb->SaveArea.Rax =3D Regs->Rax; + GhcbSetRegValid (Ghcb, GhcbRax); + Ghcb->SaveArea.Rcx =3D Regs->Rcx; + GhcbSetRegValid (Ghcb, GhcbRcx); + + Status =3D VmgExit (Ghcb, SvmExitMwait, 0, 0); + if (Status) { + return Status; + } + + return 0; +} + STATIC UINT64 MonitorExit ( @@ -1107,6 +1132,10 @@ DoVcCommon ( NaeExit =3D MonitorExit; break; =20 + case SvmExitMwait: + NaeExit =3D MwaitExit; + break; + case SvmExitNpf: NaeExit =3D MmioExit; break; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:07:50 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8394c731-4b7e-482b-df52-08d7befe8839 X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55267+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: Ep8t7oiShyByKwu+QyoT+hCVY/n88KoEcKu2hCsA+szqu8Ok8KSVpir5QdhVyx1vqcw4yvHBrYPxVlkc00EvgrRcbB75tzvPNhHO2iCpKGxa01AeJnKZx3vGI6tNfb2q80YPSYAOBDq/p68wrj15iw1xeAHOTA7jKUtS6sxiFA8E/agJplJYtryLGziP75F9DlDwXVh9qsi/pWPEh0d68zr8OP9t092JuCWg256GybTk1MTeC6qRJpBT4bqEZS8ApBcIe1lW8bmlW7Zk0aRTwf/LEht/Ie0/SM7L87ir45rx7tUDMONJCDhFXQwm7R6ZwmY3n6xJz7MxZd2tBvZgab6SU6hdpv6L/AvJSUCzuHSnIHGSWUpewkvXcupfjz+RLx/Kr6dNsjscJXX8gp1EZqA5M+P1ERyJIY6zNKTLaUpV4OeZRhpWCAcQubtW7y7tj16u4/GW38gkPIgTLThJV/yQxkftqhomIJr6p1Bq5qbRJHYdCLIZl0VjD1EU5SXtP/KHJ/GRrZGceBOj5Rr/Dw== X-MS-Exchange-AntiSpam-MessageData: T5N9o/kvJ8SP7duFVO4kkibb0e43ojq/Hsmb8h/yiDUHZ01PmzlBWJYUBiYwGXTmIFG02eTUbzoKxogK+6zmPS4SntZzc0iATzwWi90QTcNruKcha9bZ3JpZaA7g9Gv1AhZRuwMbkZ4i8eADu++I6w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8394c731-4b7e-482b-df52-08d7befe8839 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:51.5497 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qrJdu/3HBDesZ0qgxHvHcWUizLp/h8fMeN62Cn2NWL9zjp2DsShRO2CBbfmQ0wsFy1eLKI5CgjVa2u1KFlwT1g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: fICl7G3wcRrjnlfqEWuulspPx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190477; bh=cd0wh7WBpVcPqotihPBLaDHahrCM2VCfz7w2340cxIk=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=FaJHKB45ABfBR8RjHpGY9MgOyRPQ1ru8QFUtRubRdcLrcy69B3lAGZeA9m6UmDBfr/r Z4AGjr57uGEy21ZHTaeqc228abIOxURcr5eJskc4DGJ24dZKpaIM0sfpVvXINIw7qYFr0 LL3XhaGjntj5LqYNCMrZU+N40q5sD6JqhDE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Under SEV-ES, a DR7 read or write intercept generates a #VC exception. The #VC handler must provide special support to the guest for this. On a DR7 write, the #VC handler must cache the value and issue a VMGEXIT to notify the hypervisor of the write. However, the #VC handler must not actually set the value of the DR7 register. On a DR7 read, the #VC handler must return the cached value of the DR7 register to the guest. VMGEXIT is not invoked for a DR7 register read. To avoid exception recursion, a #VC exception will not try to read and push the actual debug registers into the EFI_SYSTEM_CONTEXT_X64 struct and instead push zeroes. The #VC exception handler does not make use of the debug registers from saved context. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- .../X64/ArchAMDSevVcHandler.c | 68 +++++++++++++++++++ .../X64/ExceptionHandlerAsm.nasm | 17 +++++ 2 files changed, 85 insertions(+) diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHand= ler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c index c35cfabd4069..253eeb54f65a 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchAMDSevVcHandler.c @@ -13,6 +13,12 @@ =20 #define CR4_OSXSAVE (1 << 18) =20 +#define DR7_RESET_VALUE 0x400 +typedef struct { + BOOLEAN Dr7Cached; + UINT64 Dr7; +} SEV_ES_PER_CPU_DATA; + typedef enum { LongMode64Bit =3D 0, LongModeCompat32Bit, @@ -1076,6 +1082,60 @@ RdtscExit ( return 0; } =20 +STATIC +UINT64 +Dr7WriteExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext =3D &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData =3D (SEV_ES_PER_CPU_DATA *) (G= hcb + 1); + INTN *Register; + UINT64 Status; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD =3D=3D 3 no matter how encoded */ + Register =3D GetRegisterPointer (Regs, Ext->ModRm.Rm); + + /* Using a value of 0 for ExitInfo1 means RAX holds the value */ + Ghcb->SaveArea.Rax =3D *Register; + GhcbSetRegValid (Ghcb, GhcbRax); + + Status =3D VmgExit (Ghcb, SvmExitDr7Write, 0, 0); + if (Status) { + return Status; + } + + SevEsData->Dr7 =3D *Register; + SevEsData->Dr7Cached =3D TRUE; + + return 0; +} + +STATIC +UINT64 +Dr7ReadExit ( + GHCB *Ghcb, + EFI_SYSTEM_CONTEXT_X64 *Regs, + SEV_ES_INSTRUCTION_DATA *InstructionData + ) +{ + SEV_ES_INSTRUCTION_OPCODE_EXT *Ext =3D &InstructionData->Ext; + SEV_ES_PER_CPU_DATA *SevEsData =3D (SEV_ES_PER_CPU_DATA *) (G= hcb + 1); + INTN *Register; + + DecodeModRm (Regs, InstructionData); + + /* MOV DRn always treats MOD =3D=3D 3 no matter how encoded */ + Register =3D GetRegisterPointer (Regs, Ext->ModRm.Rm); + *Register =3D (SevEsData->Dr7Cached) ? SevEsData->Dr7 : DR7_RESET_VALUE; + + return 0; +} + UINTN DoVcCommon ( GHCB *Ghcb, @@ -1092,6 +1152,14 @@ DoVcCommon ( =20 ExitCode =3D Regs->ExceptionData; switch (ExitCode) { + case SvmExitDr7Read: + NaeExit =3D Dr7ReadExit; + break; + + case SvmExitDr7Write: + NaeExit =3D Dr7WriteExit; + break; + case SvmExitRdtsc: NaeExit =3D RdtscExit; break; diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandler= Asm.nasm b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAs= m.nasm index 19198f273137..26cae56cc5cf 100644 --- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm +++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ExceptionHandlerAsm.nasm @@ -18,6 +18,8 @@ ; CommonExceptionHandler() ; =20 +%define VC_EXCEPTION 29 + extern ASM_PFX(mErrorCodeFlag) ; Error code flags for exceptions extern ASM_PFX(mDoFarReturnFlag) ; Do far return flag extern ASM_PFX(CommonExceptionHandler) @@ -225,6 +227,9 @@ HasErrorCode: push rax =20 ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; + cmp qword [rbp + 8], VC_EXCEPTION + je VcDebugRegs ; For SEV-ES (#VC) Debug registers ignored + mov rax, dr7 push rax mov rax, dr6 @@ -237,7 +242,19 @@ HasErrorCode: push rax mov rax, dr0 push rax + jmp DrFinish =20 +VcDebugRegs: +;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7 are skipped for #VC to avoid excep= tion recursion + xor rax, rax + push rax + push rax + push rax + push rax + push rax + push rax + +DrFinish: ;; FX_SAVE_STATE_X64 FxSaveState; sub rsp, 512 mov rdi, rsp --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:07:53 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:52 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 25/42] OvmfPkg/MemEncryptSevLib: Add an SEV-ES guest indicator function Date: Mon, 2 Mar 2020 17:06:56 -0600 Message-Id: <90437a20a8661bdb3d7b5009a088e3323a048014.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Ce1f5op27MKeSQoQFVNz7m3Lx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190477; bh=lXg+spFzEQC7yLzUxR8Vb0RICInNXGIrkjv03zkfXnI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=PP2HaW5iLXv8OT2tGygFFzm4tFEWqaq8D03oFrwAiNxKp6rj+Ybht1KcXEf3tHxpOv4 GyWUoAV2tcO4+TI5r2pi/dyaXCyfxqIKPNKTnqlJi6+chFcUcBKXP7CCCSDeyDEfbx7sA VZD38Cro9ysRkVWo1/9VdRCSPd6Q+m2tIac= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Create a function that can be used to determine if the VM is running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Include/Library/MemEncryptSevLib.h | 12 +++ .../MemEncryptSevLibInternal.c | 75 ++++++++++++------- 2 files changed, 60 insertions(+), 27 deletions(-) diff --git a/OvmfPkg/Include/Library/MemEncryptSevLib.h b/OvmfPkg/Include/L= ibrary/MemEncryptSevLib.h index 64dd6977b0f8..a50a0de9c870 100644 --- a/OvmfPkg/Include/Library/MemEncryptSevLib.h +++ b/OvmfPkg/Include/Library/MemEncryptSevLib.h @@ -13,6 +13,18 @@ =20 #include =20 +/** + Returns a boolean to indicate whether SEV-ES is enabled + + @retval TRUE SEV-ES is enabled + @retval FALSE SEV-ES is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevEsIsEnabled ( + VOID + ); + /** Returns a boolean to indicate whether SEV is enabled =20 diff --git a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.= c b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c index 96a66e373f11..c859bb141963 100644 --- a/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c +++ b/OvmfPkg/Library/BaseMemEncryptSevLib/MemEncryptSevLibInternal.c @@ -20,19 +20,17 @@ #include =20 STATIC BOOLEAN mSevStatus =3D FALSE; +STATIC BOOLEAN mSevEsStatus =3D FALSE; STATIC BOOLEAN mSevStatusChecked =3D FALSE; =20 /** =20 - Returns a boolean to indicate whether SEV is enabled - - @retval TRUE SEV is enabled - @retval FALSE SEV is not enabled + Reads and sets the status of SEV features **/ STATIC -BOOLEAN +VOID EFIAPI -InternalMemEncryptSevIsEnabled ( +InternalMemEncryptSevStatus ( VOID ) { @@ -56,32 +54,55 @@ InternalMemEncryptSevIsEnabled ( // Msr.Uint32 =3D AsmReadMsr32 (MSR_SEV_STATUS); if (Msr.Bits.SevBit) { - return TRUE; + mSevStatus =3D TRUE; + } + + // + // Check MSR_0xC0010131 Bit 1 (Sev-Es Enabled) + // + if (Msr.Bits.SevEsBit) { + mSevEsStatus =3D TRUE; } } } =20 - return FALSE; -} - -/** - Returns a boolean to indicate whether SEV is enabled - - @retval TRUE SEV is enabled - @retval FALSE SEV is not enabled -**/ -BOOLEAN -EFIAPI -MemEncryptSevIsEnabled ( - VOID - ) -{ - if (mSevStatusChecked) { - return mSevStatus; - } - - mSevStatus =3D InternalMemEncryptSevIsEnabled(); mSevStatusChecked =3D TRUE; +} + +/** + Returns a boolean to indicate whether SEV-ES is enabled + + @retval TRUE SEV-ES is enabled + @retval FALSE SEV-ES is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevEsIsEnabled ( + VOID + ) +{ + if (!mSevStatusChecked) { + InternalMemEncryptSevStatus(); + } + + return mSevEsStatus; +} + +/** + Returns a boolean to indicate whether SEV is enabled + + @retval TRUE SEV is enabled + @retval FALSE SEV is not enabled +**/ +BOOLEAN +EFIAPI +MemEncryptSevIsEnabled ( + VOID + ) +{ + if (!mSevStatusChecked) { + InternalMemEncryptSevStatus(); + } =20 return mSevStatus; } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:07:53 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:07:53 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 26/42] OvmfPkg: Add support to perform SEV-ES initialization Date: Mon, 2 Mar 2020 17:06:57 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:07:52 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: b8ba4907-863d-4eb3-bdb5-08d7befe895f X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55262+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: S416OsW2jD8AQme90G0ivGFrw3yo7L+oyFWwT5CTVLZqXFku3bMl3BklY/stLRjCWVbcfgqTnikWTUJvY+bGTELBk40AXYPD4R/VRaCiRt32MW114LgvxeUxYho3RrYvNpN8rLONk6ojYj80yBjgrlHZeASl6tKXy8kSiPLnSBhY1k6pbTdV1yE7Df7wkkAi4qEPneLR5TGYAOqJvu8wtL4AGa1zjEEu56DUzRhC2chV7DoBz8LtFOGkTRxPLeoHNGaZEXr5z/QpISmClTVmWT/+ndwQx6kD8QP8Be/cNdENlNN/xhJJYLSHcRN+sequ49HWR/hVdStH64qTuo/eo/ULhNVjctjaFphFTiyxhGtXQtUE6nBmXitn0tU0GQiR4aXkdvMYco4ZUuzibJv83mvnSTHqGtDrvMMq9PAh4EpmTRFaI4mC7wRFIu5wAcrk9MgNMhUllb55Q7QdWKdToSlzlQuQ57gmNvYp3iTrbJahucYLHqBlpG0D7JFb1uaN92XPldxX2Yab6lF8Empbbw== X-MS-Exchange-AntiSpam-MessageData: roTJeBbKf5SOBjhj3P8o9Tp7FZZ+TiSTiqTDlz5cH839fuC4uK8Kiwwo9dafIGMlKAkmrlOKejwlYPw1258L1ZwD7aoSAYIkzEIaL+0HDkcwfW4bZVhQ+Qu2X5v5VM4ZYmJpHuWkmhjIeUFVTdsjWw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: b8ba4907-863d-4eb3-bdb5-08d7befe895f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:53.4136 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Q3d/34UgOPk+UbwFfdjAyBPLjzkJIW+MZDW51CfXPZBbloqO1kzf6LPOLMXy82V1lgZB2BDc5mw0EfXCGYc4JA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: na5GnhFpTcICAsJIZU8f6gETx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190476; bh=ymTL2Heog/QKaBMCgKRztvhpKJI1mdEOD8qB4Om7oWA=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=F5FISrYL20T1jGlV7YUthGm0kstSaaEuSzFfygbNLM+Y9BVT6gJFp43tl5m/LbNI0KM vXOeWPrzQKOwFMY4ewdaIX/m8S+cjIiTeEk7jX1eFkZx0dtHO9BJvj5qngEt62DplvhGA OI9G8CI59Ihx1QdZpMCTM2mYaIz+TgdOdrI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 When SEV-ES is enabled, then SEV is also enabled. Add support to the SEV initialization function to also check for SEV-ES being enabled, and if enabled, set the SEV-ES enabled PCD (PcdSevEsIsEnabled). Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 3 +++ OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++ OvmfPkg/OvmfPkgX64.dsc | 3 +++ OvmfPkg/PlatformPei/PlatformPei.inf | 1 + OvmfPkg/PlatformPei/AmdSev.c | 26 ++++++++++++++++++++++++++ 5 files changed, 36 insertions(+) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index c842404287dc..6eb3817909f4 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -567,6 +567,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index c082617be9d8..fa521321e2b3 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -579,6 +579,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index d3a96e5a7be6..dd6f86fa087d 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -578,6 +578,9 @@ [PcdsDynamicDefault] # Set memory encryption mask gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 + # Set SEV-ES defaults + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 + !if $(SMM_REQUIRE) =3D=3D TRUE gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8 gUefiOvmfPkgTokenSpaceGuid.PcdQ35SmramAtDefaultSmbase|FALSE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index c51a6176aa2e..5b2585a4f09c 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -101,6 +101,7 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuBootLogicalProcessorNumber gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled =20 [FixedPcd] gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index e484f4b311fe..4dc5340caa7a 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -21,6 +21,27 @@ =20 #include "Platform.h" =20 +/** + + Initialize SEV-ES support if running as an SEV-ES guest. + + **/ +STATIC +VOID +AmdSevEsInitialize ( + VOID + ) +{ + RETURN_STATUS PcdStatus; + + if (!MemEncryptSevEsIsEnabled ()) { + return; + } + + PcdStatus =3D PcdSetBoolS (PcdSevEsIsEnabled, TRUE); + ASSERT_RETURN_ERROR (PcdStatus); +} + /** =20 Function checks if SEV support is available, if present then it sets @@ -103,4 +124,9 @@ AmdSevInitialize ( ); } } + + // + // Check and perform SEV-ES initialization if required. + // + AmdSevEsInitialize (); } --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: hMTLFdQrvQFWJ6TouOm9Utysx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190476; bh=z4vOYkQi9ZrdR8qgFAK7ApKUeGDMMS3rx/umGPuhAWI=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=O2LAU1arKkCEbzEIh2QkO/Ywtc7KDywbqFS8HP7CJYh9+8qYnjEMj4zxl10NXH4zj2R LSU5YphcLI/AmS+yFYW5VyVEU6KKFcyWc6yPmxhiI6vcnuKx0oJVNLohrGVcSeSpHcSMW j9ib4+aNnmEgxkGzN5ewzm0tgDf0LNWR9GE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A GHCB page is needed during the Sec phase, so this new page must be created. Since the #VC exception handler routines assume that a per-CPU variable area is immediately after the GHCB, this per-CPU variable area must also be created. Since the GHCB must be marked as an un-encrypted, or shared, page, an additional pagetable page is required to break down the 2MB region where the GHCB page lives into 4K pagetable entries. Create a new entry in the OVMF memory layout for the new page table page and for the SEC GHCB and per-CPU variable pages. After breaking down the 2MB page, update the GHCB page table entry to remove the encryption mask. The GHCB page will be used by the SEC #VC exception handler. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB in order to perform the requested function. Two new fixed PCDs are needed to support the SEC GHCB page: - PcdOvmfSecGhcbBase UINT64 value that is the base address of the GHCB used during the SEC phase. - PcdOvmfSecGhcbSize UINT64 value that is the size, in bytes, of the GHCB area used during the SEC phase. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkg.dec | 9 +++ OvmfPkg/OvmfPkgX64.fdf | 6 ++ OvmfPkg/ResetVector/ResetVector.inf | 5 ++ OvmfPkg/ResetVector/Ia32/PageTables64.asm | 76 +++++++++++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 17 +++++ 5 files changed, 113 insertions(+) diff --git a/OvmfPkg/OvmfPkg.dec b/OvmfPkg/OvmfPkg.dec index 4c5b6511cb97..0e11913ee2e4 100644 --- a/OvmfPkg/OvmfPkg.dec +++ b/OvmfPkg/OvmfPkg.dec @@ -228,6 +228,15 @@ [PcdsFixedAtBuild] ## Number of page frames to use for storing grant table entries. gUefiOvmfPkgTokenSpaceGuid.PcdXenGrantFrames|4|UINT32|0x33 =20 + ## Specify the extra page table needed to mark the GHCB as unencrypted. + # The value should be a multiple of 4KB for each. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|0x0|UINT32|0x34 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize|0x0|UINT32|0x35 + + ## The base address of the SEC GHCB page used by SEV-ES. + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|0|UINT32|0x36 + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize|0|UINT32|0x37 + [PcdsDynamic, PcdsDynamicEx] gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10 diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index 0488e5d95ffe..39291f413f6d 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -76,6 +76,12 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize =20 +0x008000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase|gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfSecGhcbPageTableSize + +0x009000|0x002000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|gUefiOvmfPkgTokenSpaceGuid.P= cdOvmfSecGhcbSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index b0ddfa5832a2..483fd90fe785 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -26,6 +26,7 @@ [Sources] [Packages] OvmfPkg/OvmfPkg.dec MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec UefiCpuPkg/UefiCpuPkg.dec =20 [BuildOptions] @@ -33,5 +34,9 @@ [BuildOptions] *_*_X64_NASMB_FLAGS =3D -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ =20 [Pcd] + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index abad009f20f5..9f86ddf6f08f 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -21,6 +21,11 @@ BITS 32 %define PAGE_2M_MBO 0x080 %define PAGE_2M_PAT 0x01000 =20 +%define PAGE_4K_PDE_ATTR (PAGE_ACCESSED + \ + PAGE_DIRTY + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + %define PAGE_2M_PDE_ATTR (PAGE_2M_MBO + \ PAGE_ACCESSED + \ PAGE_DIRTY + \ @@ -75,6 +80,37 @@ NoSev: SevExit: OneTimeCallRet CheckSevFeature =20 +; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feat= ure +; is enabled. +; +; Modified: EAX, EBX, ECX +; +; If SEV-ES is enabled then EAX will be non-zero. +; If SEV-ES is disabled then EAX will be zero. +; +CheckSevEsFeature: + xor eax, eax + + ; SEV-ES can't be enabled if SEV isn't, so first check the encryption + ; mask. + test edx, edx + jz NoSevEs + + ; Save current value of encryption mask + mov ebx, edx + + ; Check if SEV-ES is enabled + ; MSR_0xC0010131 - Bit 1 (SEV-ES enabled) + mov ecx, 0xc0010131 + rdmsr + and eax, 2 + + ; Restore encryption mask + mov edx, ebx + +NoSevEs: + OneTimeCallRet CheckSevEsFeature + ; ; Modified: EAX, EBX, ECX, EDX ; @@ -139,6 +175,46 @@ pageTableEntriesLoop: mov [(ecx * 8 + PT_ADDR (0x2000 - 8)) + 4], edx loop pageTableEntriesLoop =20 + OneTimeCall CheckSevEsFeature + test eax, eax + jz SetCr3 + + ; + ; The initial GHCB will live at GHCB_BASE and needs to be un-encrypted. + ; This requires the 2MB page for this range be broken down into 512 4KB + ; pages. All will be marked encrypted, except for the GHCB. + ; + mov ecx, (GHCB_BASE >> 21) + mov eax, GHCB_PT_ADDR + PAGE_PDP_ATTR + mov [ecx * 8 + PT_ADDR (0x2000)], eax + + ; + ; Page Table Entries (512 * 4KB entries =3D> 2MB) + ; + mov ecx, 512 +pageTableEntries4kLoop: + mov eax, ecx + dec eax + shl eax, 12 + add eax, GHCB_BASE & 0xFFE0_0000 + add eax, PAGE_4K_PDE_ATTR + mov [ecx * 8 + GHCB_PT_ADDR - 8], eax + mov [(ecx * 8 + GHCB_PT_ADDR - 8) + 4], edx + loop pageTableEntries4kLoop + + ; + ; Clear the encryption bit from the GHCB entry + ; + mov ecx, (GHCB_BASE & 0x1F_FFFF) >> 12 + mov [ecx * 8 + GHCB_PT_ADDR + 4], strict dword 0 + + mov ecx, GHCB_SIZE / 4 + xor eax, eax +clearGhcbMemoryLoop: + mov dword[ecx * 4 + GHCB_BASE - 4], eax + loop clearGhcbMemoryLoop + +SetCr3: ; ; Set CR3 now that the paging structures are available ; diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 75cfe16654b1..bfb77e439105 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -53,8 +53,25 @@ %error "This implementation inherently depends on PcdOvmfSecPageTables= Size" %endif =20 + %if (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize) !=3D 0x1000) + %error "This implementation inherently depends on PcdOvmfSecGhcbPageTa= bleSize" + %endif + + %if (FixedPcdGet32 (PcdOvmfSecGhcbSize) !=3D 0x2000) + %error "This implementation inherently depends on PcdOvmfSecGhcbSize" + %endif + + %if ((FixedPcdGet32 (PcdOvmfSecGhcbBase) >> 21) !=3D \ + ((FixedPcdGet32 (PcdOvmfSecGhcbBase) + FixedPcdGet32 (PcdOvmfSecGhc= bSize) - 1) >> 21)) + %error "This implementation inherently depends on PcdOvmfSecGhcbBase n= ot straddling a 2MB boundary" + %endif + %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) %include "Ia32/Flat32ToFlat64.asm" + + %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) + %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) + %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) %include "Ia32/PageTables64.asm" %endif =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55263): https://edk2.groups.io/g/devel/message/55263 Mute This Topic: https://groups.io/mt/71687819/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55268+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190479230399.73144701749095; Mon, 2 Mar 2020 15:07:59 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id UgiUYY1788612xDgNOVmtw8J; Mon, 02 Mar 2020 15:07:58 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.694.1583190475799820802 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: ybV9lNHtNj4QMgBWnBhNQIxnx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190478; bh=tSHpN2vlEGm1y48eKvD0Ijwv0XcIvM7AX72IUI1EwVY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=sYAyY1iZkHLLE2QcwD1T4+ynEt7kP/Mv6edVVHMITOYKJreNy6dmrkENbJbZhX0CVlD If/yfKm7nd7qLNbnRlaqKwX5P39FPGtfvQNQGdjA/UIzi6Pko+AdDOWdZMxKiZ72sqsUF cHCfxr/bUVhwDIL0km2+yhhYwY325aJLjD4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Protect the memory used by an SEV-ES guest when S3 is supported. This includes the page table used to break down the 2MB page that contains the GHCB so that it can be marked un-encrypted, as well as the GHCB area. Regarding the lifecycle of the GHCB-related memory areas: PcdOvmfSecGhcbPageTableBase PcdOvmfSecGhcbBase (a) when and how it is initialized after first boot of the VM If SEV-ES is enabled, the GHCB-related areas are initialized during the SEC phase [OvmfPkg/ResetVector/Ia32/PageTables64.asm]. (b) how it is protected from memory allocations during DXE If S3 and SEV-ES are enabled, then InitializeRamRegions() [OvmfPkg/PlatformPei/MemDetect.c] protects the ranges with an AcpiNVS memory allocation HOB, in PEI. If S3 is disabled, then these ranges are not protected. DXE's own page tables are first built while still in PEI (see HandOffToDxeCore() [MdeModulePkg/Core/DxeIplPeim/X64/DxeLoadFunc.c]). Those tables are located in permanent PEI memory. After CR3 is switched over to them (which occurs before jumping to the DXE core entry point), we don't have to preserve PcdOvmfSecGhcbPageTableBase. PEI switches to GHCB pages in permanent PEI memory and DXE will use these PEI GHCB pages, so we don't have to preserve PcdOvmfSecGhcbBase. (c) how it is protected from the OS If S3 is enabled, then (b) reserves it from the OS too. If S3 is disabled, then the range needs no protection. (d) how it is accessed on the S3 resume path It is rewritten same as in (a), which is fine because (b) reserved it. (e) how it is accessed on the warm reset path It is rewritten same as in (a). Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Cc: Anthony Perard Cc: Julien Grall Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/PlatformPei.inf | 4 ++++ OvmfPkg/PlatformPei/MemDetect.c | 23 +++++++++++++++++++++++ 2 files changed, 27 insertions(+) diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 5b2585a4f09c..f1c2024526c8 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -72,6 +72,10 @@ [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 47dc9c543719..200021098161 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -27,6 +27,7 @@ Module Name: #include #include #include +#include #include #include #include @@ -860,6 +861,28 @@ InitializeRamRegions ( (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize), EfiACPIMemoryNVS ); + + if (MemEncryptSevEsIsEnabled ()) { + // + // If SEV-ES is enabled, reserve the GHCB-related memory area. This + // includes the extra page table used to break down the 2MB page + // mapping into 4KB page entries where the GHCB resides and the + // GHCB area itself. + // + // Since this memory range will be used by the Reset Vector on S3 + // resume, it must be reserved as ACPI NVS. + // + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableBas= e), + (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbPageTableSize), + EfiACPIMemoryNVS + ); + BuildMemoryAllocationHob ( + (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecGhcbBase), + (UINT64)(UINTN) PcdGet32 (PcdOvmfSecGhcbSize), + EfiACPIMemoryNVS + ); + } #endif } =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55268): https://edk2.groups.io/g/devel/message/55268 Mute This Topic: https://groups.io/mt/71687825/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55269+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 158319047959986.25251687441198; Mon, 2 Mar 2020 15:07:59 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7AfgYY1788612xTAEixPQkKg; Mon, 02 Mar 2020 15:07:58 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.694.1583190475799820802 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: My8JZpLA3H3rd4MMyb6gYILhx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190478; bh=NwI97HuYsLKJOgAjwG7liFYwD3ym8jPnFOCnajdVY7s=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=O+RdF7kIMiXlSISv2hbqMTeg216HVdWYG4W1aqY7gRqh2B91Y1PnE103HOoHvEYSDTu YTt9jR9Rb2YI76I4S/7KBR40tXA0WUjYqXmNw80bK8VF/ueleh06UNJTYL7LyWX5O3abJ JKSKmTIgZ/Cz8GQAY3/T0MBMA1YjYYMIHKg= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Allocate memory for the GHCB pages and the per-CPU variable pages during SEV initialization for use during Pei and Dxe phases. The GHCB page(s) must be shared pages, so clear the encryption mask from the current page table entries. Upon successful allocation, set the GHCB PCDs (PcdGhcbBase and PcdGhcbSize). The per-CPU variable page needs to be unique per AP. Using the page after the GHCB ensures that it is unique per AP. But, it also ends up being marked shared/unencrypted when it doesn't need to be. It is possible during PEI to mark only the GHCB pages as shared (and that is done), but DXE is not as easy. There needs to be a way to change the pagetables created for DXE using CreateIdentityMappingPageTables() before switching to them. The GHCB pages (one per vCPU) will be used by the PEI and DXE #VC exception handlers. The #VC exception handler will fill in the necessary fields of the GHCB and exit to the hypervisor using the VMGEXIT instruction. The hypervisor then accesses the GHCB associated with the vCPU in order to perform the requested function. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 2 ++ OvmfPkg/OvmfPkgIa32X64.dsc | 2 ++ OvmfPkg/OvmfPkgX64.dsc | 2 ++ OvmfPkg/PlatformPei/PlatformPei.inf | 2 ++ OvmfPkg/PlatformPei/AmdSev.c | 38 ++++++++++++++++++++++++++++- 5 files changed, 45 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 6eb3817909f4..51d7acafdda3 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -568,6 +568,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index fa521321e2b3..764fa8c287a0 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -580,6 +580,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index dd6f86fa087d..b6e29e09db97 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -579,6 +579,8 @@ [PcdsDynamicDefault] gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask|0x0 =20 # Set SEV-ES defaults + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase|0 + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize|0 gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled|0 =20 !if $(SMM_REQUIRE) =3D=3D TRUE diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index f1c2024526c8..47fc7e9c65aa 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -100,6 +100,8 @@ [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPropertiesTableEnable gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiS3Enable gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 4dc5340caa7a..5f0946763507 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -10,12 +10,15 @@ // The package level header files this module uses // #include +#include #include #include #include +#include #include #include #include +#include #include #include =20 @@ -32,7 +35,10 @@ AmdSevEsInitialize ( VOID ) { - RETURN_STATUS PcdStatus; + VOID *GhcbBase; + PHYSICAL_ADDRESS GhcbBasePa; + UINTN GhcbPageCount; + RETURN_STATUS PcdStatus, DecryptStatus; =20 if (!MemEncryptSevEsIsEnabled ()) { return; @@ -40,6 +46,36 @@ AmdSevEsInitialize ( =20 PcdStatus =3D PcdSetBoolS (PcdSevEsIsEnabled, TRUE); ASSERT_RETURN_ERROR (PcdStatus); + + // + // Allocate GHCB and per-CPU variable pages. + // + GhcbPageCount =3D mMaxCpuCount * 2; + GhcbBase =3D AllocatePages (GhcbPageCount); + ASSERT (GhcbBase !=3D NULL); + + GhcbBasePa =3D (PHYSICAL_ADDRESS)(UINTN) GhcbBase; + + DecryptStatus =3D MemEncryptSevClearPageEncMask ( + 0, + GhcbBasePa, + GhcbPageCount, + TRUE + ); + ASSERT_RETURN_ERROR (DecryptStatus); + + ZeroMem (GhcbBase, EFI_PAGES_TO_SIZE (GhcbPageCount)); + + PcdStatus =3D PcdSet64S (PcdGhcbBase, GhcbBasePa); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdGhcbSize, EFI_PAGES_TO_SIZE (GhcbPageCount)); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG ((DEBUG_INFO, + "SEV-ES is enabled, %lu GHCB pages allocated starting at 0x%p\n", + (UINT64)GhcbPageCount, GhcbBase)); + + AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); } =20 /** --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: MpUJbmDO98j2eyJhZSlYsswqx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190508; bh=o3pAN4nqE/SYJtOISIlAqnkWTQ77gmdUyaEQmGad51I=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=AgJTv/DjUFzf87zGewaut53yU10b0K8KaxBE4wyQJJPjP5LpiudGvuYi2eBMJYh7gNR xUZMV9E9iIH7+sp/JUjkxM9GTbDKF94LzXkK6CfqHIW8FQ421gS4aBifwyM+fugHI1lJa pWUJ+EJkOfjrittbWUai2oonvfDUEXZFqbA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The SEV support will clear the C-bit from non-RAM areas. The early GDT lives in a non-RAM area, so when an exception occurs (like a #VC) the GDT will be read as un-encrypted even though it is encrypted. This will result in a failure to be able to handle the exception. Move the GDT into RAM so it can be accessed without error when running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/AmdSev.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 5f0946763507..38885de359af 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -39,6 +39,8 @@ AmdSevEsInitialize ( PHYSICAL_ADDRESS GhcbBasePa; UINTN GhcbPageCount; RETURN_STATUS PcdStatus, DecryptStatus; + IA32_DESCRIPTOR Gdtr; + VOID *Gdt; =20 if (!MemEncryptSevEsIsEnabled ()) { return; @@ -76,6 +78,22 @@ AmdSevEsInitialize ( (UINT64)GhcbPageCount, GhcbBase)); =20 AsmWriteMsr64 (MSR_SEV_ES_GHCB, GhcbBasePa); + + // + // The SEV support will clear the C-bit from non-RAM areas. The early G= DT + // lives in a non-RAM area, so when an exception occurs (like a #VC) the= GDT + // will be read as un-encrypted even though it was created before the C-= bit + // was cleared (encrypted). This will result in a failure to be able to + // handle the exception. + // + AsmReadGdtr (&Gdtr); + + Gdt =3D AllocatePages (EFI_SIZE_TO_PAGES ((UINTN) Gdtr.Limit + 1)); + ASSERT (Gdt !=3D NULL); + + CopyMem (Gdt, (VOID *) Gdtr.Base, Gdtr.Limit + 1); + Gdtr.Base =3D (UINTN) Gdt; + AsmWriteGdtr (&Gdtr); } =20 /** --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55270): https://edk2.groups.io/g/devel/message/55270 Mute This Topic: https://groups.io/mt/71687832/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55271+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190510442918.5651161690254; Mon, 2 Mar 2020 15:08:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id X6wNYY1788612xaf1pl1qLo4; Mon, 02 Mar 2020 15:08:29 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.698.1583190508386134261 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:08:27 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:08:27 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 31/42] UefiCpuPkg: Create an SEV-ES workarea PCD Date: Mon, 2 Mar 2020 17:07:02 -0600 Message-Id: <2fc229ff271b4127b01f4e327c7c9feb1289f1ca.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:07:57 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 290c6347-6886-4346-2422-08d7befe8c20 X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3383; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55271+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: COzlBJ0U3FDjD4Krz15w0gRvj23Wsdq2vp1DJUUw+vcu8GFv+uHXqgNONOiUQgJT3EDIcV0Lk0iv4cn5pZ146GjUpcGDUfT6Woc3mt7ATh2eVvTvQ7ksEDQIvJ84gtmPzPK2fFt3sfM2BNoqf32f2zQrYYOlZou92/M5PIsX+/1Ivm1TlyYPkWwUSwgGbzSvRjS4vakq/6aVx9WJCMt2e4xJJFbUUcXvrjDqkyjjU7Z4z67NKuGS/BnZIX8bftL2R+p1N6yxx1iaLbS2p3c96/VaC/6neTScgOj2NWGc3x168Tbdxn+NWNZKwuPoqcdYk04j9A/QBJUc3nvQv3IVaHcmXEOXi5yXTKjOzUh6CYMoO6GX+m0hPG28aittiTV7ox8tLKbWBsJxZQ01P7nm2xwc21R0pEsaI6V0iKEg/wFVJ6KacveIfHzz1ZGsOj+iXtP3zJF+r8QQBskdxCeBQVV2SI1NzqZ56AJ9kJVvypX2T2K4Aq9BV3jt6WLHz4wIbi0YrPKrkVX2uEcMm0AeFQ== X-MS-Exchange-AntiSpam-MessageData: 3RkwLUJ0nMfeT3GwtTBluf5UVTExA38AQKmlWx0bbzaULC2rUjlupA+/j8KKolCV6h9MLh224V3yDmNrkZ9tILcUtlpbYyHoDf5xNlnjV3qNgdSxi/IFYe2nOquWNLxy851EXC5K0UpE4ogN7EcsGQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 290c6347-6886-4346-2422-08d7befe8c20 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:07:57.9830 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ISDorGL6V5EB0lFoOzoCBVs9niJrvCN2kG9jxmp2ljqIMpbYL+CDr2B9qW9OAneShoIUOCEaOCJGLIgQCglsZQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: ArlepweiFeufMZcf5qmQkZoKx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190509; bh=pG6ujXjGTAyUAhMy+BAX/5Un1AumquAactXi6COaTlY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=FiXR1+AvbNBvTIV8MKlkTl4V+urT1KH1C8jGh6AX347yVVtWCB1o+K6cUMedVNCCgGc 12cXHebmtKh69IRzM0zIma7VJHob3/siH1VfayIdu6OOFD8CX+vC/E5iJH6deqNS4TYbP vv5ZNw2ai0d8V5d/KYkTVBe7eIUZA3usagc= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Create an SEV-ES workarea PCD. This PCD will be used for BSP communication during SEC and for AP startup during PEI and DXE phases, the latter is the reason for creating it in the UefiCpuPkg. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/UefiCpuPkg.dec | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 795d1c8dedba..c3c2c7bc78de 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -161,6 +161,14 @@ [PcdsFixedAtBuild] # @Prompt Specify the count of pre allocated SMM MP tokens per chunk. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmMpTokenCountPerChunk|64|UINT32|0x3000= 2002 =20 + ## Area of memory where the SEV-ES work area block lives. + # @Prompt Configure the SEV-ES work area base + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|0x0|UINT32|0x30002005 + + ## Size of teh area of memory where the SEV-ES work area block lives. + # @Prompt Configure the SEV-ES work area base + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize|0x0|UINT32|0x30002006 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## This value is the CPU Local APIC base address, which aligns the addre= ss on a 4-KByte boundary. # @Prompt Configure base address of CPU Local APIC --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55271): https://edk2.groups.io/g/devel/message/55271 Mute This Topic: https://groups.io/mt/71687833/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55272+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190510721171.07405097457604; Mon, 2 Mar 2020 15:08:30 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id FzfcYY1788612xtdmZccVSL9; Mon, 02 Mar 2020 15:08:29 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web11.698.1583190508386134261 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:08:27 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:08:27 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 32/42] OvmfPkg: Reserve a page in memory for the SEV-ES usage Date: Mon, 2 Mar 2020 17:07:03 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: PyCp7uq8FR5v30u1Y7q1sbo7x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190509; bh=/2mkz5SCgh+nQtdM7KBDTzGB4fFXT58viq9R9JXJfIM=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=mWfu/26wCvkMjoPRPz79E6tLa4B+vEySBvXoqfiR7QJpl2XdVSD8vhO4AqPmHqH7RcQ PturOJ2ou0FVc8eA+kILPlOkxxiphS71/SI+4xNiwZYEH4YRCZw2XOW9FBuJ47SDshcdU qnCwgq9MKQUFoMKbVF4/xYBAIdDH+SK0QSk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Reserve a fixed area of memory for SEV-ES use and set a fixed PCD, PcdSevEsWorkAreaBase, to this value. This area will be used by SEV-ES support for two purposes: 1. Communicating the SEV-ES status during BSP boot to SEC: Using a byte of memory from the page, the BSP reset vector code can communicate the SEV-ES status to SEC for use before exception handling can be enabled in SEC. After SEC, this field is no longer valid and the standard way of determine if SEV-ES is active should be used. 2. Establishing an area of memory for AP boot support: A hypervisor is not allowed to update an SEV-ES guest's register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead an SEV-ES AP must be re-directed from within the guest to the actual requested staring location as specified in the INIT-SIPI-SIPI sequence. Use this memory for reset vector code that can be programmed to have the AP jump to the desired RIP location after starting the AP. This is required for only the very first AP reset. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgX64.fdf | 3 +++ 1 file changed, 3 insertions(+) diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index 39291f413f6d..0fc64075d048 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -82,6 +82,9 @@ [FD.MEMFD] 0x009000|0x002000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase|gUefiOvmfPkgTokenSpaceGuid.P= cdOvmfSecGhcbSize =20 +0x00B000|0x001000 +gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase|gUefiCpuPkgTokenSpaceGuid.P= cdSevEsWorkAreaSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55272): https://edk2.groups.io/g/devel/message/55272 Mute This Topic: https://groups.io/mt/71687834/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55273+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190511251395.7991739958172; Mon, 2 Mar 2020 15:08:31 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id nswEYY1788612xqaVqBOD55G; Mon, 02 Mar 2020 15:08:30 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com [40.107.220.47]) by mx.groups.io with SMTP id smtpd.web12.670.1583190509745452410 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:08:28 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:08:28 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 33/42] OvmfPkg/ResetVector: Add support for a 32-bit SEV check Date: Mon, 2 Mar 2020 17:07:04 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: rNtvIUOwauhUEhxddJmHiY59x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190510; bh=5gzmL0LrotkhUgotxERT97UqSmczcYy/kvtneUA0xEo=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=gKLjlNRY3WEiZjLk6bS7hvUn4VuZ+jftPIpJM+U3pnRvUiG/DFGQeiFTgF50lEciYv+ s/I1vwVvgR648ZaOB2v6IEYgWsMd8Kq2bqJ/+OhcTZ5MhTt7Gw5uxdgujEkZERySiOk3v ndBer0vOP5RzwpRg0BnC3/d5a8eEhYmjhwk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 During BSP startup, the reset vector code will issue a CPUID instruction while in 32-bit mode. When running as an SEV-ES guest, this will trigger a #VC exception. Add exception handling support to the early reset vector code to catch these exceptions. Also, since the guest is in 32-bit mode at this point, writes to the GHCB will be encrypted and thus not able to be read by the hypervisor, so use the GHCB CPUID request/response protocol to obtain the requested CPUID function values and provide these to the guest. The exception handling support is active during the SEV check and uses the OVMF temporary RAM space for a stack. After the SEV check is complete, the exception handling support is removed and the stack pointer cleared. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/ResetVector/ResetVector.inf | 3 + OvmfPkg/ResetVector/Ia32/PageTables64.asm | 275 +++++++++++++++++++++- OvmfPkg/ResetVector/ResetVector.nasmb | 2 + 3 files changed, 277 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/Rese= tVector.inf index 483fd90fe785..a53ae6c194ae 100644 --- a/OvmfPkg/ResetVector/ResetVector.inf +++ b/OvmfPkg/ResetVector/ResetVector.inf @@ -34,9 +34,12 @@ [BuildOptions] *_*_X64_NASMB_FLAGS =3D -I$(WORKSPACE)/UefiCpuPkg/ResetVector/Vtf0/ =20 [Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize diff --git a/OvmfPkg/ResetVector/Ia32/PageTables64.asm b/OvmfPkg/ResetVecto= r/Ia32/PageTables64.asm index 9f86ddf6f08f..7c72128a84d6 100644 --- a/OvmfPkg/ResetVector/Ia32/PageTables64.asm +++ b/OvmfPkg/ResetVector/Ia32/PageTables64.asm @@ -36,13 +36,58 @@ BITS 32 PAGE_READ_WRITE + \ PAGE_PRESENT) =20 +; +; SEV-ES #VC exception handler support +; +; #VC handler local variable locations +; +%define VC_CPUID_RESULT_EAX 0 +%define VC_CPUID_RESULT_EBX 4 +%define VC_CPUID_RESULT_ECX 8 +%define VC_CPUID_RESULT_EDX 12 +%define VC_GHCB_MSR_EDX 16 +%define VC_GHCB_MSR_EAX 20 +%define VC_CPUID_REQUEST_REGISTER 24 +%define VC_CPUID_FUNCTION 28 + +; #VC handler total local variable size +; +%define VC_VARIABLE_SIZE 32 + +; #VC handler GHCB CPUID request/response protocol values +; +%define GHCB_CPUID_REQUEST 4 +%define GHCB_CPUID_RESPONSE 5 +%define GHCB_CPUID_REGISTER_SHIFT 30 +%define CPUID_INSN_LEN 2 + + ; Check if Secure Encrypted Virtualization (SEV) feature is enabled ; -; If SEV is enabled then EAX will be at least 32 +; Modified: EAX, EBX, ECX, EDX, ESP +; +; If SEV is enabled then EAX will be at least 32. ; If SEV is disabled then EAX will be zero. ; CheckSevFeature: + ; Set the first byte of the workarea to zero to communicate to the SEC + ; phase that SEV-ES is not enabled. If SEV-ES is enabled, the CPUID + ; instruction will trigger a #VC exception where the first byte of the + ; workarea will be set to one. + mov byte[SEV_ES_WORK_AREA], 0 + + ; + ; Set up exception handlers to check for SEV-ES + ; Load temporary RAM stack based on PCDs (see SevEsIdtVmmComm for + ; stack usage) + ; Establish exception handlers + ; + mov esp, SEV_ES_VC_TOP_OF_STACK + mov eax, ADDR_OF(Idtr) + lidt [cs:eax] + ; Check if we have a valid (0x8000_001F) CPUID leaf + ; CPUID raises a #VC exception if running as an SEV-ES guest mov eax, 0x80000000 cpuid =20 @@ -53,8 +98,8 @@ CheckSevFeature: jl NoSev =20 ; Check for memory encryption feature: - ; CPUID Fn8000_001F[EAX] - Bit 1 - ; + ; CPUID Fn8000_001F[EAX] - Bit 1 + ; CPUID raises a #VC exception if running as an SEV-ES guest mov eax, 0x8000001f cpuid bt eax, 1 @@ -78,6 +123,15 @@ NoSev: xor eax, eax =20 SevExit: + ; + ; Clear exception handlers and stack + ; + push eax + mov eax, ADDR_OF(IdtrClear) + lidt [cs:eax] + pop eax + mov esp, 0 + OneTimeCallRet CheckSevFeature =20 ; Check if Secure Encrypted Virtualization - Encrypted State (SEV-ES) feat= ure @@ -222,3 +276,218 @@ SetCr3: mov cr3, eax =20 OneTimeCallRet SetCr3ForPageTables64 + +; +; Start of #VC exception handling routines +; + +SevEsIdtNotCpuid: + ; + ; Use VMGEXIT to request termination. + ; 1 - #VC was not for CPUID + ; + mov eax, 1 + jmp SevEsIdtTerminate + +SevEsIdtNoCpuidResponse: + ; + ; Use VMGEXIT to request termination. + ; 2 - GHCB_CPUID_RESPONSE not received + ; + mov eax, 2 + +SevEsIdtTerminate: + ; + ; Use VMGEXIT to request termination. At this point the reason code is + ; located in EAX, so shift it left 16 bits to the proper location. + ; + ; EAX[11:0] =3D> 0x100 - request termination + ; EAX[15:12] =3D> 0x1 - OVMF + ; EAX[23:16] =3D> 0xXX - REASON CODE + ; + shl eax, 16 + or eax, 0x1100 + xor edx, edx + mov ecx, 0xc0010130 + wrmsr + ; + ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-b= it + ; mode, so work around this by temporarily switching to 64-bit mode. + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; We shouldn't come back from the VMGEXIT, but if we do, just loop. + ; +SevEsIdtHlt: + hlt + jmp SevEsIdtHlt + iret + + ; + ; Total stack usage for the #VC handler is 44 bytes: + ; - 12 bytes for the exception IRET (after popping error code) + ; - 32 bytes for the local variables. + ; +SevEsIdtVmmComm: + ; + ; If we're here, then we are an SEV-ES guest and this + ; was triggered by a CPUID instruction + ; + ; Set the first byte of the workarea to one to communicate to the SEC + ; phase that SEV-ES is enabled. + mov byte[SEV_ES_WORK_AREA], 1 + + pop ecx ; Error code + cmp ecx, 0x72 ; Be sure it was CPUID + jne SevEsIdtNotCpuid + + ; Set up local variable room on the stack + ; CPUID function : + 28 + ; CPUID request register : + 24 + ; GHCB MSR (EAX) : + 20 + ; GHCB MSR (EDX) : + 16 + ; CPUID result (EDX) : + 12 + ; CPUID result (ECX) : + 8 + ; CPUID result (EBX) : + 4 + ; CPUID result (EAX) : + 0 + sub esp, VC_VARIABLE_SIZE + + ; Save the CPUID function being requested + mov [esp + VC_CPUID_FUNCTION], eax + + ; The GHCB CPUID protocol uses the following mapping to request + ; a specific register: + ; 0 =3D> EAX, 1 =3D> EBX, 2 =3D> ECX, 3 =3D> EDX + ; + ; Set EAX as the first register to request. This will also be used as a + ; loop variable to request all register values (EAX to EDX). + xor eax, eax + mov [esp + VC_CPUID_REQUEST_REGISTER], eax + + ; Save current GHCB MSR value + mov ecx, 0xc0010130 + rdmsr + mov [esp + VC_GHCB_MSR_EAX], eax + mov [esp + VC_GHCB_MSR_EDX], edx + +NextReg: + ; + ; Setup GHCB MSR + ; GHCB_MSR[63:32] =3D CPUID function + ; GHCB_MSR[31:30] =3D CPUID register + ; GHCB_MSR[11:0] =3D CPUID request protocol + ; + mov eax, [esp + VC_CPUID_REQUEST_REGISTER] + cmp eax, 4 + jge VmmDone + + shl eax, GHCB_CPUID_REGISTER_SHIFT + or eax, GHCB_CPUID_REQUEST + mov edx, [esp + VC_CPUID_FUNCTION] + mov ecx, 0xc0010130 + wrmsr + + ; + ; Issue VMGEXIT - NASM doesn't support the vmmcall instruction in 32-b= it + ; mode, so work around this by temporarily switching to 64-bit mode. + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Read GHCB MSR + ; GHCB_MSR[63:32] =3D CPUID register value + ; GHCB_MSR[31:30] =3D CPUID register + ; GHCB_MSR[11:0] =3D CPUID response protocol + ; + mov ecx, 0xc0010130 + rdmsr + mov ecx, eax + and ecx, 0xfff + cmp ecx, GHCB_CPUID_RESPONSE + jne SevEsIdtNoCpuidResponse + + ; Save returned value + shr eax, GHCB_CPUID_REGISTER_SHIFT + mov [esp + eax * 4], edx + + ; Next register + inc word [esp + VC_CPUID_REQUEST_REGISTER] + + jmp NextReg + +VmmDone: + ; + ; At this point we have all CPUID register values. Restore the GHCB MS= R, + ; set the return register values and return. + ; + mov eax, [esp + VC_GHCB_MSR_EAX] + mov edx, [esp + VC_GHCB_MSR_EDX] + mov ecx, 0xc0010130 + wrmsr + + mov eax, [esp + VC_CPUID_RESULT_EAX] + mov ebx, [esp + VC_CPUID_RESULT_EBX] + mov ecx, [esp + VC_CPUID_RESULT_ECX] + mov edx, [esp + VC_CPUID_RESULT_EDX] + + add esp, VC_VARIABLE_SIZE + + ; Update the EIP value to skip over the now handled CPUID instruction + ; (the CPUID instruction has a length of 2) + add word [esp], CPUID_INSN_LEN + iret + +ALIGN 2 + +Idtr: + dw IDT_END - IDT_BASE - 1 ; Limit + dd ADDR_OF(IDT_BASE) ; Base + +IdtrClear: + dw 0 ; Limit + dd 0 ; Base + +ALIGN 16 + +; +; The Interrupt Descriptor Table (IDT) +; This will be used to determine if SEV-ES is enabled. Upon execution +; of the CPUID instruction, a VMM Communication Exception will occur. +; This will tell us if SEV-ES is enabled. We can use the current value +; of the GHCB MSR to determine the SEV attributes. +; +IDT_BASE: +; +; Vectors 0 - 28 (No handlers) +; +%rep 29 + dw 0 ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw 0 ; Offset high bits 31..16 +%endrep +; +; Vector 29 (VMM Communication Exception) +; + dw (ADDR_OF(SevEsIdtVmmComm) & 0xffff) ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw (ADDR_OF(SevEsIdtVmmComm) >> 16) ; Offset high bits 31..16 +; +; Vectors 30 - 31 (No handlers) +; +%rep 2 + dw 0 ; Offset low bits 15..0 + dw 0x10 ; Selector + db 0 ; Reserved + db 0x8E ; Gate Type (IA32_IDT_GAT= E_TYPE_INTERRUPT_32) + dw 0 ; Offset high bits 31..16 +%endrep +IDT_END: diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index bfb77e439105..762661115d50 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -72,6 +72,8 @@ %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) + %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase)) + %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) %include "Ia32/PageTables64.asm" %endif =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: XY33xj4H6WlfgE107Xo1D1dHx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190510; bh=Y0bOa+BaXYB//f8I3EfIOtiMIN/v4sRFMixY4+6gfXc=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=r1zn5HQjZZbOrBv05dfwwJ9Jcse812ywazGZjWOi4MAZnzPS+OviUBiOfq7v9aO1HrO zpT/qOnr6sAEkFi5uw36Hx7rYbUHUN3Zx6B4yqKRf8W5tfu8rejRovpDiawTqwkTFYAOb iAeleV5N0K+CYB8cU2ED97koIMJkNEN3WTA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 An SEV-ES guest will generate a #VC exception when it encounters a non-automatic exit (NAE) event. It is expected that the #VC exception handler will communicate with the hypervisor using the GHCB to handle the NAE event. NAE events can occur during the Sec phase, so initialize exception handling early in the OVMF Sec support. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Sec/SecMain.inf | 4 ++ OvmfPkg/Sec/SecMain.c | 151 ++++++++++++++++++++++++++++++++++++---- 2 files changed, 142 insertions(+), 13 deletions(-) diff --git a/OvmfPkg/Sec/SecMain.inf b/OvmfPkg/Sec/SecMain.inf index 63ba4cb555fb..7f78dcee2772 100644 --- a/OvmfPkg/Sec/SecMain.inf +++ b/OvmfPkg/Sec/SecMain.inf @@ -50,15 +50,19 @@ [LibraryClasses] PeCoffExtraActionLib ExtractGuidedSectionLib LocalApicLib + CpuExceptionHandlerLib =20 [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED =20 [Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index bae9764577f0..577596a949f9 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -24,6 +24,9 @@ #include #include #include +#include +#include +#include =20 #include =20 @@ -34,6 +37,10 @@ typedef struct _SEC_IDT_TABLE { IA32_IDT_GATE_DESCRIPTOR IdtTable[SEC_IDT_ENTRY_COUNT]; } SEC_IDT_TABLE; =20 +typedef struct _SEC_SEV_ES_WORK_AREA { + UINT8 SevEsEnabled; +} SEC_SEV_ES_WORK_AREA; + VOID EFIAPI SecStartupPhase2 ( @@ -712,6 +719,90 @@ FindAndReportEntryPoints ( return; } =20 +STATIC +VOID +SevEsProtocolFailure ( + IN UINT8 ReasonCode + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + + // + // Use the GHCB MSR Protocol to request termination by the hypervisor + // + Msr.GhcbPhysicalAddress =3D 0; + Msr.GhcbTerminate.Function =3D GHCB_INFO_TERMINATE_REQUEST; + Msr.GhcbTerminate.ReasonCodeSet =3D GHCB_TERMINATE_GHCB; + Msr.GhcbTerminate.ReasonCode =3D ReasonCode; + AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + AsmVmgExit (); + + ASSERT (0); + CpuDeadLoop (); +} + +STATIC +VOID +SevEsProtocolCheck ( + VOID + ) +{ + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + + // + // Use the GHCB MSR Protocol to obtain the GHCB SEV-ES Information for + // protocol checking + // + Msr.GhcbPhysicalAddress =3D 0; + Msr.GhcbInfo.Function =3D GHCB_INFO_SEV_INFO_GET; + AsmWriteMsr64 (MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + AsmVmgExit (); + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + + if (Msr.GhcbInfo.Function !=3D GHCB_INFO_SEV_INFO) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_GENERAL); + } + + if (Msr.GhcbProtocol.SevEsProtocolMin > Msr.GhcbProtocol.SevEsProtocolMa= x) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_PROTOCOL); + } + + if ((Msr.GhcbProtocol.SevEsProtocolMin > GHCB_VERSION_MAX) || + (Msr.GhcbProtocol.SevEsProtocolMax < GHCB_VERSION_MIN)) { + SevEsProtocolFailure (GHCB_TERMINATE_GHCB_PROTOCOL); + } + + // + // SEV-ES protocol checking succeeded, set the initial GHCB address + // + Msr.GhcbPhysicalAddress =3D FixedPcdGet32 (PcdOvmfSecGhcbBase); + AsmWriteMsr64(MSR_SEV_ES_GHCB, Msr.GhcbPhysicalAddress); + + Ghcb =3D Msr.Ghcb; + SetMem (Ghcb, sizeof (*Ghcb), 0); + + /* Set the version to the maximum that can be supported */ + Ghcb->ProtocolVersion =3D MIN (Msr.GhcbProtocol.SevEsProtocolMax, GHCB_V= ERSION_MAX); + Ghcb->GhcbUsage =3D GHCB_STANDARD_USAGE; +} + +STATIC +BOOLEAN +SevEsIsEnabled ( + VOID + ) +{ + SEC_SEV_ES_WORK_AREA *SevEsWorkArea; + + SevEsWorkArea =3D (SEC_SEV_ES_WORK_AREA *) FixedPcdGet32 (PcdSevEsWorkAr= eaBase); + + return ((SevEsWorkArea !=3D NULL) && (SevEsWorkArea->SevEsEnabled !=3D 0= )); +} + VOID EFIAPI SecCoreStartupWithStack ( @@ -737,8 +828,55 @@ SecCoreStartupWithStack ( Table[Index] =3D 0; } =20 + // + // Initialize IDT - Since this is before library constructors are called, + // we use a loop rather than CopyMem. + // + IdtTableInStack.PeiService =3D NULL; + for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { + UINT8 *Src, *Dst; + UINTN Byte; + + Src =3D (UINT8 *) &mIdtEntryTemplate; + Dst =3D (UINT8 *) &IdtTableInStack.IdtTable[Index]; + for (Byte =3D 0; Byte < sizeof (mIdtEntryTemplate); Byte++) { + Dst[Byte] =3D Src[Byte]; + } + } + + IdtDescriptor.Base =3D (UINTN)&IdtTableInStack.IdtTable; + IdtDescriptor.Limit =3D (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1); + + if (SevEsIsEnabled ()) { + SevEsProtocolCheck (); + + // + // For SEV-ES guests, the exception handler is needed before calling + // ProcessLibraryConstructorList() because some of the library constru= ctors + // perform some functions that result in #VC exceptions being generate= d. + // + // Due to this code executing before library constructors, *all* libra= ry + // API calls are theoretically interface contract violations. However, + // because this is SEC (executing in flash), those constructors cannot + // write variables with static storage duration anyway. Furthermore, o= nly + // a small, restricted set of APIs, such as AsmWriteIdtr() and + // InitializeCpuExceptionHandlers(), are called, where we require that= the + // underlying library not require constructors to have been invoked and + // that the library instance not trigger any #VC exceptions. + // + AsmWriteIdtr (&IdtDescriptor); + InitializeCpuExceptionHandlers (NULL); + } + ProcessLibraryConstructorList (NULL, NULL); =20 + if (!SevEsIsEnabled ()) { + // + // For non SEV-ES guests, just load the IDTR. + // + AsmWriteIdtr (&IdtDescriptor); + } + DEBUG ((EFI_D_INFO, "SecCoreStartupWithStack(0x%x, 0x%x)\n", (UINT32)(UINTN)BootFv, @@ -751,19 +889,6 @@ SecCoreStartupWithStack ( // InitializeFloatingPointUnits (); =20 - // - // Initialize IDT - // - IdtTableInStack.PeiService =3D NULL; - for (Index =3D 0; Index < SEC_IDT_ENTRY_COUNT; Index ++) { - CopyMem (&IdtTableInStack.IdtTable[Index], &mIdtEntryTemplate, sizeof = (mIdtEntryTemplate)); - } - - IdtDescriptor.Base =3D (UINTN)&IdtTableInStack.IdtTable; - IdtDescriptor.Limit =3D (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1); - - AsmWriteIdtr (&IdtDescriptor); - #if defined (MDE_CPU_X64) // // ASSERT that the Page Tables were set by the reset vector code to --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55274): https://edk2.groups.io/g/devel/message/55274 Mute This Topic: https://groups.io/mt/71687836/1787277 Mute #vc: https://groups.io/mk?hashtag=3Dvc&subid=3D3901457 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55275+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583190512208806.3550548266949; Mon, 2 Mar 2020 15:08:32 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Aw0NYY1788612xIiVaqLNjos; Mon, 02 Mar 2020 15:08:31 -0800 X-Received: from NAM11-CO1-obe.outbound.protection.outlook.com (NAM11-CO1-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web12.670.1583190509745452410 for ; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: rPeCpXk5mFN42NtQ6ETlwyqVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190511; bh=7t1HvPdYF0ZmW7/0cApmBMcfZVd7A0OlgA30z84EYJ8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=vUDVTUNortSJGQSs6WypEuDbphylXQVfipJQXCgW4g2Wq+3iR8xuBaqkiQBEG3bFqJM EVwZi2fGVNaL+hgR1LPrI18TzaaOUoojAaxczmjxxrU5+8KNS/Ovic0bO7C62YwEjNFzE Un/ha1agQBmHWZsGUawTEvbdpBA12ub6nRA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Currently, the OVMF code relies on the hypervisor to enable the cache support on the processor in order to improve the boot speed. However, with SEV-ES, the hypervisor is not allowed to change the CR0 register to enable caching. Update the OVMF Sec support to enable caching in order to improve the boot speed when running as an SEV-ES guest. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/Sec/SecMain.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/OvmfPkg/Sec/SecMain.c b/OvmfPkg/Sec/SecMain.c index 577596a949f9..2aeb24d8e3ee 100644 --- a/OvmfPkg/Sec/SecMain.c +++ b/OvmfPkg/Sec/SecMain.c @@ -875,6 +875,13 @@ SecCoreStartupWithStack ( // For non SEV-ES guests, just load the IDTR. // AsmWriteIdtr (&IdtDescriptor); + } else { + // + // Under SEV-ES, the hypervisor can't modify CR0 and so can't enable + // caching in order to speed up the boot. Enable caching early for + // an SEV-ES guest. + // + AsmEnableCache (); } =20 DEBUG ((EFI_D_INFO, --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: qRVw3rQgdMfGIfPFYDPDwgjZx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190511; bh=DKqwlO5oIRe9ZmCXGcQBTkZ7As6WkIt54Fh7mo+FVd4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=q4HgBfsOaHMuWHxUTdsoqr5l+8ACUi2/fVUrUtV0Nw8sE2Lz0NeCrqnKxhB/bLJ0L09 jqYw3s6zhiZWPUM1EmvlR8MH9Ey9QAxtawdj/vR1rpfgX+P0iYe4Z6HiwijgglAE9y88L sTOywyp2rtY/79+Mvx27ccgndpfz1fwCJ54= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 The flash detection routine will attempt to determine how the flash device behaves (e.g. ROM, RAM, Flash). But when SEV-ES is enabled and the flash device behaves as a ROM device (meaning it is marked read-only by the hypervisor), this check may result in an infinite nested page fault because of the attempted write. Since the instruction cannot be emulated when SEV-ES is enabled, the RIP is never advanced, resulting in repeated nested page faults. When SEV-ES is enabled, exit the flash detection early and assume that the FD behaves as Flash. This will result in QemuFlashWrite() being called to store EFI variables, which will also result in an infinite nested page fault when the write is performed. In this case, update QemuFlashWrite() to use the VmgMmioWrite function from the VmgExitLib library to have the hypervisor perform the write without having to emulate the instruction. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + .../FvbServicesRuntimeDxe.inf | 2 ++ .../QemuFlash.h | 6 +++++ .../QemuFlash.c | 23 ++++++++++++++++--- .../QemuFlashDxe.c | 15 ++++++++++++ .../QemuFlashSmm.c | 9 ++++++++ 8 files changed, 55 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 51d7acafdda3..2531b7edccf5 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -318,6 +318,7 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.UEFI_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 764fa8c287a0..629725ef2b44 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -323,6 +323,7 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.UEFI_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index b6e29e09db97..74076cbe7692 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -323,6 +323,7 @@ [LibraryClasses.common.DXE_RUNTIME_DRIVER] BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf PciLib|OvmfPkg/Library/DxePciLibI440FxQ35/DxePciLibI440FxQ35.inf QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/DxeQemuFwCfgS3LibFwCfg.inf + VmgExitLib|UefiCpuPkg/Library/VmgExitLib/VmgExitLib.inf =20 [LibraryClasses.common.UEFI_DRIVER] PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.i= nf b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf index 8125fd0735a1..3ce19d1bfa8e 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf @@ -38,6 +38,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec OvmfPkg/OvmfPkg.dec =20 [LibraryClasses] @@ -52,6 +53,7 @@ [LibraryClasses] UefiBootServicesTableLib UefiDriverEntryPoint UefiRuntimeLib + VmgExitLib =20 [Guids] gEfiEventVirtualAddressChangeGuid # ALWAYS_CONSUMED diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h b/OvmfPkg/Q= emuFlashFvbServicesRuntimeDxe/QemuFlash.h index f1afabcbe6ae..19ac1f733279 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.h @@ -89,5 +89,11 @@ QemuFlashBeforeProbe ( IN UINTN FdBlockCount ); =20 +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ); + #endif =20 diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c b/OvmfPkg/Q= emuFlashFvbServicesRuntimeDxe/QemuFlash.c index c81c58972bf2..ccf5ad7f7afb 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c @@ -9,6 +9,7 @@ =20 #include #include +#include #include =20 #include "QemuFlash.h" @@ -80,6 +81,21 @@ QemuFlashDetected ( =20 DEBUG ((EFI_D_INFO, "QEMU Flash: Attempting flash detection at %p\n", Pt= r)); =20 + if (MemEncryptSevEsIsEnabled()) { + // + // When SEV-ES is enabled, the check below can result in an infinite + // loop with respect to a nested page fault. When the memslot is mapped + // read-only, the nested page table entry is read-only. The check below + // will cause a nested page fault that cannot be emulated, causing + // the instruction to retried over and over. For SEV-ES, acknowledge t= hat + // the FD appears as ROM and not as FLASH, but report FLASH anyway bec= ause + // FLASH behavior can be simulated using VMGEXIT. + // + DEBUG ((DEBUG_INFO, + "QEMU Flash: SEV-ES enabled, assuming FD behaves as FLASH\n")); + return TRUE; + } + OriginalUint8 =3D *Ptr; *Ptr =3D CLEAR_STATUS_CMD; ProbeUint8 =3D *Ptr; @@ -181,8 +197,9 @@ QemuFlashWrite ( // Ptr =3D QemuFlashPtr (Lba, Offset); for (Loop =3D 0; Loop < *NumBytes; Loop++) { - *Ptr =3D WRITE_BYTE_CMD; - *Ptr =3D Buffer[Loop]; + QemuFlashPtrWrite (Ptr, WRITE_BYTE_CMD); + QemuFlashPtrWrite (Ptr, Buffer[Loop]); + Ptr++; } =20 @@ -190,7 +207,7 @@ QemuFlashWrite ( // Restore flash to read mode // if (*NumBytes > 0) { - *(Ptr - 1) =3D READ_ARRAY_CMD; + QemuFlashPtrWrite (Ptr - 1, READ_ARRAY_CMD); } =20 return EFI_SUCCESS; diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c b/OvmfPk= g/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c index 5aabe9d7b59c..939463a8e17c 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashDxe.c @@ -10,6 +10,8 @@ **/ =20 #include +#include +#include =20 #include "QemuFlash.h" =20 @@ -32,3 +34,16 @@ QemuFlashBeforeProbe ( // Do nothing // } + +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ) +{ + if (MemEncryptSevEsIsEnabled()) { + VmgMmioWrite ((UINT8 *) Ptr, &Value, 1); + } else { + *Ptr =3D Value; + } +} diff --git a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c b/OvmfPk= g/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c index 7eb426e03855..eff40ae28032 100644 --- a/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c +++ b/OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlashSmm.c @@ -46,3 +46,12 @@ QemuFlashBeforeProbe ( ); ASSERT_EFI_ERROR (Status); } + +VOID +QemuFlashPtrWrite ( + IN volatile UINT8 *Ptr, + IN UINT8 Value + ) +{ + *Ptr =3D Value; +} --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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Mon, 2 Mar 2020 23:08:02 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7644d018-85bd-48b0-e578-08d7befe8ee3 X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:5797; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55277+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: mkk+BUV1E3JE72d/2QKCHRoIIoKi1281129yPwE1hA9D2nyTx5AU/TjJ4VVVOuYp8YI9304QRFM31KghDdk3LQR/6MtDWWfX+8cYn0b2yb5jHlXM7vkr3ps/iFh6+591RWOMZfhz18+BQ6BMajYwGAhbd7sgxTgki3f7zCMUVtFgMXyXZ9Cecu6ZpGrzj0BDX/DuAl7Vs+IS3XhKYCULbBMHIB7VB141feoedJaTpbWNlYiN2vHy+dlyj0IjqxJpj+jkYJR66M4aJS/SeLibtiVu4q5HWFFHpxvjfysfcbgJIhi/YfT11VpW9GS7FrF5mAYv8VOJ1qrSTlDoVyiahltUeI56gJvyHzfJ7xZe5/0nkjQ6CTEX3ASBfSTpAAclXjKf6ycHyyYIz06CN2z1iKid4FYwdfCLJbIVI4kNCcX+jqXV8IppkwJ1fFHfvOjrQAMuaFQrqOWPokOn8jFt9tfmmb00dpO+tsYkK8R/1GK9a7mlSpTwmSt2RmnlFHz6YRPLR8P65IsC4POuybw4uA== X-MS-Exchange-AntiSpam-MessageData: KCE9Qm4ppZSV6/iGJmGUMBBAD5PLfu072OnVKRYGB/CdmZRw0rd3tUhbM4AO5pBupoueALtyrct3GHaWVi8ryIINN8ZaSDAJtMPkm8RitzfCgYul+DJDQHrrRqKCHACwTqWzNDEFVUbuaN+mAk5pgg== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7644d018-85bd-48b0-e578-08d7befe8ee3 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:08:02.6923 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: OSTxWN0bexlGml/MPSz6j3pFEjRtbm7ZIEMFxakQ36dyA1jNGExexo3VDnerUDcH48+I7gd4uMPdW1/u55Fxxg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 9xai6xhFEZjpQ2o3aLGoOKLWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190511; bh=aT+ZNN1gsqSgmM69jAUU1g1Pe2EeJg6wRHMfU3XCEnE=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=BLm+AUDQG/f3VDtselGv4+N1vq7HJ8bjkeCqNfnqLgrBzUR119eCDMu2iBBBx2qIBtf t6xJO5s4/WeZ7QPxjyWDXCQ67K94AlyxJjGWOfbrubes4oEqDaYWxQ8VEnBPz5lWbQzVL ZJQF0uVkl1lvMeRf0zrgsNxkKQQs2XTeyOk= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A hypervisor is not allowed to update an SEV-ES guests register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead, an SEV-ES AP must be transition from 64-bit long mode to 16-bit real mode in response to an INIT-SIPI-SIPI sequence. This requires a 16-bit code segment descriptor. For PEI, create this descriptor in the reset vector GDT table. For DXE, create this descriptor from the newly reserved entry at location 0x28. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/CpuDxe/CpuGdt.h | 4 ++-- UefiCpuPkg/CpuDxe/CpuGdt.c | 8 ++++---- UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm | 9 +++++++++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.h b/UefiCpuPkg/CpuDxe/CpuGdt.h index 3a0210b2f172..1c94487cbee8 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.h +++ b/UefiCpuPkg/CpuDxe/CpuGdt.h @@ -36,7 +36,7 @@ struct _GDT_ENTRIES { GDT_ENTRY LinearCode; GDT_ENTRY SysData; GDT_ENTRY SysCode; - GDT_ENTRY Spare4; + GDT_ENTRY SysCode16; GDT_ENTRY LinearData64; GDT_ENTRY LinearCode64; GDT_ENTRY Spare5; @@ -49,7 +49,7 @@ struct _GDT_ENTRIES { #define LINEAR_CODE_SEL OFFSET_OF (GDT_ENTRIES, LinearCode) #define SYS_DATA_SEL OFFSET_OF (GDT_ENTRIES, SysData) #define SYS_CODE_SEL OFFSET_OF (GDT_ENTRIES, SysCode) -#define SPARE4_SEL OFFSET_OF (GDT_ENTRIES, Spare4) +#define SYS_CODE16_SEL OFFSET_OF (GDT_ENTRIES, SysCode16) #define LINEAR_DATA64_SEL OFFSET_OF (GDT_ENTRIES, LinearData64) #define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64) #define SPARE5_SEL OFFSET_OF (GDT_ENTRIES, Spare5) diff --git a/UefiCpuPkg/CpuDxe/CpuGdt.c b/UefiCpuPkg/CpuDxe/CpuGdt.c index 64efadeba601..a1ab543f2da5 100644 --- a/UefiCpuPkg/CpuDxe/CpuGdt.c +++ b/UefiCpuPkg/CpuDxe/CpuGdt.c @@ -70,14 +70,14 @@ STATIC GDT_ENTRIES GdtTemplate =3D { 0x0, }, // - // SPARE4_SEL + // SYS_CODE16_SEL // { - 0x0, // limit 15:0 + 0x0FFFF, // limit 15:0 0x0, // base 15:0 0x0, // base 23:16 - 0x0, // type - 0x0, // limit 19:16, flags + 0x09A, // present, ring 0, code, execute/read + 0x08F, // page-granular, 16-bit 0x0, // base 31:24 }, // diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm b/UefiCpuP= kg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm index ce4ebfffb688..0e79a3984b16 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia16/Real16ToFlat32.asm @@ -129,5 +129,14 @@ LINEAR_CODE64_SEL equ $-GDT_BASE DB 0 ; base 31:24 %endif =20 +; linear code segment descriptor +LINEAR_CODE16_SEL equ $-GDT_BASE + DW 0xffff ; limit 15:0 + DW 0 ; base 15:0 + DB 0 ; base 23:16 + DB PRESENT_FLAG(1)|DPL(0)|SYSTEM_FLAG(1)|DESC_TYPE(CODE32_TYPE) + DB GRANULARITY_FLAG(1)|DEFAULT_SIZE32(0)|CODE64_FLAG(0)|UPPER_LIM= IT(0xf) + DB 0 ; base 31:24 + GDT_END: =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB4201.namprd12.prod.outlook.com (2603:10b6:5:216::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.18; Mon, 2 Mar 2020 23:08:29 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Mon, 2 Mar 2020 23:08:29 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Cc: Jordan Justen , Laszlo Ersek , Ard Biesheuvel , Michael D Kinney , Liming Gao , Eric Dong , Ray Ni , Brijesh Singh Subject: [edk2-devel] [PATCH v5 38/42] UefiCpuPkg/MpInitLib: Add CPU MP data flag to indicate if SEV-ES is enabled Date: Mon, 2 Mar 2020 17:07:09 -0600 Message-Id: <75150c4f1149d37216677856dd5cb4624243d256.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by DM5PR2001CA0013.namprd20.prod.outlook.com (2603:10b6:4:16::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16 via Frontend Transport; Mon, 2 Mar 2020 23:08:02 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 7041acde-ad0f-4064-e078-08d7befe8f68 X-MS-TrafficTypeDiagnostic: DM6PR12MB4201:|DM6PR12MB4201: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7691; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55278+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: UAH1pYKSrsWXo3bkm9WfZXeizwGL4/PXdYNbOWwzNuOjN0+1wyecxZM8Mh5lvOzdY8bkHgDEa8l3IHPKgbIujKewxqFtTXEIpaI/GPHDeN5wXCyPRSmNI5o0m3GkMzIj3213vVvPSA66sWTH5MiAswgFF/TDoXBJp8pBxnW2SomXLPGPECOqBcpsVMZXGHpS2fk7MOoQiiZgNcTo/ZTHm1lD3T5vxVxwnrZWB+x7aixx1TDYc3ZwItv8eQt+svNNwsbhJ9OtjJEYF7TR/dFqusrxrY6fIqwDeP5j4mBx+KEpvsNRkFkzcf5j2mnaGcsk8jmjrrXU+AEGkIpxduE3tmMGQTQ3+d6euNr68WL1P7d+mOR89G/MBBQOvRN9txND/h6wbIoHJqeDnyvrgx6qPh22oBVtuKM9WKUA/IE9vJZulLMIRyaWgKo5X68M7YRCx/kjDLjBKRR1+JmhPYi5g1uqL56cYvRpKPgFOtGjn3ZBxySOJKz7QGvlbNz610mC9eWT1RqCcxLYo52Gu4C+pQ== X-MS-Exchange-AntiSpam-MessageData: Tpo9+lAUk4TzfmJRrIprBUduvJk9HiDXAF0Zr1jUo0Dxi5JbqjZELYMLaIAzwVPEVsLmejo+N6TigKuyDn1IfFcu9SKINdI492d2XkZ20YIEU8M4TU7FrBPtJ3NjZDjbNNbY6rtRCcBCPiFfhB2DdQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7041acde-ad0f-4064-e078-08d7befe8f68 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Mar 2020 23:08:03.5488 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Wh+ps5yy6Oon/PFOYGhUnojU2TVycwY2UeN1qnChbD+szFaHqhGn8uJIj1gZb0EFSB61z6LfJe/NNNBwDY+f2w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4201 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: vnLHBVvVaFOYDnNrs9W91obTx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190512; bh=Ur/dcqyOxI0J65pEmhsa7LI3JgM+c4x/5K42kuJbLM4=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=OkwUZ4x5CQfeCKzvIBtwnD9AvhHhQOe3JqJl5JQwguKOCHWxbfRAYdkDboL6TLsnBkf v73lVwuypeq5QwxocMnWOkn3qkFGkmqzI3as9HvKNeCjoK/fAVGiKseqUbLkbmqc50mts aZ70q98u4bvrxuUpufJC9M7iNaXdw1ggnf8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 When starting APs in an SMP configuration, the AP needs to know if it is running as an SEV-ES guest in order to assign a GHCB page. Add a field to the CPU_MP_DATA structure that will indicate if SEV-ES is enabled. This new field is set during MP library initialization with the PCD value PcdSevEsIsEnabled. This flag can then be used to determine if SEV-ES is enabled. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 2 ++ UefiCpuPkg/Library/MpInitLib/MpLib.c | 1 + 4 files changed, 5 insertions(+) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 45aaa179ff2e..8b0eb1df9594 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -69,5 +69,6 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONS= UMES =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index d78d328b4252..b4dc7e69d829 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -60,6 +60,7 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES =20 [Ppis] gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 0c89f8a6e732..edd936f06396 100755 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -275,6 +275,8 @@ struct _CPU_MP_DATA { // driver. // BOOLEAN WakeUpByInitSipiSipi; + + BOOLEAN SevEsIsEnabled; }; =20 extern EFI_GUID mCpuInitMpLibHobGuid; diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 64a4c3546e22..81c5b1a5b701 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1714,6 +1714,7 @@ MpInitLibInitialize ( CpuMpData->CpuData =3D (CPU_AP_DATA *) (CpuMpData + 1); CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); InitializeSpinLock(&CpuMpData->MpLock); + CpuMpData->SevEsIsEnabled =3D PcdGetBool (PcdSevEsIsEnabled); =20 // // Make sure no memory usage outside of the allocated buffer. --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 78bQja9lFwwFIm4ayJIptCNUx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583190512; bh=FF6oecO/qSM1J0WjYv+TlSDW0re5ceosDkKIw3/EXC8=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=j+9GsR4UUvOFaeSz0D1YyTpzhi2ZGLrPprf2aduJuIjuf7BU32N/WrSV/bzComXaDPR 4OF5x9JuJmaSo/xB/J1rOqONfZ+9M7FZjohzuU4sMOAbXuiZmRdiIOV755FEuKMZtW/G9 hrUfGFU0Va5Jy2Oiz1hjwyWE+LM1MCVnuW8= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Typically, an AP is booted using the INIT-SIPI-SIPI sequence. This sequence is intercepted by the hypervisor, which sets the AP's registers to the values requested by the sequence. At that point, the hypervisor can start the AP, which will then begin execution at the appropriate location. Under SEV-ES, AP booting presents some challenges since the hypervisor is not allowed to alter the AP's register state. In this situation, we have to distinguish between the AP's first boot and AP's subsequent boots. First boot: Once the AP's register state has been defined (which is before the guest is first booted) it cannot be altered. Should the hypervisor attempt to alter the register state, the change would be detected by the hardware and the VMRUN instruction would fail. Given this, the first boot for the AP is required to begin execution with this initial register state, which is typically the reset vector. This prevents the BSP from directing the AP startup location through the INIT-SIPI-SIPI sequence. To work around this, the firmware will provide a build time reserved area that can be used as the initial IP value. The hypervisor can extract this location value by checking for the SEV-ES reset block GUID that must be located 48-bytes from the end of the firmware. The format of the SEV-ES reset block area is: 0x00 - 0x01 - SEV-ES Reset IP 0x02 - 0x03 - SEV-ES Reset CS Segment Base[31:16] 0x04 - 0x05 - Size of the SEV-ES reset block 0x06 - 0x15 - SEV-ES Reset Block GUID (00f771de-1a7e-4fcb-890e-68c77e2fb44e) The total size is 22 bytes. Any expansion to this block must be done by adding new values before existing values. The hypervisor will use the IP and CS values obtained from the SEV-ES reset block to set as the AP's initial values. The CS Segment Base represents the upper 16 bits of the CS segment base and must be left shifted by 16 bits to form the complete CS segment base value. Before booting the AP for the first time, the BSP must initialize the SEV-ES reset area. This consists of programming a FAR JMP instruction to the contents of a memory location that is also located in the SEV-ES reset area. The BSP must program the IP and CS values for the FAR JMP based on values drived from the INIT-SIPI-SIPI sequence. Subsequent boots: Again, the hypervisor cannot alter the AP register state, so a method is required to take the AP out of halt state and redirect it to the desired IP location. If it is determined that the AP is running in an SEV-ES guest, then instead of calling CpuSleep(), a VMGEXIT is issued with the AP Reset Hold exit code (0x80000004). The hypervisor will put the AP in a halt state, waiting for an INIT-SIPI-SIPI sequence. Once the sequence is recognized, the hypervisor will resume the AP. At this point the AP must transition from the current 64-bit long mode down to 16-bit real mode and begin executing at the derived location from the INIT-SIPI-SIPI sequence. Another change is around the area of obtaining the (x2)APIC ID during AP startup. During AP startup, the AP can't take a #VC exception before the AP has established a stack. However, the AP stack is set by using the (x2)APIC ID, which is obtained through CPUID instructions. A CPUID instruction will cause a #VC, so a different method must be used. The GHCB protocol supports a method to obtain CPUID information from the hypervisor through the GHCB MSR. This method does not require a stack, so it is used to obtain the necessary CPUID information to determine the (x2)APIC ID. The new 16-bit protected mode GDT entry is used in order to transition from 64-bit long mode down to 16-bit real mode. A new assembler routine is created that takes the AP from 64-bit long mode to 16-bit real mode. This is located under 1MB in memory and transitions from 64-bit long mode to 32-bit compatibility mode to 16-bit protected mode and finally 16-bit real mode. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 3 + UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 3 + UefiCpuPkg/Library/MpInitLib/MpLib.h | 60 ++++ UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 70 ++++- UefiCpuPkg/Library/MpInitLib/MpLib.c | 256 +++++++++++++++++- UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 19 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 2 +- UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 2 +- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 15 + UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 4 +- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 239 ++++++++++++++++ 11 files changed, 659 insertions(+), 14 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 8b0eb1df9594..12c175608c3a 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -51,6 +51,7 @@ [LibraryClasses] UefiBootServicesTableLib DebugAgentLib SynchronizationLib + VmgExitLib =20 [Protocols] gEfiTimerArchProtocolGuid ## SOMETIMES_CONSUMES @@ -70,5 +71,7 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOME= TIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONS= UMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONS= UMES =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index b4dc7e69d829..c684bb4812c1 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -50,6 +50,7 @@ [LibraryClasses] UefiCpuLib SynchronizationLib PeiServicesLib + VmgExitLib =20 [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONS= UMES @@ -61,6 +62,8 @@ [Pcd] gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES gUefiCpuPkgTokenSpaceGuid.PcdSevEsIsEnabled ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase ## SOME= TIMES_CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONS= UMES =20 [Ppis] gEdkiiPeiShadowMicrocodePpiGuid ## SOMETIMES_CONSUMES diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index edd936f06396..56bfd9cc253c 100755 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -172,6 +172,11 @@ typedef struct { UINT8 *RelocateApLoopFuncAddress; UINTN RelocateApLoopFuncSize; UINTN ModeTransitionOffset; + UINTN SwitchToRealSize; + UINTN SwitchToRealOffset; + UINTN SwitchToRealNoNxOffset; + UINTN SwitchToRealPM16ModeOffset; + UINTN SwitchToRealPM16ModeSize; } MP_ASSEMBLY_ADDRESS_MAP; =20 typedef struct _CPU_MP_DATA CPU_MP_DATA; @@ -210,6 +215,8 @@ typedef struct { // Enable5LevelPaging indicates whether 5-level paging is enabled in lon= g mode. // BOOLEAN Enable5LevelPaging; + BOOLEAN SevEsIsEnabled; + UINTN GhcbBase; } MP_CPU_EXCHANGE_INFO; =20 #pragma pack() @@ -256,6 +263,7 @@ struct _CPU_MP_DATA { UINT8 ApLoopMode; UINT8 ApTargetCState; UINT16 PmCodeSegment; + UINT16 Pm16CodeSegment; CPU_AP_DATA *CpuData; volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo; =20 @@ -277,8 +285,47 @@ struct _CPU_MP_DATA { BOOLEAN WakeUpByInitSipiSipi; =20 BOOLEAN SevEsIsEnabled; + UINTN SevEsAPBuffer; + UINTN SevEsAPResetStackStart; + CPU_MP_DATA *NewCpuMpData; + + UINT64 GhcbBase; }; =20 +#define AP_RESET_STACK_SIZE 64 + +#pragma pack(1) + +typedef struct { + UINT8 InsnBuffer[8]; + UINT16 Rip; + UINT16 Segment; +} SEV_ES_AP_JMP_FAR; + +#pragma pack() + +/** + Assembly code to move an AP from long mode to real mode. + + Move an AP from long mode to real mode in preparation to invoking + the reset vector. This is used for SEV-ES guests where a hypervisor + is not allowed to set the CS and RIP to point to the reset vector. + + @param[in] BufferStart The reset vector target. + @param[in] Code16 16-bit protected mode code segment value. + @param[in] Code32 32-bit protected mode code segment value. + @param[in] StackStart The start of a stack to be used for transitioni= ng + from long mode to real mode. +**/ +typedef +VOID +(EFIAPI AP_RESET) ( + IN UINTN BufferStart, + IN UINT16 Code16, + IN UINT16 Code32, + IN UINTN StackStart + ); + extern EFI_GUID mCpuInitMpLibHobGuid; =20 /** @@ -384,6 +431,19 @@ GetModeTransitionBuffer ( IN UINTN BufferSize ); =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @retval other Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ); + /** This function will be called by BSP to wakeup AP. =20 diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index a987c3210957..8510a13145f3 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -12,6 +12,8 @@ #include #include #include +#include +#include =20 #include =20 @@ -145,6 +147,39 @@ GetModeTransitionBuffer ( return (UINTN)StartAddress; } =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @retval other Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS StartAddress; + + // + // Allocate 1 page for AP jump table page + // + StartAddress =3D BASE_4GB - 1; + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiReservedMemoryType, + 1, + &StartAddress + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory =3D %lx\n", (UINTN) StartAddress= )); + + return (UINTN) StartAddress; +} + /** Checks APs status and updates APs status if needed. =20 @@ -219,6 +254,38 @@ CheckApsStatus ( } } =20 +/** + Get Protected mode code segment with 16-bit default addressing + from current GDT table. + + @return Protected mode 16-bit code segment value. +**/ +UINT16 +GetProtectedMode16CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 0) { + break; + } + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + /** Get Protected mode code segment from current GDT table. =20 @@ -239,7 +306,7 @@ GetProtectedModeCS ( GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; for (Index =3D 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L =3D=3D 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 1) { break; } } @@ -301,6 +368,7 @@ MpInitChangeApLoopCallback ( =20 CpuMpData =3D GetCpuMpData (); CpuMpData->PmCodeSegment =3D GetProtectedModeCS (); + CpuMpData->Pm16CodeSegment =3D GetProtectedMode16CS (); CpuMpData->ApLoopMode =3D PcdGet8 (PcdCpuApLoopMode); mNumberToFinish =3D CpuMpData->CpuCount - 1; WakeUpAP (CpuMpData, TRUE, 0, RelocateApLoop, NULL, TRUE); diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index 81c5b1a5b701..c5a5babaf85c 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -9,6 +9,9 @@ **/ =20 #include "MpLib.h" +#include +#include +#include =20 EFI_GUID mCpuInitMpLibHobGuid =3D CPU_INIT_MP_LIB_HOB_GUID; =20 @@ -314,6 +317,14 @@ GetApLoopMode ( // ApLoopMode =3D ApInHltLoop; } + + if (PcdGetBool (PcdSevEsIsEnabled)) { + // + // For SEV-ES, force AP in Hlt-loop mode in order to use the GHCB + // protocol for starting APs + // + ApLoopMode =3D ApInHltLoop; + } } =20 if (ApLoopMode !=3D ApInMwaitLoop) { @@ -610,6 +621,108 @@ InitializeApData ( SetApState (&CpuMpData->CpuData[ProcessorNumber], CpuStateIdle); } =20 +/** + Get Protected mode code segment with 16-bit default addressing + from current GDT table. + + @return Protected mode 16-bit code segment value. +**/ +STATIC +UINT16 +GetProtectedMode16CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0 && + GdtEntry->Bits.DB =3D=3D 0 && + GdtEntry->Bits.Type > 8) { + break; + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + +/** + Get Protected mode code segment with 32-bit default addressing + from current GDT table. + + @return Protected mode 32-bit code segment value. +**/ +STATIC +UINT16 +GetProtectedMode32CS ( + VOID + ) +{ + IA32_DESCRIPTOR GdtrDesc; + IA32_SEGMENT_DESCRIPTOR *GdtEntry; + UINTN GdtEntryCount; + UINT16 Index; + + Index =3D (UINT16) -1; + AsmReadGdtr (&GdtrDesc); + GdtEntryCount =3D (GdtrDesc.Limit + 1) / sizeof (IA32_SEGMENT_DESCRIPTOR= ); + GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; + for (Index =3D 0; Index < GdtEntryCount; Index++) { + if (GdtEntry->Bits.L =3D=3D 0 && + GdtEntry->Bits.DB =3D=3D 1 && + GdtEntry->Bits.Type > 8) { + break; + } + GdtEntry++; + } + ASSERT (Index !=3D GdtEntryCount); + return Index * 8; +} + +/** + Reset an AP when in SEV-ES mode. + + @retval EFI_DEVICE_ERROR Reset of AP failed. +**/ +STATIC +VOID +MpInitLibSevEsAPReset ( + GHCB *Ghcb, + CPU_MP_DATA *CpuMpData + ) +{ + UINT16 Code16, Code32; + AP_RESET *APResetFn; + UINTN BufferStart; + UINTN StackStart; + + Code16 =3D GetProtectedMode16CS (); + Code32 =3D GetProtectedMode32CS (); + + if (CpuMpData->WakeupBufferHigh !=3D 0) { + APResetFn =3D (AP_RESET *) (CpuMpData->WakeupBufferHigh + CpuMpData->A= ddressMap.SwitchToRealNoNxOffset); + } else { + APResetFn =3D (AP_RESET *) (CpuMpData->MpCpuExchangeInfo->BufferStart = + CpuMpData->AddressMap.SwitchToRealOffset); + } + + BufferStart =3D CpuMpData->MpCpuExchangeInfo->BufferStart; + StackStart =3D CpuMpData->SevEsAPResetStackStart - + (AP_RESET_STACK_SIZE * GetApicId ()); + + // + // This call never returns. + // + APResetFn (BufferStart, Code16, Code32, StackStart); +} + /** This function will be called from AP reset code if BSP uses WakeUpAP. =20 @@ -765,7 +878,28 @@ ApWakeupFunction ( // while (TRUE) { DisableInterrupts (); - CpuSleep (); + if (CpuMpData->SevEsIsEnabled) { + MSR_SEV_ES_GHCB_REGISTER Msr; + GHCB *Ghcb; + + Msr.GhcbPhysicalAddress =3D AsmReadMsr64 (MSR_SEV_ES_GHCB); + Ghcb =3D Msr.Ghcb; + + VmgInit (Ghcb); + VmgExit (Ghcb, SvmExitApResetHold, 0, 0); + /*TODO: Check return value to verify SIPI issued */ + + // + // Awakened in a new phase? Use the new CpuMpData + // + if (CpuMpData->NewCpuMpData) { + CpuMpData =3D CpuMpData->NewCpuMpData; + } + + MpInitLibSevEsAPReset (Ghcb, CpuMpData); + } else { + CpuSleep (); + } CpuPause (); } } @@ -878,6 +1012,9 @@ FillExchangeInfoData ( ExchangeInfo->Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1); DEBUG ((DEBUG_INFO, "%a: 5-Level Paging =3D %d\n", gEfiCallerBaseName, E= xchangeInfo->Enable5LevelPaging)); =20 + ExchangeInfo->SevEsIsEnabled =3D CpuMpData->SevEsIsEnabled; + ExchangeInfo->GhcbBase =3D CpuMpData->GhcbBase; + // // Get the BSP's data of GDT and IDT // @@ -904,8 +1041,9 @@ FillExchangeInfoData ( // EfiBootServicesCode to avoid page fault if NX memory protection is en= abled. // if (CpuMpData->WakeupBufferHigh !=3D 0) { - Size =3D CpuMpData->AddressMap.RendezvousFunnelSize - - CpuMpData->AddressMap.ModeTransitionOffset; + Size =3D CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize - + CpuMpData->AddressMap.ModeTransitionOffset; CopyMem ( (VOID *)CpuMpData->WakeupBufferHigh, CpuMpData->AddressMap.RendezvousFunnelAddress + @@ -958,7 +1096,8 @@ BackupAndPrepareWakeupBuffer( CopyMem ( (VOID *) CpuMpData->WakeupBuffer, (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress, - CpuMpData->AddressMap.RendezvousFunnelSize + CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize ); } =20 @@ -979,6 +1118,40 @@ RestoreWakeupBuffer( ); } =20 +/** + Calculate the size of the reset stack. +**/ +STATIC +UINTN +GetApResetStackSize( + VOID + ) +{ + return AP_RESET_STACK_SIZE * PcdGet32(PcdCpuMaxLogicalProcessorNumber); +} + +/** + Calculate the size of the reset vector. + + @param[in] AddressMap The pointer to Address Map structure. +**/ +STATIC +UINTN +GetApResetVectorSize( + IN MP_ASSEMBLY_ADDRESS_MAP *AddressMap + ) +{ + UINTN Size; + + Size =3D ALIGN_VALUE (AddressMap->RendezvousFunnelSize + + AddressMap->SwitchToRealSize + + sizeof (MP_CPU_EXCHANGE_INFO), + CPU_STACK_ALIGNMENT); + Size +=3D GetApResetStackSize (); + + return Size; +} + /** Allocate reset vector buffer. =20 @@ -992,16 +1165,22 @@ AllocateResetVector ( UINTN ApResetVectorSize; =20 if (CpuMpData->WakeupBuffer =3D=3D (UINTN) -1) { - ApResetVectorSize =3D CpuMpData->AddressMap.RendezvousFunnelSize + - sizeof (MP_CPU_EXCHANGE_INFO); + ApResetVectorSize =3D GetApResetVectorSize (&CpuMpData->AddressMap); =20 CpuMpData->WakeupBuffer =3D GetWakeupBuffer (ApResetVectorSize); CpuMpData->MpCpuExchangeInfo =3D (MP_CPU_EXCHANGE_INFO *) (UINTN) - (CpuMpData->WakeupBuffer + CpuMpData->AddressMap.Rende= zvousFunnelSize); + (CpuMpData->WakeupBuffer + + CpuMpData->AddressMap.RendezvousFunnelSize + + CpuMpData->AddressMap.SwitchToRealSize); CpuMpData->WakeupBufferHigh =3D GetModeTransitionBuffer ( - CpuMpData->AddressMap.RendezvousFunnel= Size - + CpuMpData->AddressMap.RendezvousFunnel= Size + + CpuMpData->AddressMap.SwitchToRealSize= - CpuMpData->AddressMap.ModeTransitionOf= fset ); + // + // The reset stack starts at the end of the buffer. + // + CpuMpData->SevEsAPResetStackStart =3D CpuMpData->WakeupBuffer + ApRese= tVectorSize; } BackupAndPrepareWakeupBuffer (CpuMpData); } @@ -1016,7 +1195,31 @@ FreeResetVector ( IN CPU_MP_DATA *CpuMpData ) { - RestoreWakeupBuffer (CpuMpData); + // + // If SEV-ES is enabled, the reset area is needed for AP parking and + // and AP startup in the OS, so the reset area is reserved. Do not + // perform the restore as this will overwrite memory which has data + // needed by SEV-ES. + // + if (!CpuMpData->SevEsIsEnabled) { + RestoreWakeupBuffer (CpuMpData); + } +} + +/** + Allocate the SEV-ES AP jump table buffer. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +AllocateSevEsAPMemory ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + if (CpuMpData->SevEsAPBuffer =3D=3D (UINTN) -1) { + CpuMpData->SevEsAPBuffer =3D + CpuMpData->SevEsIsEnabled ? GetSevEsAPMemory () : 0; + } } =20 /** @@ -1053,6 +1256,7 @@ WakeUpAP ( CpuMpData->InitFlag !=3D ApInitDone) { ResetVectorRequired =3D TRUE; AllocateResetVector (CpuMpData); + AllocateSevEsAPMemory (CpuMpData); FillExchangeInfoData (CpuMpData); SaveLocalApicTimerSetting (CpuMpData); } @@ -1089,6 +1293,35 @@ WakeUpAP ( } } if (ResetVectorRequired) { + // + // For SEV-ES, the initial AP boot address will be defined by + // PcdSevEsWorkAreaBase. The Segment/Rip must be the jump address + // from the original INIT-SIPI-SIPI. + // + if (CpuMpData->SevEsIsEnabled) { + SEV_ES_AP_JMP_FAR *JmpFar; + UINT32 Offset, InsnByte; + UINT8 LoNib, HiNib; + + JmpFar =3D (SEV_ES_AP_JMP_FAR *) FixedPcdGet32 (PcdSevEsWorkAreaBa= se); + ASSERT (JmpFar !=3D NULL); + + Offset =3D FixedPcdGet32 (PcdSevEsWorkAreaBase); + Offset +=3D sizeof(JmpFar->InsnBuffer); + LoNib =3D (UINT8) Offset; + HiNib =3D (UINT8) (Offset >> 8); + + // JMP FAR [CS:XXYY] =3D> 2E FF 2E YY XX + InsnByte =3D 0; + JmpFar->InsnBuffer[InsnByte++] =3D 0x2E; // CS override prefix + JmpFar->InsnBuffer[InsnByte++] =3D 0xFF; // JMP (FAR) + JmpFar->InsnBuffer[InsnByte++] =3D 0x2E; // ModRM (JMP memory loc= ation) + JmpFar->InsnBuffer[InsnByte++] =3D LoNib; // YY offset ... + JmpFar->InsnBuffer[InsnByte++] =3D HiNib; // XX offset ... + + JmpFar->Rip =3D 0; + JmpFar->Segment =3D (UINT16) (ExchangeInfo->BufferStart >> 4); + } // // Wakeup all APs // @@ -1656,7 +1889,7 @@ MpInitLibInitialize ( ASSERT (MaxLogicalProcessorNumber !=3D 0); =20 AsmGetAddressMap (&AddressMap); - ApResetVectorSize =3D AddressMap.RendezvousFunnelSize + sizeof (MP_CPU_E= XCHANGE_INFO); + ApResetVectorSize =3D GetApResetVectorSize (&AddressMap); ApStackSize =3D PcdGet32(PcdCpuApStackSize); ApLoopMode =3D GetApLoopMode (&MonitorFilterSize); =20 @@ -1715,6 +1948,8 @@ MpInitLibInitialize ( CpuMpData->CpuInfoInHob =3D (UINT64) (UINTN) (CpuMpData->CpuData + M= axLogicalProcessorNumber); InitializeSpinLock(&CpuMpData->MpLock); CpuMpData->SevEsIsEnabled =3D PcdGetBool (PcdSevEsIsEnabled); + CpuMpData->SevEsAPBuffer =3D (UINTN) -1; + CpuMpData->GhcbBase =3D PcdGet64 (PcdGhcbBase); =20 // // Make sure no memory usage outside of the allocated buffer. @@ -1773,6 +2008,7 @@ MpInitLibInitialize ( // APs have been wakeup before, just get the CPU Information // from HOB // + OldCpuMpData->NewCpuMpData =3D CpuMpData; CpuMpData->CpuCount =3D OldCpuMpData->CpuCount; CpuMpData->BspNumber =3D OldCpuMpData->BspNumber; CpuMpData->CpuInfoInHob =3D OldCpuMpData->CpuInfoInHob; diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 17b60903c5a6..36f7764d5fe8 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -280,6 +280,25 @@ GetModeTransitionBuffer ( return 0; } =20 +/** + Return the address of the SEV-ES AP jump table. + + This buffer is required in order for an SEV-ES guest to transition from + UEFI into an OS. + + @retval other Return SEV-ES AP jump table buffer +**/ +UINTN +GetSevEsAPMemory ( + VOID + ) +{ + // + // PEI phase doesn't need to do such transition. So simply return 0. + // + return 0; +} + /** Checks APs status and updates APs status if needed. =20 diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c b/UefiCpuPkg/PiSm= mCpuDxeSmm/X64/SmmFuncsArch.c index 6298571e29b2..28f8e8e133e5 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c @@ -121,7 +121,7 @@ GetProtectedModeCS ( GdtEntry =3D (IA32_SEGMENT_DESCRIPTOR *) GdtrDesc.Base; for (Index =3D 0; Index < GdtEntryCount; Index++) { if (GdtEntry->Bits.L =3D=3D 0) { - if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.L =3D=3D 0) { + if (GdtEntry->Bits.Type > 8 && GdtEntry->Bits.DB =3D=3D 1) { break; } } diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc b/UefiCpuPkg/Libra= ry/MpInitLib/Ia32/MpEqu.inc index efb1bc2bf7cb..4f5a7c859a56 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc @@ -19,7 +19,7 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1 CPU_SWITCH_STATE_LOADED equ 2 =20 -LockLocation equ (RendezvousFunnelProcEnd - Rendez= vousFunnelProcStart) +LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart) StackStartAddressLocation equ LockLocation + 04h StackSizeLocation equ LockLocation + 08h ApProcedureLocation equ LockLocation + 0Ch diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index b74046b76af3..309d53bf3b37 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -215,6 +215,16 @@ CProcedureInvoke: jmp $ ; Never reach here RendezvousFunnelProcEnd: =20 +;-------------------------------------------------------------------------= ------------ +;SwitchToRealProc procedure follows. +;NOT USED IN 32 BIT MODE. +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(SwitchToRealProc) +ASM_PFX(SwitchToRealProc): +SwitchToRealProcStart: + jmp $ ; Never reach here +SwitchToRealProcEnd: + ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); ;-------------------------------------------------------------------------= ------------ @@ -263,6 +273,11 @@ ASM_PFX(AsmGetAddressMap): mov dword [ebx + 0Ch], AsmRelocateApLoopStart mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start mov dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart + mov dword [ebx + 18h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize + mov dword [ebx + 1Ch], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset + mov dword [ebx + 20h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset + mov dword [ebx + 24h], 0 = ; SwitchToRealPM16ModeOffset + mov dword [ebx + 28h], 0 = ; SwitchToRealPM16ModeSize =20 popad ret diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc index 58ef369342a7..c92daaaffd6b 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -19,7 +19,7 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1 CPU_SWITCH_STATE_LOADED equ 2 =20 -LockLocation equ (RendezvousFunnelProcEnd - Rendez= vousFunnelProcStart) +LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart) StackStartAddressLocation equ LockLocation + 08h StackSizeLocation equ LockLocation + 10h ApProcedureLocation equ LockLocation + 18h @@ -41,3 +41,5 @@ ModeTransitionSegmentLocation equ LockLocation + 9= 8h ModeHighMemoryLocation equ LockLocation + 9Ah ModeHighSegmentLocation equ LockLocation + 9Eh Enable5LevelPagingLocation equ LockLocation + 0A0h +SevEsIsEnabledLocation equ LockLocation + 0A1h +GhcbBaseLocation equ LockLocation + 0A2h diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 87f2523e856f..6956b408d004 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -184,9 +184,97 @@ Releaselock: add edi, StackStartAddressLocation add rax, qword [edi] mov rsp, rax + + lea edi, [esi + SevEsIsEnabledLocation] + cmp byte [edi], 1 ; SevEsIsEnabled + jne CProcedureInvoke + + ; + ; program GHCB + ; Each page after the GHCB is a per-CPU page, so the calculation pro= grams + ; a GHCB to be every 8KB. + ; + mov eax, SIZE_4KB + shl eax, 1 ; EAX =3D SIZE_4K * 2 + mov ecx, ebx + mul ecx ; EAX =3D SIZE_4K * 2 * C= puNumber + mov edi, esi + add edi, GhcbBaseLocation + add rax, qword [edi] + mov rdx, rax + shr rdx, 32 + mov rcx, 0xc0010130 + wrmsr jmp CProcedureInvoke =20 GetApicId: + lea edi, [esi + SevEsIsEnabledLocation] + cmp byte [edi], 1 ; SevEsIsEnabled + jne DoCpuid + + ; + ; Since we don't have a stack yet, we can't take a #VC + ; exception. Use the GHCB protocol to perform the CPUID + ; calls. + ; + mov rcx, 0xc0010130 + rdmsr + shl rdx, 32 + or rax, rdx + mov rdi, rax ; RDI now holds the original GHCB GPA + + mov rdx, 0 ; CPUID function 0 + mov rax, 0 ; RAX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + cmp edx, 0bh + jb NoX2ApicSevEs ; CPUID level below CPUID_EXTENDED_TOP= OLOGY + + mov rdx, 0bh ; CPUID function 0x0b + mov rax, 040000000h ; RBX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + test edx, 0ffffh + jz NoX2ApicSevEs ; CPUID.0BH:EBX[15:0] is zero + + mov rdx, 0bh ; CPUID function 0x0b + mov rax, 0c0000000h ; RDX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + + ; Processor is x2APIC capable; 32-bit x2APIC ID is now in EDX + jmp RestoreGhcb + +NoX2ApicSevEs: + ; Processor is not x2APIC capable, so get 8-bit APIC ID + mov rdx, 1 ; CPUID function 1 + mov rax, 040000000h ; RBX register requested + or rax, 4 + wrmsr + rep vmmcall + rdmsr + shr edx, 24 + +RestoreGhcb: + mov rbx, rdx ; Save x2APIC/APIC ID + + mov rdx, rdi ; RDI holds the saved GHCB GPA + shr rdx, 32 + mov eax, edi + wrmsr + + mov rdx, rbx + + ; x2APIC ID or APIC ID is in EDX + jmp GetProcessorNumber + +DoCpuid: mov eax, 0 cpuid cmp eax, 0bh @@ -253,12 +341,158 @@ CProcedureInvoke: =20 RendezvousFunnelProcEnd: =20 +;-------------------------------------------------------------------------= ------------ +;SwitchToRealProc procedure follows. +;ALSO THIS PROCEDURE IS EXECUTED BY APs TRANSITIONING TO 16 BIT MODE. HENC= E THIS PROC +;IS IN MACHINE CODE. +; SwitchToRealProc (UINTN BufferStart, UINT16 Code16, UINT16 Code32, UINT= N StackStart) +; rcx - Buffer Start +; rdx - Code16 Selector Offset +; r8 - Code32 Selector Offset +; r9 - Stack Start +;-------------------------------------------------------------------------= ------------ +global ASM_PFX(SwitchToRealProc) +ASM_PFX(SwitchToRealProc): +SwitchToRealProcStart: +BITS 64 + cli + + ; + ; Get RDX reset value before changing stacks since the + ; new stack won't be able to accomodate a #VC exception. + ; + push rax + push rbx + push rcx + push rdx + + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for = RDX + + pop rdx + pop rcx + pop rbx + pop rax + + ; + ; Establish stack below 1MB + ; + mov rsp, r9 + + ; + ; Push ultimate Reset Vector onto the stack + ; + mov rax, rcx + shr rax, 4 + push word 0x0002 ; RFLAGS + push ax ; CS + push word 0x0000 ; RIP + push word 0x0000 ; For alignment, will be discar= ded + + ; + ; Get address of "16-bit operand size" label + ; + lea rbx, [PM16Mode] + + ; + ; Push addresses used to change to compatibility mode + ; + lea rax, [CompatMode] + push r8 + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + +BITS 32 +CompatMode: + ; + ; Set up stack to prepare for exiting protected mode + ; + push edx ; Code16 CS + push ebx ; PM16Mode label address + + ; + ; Disable paging + ; + mov eax, cr0 ; Read CR0 + btr eax, 31 ; Set PG=3D0 + mov cr0, eax ; Write CR0 + + ; + ; Disable long mode + ; + mov ecx, 0c0000080h ; EFER MSR number + rdmsr ; Read EFER + btr eax, 8 ; Set LME=3D0 + wrmsr ; Write EFER + + ; + ; Disable PAE + ; + mov eax, cr4 ; Read CR4 + btr eax, 5 ; Set PAE=3D0 + mov cr4, eax ; Write CR4 + + mov edx, esi ; Restore RDX reset value + + ; + ; Switch to 16-bit operand size + ; + retf + +BITS 16 + ; + ; At entry to this label + ; - RDX will have its reset value + ; - On the top of the stack + ; - Alignment data (two bytes) to be discarded + ; - IP for Real Mode (two bytes) + ; - CS for Real Mode (two bytes) + ; +PM16Mode: + mov eax, cr0 ; Read CR0 + btr eax, 0 ; Set PE=3D0 + mov cr0, eax ; Write CR0 + + pop ax ; Discard alignment data + + ; + ; Clear registers (except RDX and RSP) before going into 16-bit mode + ; + xor eax, eax + xor ebx, ebx + xor ecx, ecx + xor esi, esi + xor edi, edi + xor ebp, ebp + + iret + +SwitchToRealProcEnd: + ;-------------------------------------------------------------------------= ------------ ; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmRelocateApLoop) ASM_PFX(AsmRelocateApLoop): AsmRelocateApLoopStart: +BITS 64 cli ; Disable interrupt before switching to 3= 2-bit mode mov rax, [rsp + 40] ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- @@ -324,6 +558,11 @@ ASM_PFX(AsmGetAddressMap): mov qword [rcx + 18h], rax mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart + mov qword [rcx + 30h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize + mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset + mov qword [rcx + 40h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset + mov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart = ; SwitchToRealPM16ModeOffset + mov qword [rcx + 50h], SwitchToRealProcEnd - PM16Mode = ; SwitchToRealPM16ModeSize ret =20 ;-------------------------------------------------------------------------= ------------ --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB3291.namprd12.prod.outlook.com (2603:10b6:5:186::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16; Tue, 3 Mar 2020 05:43:47 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Tue, 3 Mar 2020 05:43:47 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v5 40/42] OvmfPkg: Use the SEV-ES work area for the SEV-ES AP reset vector Date: Mon, 2 Mar 2020 23:43:33 -0600 Message-Id: <76139cc5f85eae6b583e8e370c57050d57bbb5e9.1583190432.git.thomas.lendacky@amd.com> In-Reply-To: References: X-ClientProxiedBy: SN4PR0501CA0066.namprd05.prod.outlook.com (2603:10b6:803:41::43) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by SN4PR0501CA0066.namprd05.prod.outlook.com (2603:10b6:803:41::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.5 via Frontend Transport; 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: Ehs3xiNudSbPo9j1fkLjvRrPx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583214231; bh=7E1xyjoWG2mwf70cl0fQq4ecKAquGL7+3WuNTZ/Og0g=; h=Content-Type:Date:From:Reply-To:Subject:To; b=fCjq43dFGLK8x3+lWJ7IDK7elbhLHSg/sBoSTSfeToVdWVN+t8GTOVerM458sShUSCv B02XlA9CRftXpTJsaSsZAPR8RI2dp/o980XdHqBnUD9oWpNrhRg8OS/TqbQOdV5bNwQWU GcBfWMAWKBzRRmUk5poP4ZmO8nTHhvFbq4E= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 A hypervisor is not allowed to update an SEV-ES guest's register state, so when booting an SEV-ES guest AP, the hypervisor is not allowed to set the RIP to the guest requested value. Instead an SEV-ES AP must be re-directed from within the guest to the actual requested staring location as specified in the INIT-SIPI-SIPI sequence. Use the SEV-ES work area for the reset vector code that contains support to jump to the desired RIP location after having been started. This is required for only the very first AP reset. This new OVMF source file, ResetVectorVtf0.asm, is used in place of the original file through the use of the include path order set in OvmfPkg/ResetVector/ResetVector.inf under "[BuildOptions]". Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 100 +++++++++++++++++++ OvmfPkg/ResetVector/ResetVector.nasmb | 1 + 2 files changed, 101 insertions(+) create mode 100644 OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm diff --git a/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm b/OvmfPkg/ResetVe= ctor/Ia16/ResetVectorVtf0.asm new file mode 100644 index 000000000000..980e0138e7fe --- /dev/null +++ b/OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm @@ -0,0 +1,100 @@ +;-------------------------------------------------------------------------= ----- +; @file +; First code executed by processor after resetting. +; Derived from UefiCpuPkg/ResetVector/Vtf0/Ia16/ResetVectorVtf0.asm +; +; Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +;-------------------------------------------------------------------------= ----- + +BITS 16 + +ALIGN 16 + +; +; Pad the image size to 4k when page tables are in VTF0 +; +; If the VTF0 image has page tables built in, then we need to make +; sure the end of VTF0 is 4k above where the page tables end. +; +; This is required so the page tables will be 4k aligned when VTF0 is +; located just below 0x100000000 (4GB) in the firmware device. +; +%ifdef ALIGN_TOP_TO_4K_FOR_PAGING + TIMES (0x1000 - ($ - EndOfPageTables) - 0x20) DB 0 +%endif + +; +; SEV-ES Processor Reset support +; +; sevEsResetBlock: +; For the initial boot of an AP under SEV-ES, the "reset" RIP must be +; programmed to the RAM area defined by SEV_ES_AP_RESET_IP. A known offs= et +; and GUID will be used to locate this block in the firmware and extract +; the build time RIP value. The GUID must always be 48 bytes from the +; end of the firmware. +; +; 0xffffffca (-0x36) - IP value +; 0xffffffcc (-0x34) - CS segment base [31:16] +; 0xffffffce (-0x32) - Size of the SEV-ES reset block +; 0xffffffd0 (-0x30) - SEV-ES reset block GUID +; (00f771de-1a7e-4fcb-890e-68c77e2fb44e) +; +; A hypervisor reads the CS segement base and IP value. The CS segment b= ase +; value represents the high order 16-bits of the CS segment base, so the +; hypervisor must left shift the value of the CS segement base by 16 bit= s to +; form the full CS segment base for the CS segment register. It would th= en +; program the EIP register with the IP value as read. +; + +TIMES (32 - (sevEsResetBlockEnd - sevEsResetBlockStart)) DB 0 + +sevEsResetBlockStart: + DD SEV_ES_AP_RESET_IP + DW sevEsResetBlockEnd - sevEsResetBlockStart + DB 0xDE, 0x71, 0xF7, 0x00, 0x7E, 0x1A, 0xCB, 0x4F + DB 0x89, 0x0E, 0x68, 0xC7, 0x7E, 0x2F, 0xB4, 0x4E +sevEsResetBlockEnd: + +ALIGN 16 + +applicationProcessorEntryPoint: +; +; Application Processors entry point +; +; GenFv generates code aligned on a 4k boundary which will jump to this +; location. (0xffffffe0) This allows the Local APIC Startup IPI to be +; used to wake up the application processors. +; + jmp EarlyApInitReal16 + +ALIGN 8 + + DD 0 + +; +; The VTF signature +; +; VTF-0 means that the VTF (Volume Top File) code does not require +; any fixups. +; +vtfSignature: + DB 'V', 'T', 'F', 0 + +ALIGN 16 + +resetVector: +; +; Reset Vector +; +; This is where the processor will begin execution +; + nop + nop + jmp EarlyBspInitReal16 + +ALIGN 16 + +fourGigabytes: + diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 762661115d50..4913b379a993 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -82,5 +82,6 @@ =20 %include "Main.asm" =20 + %define SEV_ES_AP_RESET_IP FixedPcdGet32 (PcdSevEsWorkAreaBase) %include "Ia16/ResetVectorVtf0.asm" =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55289): https://edk2.groups.io/g/devel/message/55289 Mute This Topic: https://groups.io/mt/71694684/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 19 02:26:45 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55290+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583214232079671.7948409524245; Mon, 2 Mar 2020 21:43:52 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 4N0rYY1788612x6Qyo1Oofwd; Mon, 02 Mar 2020 21:43:51 -0800 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (NAM12-MW2-obe.outbound.protection.outlook.com []) by mx.groups.io with SMTP id smtpd.web10.91.1583214230107484776 for ; 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mx.microsoft.com 1; spf=pass smtp.mailfrom=amd.com; dmarc=pass action=none header.from=amd.com; dkim=pass header.d=amd.com; arc=none X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) by DM6PR12MB3291.namprd12.prod.outlook.com (2603:10b6:5:186::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2772.16; Tue, 3 Mar 2020 05:43:48 +0000 X-Received: from DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733]) by DM6PR12MB3163.namprd12.prod.outlook.com ([fe80::f0f9:a88f:f840:2733%7]) with mapi id 15.20.2772.019; Tue, 3 Mar 2020 05:43:48 +0000 From: "Lendacky, Thomas" To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH v5 41/42] OvmfPkg: Move the GHCB allocations into reserved memory Date: Mon, 2 Mar 2020 23:43:34 -0600 Message-Id: In-Reply-To: References: X-ClientProxiedBy: SN4PR0501CA0066.namprd05.prod.outlook.com (2603:10b6:803:41::43) To DM6PR12MB3163.namprd12.prod.outlook.com (2603:10b6:5:15e::26) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-Received: from tlendack-t1.amd.com (165.204.77.1) by SN4PR0501CA0066.namprd05.prod.outlook.com (2603:10b6:803:41::43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.2793.5 via Frontend Transport; Tue, 3 Mar 2020 05:43:47 +0000 X-Originating-IP: [165.204.77.1] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 78a83004-74c7-450a-344d-08d7bf35d827 X-MS-TrafficTypeDiagnostic: DM6PR12MB3291: X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:3044; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55290+1787277+3901457@groups.io; helo=web01.groups.io; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info: 7z2opyOBkHS59TEWV6/eyES49SO6/Tdw0dM1ud8M9KUduNlmVEuKyLKfUaQVJajrKsdUhyCjCqFDZhC2ozllv7bct2MlBjtsF6ohV6snL3mJtSLKQ4X8anUfJL/iDPcjIm1BwVr6ovizTnwSJtnnC8ZkDAnGd9EsdtT/LtcHizjqIP6aXBw0pl6OD7zFMg5R64RqiF53SvrYMHrx3VVJREEE4rqYJZSVebhNk8AWExyrBAEBgu/7YdrJBIhjVKbbO3Zk0AisgV6VeRoCjdKTZKdfn3i/vqKhXRm4QNzJttE7ceeHz3AR6qRKHyIULUgvJXLOk6X4hqR8Lw8Nthp4PFpxMZvX48vbOj5x5amKYob0FxRyFq5XxirTXnzIvqSvkELpWrcyemAodqB6B2Y1t+562eh/u06VyYwBf7c05t7jQvuytlO+P/amyk0MYb0TeXYtdsHqs/j1Eo6J6Whjh3wUwk+k3CarVNM7N7lI9tT3c90n4A5IsuB+bbHeVV7WQ1+vsu+ghD2lnfXItZu0EA== X-MS-Exchange-AntiSpam-MessageData: bujRI6OSSti2KZhMjqe/Z9toYoIG6xvxDlXqJXOPWMJxCpaY6JcRGYoej+CoAYBhfakmJf+UbSfLPr04c8rca1KTgVWZZO1GY4qR0Zd0aVEN38TtjuElhpOqHRcdj1QHkF6tMwMmPaXLlkpUNYTLTA== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 78a83004-74c7-450a-344d-08d7bf35d827 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2020 05:43:47.8333 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: kNdjKCh3ZH5MMv1ocC3PCl+9LQ4V+21+FRZdg3YSVHUBhDERcAHDoJGGUjJqv3+1JEM7e/FRHoYUcRR6fF91qQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB3291 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: lQ8unvDegKMBKAoOJ6swFt3nx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583214231; bh=fm4rPyizeQtdGcoPs0O04xObPD+dNbLfDDTHgXytYWA=; h=Content-Type:Date:From:Reply-To:Subject:To; b=Md/xkipG9t6+k8vEMyrG70ku/0iVDpowlrvsTRjKYAwcIN6CtgubqMUCda+dKBm8j4T 4B71XwQcWHXeXevkJUhs1V95L0eK5+ztHCWJDvk8iAvtYEZ6iWMo8tbhlTFPDy41zZtco lTwsXEEF6f+Xt96Mzsy8c9U/jNLeWQFPRqQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 After having transitioned from UEFI to the OS, the OS will need to boot the APs. For an SEV-ES guest, the APs will have been parked by UEFI using GHCB pages allocated by UEFI. The hypervisor will write to the GHCB SW_EXITINFO2 field of the GHCB when the AP is booted. As a result, the GHCB pages must be marked reserved so that the OS does not attempt to use them and experience memory corruption because of the hypervisor write. Change the GHCB allocation from the default boot services memory to reserved memory. Cc: Jordan Justen Cc: Laszlo Ersek Cc: Ard Biesheuvel Reviewed-by: Laszlo Ersek Signed-off-by: Tom Lendacky --- OvmfPkg/PlatformPei/AmdSev.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/PlatformPei/AmdSev.c b/OvmfPkg/PlatformPei/AmdSev.c index 38885de359af..2b6c965808e9 100644 --- a/OvmfPkg/PlatformPei/AmdSev.c +++ b/OvmfPkg/PlatformPei/AmdSev.c @@ -51,9 +51,11 @@ AmdSevEsInitialize ( =20 // // Allocate GHCB and per-CPU variable pages. + // Since the pages must survive across the UEFI to OS transition + // make them reserved. // GhcbPageCount =3D mMaxCpuCount * 2; - GhcbBase =3D AllocatePages (GhcbPageCount); + GhcbBase =3D AllocateReservedPages (GhcbPageCount); ASSERT (GhcbBase !=3D NULL); =20 GhcbBasePa =3D (PHYSICAL_ADDRESS)(UINTN) GhcbBase; --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 5TRXQwGwvvUoW6Euz6MIg9Nux1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583214231; bh=hOsHEbw2yklOYIYSHn7Y9YeLisQjvia3TQWyTz8H1Hs=; h=Content-Type:Date:From:Reply-To:Subject:To; b=vg2wjsoP/rKPMB6ds43girFrP43mI4hkF/Q3bcelUDQBT3oBtCw9T+Wes6d86mNGIgp 46VJB9Zk54Spdmt283PQc12Os2boMfWtUYc2HVgbMn33PH3AZgDckg8cJVv0j10KKFOVW YK+W7cLqccHgXza/rfgk3UqTheYJvxGAgTQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2198 Before UEFI transfers control to the OS, it must park the AP. This is done using the AsmRelocateApLoop function to transition into 32-bit non-paging mode. For an SEV-ES guest, a few additional things must be done: - AsmRelocateApLoop must be updated to support SEV-ES. This means performing a VMGEXIT AP Reset Hold instead of an MWAIT or HLT loop. - Since the AP must transition to real mode, a small routine is copied to the WakeupBuffer area. Since the WakeupBuffer will be used by the AP during OS booting, it must be placed in reserved memory. Additionally, the AP stack must be located where it can be accessed in real mode. - Once the AP is in real mode it will transfer control to the destination specified by the OS in the SEV-ES AP Jump Table. The SEV-ES AP Jump Table address is saved by the hypervisor for the OS using the GHCB VMGEXIT AP Jump Table exit code. Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Tom Lendacky --- UefiCpuPkg/Library/MpInitLib/MpLib.h | 8 +- UefiCpuPkg/Library/MpInitLib/DxeMpLib.c | 44 +++++- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 131 ++++++++++++++++-- 3 files changed, 166 insertions(+), 17 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 56bfd9cc253c..0cc92d011bd8 100755 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -292,7 +292,8 @@ struct _CPU_MP_DATA { UINT64 GhcbBase; }; =20 -#define AP_RESET_STACK_SIZE 64 +#define AP_SAFE_STACK_SIZE 128 +#define AP_RESET_STACK_SIZE AP_SAFE_STACK_SIZE =20 #pragma pack(1) =20 @@ -348,8 +349,11 @@ VOID IN BOOLEAN MwaitSupport, IN UINTN ApTargetCState, IN UINTN PmCodeSegment, + IN UINTN Pm16CodeSegment, IN UINTN TopOfApStack, - IN UINTN NumberToFinish + IN UINTN NumberToFinish, + IN UINTN SevEsAPJumpTable, + IN UINTN WakeupBuffer ); =20 /** diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c b/UefiCpuPkg/Library/M= pInitLib/DxeMpLib.c index 8510a13145f3..db15f88a3f29 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpLib.c @@ -12,13 +12,13 @@ #include #include #include +#include #include #include =20 #include =20 #define AP_CHECK_INTERVAL (EFI_TIMER_PERIOD_MILLISECONDS (100)) -#define AP_SAFE_STACK_SIZE 128 =20 CPU_MP_DATA *mCpuMpData =3D NULL; EFI_EVENT mCheckAllApsEvent =3D NULL; @@ -86,6 +86,13 @@ GetWakeupBuffer ( { EFI_STATUS Status; EFI_PHYSICAL_ADDRESS StartAddress; + EFI_MEMORY_TYPE MemoryType; + + if (PcdGetBool (PcdSevEsIsEnabled)) { + MemoryType =3D EfiReservedMemoryType; + } else { + MemoryType =3D EfiBootServicesData; + } =20 // // Try to allocate buffer below 1M for waking vector. @@ -98,7 +105,7 @@ GetWakeupBuffer ( StartAddress =3D 0x88000; Status =3D gBS->AllocatePages ( AllocateMaxAddress, - EfiBootServicesData, + MemoryType, EFI_SIZE_TO_PAGES (WakeupBufferSize), &StartAddress ); @@ -177,6 +184,11 @@ GetSevEsAPMemory ( =20 DEBUG ((DEBUG_INFO, "Dxe: SevEsAPMemory =3D %lx\n", (UINTN) StartAddress= )); =20 + // + // Save the SevEsAPMemory as the AP jump table. + // + VmgExitSetAPJumpTable (StartAddress); + return (UINTN) StartAddress; } =20 @@ -331,17 +343,26 @@ RelocateApLoop ( BOOLEAN MwaitSupport; ASM_RELOCATE_AP_LOOP AsmRelocateApLoopFunc; UINTN ProcessorNumber; + UINTN StackStart; =20 MpInitLibWhoAmI (&ProcessorNumber); CpuMpData =3D GetCpuMpData (); MwaitSupport =3D IsMwaitSupport (); + if (CpuMpData->SevEsIsEnabled) { + StackStart =3D CpuMpData->SevEsAPResetStackStart; + } else { + StackStart =3D mReservedTopOfApStack; + } AsmRelocateApLoopFunc =3D (ASM_RELOCATE_AP_LOOP) (UINTN) mReservedApLoop= Func; AsmRelocateApLoopFunc ( MwaitSupport, CpuMpData->ApTargetCState, CpuMpData->PmCodeSegment, - mReservedTopOfApStack - ProcessorNumber * AP_SAFE_STACK_SIZE, - (UINTN) &mNumberToFinish + CpuMpData->Pm16CodeSegment, + StackStart - ProcessorNumber * AP_SAFE_STACK_SIZE, + (UINTN) &mNumberToFinish, + CpuMpData->SevEsAPBuffer, + CpuMpData->WakeupBuffer ); // // It should never reach here @@ -375,6 +396,21 @@ MpInitChangeApLoopCallback ( while (mNumberToFinish > 0) { CpuPause (); } + + if (CpuMpData->SevEsIsEnabled && (CpuMpData->WakeupBuffer !=3D (UINTN) -= 1)) { + // + // There are APs present. Re-use reserved memory area below 1MB from + // WakeupBuffer as the area to be used for transitioning to 16-bit mode + // in support of booting of the AP by an OS. + // + CopyMem ( + (VOID *) CpuMpData->WakeupBuffer, + (VOID *) CpuMpData->AddressMap.RendezvousFunnelAddress + + CpuMpData->AddressMap.SwitchToRealPM16ModeOffset, + CpuMpData->AddressMap.SwitchToRealPM16ModeSize + ); + } + DEBUG ((DEBUG_INFO, "%a() done!\n", __FUNCTION__)); } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index 6956b408d004..3b8ec477b8b3 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -465,6 +465,10 @@ BITS 16 ; - IP for Real Mode (two bytes) ; - CS for Real Mode (two bytes) ; + ; This label is also used with AsmRelocateApLoop. During MP finalizati= on, + ; the code from PM16Mode to SwitchToRealProcEnd is copied to the start= of + ; the WakeupBuffer, allowing a parked AP to be booted by an OS. + ; PM16Mode: mov eax, cr0 ; Read CR0 btr eax, 0 ; Set PE=3D0 @@ -487,32 +491,95 @@ PM16Mode: SwitchToRealProcEnd: =20 ;-------------------------------------------------------------------------= ------------ -; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, TopOfAp= Stack, CountTofinish); +; AsmRelocateApLoop (MwaitSupport, ApTargetCState, PmCodeSegment, Pm16Cod= eSegment, TopOfApStack, CountTofinish, SevEsAPJumpTable, WakeupBuffer); ;-------------------------------------------------------------------------= ------------ global ASM_PFX(AsmRelocateApLoop) ASM_PFX(AsmRelocateApLoop): AsmRelocateApLoopStart: BITS 64 + cmp qword [rsp + 56], 0 + je NoSevEs + + ; + ; Perform some SEV-ES related setup before leaving 64-bit mode + ; + push rcx + push rdx + + ; + ; Get the RDX reset value using CPUID + ; + mov rax, 1 + cpuid + mov rsi, rax ; Save off the reset value for RDX + + ; + ; Prepare the GHCB for the AP_HLT_LOOP VMGEXIT call + ; - Must be done while in 64-bit long mode so that writes to + ; the GHCB memory will be unencrypted. + ; - No NAE events can be generated once this is set otherwise + ; the AP_RESET_HOLD SW_EXITCODE will be overwritten. + ; + mov rcx, 0xc0010130 + rdmsr ; Retrieve current GHCB address + shl rdx, 32 + or rdx, rax + + mov rdi, rdx + xor rax, rax + mov rcx, 0x800 + shr rcx, 3 + rep stosq ; Clear the GHCB + + mov rax, 0x80000004 ; VMGEXIT AP_RESET_HOLD + mov [rdx + 0x390], rax + + pop rdx + pop rcx + +NoSevEs: cli ; Disable interrupt before switching to 3= 2-bit mode - mov rax, [rsp + 40] ; CountTofinish + mov rax, [rsp + 48] ; CountTofinish lock dec dword [rax] ; (*CountTofinish)-- - mov rsp, r9 - push rcx - push rdx =20 - lea rsi, [PmEntry] ; rsi <- The start address of transition = code + mov rax, [rsp + 56] ; SevEsAPJumpTable + mov rbx, [rsp + 64] ; WakeupBuffer + mov rsp, [rsp + 40] ; TopOfApStack + + push rax ; Save SevEsAPJumpTable + push rbx ; Save WakeupBuffer + push r9 ; Save Pm16CodeSegment + push rcx ; Save MwaitSupport + push rdx ; Save ApTargetCState + + lea rax, [PmEntry] ; rax <- The start address of transition = code =20 push r8 - push rsi - DB 0x48 - retf + push rax + + ; + ; Clear R8 - R15, for reset, before going into 32-bit mode + ; + xor r8, r8 + xor r9, r9 + xor r10, r10 + xor r11, r11 + xor r12, r12 + xor r13, r13 + xor r14, r14 + xor r15, r15 + + ; + ; Far return into 32-bit mode + ; +o64 retf + BITS 32 PmEntry: mov eax, cr0 btr eax, 31 ; Clear CR0.PG mov cr0, eax ; Disable paging and caches =20 - mov ebx, edx ; Save EntryPoint to rbx, for rdmsr will = overwrite rdx mov ecx, 0xc0000080 rdmsr and ah, ~ 1 ; Clear LME @@ -525,6 +592,8 @@ PmEntry: add esp, 4 pop ecx, add esp, 4 + +MwaitCheck: cmp cl, 1 ; Check mwait-monitor support jnz HltLoop mov ebx, edx ; Save C-State to ebx @@ -538,10 +607,50 @@ MwaitLoop: shl eax, 4 mwait jmp MwaitLoop + HltLoop: + pop edx ; PM16CodeSegment + add esp, 4 + pop ebx ; WakeupBuffer + add esp, 4 + pop eax ; SevEsAPJumpTable + add esp, 4 + cmp eax, 0 ; Check for SEV-ES + je DoHlt + + cli + ; + ; SEV-ES is enabled, use VMGEXIT (GHCB information already + ; set by caller) + ; +BITS 64 + rep vmmcall +BITS 32 + + ; + ; Back from VMGEXIT AP_HLT_LOOP + ; Push the FLAGS/CS/IP values to use + ; + push word 0x0002 ; EFLAGS + xor ecx, ecx + mov cx, [eax + 2] ; CS + push cx + mov cx, [eax] ; IP + push cx + push word 0x0000 ; For alignment, will be discarded + + push edx + push ebx + + mov edx, esi ; Restore RDX reset value + + retf + +DoHlt: cli hlt - jmp HltLoop + jmp DoHlt + BITS 64 AsmRelocateApLoopEnd: =20 --=20 2.17.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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