From nobody Fri Apr 19 21:28:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+53041+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53041+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1578536051; cv=none; d=zohomail.com; s=zohoarc; b=li8bAdqGDvbBZtpLsa1NZnxf8CEqhUI7EZ6DKBJA7REPgE07ANw3VhjnS7w7hxwsEJDrUoLMgIL5DqhlZfyjk6QMRxqf7kOy/P5fKxIos6zgsQuCbuJzrfXs9Vj1sRS4irwTvYNbr6FBoTXQg0tSXiwPHVoXxC9S2RnPNJTL7wg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578536051; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=TBrNNC48JXVepAInD9Y72QHw3TUgreusxCxLc+IZkDA=; b=GheQPL9p9BU9ZSINDpdKcURPMLN71mBkfYxM02KRFYJrlNfEKQEQiNjpZDMCkm3XeMvVmiVN8IOFX1OuRJD2naqYkdiwiJaAVMAs9kBHF1POsiQw+fFVzql9UCFunBH3fJtb2FmSg2CtpusnmIqjL5s92pRQ1tZB2O8B3zG4w8k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53041+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1578536051964592.7889622918887; Wed, 8 Jan 2020 18:14:11 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id ok2dYY1788612xIwlsZ7bJ7D; Wed, 08 Jan 2020 18:14:11 -0800 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web12.3250.1578536050086858825 for ; Wed, 08 Jan 2020 18:14:11 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jan 2020 18:14:10 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,412,1571727600"; d="scan'208";a="421640406" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga005.fm.intel.com with ESMTP; 08 Jan 2020 18:14:09 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, liming.gao@intel.com, eric.dong@intel.com, ray.ni@intel.com, lersek@redhat.com Subject: [edk2-devel] [PATCH v2 1/2] MdePkg: Add header file for Firmware Interface Table specification. Date: Thu, 9 Jan 2020 10:14:04 +0800 Message-Id: <22247fcc9c3a4f5fe237ff2e9ec289fb41ceb3ec.1578535686.git.siyuan.fu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: VtxGIoCaeqe9dcFFWubUKfDDx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1578536051; bh=Z0zipYsC61mFeaMbDLDue2A22++7j//l0/tWIGzPZQ8=; h=Cc:Date:From:Reply-To:Subject:To; b=jCypxaEWSZjxWsXBNfuY83lcerF74y7TG7ze4iUutGq5WG6G3U4iEPesZXv67jveQ/m wa1L/61l1quB5SiF3A2cXpIm213bHP1++jmveICGI0qcC6KVJEKMSWyPHJ3Tko144toXM ScOzHVUSh+tTU6eLVOdE8U5Y5PvJX0t6COs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch add FirmwareInterfaceTable.h for the Firmware Interface Table BIOS specification. This is to remove future edk2 dependency on edk2-platforms repo. The file content comes from edk2-platforms\Silicon\Intel\IntelSiliconPkg\Include\IndustryStandard BZ link: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 Cc: Michael D Kinney Cc: Liming Gao Signed-off-by: Siyuan Fu Reviewed-by: Liming Gao --- .../IndustryStandard/FirmwareInterfaceTable.h | 76 +++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h diff --git a/MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h b/Mde= Pkg/Include/IndustryStandard/FirmwareInterfaceTable.h new file mode 100644 index 0000000000..be3e34ae1b --- /dev/null +++ b/MdePkg/Include/IndustryStandard/FirmwareInterfaceTable.h @@ -0,0 +1,76 @@ +/** @file + Industry Standard Definitions of Firmware Interface Table BIOS Specifica= tion 1.0. + + Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __FIRMWARE_INTERFACE_TABLE_H__ +#define __FIRMWARE_INTERFACE_TABLE_H__ + +// +// FIT Entry type definitions +// +#define FIT_TYPE_00_HEADER 0x00 +#define FIT_TYPE_01_MICROCODE 0x01 +#define FIT_TYPE_02_STARTUP_ACM 0x02 +#define FIT_TYPE_07_BIOS_STARTUP_MODULE 0x07 +#define FIT_TYPE_08_TPM_POLICY 0x08 +#define FIT_TYPE_09_BIOS_POLICY 0x09 +#define FIT_TYPE_0A_TXT_POLICY 0x0A +#define FIT_TYPE_0B_KEY_MANIFEST 0x0B +#define FIT_TYPE_0C_BOOT_POLICY_MANIFEST 0x0C +#define FIT_TYPE_10_CSE_SECURE_BOOT 0x10 +#define FIT_TYPE_2D_TXTSX_POLICY 0x2D +#define FIT_TYPE_2F_JMP_DEBUG_POLICY 0x2F +#define FIT_TYPE_7F_SKIP 0x7F + +#define FIT_POINTER_ADDRESS 0xFFFFFFC0 ///< Fixed address = at 4G - 40h + +#define FIT_TYPE_VERSION 0x0100 + +#define FIT_TYPE_00_SIGNATURE SIGNATURE_64 ('_', 'F', 'I', 'T', '_', ' ',= ' ', ' ') + +#pragma pack(1) + +typedef struct { + // + // Address is the base address of the firmware component + // must be aligned on 16 byte boundary + // + UINT64 Address; + // + // Size is the span of the component in multiple of 16 bytes + // + UINT8 Size[3]; + // + // Reserved must be set to 0 + // + UINT8 Reserved; + // + // Component's version number in binary coded decimal (BCD) format. + // For the FIT header entry, the value in this field will indicate the r= evision + // number of the FIT data structure. The upper byte of the revision field + // indicates the major revision and the lower byte indicates the minor r= evision. + // + UINT16 Version; + // + // FIT types 0x00 to 0x7F + // + UINT8 Type : 7; + // + // Checksum Valid indicates whether component has valid checksum. + // + UINT8 C_V : 1; + // + // Component's checksum. The modulo sum of all the bytes in the componen= t and + // the value in this field (Chksum) must add up to zero. This field is o= nly + // valid if the C_V flag is non-zero. + // + UINT8 Chksum; +} FIRMWARE_INTERFACE_TABLE_ENTRY; + +#pragma pack() + +#endif --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#53041): https://edk2.groups.io/g/devel/message/53041 Mute This Topic: https://groups.io/mt/69559935/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Fri Apr 19 21:28:37 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+53042+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53042+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1578536054; cv=none; d=zohomail.com; s=zohoarc; b=AEdrN6OBaOPy3pNmy6bFvZc61DiTh/E0YDlZ/liWCavTzs0DvvZq0xG8hfpeNTf5jP6UZgOqo7PSGGMn30sOdET7/dX40aG3Q2+BnThXrmp398zQSE7uYpGng8Cbr2AJvwBxXdpSEs4e8v1PvDdXKitd1rVPYGxpwwUZHW2wbx8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578536054; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=hazcbv+K5A8QAdqEKf6lBsl1kxAjUZ1d4tPSQQwCCBQ=; b=FX6whuSdASQXu/LZ+j7+M6lDotlrZ4bha8kuYFeA9XMAhg6eG1reP8+rIOxOlsf4DA1PfHympp0bN03YFpBirCBaPv2LOVJMXctpTVp1eyFWXinsDGT74gT/RIdKcYiqEuIm9C1tACvNTpEwKhaXXulLFigap6bIF6/baVWU1IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53042+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1578536054156137.79258314313097; Wed, 8 Jan 2020 18:14:14 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Y8a1YY1788612xSRnSd09kFB; Wed, 08 Jan 2020 18:14:13 -0800 X-Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web12.3250.1578536050086858825 for ; Wed, 08 Jan 2020 18:14:13 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Jan 2020 18:14:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,412,1571727600"; d="scan'208";a="421640422" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga005.fm.intel.com with ESMTP; 08 Jan 2020 18:14:10 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: michael.d.kinney@intel.com, liming.gao@intel.com, eric.dong@intel.com, ray.ni@intel.com, lersek@redhat.com Subject: [edk2-devel] [PATCH v2 2/2] UefiCpuPkg: Shadow microcode patch according to FIT microcode entry. Date: Thu, 9 Jan 2020 10:14:05 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: VaF76JOmij87nN8xkA48VMKUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1578536053; bh=ABHN8yadVPGYcOtX7PAO3pm2Q8yeUCduXYPWFQZ6GjU=; h=Cc:Date:From:Reply-To:Subject:To; b=XBy3esgLYweDOQHB6QA0vAZNJ9l0tlH60JOKtBMo2tR7sBDJAaG/kN0NNWwAxbRCZod Xt4W4uKXe8LNGLKXfRvZUxUfvivMNXS9kZLbqQyHIuBUMpwP7mOr+VrQtkuxnSfo/G0mx IHua6KeiOxZ0noDuEesNxtowgCtGW9HV188= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The existing MpInitLib will shadow the microcode update patches from flash to memory and this is done by searching microcode region specified by PCD PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize. This brings a limition to platform FW that all the microcode patches must be placed in one continuous flash space. This patch shadows microcode update according to FIT microcode entries if it's present, otherwise it will fallback to original logic (by PCD). A new featured PCD gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit is added for enabling/disabling this support. TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Siyuan Fu Acked-by: Laszlo Ersek Reviewed-by: Eric Dong --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 1 + UefiCpuPkg/Library/MpInitLib/Microcode.c | 262 +++++++++++++----- UefiCpuPkg/Library/MpInitLib/MpLib.c | 4 +- UefiCpuPkg/Library/MpInitLib/MpLib.h | 7 +- UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 4 +- UefiCpuPkg/UefiCpuPkg.dec | 6 + 6 files changed, 216 insertions(+), 68 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index cd912ab0c5..0fd420ac93 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -69,4 +69,5 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONS= UMES + gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit ## CONS= UMES =20 diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 8f4d4da40c..9389e52ae5 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -318,7 +318,7 @@ Done: } =20 /** - Determine if a microcode patch will be loaded into memory. + Determine if a microcode patch matchs the specific processor signature a= nd flag. =20 @param[in] CpuMpData The pointer to CPU MP Data structure. @param[in] ProcessorSignature The processor signature field value @@ -330,7 +330,7 @@ Done: @retval FALSE The specified microcode patch will not be loaded. **/ BOOLEAN -IsMicrocodePatchNeedLoad ( +IsProcessorMatchedMicrocodePatch ( IN CPU_MP_DATA *CpuMpData, IN UINT32 ProcessorSignature, IN UINT32 ProcessorFlags @@ -351,7 +351,77 @@ IsMicrocodePatchNeedLoad ( } =20 /** - Actual worker function that loads the required microcode patches into me= mory. + Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode + patch header with the CPUID and PlatformID of the processors within + system to decide if it will be copied into memory. + + @param[in] CpuMpData The pointer to CPU MP Data structure. + @param[in] MicrocodeEntryPoint The pointer to the microcode patch hea= der. + + @retval TRUE The specified microcode patch need to be loaded. + @retval FALSE The specified microcode patch dosen't need to be loaded. +**/ +BOOLEAN +IsMicrocodePatchNeedLoad ( + IN CPU_MP_DATA *CpuMpData, + CPU_MICROCODE_HEADER *MicrocodeEntryPoint + ) +{ + BOOLEAN NeedLoad; + UINTN DataSize; + UINTN TotalSize; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + UINT32 ExtendedTableCount; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + UINTN Index; + + // + // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcode patc= h header. + // + NeedLoad =3D IsProcessorMatchedMicrocodePatch ( + CpuMpData, + MicrocodeEntryPoint->ProcessorSignature.Uint32, + MicrocodeEntryPoint->ProcessorFlags + ); + + // + // If the Extended Signature Table exists, check if the processor is in = the + // support list + // + DataSize =3D MicrocodeEntryPoint->DataSize; + TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalSiz= e; + if ((!NeedLoad) && (DataSize !=3D 0) && + (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) + + sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)= )) { + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT= 8 *) (MicrocodeEntryPoint) + + DataSize + sizeof (CPU_MICROCODE_HEADER)); + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount; + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTabl= eHeader + 1); + + for (Index =3D 0; Index < ExtendedTableCount; Index ++) { + // + // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Extended + // Signature Table entry with the CPUID and PlatformID of the proces= sors + // within system to decide if it will be copied into memory + // + NeedLoad =3D IsProcessorMatchedMicrocodePatch ( + CpuMpData, + ExtendedTable->ProcessorSignature.Uint32, + ExtendedTable->ProcessorFlag + ); + if (NeedLoad) { + break; + } + ExtendedTable ++; + } + } + + return NeedLoad; +} + + +/** + Actual worker function that shadows the required microcode patches into = memory. =20 @param[in, out] CpuMpData The pointer to CPU MP Data structure. @param[in] Patches The pointer to an array of information= on @@ -363,7 +433,7 @@ IsMicrocodePatchNeedLoad ( to be loaded. **/ VOID -LoadMicrocodePatchWorker ( +ShadowMicrocodePatchWorker ( IN OUT CPU_MP_DATA *CpuMpData, IN MICROCODE_PATCH_INFO *Patches, IN UINTN PatchCount, @@ -390,7 +460,6 @@ LoadMicrocodePatchWorker ( (VOID *) Patches[Index].Address, Patches[Index].Size ); - Walker +=3D Patches[Index].Size; } =20 @@ -410,12 +479,13 @@ LoadMicrocodePatchWorker ( } =20 /** - Load the required microcode patches data into memory. + Shadow the required microcode patches data into memory according to PCD + PcdCpuMicrocodePatchAddress and PcdCpuMicrocodePatchRegionSize. =20 @param[in, out] CpuMpData The pointer to CPU MP Data structure. **/ VOID -LoadMicrocodePatch ( +ShadowMicrocodePatchByPcd ( IN OUT CPU_MP_DATA *CpuMpData ) { @@ -423,15 +493,10 @@ LoadMicrocodePatch ( UINTN MicrocodeEnd; UINTN DataSize; UINTN TotalSize; - CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; - UINT32 ExtendedTableCount; - CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; MICROCODE_PATCH_INFO *PatchInfoBuffer; UINTN MaxPatchNumber; UINTN PatchCount; UINTN TotalLoadSize; - UINTN Index; - BOOLEAN NeedLoad; =20 // // Initialize the microcode patch related fields in CpuMpData as the val= ues @@ -487,55 +552,7 @@ LoadMicrocodePatch ( continue; } =20 - // - // Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode - // patch header with the CPUID and PlatformID of the processors within - // system to decide if it will be copied into memory - // - NeedLoad =3D IsMicrocodePatchNeedLoad ( - CpuMpData, - MicrocodeEntryPoint->ProcessorSignature.Uint32, - MicrocodeEntryPoint->ProcessorFlags - ); - - // - // If the Extended Signature Table exists, check if the processor is i= n the - // support list - // - if ((!NeedLoad) && (DataSize !=3D 0) && - (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) + - sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADE= R))) { - ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UI= NT8 *) (MicrocodeEntryPoint) - + DataSize + sizeof (CPU_MICROCODE_HEADER)); - ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount; - ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTa= bleHeader + 1); - - for (Index =3D 0; Index < ExtendedTableCount; Index ++) { - // - // Avoid access content beyond MicrocodeEnd - // - if ((UINTN) ExtendedTable > MicrocodeEnd - sizeof (CPU_MICROCODE_E= XTENDED_TABLE)) { - break; - } - - // - // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Exten= ded - // Signature Table entry with the CPUID and PlatformID of the proc= essors - // within system to decide if it will be copied into memory - // - NeedLoad =3D IsMicrocodePatchNeedLoad ( - CpuMpData, - ExtendedTable->ProcessorSignature.Uint32, - ExtendedTable->ProcessorFlag - ); - if (NeedLoad) { - break; - } - ExtendedTable ++; - } - } - - if (NeedLoad) { + if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { PatchCount++; if (PatchCount > MaxPatchNumber) { // @@ -581,7 +598,7 @@ LoadMicrocodePatch ( __FUNCTION__, PatchCount, TotalLoadSize )); =20 - LoadMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, Tota= lLoadSize); + ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, To= talLoadSize); } =20 OnExit: @@ -590,3 +607,124 @@ OnExit: } return; } + +/** + Shadow the required microcode patches data into memory according to FIT = microcode entry. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. + + @return EFI_SUCCESS Microcode patch is shadowed into memory. + @return EFI_UNSUPPORTED FIT based microcode shadowing is not suppo= rted. + @return EFI_OUT_OF_RESOURCES No enough memory resource. + @return EFI_NOT_FOUND There is something wrong in FIT microcode = entry. + +**/ +EFI_STATUS +ShadowMicrocodePatchByFit ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + UINT64 FitPointer; + FIRMWARE_INTERFACE_TABLE_ENTRY *FitEntry; + UINT32 EntryNum; + UINT32 Index; + MICROCODE_PATCH_INFO *PatchInfoBuffer; + UINTN MaxPatchNumber; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN PatchCount; + UINTN TotalSize; + UINTN TotalLoadSize; + + if (!FeaturePcdGet (PcdCpuShadowMicrocodeByFit)) { + return EFI_UNSUPPORTED; + } + + FitPointer =3D *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; + if ((FitPointer =3D=3D 0) || + (FitPointer =3D=3D 0xFFFFFFFFFFFFFFFF) || + (FitPointer =3D=3D 0xEEEEEEEEEEEEEEEE)) { + // + // No FIT table. + // + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + FitEntry =3D (FIRMWARE_INTERFACE_TABLE_ENTRY *) (UINTN) FitPointer; + if ((FitEntry[0].Type !=3D FIT_TYPE_00_HEADER) || + (FitEntry[0].Address !=3D FIT_TYPE_00_SIGNATURE)) { + // + // Invalid FIT table, treat it as no FIT table. + // + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + + EntryNum =3D *(UINT32 *)(&FitEntry[0].Size[0]) & 0xFFFFFF; + + // + // Calculate microcode entry number + // + MaxPatchNumber =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + MaxPatchNumber++; + } + } + if (MaxPatchNumber =3D=3D 0) { + return EFI_NOT_FOUND; + } + + PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + if (PatchInfoBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Fill up microcode patch info buffer according to FIT table. + // + PatchCount =3D 0; + TotalLoadSize =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[In= dex].Address; + TotalSize =3D (MicrocodeEntryPoint->DataSize =3D=3D 0) ? 2048 : Micr= ocodeEntryPoint->TotalSize; + if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { + PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntry= Point; + PatchInfoBuffer[PatchCount].Size =3D TotalSize; + TotalLoadSize +=3D TotalSize; + PatchCount++; + } + } + } + + if (PatchCount !=3D 0) { + DEBUG (( + DEBUG_INFO, + "%a: 0x%x microcode patches will be loaded into memory, with size 0x= %x.\n", + __FUNCTION__, PatchCount, TotalLoadSize + )); + + ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, To= talLoadSize); + } + + FreePool (PatchInfoBuffer); + return EFI_SUCCESS; +} + +/** + Shadow the required microcode patches data into memory. + + @param[in, out] CpuMpData The pointer to CPU MP Data structure. +**/ +VOID +ShadowMicrocodeUpdatePatch ( + IN OUT CPU_MP_DATA *CpuMpData + ) +{ + EFI_STATUS Status; + + Status =3D ShadowMicrocodePatchByFit (CpuMpData); + if (EFI_ERROR (Status)) { + ShadowMicrocodePatchByPcd (CpuMpData); + } +} diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.c b/UefiCpuPkg/Library/MpIn= itLib/MpLib.c index e611a8ca40..6ec9b172b8 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.c @@ -1,7 +1,7 @@ /** @file CPU MP Initialize Library common functions. =20 - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -1744,7 +1744,7 @@ MpInitLibInitialize ( // // Load required microcode patches data into memory // - LoadMicrocodePatch (CpuMpData); + ShadowMicrocodeUpdatePatch (CpuMpData); } else { // // APs have been wakeup before, just get the CPU Information diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index b6e5a1afab..7c62d75acc 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -29,6 +29,9 @@ #include #include =20 +#include + + #define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P') =20 #define CPU_INIT_MP_LIB_HOB_GUID \ @@ -587,12 +590,12 @@ MicrocodeDetect ( ); =20 /** - Load the required microcode patches data into memory. + Shadow the required microcode patches data into memory. =20 @param[in, out] CpuMpData The pointer to CPU MP Data structure. **/ VOID -LoadMicrocodePatch ( +ShadowMicrocodeUpdatePatch ( IN OUT CPU_MP_DATA *CpuMpData ); =20 diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 326703cc9a..5b4a1f31c8 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -1,7 +1,7 @@ ## @file # MP Initialize Library instance for PEI driver. # -# Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -60,7 +60,7 @@ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONS= UMES gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOME= TIMES_CONSUMES - + gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit ## CONS= UMES [Guids] gEdkiiS3SmmInitDoneGuid gEdkiiMicrocodePatchHobGuid diff --git a/UefiCpuPkg/UefiCpuPkg.dec b/UefiCpuPkg/UefiCpuPkg.dec index 45b267ac61..a6ebdde1cf 100644 --- a/UefiCpuPkg/UefiCpuPkg.dec +++ b/UefiCpuPkg/UefiCpuPkg.dec @@ -139,6 +139,12 @@ # @Prompt Lock SMM Feature Control MSR. gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmFeatureControlMsrLock|TRUE|BOOLEAN|0x= 3213210B =20 + ## Indicates if FIT based microcode shadowing will be enabled.

+ # TRUE - FIT base microcode shadowing will be enabled.
+ # FALSE - FIT base microcode shadowing will be disabled.
+ # @Prompt FIT based microcode shadowing. + gUefiCpuPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|0x321= 3210D + [PcdsFixedAtBuild] ## List of exception vectors which need switching stack. # This PCD will only take into effect if PcdCpuStackGuard is enabled. --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#53042): https://edk2.groups.io/g/devel/message/53042 Mute This Topic: https://groups.io/mt/69559936/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-