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[176.169.168.38]) by smtp.gmail.com with ESMTPSA id x2sm7573125wrn.81.2019.09.18.05.27.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 05:27:00 -0700 (PDT) From: "Baptiste Gerondeau" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, shenglei.zhang@intel.com, Baptiste Gerondeau , Baptiste GERONDEAU Subject: [edk2-devel] [PATCH 1/3] ArmPkg/MdePkg : Unify INF files format Date: Wed, 18 Sep 2019 14:25:04 +0200 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,baptiste.gerondeau@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568809835; bh=ZXZVkrGY191nd7gm8QCNFx1O9fYwOrhi58576mLLKoY=; h=Cc:Date:From:Reply-To:Subject:To; b=hNYYxuV68dCCUP+0vYgz2hzHeJvQ0ccbgHHOBIVhWoTR3CsH3RJsaKT74mpmfu1jcIw 8Q6RrWTUWu78zluLFuRZq+GI8Uqp7rhSMAt6oOYDZ/8PYoakPA2mQlIr59UXmHw8o3ct9 rQpbNWsXrgRuzVseRq98SFVMbBVdnH+92lI= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Baptiste GERONDEAU Add a space between the '|' and the name of the toolchain to use, as is the case in all other INF files. Note that I did not touch the RVCT lines, since a following commit in the set will address those. Signed-off-by: Baptiste Gerondeau Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 +- MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index f4fecbb4098a..33dddf1e2b97 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -22,7 +22,7 @@ [Sources.AARCH64] =20 [Sources.ARM] Arm/ArmMmuLibCore.c - Arm/ArmMmuLibV7Support.S |GCC=20 + Arm/ArmMmuLibV7Support.S | GCC Arm/ArmMmuLibV7Support.asm |RVCT=20 =20 [Packages] diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M= dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf index e4e3d532e7b8..d38e1397eee1 100644 --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf @@ -79,11 +79,11 @@ [Defines.ARM, Defines.AARCH64] LIBRARY_CLASS =3D BaseMemoryLib|DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER U= EFI_DRIVER UEFI_APPLICATION =20 [Sources.ARM] - Arm/ScanMem.S |GCC - Arm/SetMem.S |GCC - Arm/CopyMem.S |GCC - Arm/CompareMem.S |GCC - Arm/CompareGuid.S |GCC + Arm/ScanMem.S | GCC + Arm/SetMem.S | GCC + Arm/CopyMem.S | GCC + Arm/CompareMem.S | GCC + Arm/CompareGuid.S | GCC =20 Arm/ScanMem.asm |RVCT Arm/SetMem.asm |RVCT --=20 2.23.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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[176.169.168.38]) by smtp.gmail.com with ESMTPSA id x2sm7573125wrn.81.2019.09.18.05.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 05:27:03 -0700 (PDT) From: "Baptiste Gerondeau" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, shenglei.zhang@intel.com, Baptiste Gerondeau , Baptiste GERONDEAU Subject: [edk2-devel] [PATCH 2/3] ARM/Assembler: Correct syntax from RVCT for MSFT Date: Wed, 18 Sep 2019 14:25:05 +0200 Message-Id: <0d024d72b50b7f5a6d3d908d309810f350c5b1f5.1568808805.git.baptiste.gerondeau@linaro.org> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,baptiste.gerondeau@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568809836; bh=81a18wWXHz/xbgqEQRjgrL33kRODe4WUUgmVG/99nNk=; h=Cc:Date:From:Reply-To:Subject:To; b=PHg07cert4AobKYnokP2oxWhxbLGgoVBKcvo7Ol1Gfm1Kz6mY8hl5n8Jg912aGQ2q11 APQ8Zk5q0NMsmisns0oMVfLAxZY2IBnhycSuQ+OdLe2o0PZmWGREI8Hib/keZDqWKnEG3 /KPWwTIuXItwfR9Uce/9Rn6uNQHS+Z9Z3LA= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Baptiste GERONDEAU RVCT and MSFT's ARM assembler share the same file syntax, but some instructions use pre-UAL syntax that is not picked up by MSFT's ARM assembler, this commit translates those instructions into MSFT-buildable ones (subset of UAL/THUMB). Signed-off-by: Baptiste Gerondeau Reviewed-by: Leif Lindholm --- ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm | 30 +++++++++++++= ++++------------- ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm | 6 ++++-- MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm | 18 +++++++++----= ----- 3 files changed, 30 insertions(+), 24 deletions(-) diff --git a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm b/ArmP= kg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm index aa0229d2e85f..880246bd6206 100644 --- a/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm +++ b/ArmPkg/Library/ArmExceptionLib/Arm/ExceptionSupport.asm @@ -90,7 +90,7 @@ Fiq ResetEntry srsfd #0x13! ; Store return state on SVC stack ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -102,7 +102,7 @@ UndefinedInstructionEntry sub LR, LR, #4 ; Only -2 for Thumb, adjust in Commo= nExceptionEntry srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -113,7 +113,7 @@ UndefinedInstructionEntry SoftwareInterruptEntry srsfd #0x13! ; Store return state on SVC stack ; We are already in SVC mode - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -125,7 +125,7 @@ PrefetchAbortEntry sub LR,LR,#4 srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -137,7 +137,7 @@ DataAbortEntry sub LR,LR,#8 srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -148,7 +148,7 @@ DataAbortEntry ReservedExceptionEntry srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -160,7 +160,7 @@ IrqEntry sub LR,LR,#4 srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state =20 @@ -172,7 +172,7 @@ FiqEntry sub LR,LR,#4 srsfd #0x13! ; Store return state on SVC stack cps #0x13 ; Switch to SVC for common stack - stmfd SP!,{LR} ; Store the link register for the cu= rrent mode + push {LR} ; Store the link register for the cu= rrent mode sub SP,SP,#0x20 ; Save space for SP, LR, PC, IFAR - = CPSR stmfd SP!,{R0-R12} ; Store the register state ; Since we have already switch to SV= C R8_fiq - R12_fiq @@ -213,9 +213,11 @@ AsmCommonExceptionEntry and R3, R1, #0x1f ; Check CPSR to see if User or System = Mode cmp R3, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D= =3D 0x1f)) cmpne R3, #0x10 ; - stmeqed R2, {lr}^ ; save unbanked lr + mrseq R8, lr_usr ; save unbanked lr to R8 + streq R2, [R8] ; make R2 point to R8 ; else - stmneed R2, {lr} ; save SVC lr + mrsne R8, lr_svc ; save SVC lr to R8 + strne R2, [R8] ; make R2 point to R8 =20 =20 ldr R5, [SP, #0x58] ; PC is the LR pushed by srsfd @@ -280,15 +282,17 @@ CommonCExceptionHandler ( and R1, R1, #0x1f ; Check to see if User or System Mode cmp R1, #0x1f ; if ((CPSR =3D=3D 0x10) || (CPSR =3D= =3D 0x1f)) cmpne R1, #0x10 ; - ldmeqed R2, {lr}^ ; restore unbanked lr + ldreq R8, [R2] ; load sys/usr lr from R2 pointer + msreq lr_usr, R8 ; restore unbanked lr ; else - ldmneed R3, {lr} ; restore SVC lr, via ldmfd SP!, {LR} + ldrne R8, [R3] ; load SVC lr from R3 pointer + msrne lr_svc, R8 ; restore SVC lr, via ldmfd SP!, {LR} =20 ldmfd SP!,{R0-R12} ; Restore general purpose registers ; Exception handler can not change SP =20 add SP,SP,#0x20 ; Clear out the remaining stack space - ldmfd SP!,{LR} ; restore the link register for this c= ontext + pop {LR} ; restore the link register for this c= ontext rfefd SP! ; return from exception via srsfd stac= k slot =20 END diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm b/ArmPkg/Library/Ar= mLib/Arm/ArmV7Support.asm index 3146c2b52181..724306399e6c 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm +++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.asm @@ -200,8 +200,10 @@ Loop2 mov R9, R4 ; R9 working copy of the max way size (rig= ht aligned) =20 Loop3 - orr R0, R10, R9, LSL R5 ; factor in the way number and cache numbe= r into R11 - orr R0, R0, R7, LSL R2 ; factor in the index number + lsl R8, R9, R5 + orr R0, R10, R8 ; factor in the way number and cache number + lsl R8, R7, R2 + orr R0, R0, R8 ; factor in the index number =20 blx R1 =20 diff --git a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm b/MdePkg= /Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm index 5a423df16bff..a46d70e41433 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm +++ b/MdePkg/Library/BaseIoLibIntrinsic/Arm/ArmVirtMmio.asm @@ -5,16 +5,16 @@ ; =20 =20 -AREA IoLibMmio, CODE, READONLY + AREA IoLibMmio, CODE, READONLY =20 -EXPORT MmioRead8Internal -EXPORT MmioWrite8Internal -EXPORT MmioRead16Internal -EXPORT MmioWrite16Internal -EXPORT MmioRead32Internal -EXPORT MmioWrite32Internal -EXPORT MmioRead64Internal -EXPORT MmioWrite64Internal + EXPORT MmioRead8Internal + EXPORT MmioWrite8Internal + EXPORT MmioRead16Internal + EXPORT MmioWrite16Internal + EXPORT MmioRead32Internal + EXPORT MmioWrite32Internal + EXPORT MmioRead64Internal + EXPORT MmioWrite64Internal =20 ; ; Reads an 8-bit MMIO register. --=20 2.23.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47480): https://edk2.groups.io/g/devel/message/47480 Mute This Topic: https://groups.io/mt/34187299/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- From nobody Sun May 5 22:49:41 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+47481+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47481+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1568809836; cv=none; d=zoho.com; s=zohoarc; b=gOnw5L4PYl8X/spRjz3m/b4PfFOzDd5GSOnpvTUIkQXDvgWGz9aGbaaJUHh+gWhzpc5TQsXkRvdVaUYR303MXWJb1w1vnYxjSDs6YHTTY1EO3QvRctKxgYhwez4bN4t4BDuGBRf2GRC8OZJuBwUtJBLdESn/OA/IDVmWSOtAiXU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1568809836; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=GNE7zsGSmzVW1pNbgbu5NVfo1GCVsDALMUNjeNI/SQo=; b=c1cr7bos3TJlbrHGrZv6hviqSwlv1MnH1Y2LEyYipFkPiREobgz+m0sCm14mahZ3W6kuRXXbieT76Q31axZWWC6ujpchMyWKNOZFuwsjnpEiBI+XUIVbmru4JaYm3U0i65GhR2ugCVZ4y0+UUVADb0M37zdQOUDlgLAMriy9NVE= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+47481+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1568809836729523.3766428099933; Wed, 18 Sep 2019 05:30:36 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 9DW8YY1788612xDeQOrvQFKU; Wed, 18 Sep 2019 05:30:36 -0700 X-Received: from mail-wr1-f66.google.com (mail-wr1-f66.google.com [209.85.221.66]) by groups.io with SMTP; Wed, 18 Sep 2019 05:27:07 -0700 X-Received: by mail-wr1-f66.google.com with SMTP id v8so6737742wrt.2 for ; Wed, 18 Sep 2019 05:27:06 -0700 (PDT) X-Gm-Message-State: 2mmla8uTqikUG7I1yOb8bPrKx1787277AA= X-Google-Smtp-Source: APXvYqzohJuxmYTt/RTpV3cyUpXOjAIIF12aFbKyqAEJzkR4+gaZQ67AMca0KVjPz0IPKNB8/48uIQ== X-Received: by 2002:a5d:4f11:: with SMTP id c17mr2872064wru.227.1568809625122; Wed, 18 Sep 2019 05:27:05 -0700 (PDT) X-Received: from localhost.localdomain (176-169-168-38.abo.bbox.fr. [176.169.168.38]) by smtp.gmail.com with ESMTPSA id x2sm7573125wrn.81.2019.09.18.05.27.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Sep 2019 05:27:04 -0700 (PDT) From: "Baptiste Gerondeau" To: devel@edk2.groups.io Cc: ard.biesheuvel@linaro.org, leif.lindholm@linaro.org, michael.d.kinney@intel.com, liming.gao@intel.com, shenglei.zhang@intel.com, Baptiste Gerondeau , Baptiste GERONDEAU Subject: [edk2-devel] [PATCH 3/3] ARM/Assembler: Reuse RVCT assembler for MSFT build Date: Wed, 18 Sep 2019 14:25:06 +0200 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,baptiste.gerondeau@linaro.org Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568809836; bh=CL+is9i+KJVFjw0ueFHV2G9tbFiaScXwyPf88ph4b4Q=; h=Cc:Date:From:Reply-To:Subject:To; b=TPya2cddv9sFXgZKS81Iet8xxXCp6ZbwdxxPPYkrsMZsb2WiLfFE5HDC1zl/2CTUY+n fhd4ZwY3slqc/bMHR5cGD65sHaSE0mqpywld/WBIfFX3CPAsW2BhZRY87VILRuPSuqwTU 4KNZPb0vFHdegxAE+mLrIcDs2eVfUivFRuQ= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" From: Baptiste GERONDEAU BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1750" Since RVCT shares the same assembler syntax as MSFT, use .asm files and associate them with MSFT, which would be a first step to addressing the above Bugzilla issue. RVCT will also have to be erased from BaseTools/rest of the build infrastructure, to fully address BZ#1750 ; this patch only addresses the "code" in itself. Signed-off-by: Baptiste Gerondeau Reviewed-by: Leif Lindholm --- ArmPkg/Drivers/ArmGic/ArmGicLib.inf | 2 = +- ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf | 2 = +- ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf | 2 = +- ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf | 2 = +- ArmPkg/Library/ArmLib/ArmBaseLib.inf | 8 = ++++---- ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf | 2 = +- ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf | 2 = +- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 2 = +- ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf | 2 = +- ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf | 2 = +- ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf | 2 = +- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf | 6 = +++--- ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf | 6 = +++--- ArmPlatformPkg/PrePi/PeiMPCore.inf | 2 = +- ArmPlatformPkg/PrePi/PeiUniCore.inf | 2 = +- MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf | 2 = +- MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf | 10 = +++++----- MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf | 2 = +- 18 files changed, 29 insertions(+), 29 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf b/ArmPkg/Drivers/ArmGic/Ar= mGicLib.inf index 5e23c732bfab..4fccb938eb6d 100644 --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.inf +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.inf @@ -22,7 +22,7 @@ [Sources] =20 [Sources.ARM] GicV3/Arm/ArmGicV3.S | GCC - GicV3/Arm/ArmGicV3.asm | RVCT + GicV3/Arm/ArmGicV3.asm | MSFT =20 [Sources.AARCH64] GicV3/AArch64/ArmGicV3.S diff --git a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf b/ArmPkg/Li= brary/ArmExceptionLib/ArmExceptionLib.inf index fdb9c24d21bc..58b2ddbff858 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf +++ b/ArmPkg/Library/ArmExceptionLib/ArmExceptionLib.inf @@ -33,7 +33,7 @@ [Sources.common] =20 [Sources.Arm] Arm/ArmException.c - Arm/ExceptionSupport.asm | RVCT + Arm/ExceptionSupport.asm | MSFT Arm/ExceptionSupport.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf b/A= rmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf index ef1a43a27c45..a404ca2ccf82 100644 --- a/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf +++ b/ArmPkg/Library/ArmExceptionLib/ArmRelocateExceptionLib.inf @@ -28,7 +28,7 @@ [Sources.common] =20 [Sources.Arm] Arm/ArmException.c - Arm/ExceptionSupport.asm | RVCT + Arm/ExceptionSupport.asm | MSFT Arm/ExceptionSupport.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf b/ArmPkg/Library/ArmHvc= Lib/ArmHvcLib.inf index 69f68f63d7a6..be8d8a228865 100644 --- a/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf +++ b/ArmPkg/Library/ArmHvcLib/ArmHvcLib.inf @@ -15,7 +15,7 @@ [Defines] LIBRARY_CLASS =3D ArmHvcLib =20 [Sources.ARM] - Arm/ArmHvc.asm | RVCT + Arm/ArmHvc.asm | MSFT Arm/ArmHvc.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmLib/ArmBaseLib.inf b/ArmPkg/Library/ArmLib/A= rmBaseLib.inf index 5e70990872f2..63e175623393 100644 --- a/ArmPkg/Library/ArmLib/ArmBaseLib.inf +++ b/ArmPkg/Library/ArmLib/ArmBaseLib.inf @@ -30,10 +30,10 @@ [Sources.ARM] Arm/ArmV7Support.S | GCC Arm/ArmV7ArchTimerSupport.S | GCC =20 - Arm/ArmLibSupport.asm | RVCT - Arm/ArmLibSupportV7.asm | RVCT - Arm/ArmV7Support.asm | RVCT - Arm/ArmV7ArchTimerSupport.asm | RVCT + Arm/ArmLibSupport.asm | MSFT + Arm/ArmLibSupportV7.asm | MSFT + Arm/ArmV7Support.asm | MSFT + Arm/ArmV7ArchTimerSupport.asm | MSFT =20 [Sources.AARCH64] AArch64/AArch64Lib.h diff --git a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf b/ArmPkg/Library/Ar= mMmuLib/ArmMmuBaseLib.inf index 33dddf1e2b97..44366f02c6d9 100644 --- a/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf +++ b/ArmPkg/Library/ArmMmuLib/ArmMmuBaseLib.inf @@ -23,7 +23,7 @@ [Sources.AARCH64] [Sources.ARM] Arm/ArmMmuLibCore.c Arm/ArmMmuLibV7Support.S | GCC - Arm/ArmMmuLibV7Support.asm |RVCT=20 + Arm/ArmMmuLibV7Support.asm | MSFT =20 [Packages] ArmPkg/ArmPkg.dec diff --git a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf b/ArmPkg/Library/ArmSmc= Lib/ArmSmcLib.inf index 4f4b09f4528a..af8c0e53cc2b 100644 --- a/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf +++ b/ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf @@ -14,7 +14,7 @@ [Defines] LIBRARY_CLASS =3D ArmSmcLib =20 [Sources.ARM] - Arm/ArmSmc.asm | RVCT + Arm/ArmSmc.asm | MSFT Arm/ArmSmc.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemL= ib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.i= nf index fa19bf649131..f4c9e5510b9a 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -21,7 +21,7 @@ [Sources.AARCH64] =20 [Sources.ARM] Arm/Reset.S | GCC - Arm/Reset.asm | RVCT + Arm/Reset.asm | MSFT =20 [Sources] ArmSmcPsciResetSystemLib.c diff --git a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf b/ArmPkg/Library/ArmSvc= Lib/ArmSvcLib.inf index 744a29fbf723..6631e40df130 100644 --- a/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf +++ b/ArmPkg/Library/ArmSvcLib/ArmSvcLib.inf @@ -14,7 +14,7 @@ [Defines] LIBRARY_CLASS =3D ArmSvcLib =20 [Sources.ARM] - Arm/ArmSvc.asm | RVCT + Arm/ArmSvc.asm | MSFT Arm/ArmSvc.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.i= nf b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf index e0d0028d8224..cc791a3a68fd 100644 --- a/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf +++ b/ArmPlatformPkg/Library/ArmPlatformLibNull/ArmPlatformLibNull.inf @@ -29,7 +29,7 @@ [Sources.common] =20 [Sources.Arm] Arm/ArmPlatformHelper.S | GCC - Arm/ArmPlatformHelper.asm | RVCT + Arm/ArmPlatformHelper.asm | MSFT =20 [Sources.AArch64] AArch64/ArmPlatformHelper.S diff --git a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib= .inf b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf index 76f809c80d9f..e88330c1c382 100644 --- a/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf +++ b/ArmPlatformPkg/Library/ArmPlatformStackLib/ArmPlatformStackLib.inf @@ -21,7 +21,7 @@ [Packages] ArmPlatformPkg/ArmPlatformPkg.dec =20 [Sources.ARM] - Arm/ArmPlatformStackLib.asm | RVCT + Arm/ArmPlatformStackLib.asm | MSFT Arm/ArmPlatformStackLib.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf b/ArmPlatformPk= g/PrePeiCore/PrePeiCoreMPCore.inf index f2ac45d171bc..b663ff749182 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf @@ -21,11 +21,11 @@ [Sources.common] =20 [Sources.ARM] Arm/ArchPrePeiCore.c - Arm/PrePeiCoreEntryPoint.asm | RVCT + Arm/PrePeiCoreEntryPoint.asm | MSFT Arm/PrePeiCoreEntryPoint.S | GCC - Arm/SwitchStack.asm | RVCT + Arm/SwitchStack.asm | MSFT Arm/SwitchStack.S | GCC - Arm/Exception.asm | RVCT + Arm/Exception.asm | MSFT Arm/Exception.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf b/ArmPlatformP= kg/PrePeiCore/PrePeiCoreUniCore.inf index 84c319c3679b..6d05ed096c4c 100644 --- a/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf +++ b/ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf @@ -21,11 +21,11 @@ [Sources.common] =20 [Sources.ARM] Arm/ArchPrePeiCore.c - Arm/PrePeiCoreEntryPoint.asm | RVCT + Arm/PrePeiCoreEntryPoint.asm | MSFT Arm/PrePeiCoreEntryPoint.S | GCC - Arm/SwitchStack.asm | RVCT + Arm/SwitchStack.asm | MSFT Arm/SwitchStack.S | GCC - Arm/Exception.asm | RVCT + Arm/Exception.asm | MSFT Arm/Exception.S | GCC =20 [Sources.AARCH64] diff --git a/ArmPlatformPkg/PrePi/PeiMPCore.inf b/ArmPlatformPkg/PrePi/PeiM= PCore.inf index 9c5da0d42a7b..fd2a35e59591 100644 --- a/ArmPlatformPkg/PrePi/PeiMPCore.inf +++ b/ArmPlatformPkg/PrePi/PeiMPCore.inf @@ -22,7 +22,7 @@ [Sources] [Sources.ARM] Arm/ArchPrePi.c Arm/ModuleEntryPoint.S | GCC - Arm/ModuleEntryPoint.asm | RVCT + Arm/ModuleEntryPoint.asm | MSFT =20 [Sources.AArch64] AArch64/ArchPrePi.c diff --git a/ArmPlatformPkg/PrePi/PeiUniCore.inf b/ArmPlatformPkg/PrePi/Pei= UniCore.inf index ee9b05b25337..de3abadfeac6 100644 --- a/ArmPlatformPkg/PrePi/PeiUniCore.inf +++ b/ArmPlatformPkg/PrePi/PeiUniCore.inf @@ -22,7 +22,7 @@ [Sources] [Sources.ARM] Arm/ArchPrePi.c Arm/ModuleEntryPoint.S | GCC - Arm/ModuleEntryPoint.asm | RVCT + Arm/ModuleEntryPoint.asm | MSFT =20 [Sources.AArch64] AArch64/ArchPrePi.c diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.in= f b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf index ad68f841fb6b..62b46377116c 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsicArmVirt.inf @@ -31,7 +31,7 @@ [Sources] [Sources.ARM] IoLibArmVirt.c Arm/ArmVirtMmio.S | GCC - Arm/ArmVirtMmio.asm | RVCT + Arm/ArmVirtMmio.asm | MSFT =20 [Sources.AARCH64] IoLibArmVirt.c diff --git a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf b/M= dePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf index d38e1397eee1..79ba2a2dfc39 100644 --- a/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf +++ b/MdePkg/Library/BaseMemoryLibOptDxe/BaseMemoryLibOptDxe.inf @@ -85,11 +85,11 @@ [Sources.ARM] Arm/CompareMem.S | GCC Arm/CompareGuid.S | GCC =20 - Arm/ScanMem.asm |RVCT - Arm/SetMem.asm |RVCT - Arm/CopyMem.asm |RVCT - Arm/CompareMem.asm |RVCT - Arm/CompareGuid.asm |RVCT + Arm/ScanMem.asm | MSFT + Arm/SetMem.asm | MSFT + Arm/CopyMem.asm | MSFT + Arm/CompareMem.asm | MSFT + Arm/CompareGuid.asm | MSFT =20 [Sources.AARCH64] AArch64/ScanMem.S diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 446bc19b63eb..39c503a28a2c 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -70,7 +70,7 @@ [Sources.EBC] =20 [Sources.ARM] Synchronization.c - Arm/Synchronization.asm | RVCT + Arm/Synchronization.asm | MSFT Arm/Synchronization.S | GCC =20 [Sources.AARCH64] --=20 2.23.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#47481): https://edk2.groups.io/g/devel/message/47481 Mute This Topic: https://groups.io/mt/34187300/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-