From nobody Mon Feb 9 07:57:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+98399+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98399+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1673567816; cv=none; d=zohomail.com; s=zohoarc; b=QzAAZhol2GG68BLSpdOIQl+clbmidFLEDwaqQgSV50kTfTHyK31R3ptssw3yg2INYDIyeDyPpwSxbMuxK5PhAC8C0VzFBloI6xGQWQuQeozkRfbcN6MGmpP2glVutcVckB6owp5m5z+sFKHzL1o5VeLbR4n35OvugNZ5zYc0GLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1673567816; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Q4tcAeYYqbutQZ78BTKzPF3fur9BCInq6cipSFUsskk=; b=ZpazJQtNrmgEgXpsagQaw1ytuq8O5coizPvf9AQ5QchvBKIPIKXs/l8VQcJPSEkHR5G1CJBfwXZ6k756+drbmjjHlwHoNB858fY/WDh0KA1qm9dU88o9sQVMObvXIDLRlw667IarfROdf1EQPZyRDV8RbbyUOs66S/6BElKlH/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+98399+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1673567816883234.6469865650206; Thu, 12 Jan 2023 15:56:56 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id rgzUYY1788612x4VY6ZPLsy3; Thu, 12 Jan 2023 15:56:56 -0800 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.73051.1673567815893727645 for ; Thu, 12 Jan 2023 15:56:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="410100303" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="410100303" X-Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:55 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10588"; a="607972202" X-IronPort-AV: E=Sophos;i="5.97,212,1669104000"; d="scan'208";a="607972202" X-Received: from iworam-desk.amr.corp.intel.com ([10.24.80.243]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Jan 2023 15:56:54 -0800 From: "Isaac Oram" To: devel@edk2.groups.io Cc: Isaac Oram , Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 1/2] WhitleySiliconPkg: Update to Whitley FSP 4.2.0.2A Date: Thu, 12 Jan 2023 15:56:34 -0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: fYYlqTsgqopBK5jNXDegimYpx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1673567816; bh=pxWLFwnc51QZ3VE04BxH5Av5cu2iC3yYFQ+Hn9twz2A=; h=Cc:Date:From:Reply-To:Subject:To; b=jYBEnP/biOgkBGeLIcKlqFnpjNiZPn8wCaZkJf7eSfa5zT9mEkO0IMxzarx9XMEZsnl 1dq4vmsvsbqj9Ro5HcQZ0fKEZGAsUuXafGyECga5jQdWTebQWWV2x2910g2orJjYVFbvf XPgHGuJJMlfIaG539Y5qao+HIFQHdfoPnBU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1673567817790100001 Content-Type: text/plain; charset="utf-8" This contains binary interface changes and requires FSP 4.2.0.2A or later Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 23 +++++++++------- .../Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 4 ++- .../Cpu/Include/CpuPolicyPeiDxeCommon.h | 2 +- .../WhitleySiliconPkg/Include/BdatSchema.h | 16 +++++++----- .../Include/Guid/MemoryMapData.h | 4 ++- .../Include/Guid/SocketIioVariable.h | 13 +++++++--- .../Include/Guid/SocketMemoryVariable.h | 3 +++ .../Include/Guid/SocketPciResourceData.h | 4 ++- .../Guid/SocketPowermanagementVariable.h | 2 ++ .../Guid/SocketProcessorCoreVariable.h | 2 +- .../WhitleySiliconPkg/Include/IioConfig.h | 11 +++----- .../Intel/WhitleySiliconPkg/Include/IioRegs.h | 1 - .../Include/Library/EnhancedWarningLogLib.h | 2 -- .../Include/PlatformInfoTypes.h | 16 +++++++----- .../Include/Ppi/MemoryPolicyPpi.h | 10 +++++++ .../Include/Ppi/RasImcS3Data.h | 6 ----- .../WhitleySiliconPkg/Include/Upi/KtiHost.h | 2 -- .../Core/Include/DataTypes.h | 10 ++++++- .../BaseMemoryCoreLib/Core/Include/MemHost.h | 6 +---- .../BaseMemoryCoreLib/Platform/PlatformHost.h | 5 ---- .../Include/Private/Library/PchSpiCommonLib.h | 1 - .../Product/Whitley/SiliconPkg10nmPcds.dsc | 5 ++++ .../SecurityIp/SecurityIpSgxTem1v0_Inputs.h | 2 +- .../SecurityIp/SecurityIpSgxTem1v0_Outputs.h | 2 +- .../Intel/WhitleySiliconPkg/SiliconPkg.dec | 26 ++++++++++++------- 25 files changed, 106 insertions(+), 72 deletions(-) diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/Wh= itleySiliconPkg/CpRcPkg.dec index 2ccdbffa35..db61caf399 100644 --- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -252,9 +252,9 @@ WhitleySiliconPkg/CpRcPkg.dec } gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0 - gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|4 gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2 - gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x002A =20 # # MRC DEFAULT SETTINGS @@ -273,7 +273,7 @@ # gEfiCpRcPkgTokenSpaceGuid.PcdEnforcePorDefault | = 0| UINT8|0x00000040 =20 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | FALSE= |BOOLEAN|0x0000003A + gEfiCpRcPkgTokenSpaceGuid.PcdReserved8 | = FALSE|BOOLEAN|0x0000003A =20 =20 gEfiCpRcPkgTokenSpaceGuid.PcdMrcMultiThreadedDefault | = FALSE|BOOLEAN|0x00000060 @@ -285,7 +285,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdMrcTxRfSlewRateDefault | = 0x2| UINT8|0x00000066 gEfiCpRcPkgTokenSpaceGuid.PcdMrcPmemMemHoleDefault | = FALSE|BOOLEAN|0x00000067 gEfiCpRcPkgTokenSpaceGuid.PcdMrcCrQosConfigDefault | = 0x6| UINT8|0x00000068 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | TRUE|BOO= LEAN|0x00000069 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved9 | = TRUE|BOOLEAN|0x00000069 gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault | = TRUE| UINT8|0x0000006A =20 =20 @@ -293,10 +293,10 @@ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthConfigString |L"MemBootHea= lthConfig"| VOID*|0x00000070 gEfiCpRcPkgTokenSpaceGuid.PcdMrcSpdPrintDefault | = FALSE|BOOLEAN|0x00000071 gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault | = FALSE|BOOLEAN|0x00000072 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 - gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | 2= | UINT8|0x0000011F - gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | TRUE= |BOOLEAN|0x00000120 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved10 | = 1| UINT8|0x00000073 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved11 | = 1| UINT8|0x00000074 + gEfiCpRcPkgTokenSpaceGuid.PcdReserved12 | = 2| UINT8|0x0000011F + gEfiCpRcPkgTokenSpaceGuid.PcdReserved13 | = TRUE|BOOLEAN|0x00000120 gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmiInitUseResetDefault | = FALSE|BOOLEAN|0x00000075 #option to choose Mem Boot Health configuration type. 00=3D>Auto (Use de= faults), 01=3D>Manual (Override defaults with setup option), 02=3D>Disable = (Disable feature) gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthCheck | = 00| UINT8|0x00000076 @@ -360,6 +360,11 @@ # Ctl timing: CtlAll gEfiCpRcPkgTokenSpaceGuid.PcdRmtMinimumCtlTimingMargin | = 5| UINT8|0x00000131 =20 + #MC VC0 Deadlock Breaker + gEfiCpRcPkgTokenSpaceGuid.PcdKeepStarveSettings | = TRUE| BOOLEAN|0x00000132 + gEfiCpRcPkgTokenSpaceGuid.PcdStarveTimer | = 18| UINT8|0x00000133 + gEfiCpRcPkgTokenSpaceGuid.PcdStarveThreshold | = 4| UINT8|0x00000134 + #Reset on Critical Margin failure to perform Memory Training from scratch gEfiCpRcPkgTokenSpaceGuid.PcdResetOnCriticalError | = 1| UINT8|0x00000087 =20 @@ -526,7 +531,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdDisableSimSlaveThread|FALSE|BOOLEAN|0x00000= 036 gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmJedecDumpStatusRegs|FALSE|BOOLEAN|0x0= 0000118 ## This PCD specifies the OEM MTS of the Memory Module Thermal Sensor - gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C + gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xC|UINT16|0x0000003C gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D =20 [PcdsDynamicEx] diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Int= el/WhitleySiliconPkg/Cpu/CpuRcPkg.dec index 7b027b58c6..763b9d31e4 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec @@ -91,7 +91,9 @@ # @Prompt CPU Config Register Table Entry Maximum Count. gCpuPkgTokenSpaceGuid.PcdCpuConfigRegTblEntryMaxCount|0x64|UINT16|0x6000= 0022 =20 -[PcdsDynamic, PcdsDynamicEx] + gCpuPkgTokenSpaceGuid.PcdCpuLowestApicIdAsBsp|TRUE|BOOLEAN|0x60000023 + +[PcdsDynamicEx] gCpuPkgTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0|UINT64|0x50000001 =20 gCpuPkgTokenSpaceGuid.PcdPlatformCpuSocketCount|0x0|UINT32|0x60000012 diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCom= mon.h b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h index 6e84e0f7a6..dc5e09ea19 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/Include/CpuPolicyPeiDxeCommon.h @@ -52,7 +52,7 @@ typedef struct { UINT8 CpuMtoIWa; BOOLEAN RunCpuPpmInPei; BOOLEAN AcExceptionOnSplitLockEnable; - BOOLEAN CpuCrashLogGprs; + BOOLEAN CpuCrashDataGprs; } CPU_POLICY_COMMON; =20 #endif diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h b/Silicon= /Intel/WhitleySiliconPkg/Include/BdatSchema.h index 0b80015c65..010e8183af 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/BdatSchema.h @@ -131,12 +131,16 @@ typedef struct { // List of all entry types supported by this revision of memory training d= ata structure // typedef enum { - MemTrainingDataCapability =3D 0, - MemTrainingDataIoGroup =3D 1, - MemTrainingDataDram =3D 2, - MemTrainingDataRcd =3D 3, - MemTrainingDataIoSignal =3D 4, - MemTrainingDataIoLatency =3D 5, + MemTrainingDataCapability =3D 0, + MemTrainingDataIoGroup =3D 1, + MemTrainingDataDram =3D 2, + MemTrainingDataRcd =3D 3, + MemTrainingDataIoSignal =3D 4, + MemTrainingDataIoLatency =3D 5, + MemTrainingDataPpin =3D 6, + MemTrainingDataBoardUuid =3D 7, + MemTrainingDataTurnaround =3D 8, + MemTrainingDataDcPmmTurnaround =3D 9, =20 MemTrainingDataTypeMax, MemTrainingDataTypeDelim =3D MAX_INT32 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h b= /Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h index 73f303594a..f7a14ff5f4 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/MemoryMapData.h @@ -85,7 +85,9 @@ struct ChannelDevice { UINT8 SpareLogicalRank[MAX_SPARE_RANK]; = // Logical rank, selected as Spare UINT8 SparePhysicalRank[MAX_SPARE_RANK]; = // Physical rank, selected as spare UINT16 SpareRankSize[MAX_SPARE_RANK]; = // spare rank size - UINT8 EnabledLogicalRanks; // Bitmap of Lo= gical ranks that are enabled + UINT8 EnabledLogicalRanks; = // Bitmap of Logical ranks that are enabled + UINT8 DdrPopulationMap; = // Bitmap to indicate location of DDR DIMMs within the channel memory slots= (BIT0: Ch.D0, BIT1: CH.D1) + UINT8 PmemPopulationMap; = // Bitmap to indicate location of PMem modules within the channel memory sl= ots (BIT0: Ch.D0, BIT1: CH.D1) MEMMAP_DIMM_DEVICE_INFO_STRUCT DimmInfo[MAX_DIMM]; }; =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable= .h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h index a820cc6c25..0fafd00c98 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h @@ -133,8 +133,8 @@ typedef struct { UINT8 PcieSubSystemMode[TOTAL_IOU_VAR]; UINT8 CompletionTimeoutGlobal; UINT8 CompletionTimeoutGlobalValue; - UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup - UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 ReservedCto[MAX_SOCKET]; // On Setup + UINT8 ReservedCtov[MAX_SOCKET]; // On Setup UINT8 CoherentReadPart; UINT8 CoherentReadFull; UINT8 PcieGlobalAspm; @@ -372,7 +372,7 @@ typedef struct { UINT8 ReservedS19; // On Setup UINT8 ReservedS20; // On Setup UINT32 ReservedS21[MAX_DEVHIDE_REGS_PER_SYSTEM]; // On Setup - UINT8 ReservedS22[TOTAL_PORTS_VAR]; // On Setup + UINT8 CompletionTimeoutValue[TOTAL_PORTS_VAR]; // On = Setup =20 UINT8 ReservedS23[TOTAL_PORTS_VAR]; //On Setup UINT8 ReservedS24[TOTAL_PORTS_VAR]; //On Setup @@ -437,7 +437,12 @@ typedef struct { UINT8 VtdPciAcsCtlBit2; UINT8 VtdPciAcsCtlBit3; UINT8 VtdPciAcsCtlBit4; - UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup + UINT8 AltAttenTable[TOTAL_PORTS_VAR]; + UINT8 PciePort10bitTag[TOTAL_PORTS_VAR]; // Controls port support for= 10-bit Tag + + UINT8 MaskPcieRpWarmResetMcaWa; //on Setup + UINT8 PostedInterruptThrottle; + } SOCKET_IIO_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVaria= ble.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h index 533489fafc..f8710ee7bb 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketMemoryVariable.h @@ -469,6 +469,9 @@ typedef struct { UINT8 RmtMinimumMarginCheck; =20 UINT8 ReservedS149; + UINT8 pTRR; + UINT8 AdrPatrolScrubDisable; + } SOCKET_MEMORY_CONFIGURATION; =20 #pragma pack() diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResource= Data.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData= .h index 567a44e73f..439f61c88d 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPciResourceData.h @@ -41,11 +41,13 @@ typedef struct { // If anything changed reset the system PCI resource configuration. // UINT64 MmioHBase; - UINT64 MmioHLimit; + UINT64 MmioHGranularity; UINT32 MmioLBase; UINT32 MmioLLimit; + UINT32 MmioLGranularity; UINT16 IoBase; UINT16 IoLimit; + UINT16 IoGranularity; UINT16 StackPresentBitmap[MAX_SOCKET]; // // Used by the PciHostBridge DXE driver, these variables don't need to b= e exposed through setup options diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanage= mentVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowerma= nagementVariable.h index 460e6e300b..c29bf51cb6 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVar= iable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketPowermanagementVar= iable.h @@ -290,6 +290,8 @@ typedef struct { UINT8 RunCpuPpmInPei; =20 UINT8 UncoreFreqRaplLimit; + + UINT8 PrgTjOffsetEn; } SOCKET_POWERMANAGEMENT_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCo= reVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessor= CoreVariable.h index 52ab370ce7..ca4ebd4d4a 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVaria= ble.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketProcessorCoreVaria= ble.h @@ -136,7 +136,7 @@ typedef struct { UINT8 CFRS3mManualCommit; UINT8 CFRPucodeEnable; UINT8 CFRPucodeManualCommit; - UINT8 CpuCrashLogGprs; + UINT8 CpuCrashDataGprs; } SOCKET_PROCESSORCORE_CONFIGURATION; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/= Intel/WhitleySiliconPkg/Include/IioConfig.h index a8e3e69255..385db192d2 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h @@ -45,6 +45,7 @@ typedef struct { UINT8 PcieAspm[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; // On Setup UINT8 PcieTxRxDetPoll[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; UINT8 PciePortLinkSpeed[MAX_TOTAL_PORTS]; + UINT8 PciePort10bitTag[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; UINT8 PciePtm; UINT8 PcieHotPlugEnable; UINT8 PCIe_LTR; @@ -104,8 +105,7 @@ typedef struct { =20 UINT8 CompletionTimeoutGlobal; UINT8 CompletionTimeoutGlobalValue; - UINT8 CompletionTimeout[MAX_SOCKET]; // On Setup - UINT8 CompletionTimeoutValue[MAX_SOCKET]; // On Setup + UINT8 CompletionTimeoutValue[MAX_SOCKET][NUMBER_PORTS_PER_SOCKET]; /= / On Setup UINT8 CoherentReadPart; UINT8 CoherentReadFull; UINT8 PcieGlobalAspm; @@ -124,7 +124,6 @@ typedef struct { UINT8 PcieLinkDis[MAX_TOTAL_PORTS]; // On Setup UINT8 PcieCommonClock[MAX_TOTAL_PORTS]; // On Setup UINT8 PcieDState[MAX_TOTAL_PORTS]; // On Setup - UINT8 PcieL0sLatency[MAX_TOTAL_PORTS]; //On Setup UINT8 PcieL1Latency[MAX_TOTAL_PORTS]; //On Setup UINT8 MsiEn[MAX_TOTAL_PORTS]; // On Setup UINT8 IODC[MAX_TOTAL_PORTS]; // On Setup @@ -273,6 +272,7 @@ typedef struct { UINT8 ProblematicPort; //on Setup UINT8 DmiAllocatingFlow; //on Setup UINT8 PcieAllocatingFlow; //on Setup + UINT8 MaskPcieRpWarmResetMcaWa; //on Setup UINT8 PcieAcpiHotPlugEnable; //on Setup BOOLEAN PcieLowLatencyRetimersEnabled; UINT8 HaltOnDmiDegraded; //on Setup @@ -335,13 +335,10 @@ typedef struct { UINT32 ReservedAC[MAX_SOCKET][NUM_DEVHIDE_UNCORE_STACKS][NUM_DEVHIDE_RE= GS_PER_STACK]; UINT32 ReservedAD[MAX_SOCKET][NUM_DEVHIDE_IIO_STACKS][NUM_DEVHIDE_REGS_= PER_STACK]; =20 - UINT8 ReservedAE[MAX_TOTAL_PORTS]; // On Setup - UINT8 ReservedAF[MAX_TOTAL_PORTS]; UINT8 ReservedAG[MAX_TOTAL_PORTS]; // On Setup BOOLEAN ReservedAH; // On Setup =20 - /** =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D IIO = Global Performance Tuner Related Setup Options =3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D @@ -374,7 +371,6 @@ typedef struct { UINT8 MSINFATEN[MAX_TOTAL_PORTS]; UINT8 MSICOREN[MAX_TOTAL_PORTS]; UINT8 ACPIPMEn[MAX_TOTAL_PORTS]; - UINT8 DISL0STx[MAX_TOTAL_PORTS]; UINT8 P2PRdDis[MAX_TOTAL_PORTS]; UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; UINT8 ACPIHP[MAX_TOTAL_PORTS]; @@ -393,6 +389,7 @@ typedef struct { IIO_PCIE_CONFIG_DATA IioPcieConfig; =20 UINT32 VtdDisabledBitmask[MAX_SOCKET]; + UINT8 PostedInterruptThrottle; } IIO_CONFIG; #pragma pack() =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h b/Silicon/In= tel/WhitleySiliconPkg/Include/IioRegs.h index 37a1e627da..66cb1e3dfc 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioRegs.h @@ -128,7 +128,6 @@ #define PCIE_PORT_0_FUNC_0 0x00 =20 #define PCIE_PORT_1A_DEV_1 0x02 -#define PCIE_PORT_1A_FUNC_1 0x00 #define PCIE_PORT_1B_DEV_1 0x03 #define PCIE_PORT_1C_DEV_1 0x04 #define PCIE_PORT_1D_DEV_1 0x05 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarnin= gLogLib.h b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarning= LogLib.h index 211dc48c86..745a52dafe 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib= .h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Library/EnhancedWarningLogLib= .h @@ -191,9 +191,7 @@ typedef struct { UINT32 EccS; UINT32 Chunk; UINT32 Column; - UINT32 ColumnExt; UINT32 Row; - UINT32 RowExt; UINT32 Bank; UINT32 Rank; UINT32 Subrank; diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index 8fc0efec24..0c14a2409f 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -41,10 +41,10 @@ typedef enum { TypeWilsonCityModular, TypeCoyotePass, TypeIdaville, - TypeMoroCityRP, - TypeBrightonCityRp, + TypeMoroCityRP =3D 0x0E, //maps to PcdDefaultBoardId + TypeBrightonCityRp =3D 0x0F, //maps to PcdDefaultBoardId value TypeJacobsville, - TypeSnrSvp, + TypeSnrSvp =3D 0x11, //maps to PcdDefaultBoardId TypeSnrSvpSodimm, TypeJacobsvilleMDV, TypeFrostCreekRP, @@ -64,13 +64,15 @@ typedef enum { TypeArcherCityXPV, TypeBigPineKey, TypeExperWorkStationRP, - TypeJunctionCity, - TypeAowanda, + TypeAmericanPass, EndOfEfiPlatformTypeEnum, // // Vendor board range currently starts at 0x80 // - TypeBoardPortTemplate // 0x80 + TypeBoardPortTemplate, // 0x80 + TypeJunctionCity, + TypeAowanda, + EndOfVendorPlatformTypeEnum } EFI_PLATFORM_TYPE; =20 #define TypePlatformUnknown 0xFF @@ -78,7 +80,7 @@ typedef enum { #define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 #define TypePlatformDefault TypeWilsonPointRP #define TypePlatformVendorMin 0x80 -#define TypePlatformVendorMax TypeBoardPortTemplate - 1 +#define TypePlatformVendorMax EndOfVendorPlatformTypeEnum - 1 =20 // // CPU type: Standard (no MCP), -F, etc diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h = b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h index 38b90713f7..7a86804d9b 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/MemoryPolicyPpi.h @@ -1905,6 +1905,7 @@ struct memSetup { /// 1 =3D High
/// 2 =3D Low
UINT8 PanicWm; + UINT8 pTRR; =20 /// @brief /// Enable/Disable LRDIMM DB DFE.
@@ -1923,6 +1924,15 @@ struct memSetup { // UINT8 VirtualNumaEnable; =20 + /// + /// @brief + /// Enable/Disable patrol scrub when entering the ADR.
+ /// @details + /// 0 - disable.
+ /// 1 - enable.
+ // + UINT8 AdrPatrolScrubDisable; + /// /// @brief /// Smart Test Key pattern.
diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h b/S= ilicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h index 2198f8516a..82725bc84e 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Ppi/RasImcS3Data.h @@ -44,13 +44,7 @@ EFI_STATUS OUT VOID *Data ); =20 -/** - RAS IMC S3 Data PPI -**/ struct _RAS_IMC_S3_DATA_PPI { - /** - Retrieves data for S3 saved memory RAS features from non-volatile stor= age. - **/ RAS_IMC_S3_DATA_PPI_GET_IMC_S3_RAS_DATA GetImcS3RasData; }; =20 diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h b/Silico= n/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h index 09a3f37edf..5cadda4907 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Upi/KtiHost.h @@ -300,12 +300,10 @@ typedef struct { =20 Contains a pointer to a 24 byte fixed length array. The array contains the 3 instances of the following c-struct - ~~~ typedef struct { UINT32 CfrImagePtr; UINT32 CfrImageSize; } - ~~~ This allows a maximum of 3 CFR/SINIT binaries to be provided by platfo= rm code. **/ UINT32 CFRImagePtr; diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/DataTypes.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCo= reLib/Core/Include/DataTypes.h index eb4bd92a1d..ef1775e1ed 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/DataTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/DataTypes.h @@ -12,11 +12,17 @@ =20 #include =20 +/// +/// 8-byte DWORD addressable unsigned value. +/// typedef struct u64_struct { UINT32 lo; UINT32 hi; } UINT64_STRUCT, *PUINT64_STRUCT; =20 +/// +/// 8-byte DWORD addressable unsigned value. +/// typedef union { struct { UINT32 Low; @@ -25,7 +31,9 @@ typedef union { UINT64 Data; } UINT64_DATA; =20 - +/// +/// 16-byte DWORD addressable unsigned value. +/// typedef struct u128_struct { UINT32 one; UINT32 two; diff --git a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core= /Include/MemHost.h b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCore= Lib/Core/Include/MemHost.h index 8eaea40f72..3ae5bcb612 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemHost.h +++ b/Silicon/Intel/WhitleySiliconPkg/Library/BaseMemoryCoreLib/Core/Includ= e/MemHost.h @@ -641,11 +641,9 @@ struct rankDevice { /// typedef struct dimmDevice { INT32 minTCK; ///< minimum tCK for this DIMM (SPD_MIN_= TCK) -#ifdef DEBUG_CODE_BLOCK UINT32 tCL; UINT16 tRCD; UINT16 tRP; -#endif // DEBUG_CODE_BLOCK UINT16 NVmemSize; UINT16 memSize; ///< Memory size for this DIMM (64MB gra= nularity) UINT16 UnmappedMemSize; @@ -653,6 +651,7 @@ typedef struct dimmDevice { struct FmcCacheSt FmcCache[MAX_FMC_CACHE]; ///< FMC cache info/status UINT8 SPDPartitionRatio[MAX_SOCKET * MAX_IMC]; ///< NVM DI= MM partitionRatios UINT8 CachedLrBuf_DFECoef[MAX_BITS_IN_BYTE][DB_DFE_TAP][MA= X_STROBE/2]; // JEDEC F3BCCx-Fx coeffcient. 8 DQ x 4 taps x 9 DB + BOOLEAN TrainingModeEnabled; //Training Mode for BPS BOOLEAN FmcWdbFlushFailed; /// < 0 =3D WDB flush failed on p= revious boot, 1 =3D WDB flush completed w/o errors on previous boot BOOLEAN EadrFlushFailed; /// < 0 =3D Extended ADR flush fa= iled on previous boot, 1 =3D Extended ADR flush completed w/o errors on pre= vious boot } DIMM_DEVICE_INFO_STRUCT; //struct dimmDevice @@ -919,9 +918,7 @@ typedef struct memVar { UINT8 callingTrngOffstCfgOnce; ///
- # BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) - # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) - # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. - # BIT3: Enable GENPROTRANGEs as PMRs replacement for IOMMU based DMA Pr= otection - # @Prompt The policy for VTd driver behavior. - gSiPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|0x00|UINT8|0x00000002 =20 ## Declares VTd PEI DMA buffer size.

# When this PCD value is referred by platform to calculate the required @@ -840,7 +833,7 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, gSiPkgTokenSpaceGuid.PcdTempRefreshOption |0|UINT8|0x7000000A =20 # Temperature refresh value default, Values are in Celcius - gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x19|UINT8|0x7000= 0001 + gSiPkgTokenSpaceGuid.PcdHalfxRefreshValue |0x00|UINT8|0x7000= 0001 gSiPkgTokenSpaceGuid.PcdTwoxRefreshValue |0x53|UINT8|0x7000= 0002 gSiPkgTokenSpaceGuid.PcdFourxRefreshValue |0x5F|UINT8|0x7000= 0003 =20 @@ -933,6 +926,8 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, # VTD PCDs End # =20 + gSiPkgTokenSpaceGuid.PcdPcieMultiVcEnable|FALSE|BOOLEAN|0xF0000038 + [PcdsDynamicEx] gReferenceCodePolicyTokenSpaceGuid.PcdEvMode |0x00|UINT8|0x00010= 001 # ReservedC: The Mailbox Command which it gona to assert. @@ -958,12 +953,26 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f= 43, {0x8d, 0xef, 0xa7, 0x43, # gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E =20 + # + # RAS: PcdRasIerrPresent - TRUE: IERR has occured need reset; FALSE: No = IERR + # + gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 + [PcdsDynamicEx] gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D gPlatformTokenSpaceGuid.PcdFlashSecOverridden|FALSE|BOOLEAN|0x6000001B =20 +## Will be set if platform is WS else remains FALSE for Server platform. + gPlatformTokenSpaceGuid.PcdIsCPUWsType|FALSE|BOOLEAN|0x6000001A + +## C2F +## Will be set if platform is resuming from a global reset after ADR trig= ger. + # C2F driver will read the PCD and determine whether to perform C2f Entr= y. + # @Prompt Provide status if Adr resume or not + + gPlatformTokenSpaceGuid.PcdAdrResumeStatus|0|UINT8|0x0000104A ## ## ME ## @@ -979,7 +988,6 @@ gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43= , {0x8d, 0xef, 0xa7, 0x43, ## RAS ## gSiPkgTokenSpaceGuid.PcdRasGlobaldataTableAddress|0x0|UINT64|0x20000001 - gSiPkgTokenSpaceGuid.PcdRasIerrPresent|FALSE|BOOLEAN|0x20000002 =20 [PcdsFeatureFlag] ## This PCD used by FPGA drivers to decide to install FPGA features. --=20 2.39.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#98399): https://edk2.groups.io/g/devel/message/98399 Mute This Topic: https://groups.io/mt/96235812/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-