From nobody Mon Apr 29 06:33:15 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40998+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40998+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1558333881; cv=none; d=zoho.com; s=zohoarc; b=OfYa+E+XZETOEBVHKQ0a7Wey61WD6/W9pFPLjc14yXegTGjVRPzarXugIkPDfMNk4Dz3tQLoIM/r0f/Lbmc2ejT3SyMcXi13VzO42ohsow+NEOyIT6EP077uNxXBqWESzqajFC/cZVbPrIPhcOWItLGj7m0E1jfo31p/6m5tuSI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1558333881; h=Content-Type:Cc:Date:From:In-Reply-To:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To:ARC-Authentication-Results; bh=+aSEeEOFKWxHcyYnwrpmuKUZCetczwwSSHb4NcKNQoo=; b=gL6ZmW69dBp1VGRzZ190lXy2BUpHeZVTakhdCFZci8flXz+yVbRXI8mBuBLXb3VZ8uuJ1OY5/24fgtFIyi76fljsvKyuM0XmHBMruUdIlsLTmC4/kWwr+pLZsMNX5kAfKcEnYhjFgRjW0rvTOMHoCQsqQnjyFTSgxt4255/3u1I= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40998+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1558333881379237.4282501548488; Sun, 19 May 2019 23:31:21 -0700 (PDT) Return-Path: X-Received: from ZXSHCAS2.zhaoxin.com (ZXSHCAS2.zhaoxin.com [203.148.12.82]) by groups.io with SMTP; Sun, 19 May 2019 23:31:19 -0700 X-Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 20 May 2019 14:31:11 +0800 X-Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by zxbjmbx3.zhaoxin.com (10.29.252.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 20 May 2019 14:31:10 +0800 X-Received: from zxbjmbx3.zhaoxin.com ([fe80::57b:6f00:3193:d8a6]) by zxbjmbx3.zhaoxin.com ([fe80::57b:6f00:3193:d8a6%8]) with mapi id 15.01.1261.035; Mon, 20 May 2019 14:31:10 +0800 From: "Jerry Zhou(BJ-RD)" To: "Yao, Jiewen" , "Zeng, Star" , "edk2-devel@lists.01.org" , "devel@edk2.groups.io" CC: "Ni, Ray" Subject: =?UTF-8?B?W2VkazItZGV2ZWxdIOetlOWkjTogW2VkazJdIFtQQVRDSF0gSW50ZWxTaWxpY29uUGtnIFZUZER4ZTogYSBxdWVzdGlvbiBhYm91dCB0aGUgc291cmNlIGNvZGU=?= Thread-Topic: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Index: AdUJNci9WEC63Y3xT7KjRAFsJUkP5QARFuIgAAC+ShABT1l1wAACY4ggAARR9EA= Date: Mon, 20 May 2019 06:31:10 +0000 Message-ID: References: <0C09AFA07DD0434D9E2A0C6AEB048310402DECF5@shsmsx102.ccr.corp.intel.com> <9b07851c347d4810a691ebaa64d1fa5e@zhaoxin.com> <0C09AFA07DD0434D9E2A0C6AEB048310402E56C9@shsmsx102.ccr.corp.intel.com> <74D8A39837DF1E4DA445A8C0B3885C503F65159E@shsmsx102.ccr.corp.intel.com> In-Reply-To: <74D8A39837DF1E4DA445A8C0B3885C503F65159E@shsmsx102.ccr.corp.intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.29.8.16] MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,JerryZhou@zhaoxin.com Content-Language: zh-CN Content-Type: multipart/alternative; boundary="_000_c4666120015a4f27bbe322359408bc70zhaoxincom_" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1558333880; bh=LcwB+pkQPe+chQERQYjBANKKk90wcjOSseNMrQMQfmg=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=WIJheDeZWzpkj5ErbOgm1PpyaUWT9CmZfSBAHpQjSVugqZbUJY/0KYDHuMgygfAORpc URQ1i0LTcaK24NdPoUELljbN0cUzrpJ7sOgnjjG/S5cDM5IkMiU+P/yG19Y1ov0y4ykNT 4vumOCglMCJJiZQrijsBeyT+1+JclzLFA3g= X-ZohoMail-DKIM: pass (identity @groups.io) --_000_c4666120015a4f27bbe322359408bc70zhaoxincom_ Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" OK. I have submitted to Bugzilla. Bug 1823 - source code about disabling the DMAR of IOMMU in IntelSiliconPkg Thank you Jerry Zhou =E5=8F=91=E4=BB=B6=E4=BA=BA: Yao, Jiewen [mailto:jiewen.yao@intel.com] =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2019=E5=B9=B45=E6=9C=8820=E6=97=A5 14= :09 =E6=94=B6=E4=BB=B6=E4=BA=BA: Zeng, Star; Jerry Zhou(BJ-RD); edk2-devel@list= s.01.org; devel@edk2.groups.io =E6=8A=84=E9=80=81: Ni, Ray; Yao, Jiewen =E4=B8=BB=E9=A2=98: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question a= bout the source code Thanks. We are also reviewing the VTd disabling flow and may update recently. If you want to file Bugzilla, please go ahead. Thank you Yao Jiewen From: Zeng, Star Sent: Sunday, May 19, 2019 8:33 PM To: Jerry Zhou(BJ-RD) ; edk2-devel@lists.01.org; dev= el@edk2.groups.io Cc: Yao, Jiewen ; Ni, Ray ; Zeng, S= tar Subject: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the so= urce code Actually, I agree with you. Personally, I think more rigorous flow could be like below. 1. Clear B_GMCD_REG_TE, wait B_GSTS_REG_TE to be cleared. 2. Set B_GMCD_REG_SRTP, wait B_GSTS_REG_RTPS to be set. 3. Zero R_RTADDR_REG. Not sure original code developer Jiewen=E2=80=99s thought about this. You may submit Bugzilla at https://bugzilla.tianocore.org if you wait. Thanks, Star From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com] Sent: Monday, May 13, 2019 7:28 PM To: Zeng, Star >; edk2-deve= l@lists.01.org; devel@edk2.groups.io Cc: Yao, Jiewen >; Ni, Ra= y > Subject: =E7=AD=94=E5=A4=8D: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a quest= ion about the source code Got it! Thanks for your reply. But you should still poll the B_GSTS_REG_TE bit, not the B_GSTS_REG_RTPS bi= t, in the judgement code of while() loop. After & operation between Reg32 and B_GSTS_REG_RTPS, the status of B_GSTS_R= EG_TE will be lost. A more tedious but more reliable operation sequence is recommended in Vt-d = specification 2.4 below: to update a bit field in this register at offset X with value of Y, software must follow below steps: 1. Tmp =3D Read GSTS_REG 2. Status =3D (Tmp & 96FFFFFFh) // Reset the one-shot bits 3. Command =3D (Status | (Y << X)) 4. Write Command to GCMD_REG 5. Wait until GSTS_REG[X] indicates command is serviced. =E5=8F=91=E4=BB=B6=E4=BA=BA: Zeng, Star [mailto:star.zeng@intel.com] =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2019=E5=B9=B45=E6=9C=8813=E6=97=A5 18= :54 =E6=94=B6=E4=BB=B6=E4=BA=BA: Jerry Zhou(BJ-RD); edk2-devel@lists.01.org =E6=8A=84=E9=80=81: Yao, Jiewen; Ni, Ray; Zeng, Star =E4=B8=BB=E9=A2=98: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question a= bout the source code Good question, my understanding is setting B_GMCD_REG_SRTP(BIT30) ONLY also= means clearing B_GMCD_REG_TE (BIT31). Thanks, Star From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com] Sent: Monday, May 13, 2019 10:59 AM To: Zeng, Star >; edk2-deve= l@lists.01.org Cc: Yao, Jiewen >; Ni, Ra= y > Subject: =E7=AD=94=E5=A4=8D: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a quest= ion about the source code Hi Star, I'am so interested in DMA protection in UEFI. It's a really good d= esign! But I have a question about the implemention of DisableDmar() in I= ntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c Is it a typing error in the code segment below? // // Disable VTd // MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG= , B_GMCD_REG_SRTP); do { Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress += R_GSTS_REG); } while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); The software should program the B_GMCD_REG_TE field in global command regis= ter and then poll the B_GSTS_REG_TE field in global status register if the = DMAR is expected to be disabled or enabled according to Vt-d specification. Thanks Jerry Zhou Ext:892418 -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- =E5=8F=91=E4=BB=B6=E4=BA=BA: edk2-devel [mailto:edk2-devel-bounces@lists.01= .org] =E4=BB=A3=E8=A1=A8 Star Zeng =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2018=E5=B9=B410=E6=9C=8824=E6=97=A5 1= 1:32 =E6=94=B6=E4=BB=B6=E4=BA=BA: edk2-devel@lists.01.org =E6=8A=84=E9=80=81: Jiewen Yao; Star Zeng =E4=B8=BB=E9=A2=98: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force = no early access attr request REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272 To have high confidence in usage for platform, add option (BIT2 of PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request recording before DMAR table is installed. Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute() and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 =3D 1. Test done: 1: Created case that has IOMMU access attribute request before DMAR table is installed, ASSERT was triggered after setting PcdVTdPolicyPropertyMask BIT2 to 1. 2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables were optimized by compiler after setting PcdVTdPolicyPropertyMask BIT2 to 1. Cc: Jiewen Yao > Cc: Rangasai V Chaganty > Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng > --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c | 8 +++++++- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 7 +++++++ IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c b/Inte= lSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c index 86d50eb6f288..7784545631b3 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c @@ -515,7 +515,13 @@ SetupVtd ( ParseDmarAcpiTableRmrr (); - ProcessRequestedAccessAttribute (); + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) =3D=3D 0) { + // + // Support IOMMU access attribute request recording before DMAR table = is installed. + // Here is to process the requests. + // + ProcessRequestedAccessAttribute (); + } for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitInf= ormation[Index].Segment)); diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c b/IntelS= iliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c index 25d7c80af1d4..09948ce50e94 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c @@ -254,6 +254,13 @@ VTdSetAttribute ( // Record the entry to driver global variable. // As such once VTd is activated, the setting can be adopted. // + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) { + // + // Force no IOMMU access attribute request recording before DMAR tab= le is installed. + // + ASSERT_EFI_ERROR (EFI_NOT_READY); + return EFI_NOT_READY; + } Status =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, L= ength, IoMmuAccess); } else { PERF_CODE ( diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSil= iconPkg.dec index b9646d773b95..900e8f63c64d 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/IntelSiliconPkg/IntelSiliconPkg.dec @@ -64,6 +64,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, Pc= dsDynamicEx] ## The mask is used to control VTd behavior.

# BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) + # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. # @Prompt The policy for VTd driver behavior. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x000000= 02 -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel =E4=BF=9D=E5=AF=86=E5=A3=B0=E6=98=8E=EF=BC=9A =E6=9C=AC=E9=82=AE=E4=BB=B6=E5=90=AB=E6=9C=89=E4=BF=9D=E5=AF=86=E6=88=96=E4= =B8=93=E6=9C=89=E4=BF=A1=E6=81=AF=EF=BC=8C=E4=BB=85=E4=BE=9B=E6=8C=87=E5=AE= =9A=E6=94=B6=E4=BB=B6=E4=BA=BA=E4=BD=BF=E7=94=A8=E3=80=82=E4=B8=A5=E7=A6=81= =E5=AF=B9=E6=9C=AC=E9=82=AE=E4=BB=B6=E6=88=96=E5=85=B6=E5=86=85=E5=AE=B9=E5= =81=9A=E4=BB=BB=E4=BD=95=E6=9C=AA=E7=BB=8F=E6=8E=88=E6=9D=83=E7=9A=84=E6=9F= =A5=E9=98=85=E3=80=81=E4=BD=BF=E7=94=A8=E3=80=81=E5=A4=8D=E5=88=B6=E6=88=96= =E8=BD=AC=E5=8F=91=E3=80=82 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is f= or the sole use of its intended recipient. Any unauthorized review, use, co= pying or forwarding of this email or the content of this email is strictly = prohibited. =E4=BF=9D=E5=AF=86=E5=A3=B0=E6=98=8E=EF=BC=9A =E6=9C=AC=E9=82=AE=E4=BB=B6=E5=90=AB=E6=9C=89=E4=BF=9D=E5=AF=86=E6=88=96=E4= =B8=93=E6=9C=89=E4=BF=A1=E6=81=AF=EF=BC=8C=E4=BB=85=E4=BE=9B=E6=8C=87=E5=AE= =9A=E6=94=B6=E4=BB=B6=E4=BA=BA=E4=BD=BF=E7=94=A8=E3=80=82=E4=B8=A5=E7=A6=81= =E5=AF=B9=E6=9C=AC=E9=82=AE=E4=BB=B6=E6=88=96=E5=85=B6=E5=86=85=E5=AE=B9=E5= =81=9A=E4=BB=BB=E4=BD=95=E6=9C=AA=E7=BB=8F=E6=8E=88=E6=9D=83=E7=9A=84=E6=9F= =A5=E9=98=85=E3=80=81=E4=BD=BF=E7=94=A8=E3=80=81=E5=A4=8D=E5=88=B6=E6=88=96= =E8=BD=AC=E5=8F=91=E3=80=82 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is f= or the sole use of its intended recipient. Any unauthorized review, use, co= pying or forwarding of this email or the content of this email is strictly = prohibited. =E4=BF=9D=E5=AF=86=E5=A3=B0=E6=98=8E=EF=BC=9A =E6=9C=AC=E9=82=AE=E4=BB=B6=E5=90=AB=E6=9C=89=E4=BF=9D=E5=AF=86=E6=88=96=E4= =B8=93=E6=9C=89=E4=BF=A1=E6=81=AF=EF=BC=8C=E4=BB=85=E4=BE=9B=E6=8C=87=E5=AE= =9A=E6=94=B6=E4=BB=B6=E4=BA=BA=E4=BD=BF=E7=94=A8=E3=80=82=E4=B8=A5=E7=A6=81= =E5=AF=B9=E6=9C=AC=E9=82=AE=E4=BB=B6=E6=88=96=E5=85=B6=E5=86=85=E5=AE=B9=E5= =81=9A=E4=BB=BB=E4=BD=95=E6=9C=AA=E7=BB=8F=E6=8E=88=E6=9D=83=E7=9A=84=E6=9F= =A5=E9=98=85=E3=80=81=E4=BD=BF=E7=94=A8=E3=80=81=E5=A4=8D=E5=88=B6=E6=88=96= =E8=BD=AC=E5=8F=91=E3=80=82 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is f= or the sole use of its intended recipient. Any unauthorized review, use, co= pying or forwarding of this email or the content of this email is strictly = prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40998): https://edk2.groups.io/g/devel/message/40998 Mute This Topic: https://groups.io/mt/31682628/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_c4666120015a4f27bbe322359408bc70zhaoxincom_ Content-Type: text/html; charset="gb2312" Content-Transfer-Encoding: quoted-printable

OK.

I have= submitted to Bugzilla.

Bug 18= 23 - source code about disabling the DMAR of IOMMU in IntelSiliconPkg<= /o:p>

&= nbsp;

Thank = you

Jerry = Zhou

=B7=A2=BC=FE=C8=CB: Yao, Jiewen [mailto:jiewen.yao@intel.com]
=B7=A2= = =CB=CD=CA=B1=BC=E4: 2019=C4=EA5=D4=C220=C8=D5 14:09
=CA=D5=BC=FE=C8=CB: Zeng, Star; Jerry Zhou(BJ-RD); edk2-devel@lists.01.org; devel@edk2= .groups.io
=B3=AD=CB=CD: Ni, Ray; Yao, Jiewen
=D6=F7=CC=E2: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source c= ode

 

Thanks= .

We are= also reviewing the VTd disabling flow and may update recently.<= /span>

&= nbsp;

If you= want to file Bugzilla, please go ahead.

&= nbsp;

Thank = you

Yao Ji= ewen

 

From: Zeng, St= ar
Sent: Sunday, May 19, 2019 8:33 PM
To: Jerry Zhou(BJ-RD) <JerryZhou@zhaoxin.com>; edk2-devel@lis= ts.01.org; devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com>; Ni, Ray <ray.ni@in= tel.com>; Zeng, Star <star.zeng@intel.com>
Subject: RE: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question abou= t the source code

 

Actually, I agree with you.

Personally, I think more rigorous flow could be like below.=

1.      Clear= B_GMCD_REG_TE, wait B_GSTS_REG_TE to be cleared.

2.      Set B= _GMCD_REG_SRTP, wait B_GSTS_REG_RTPS to be set.

3.      Zero = R_RTADDR_REG.

 

Not sure original code developer Jiewen=A1=AFs thought about thi= s.

 

 

You may submit Bugzilla at https://bu= gzilla.tianocore.org if you wait.

 

 

Thanks,

Star

 

From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com]
Sent: Monday, May 13, 2019 7:28 PM
To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org; devel@edk2.groups.io
Cc: Yao, Jiewen <jiewen.yao@intel.com<= /span>>; Ni, = Ray <ray.ni@intel.com>
Subject: =B4=F0=B8=B4: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<= o:p>

 

Got it= ! Thanks for your reply.

But yo= u should still poll the B_GSTS_REG_TE bit, not the B_GSTS_REG_RTPS bit, in = the judgement code of while() loop.

After = & operation between Reg32 and B_GSTS_REG_RTPS, the status of B_GSTS_REG= _TE will be lost.

&= nbsp;

A more= tedious but more reliable operation sequence is recommended in Vt-d specif= ication 2.4 below:

&= nbsp;

to update a bit field in = this register at offset X with value of Y, software

must follow below steps:<= o:p>

1. Tmp =3D Read GSTS_REG<= o:p>

2. Status =3D (Tmp & = 96FFFFFFh) // Reset the one-shot bits

3. Command =3D (Status | = (Y << X))

4. Write Command to GCMD_= REG

5. Wait until GSTS_REG[X]= indicates command is serviced.

=B7=A2=BC=FE=C8=CB: Zeng, Star [mailto:star.zeng@intel.com]
=B7=A2= = =CB=CD=CA=B1=BC=E4: 2019=C4=EA5=D4=C213=C8=D5 18:54
=CA=D5=BC=FE=C8=CB: Jerry Zhou(BJ-RD); edk2-devel@li= sts.01.org
=B3=AD= = =CB=CD: Yao, Jiewen; Ni, Ray; Zeng= , Star
=D6=F7= = =CC=E2: RE: [edk2] [PATCH] IntelSi= liconPkg VTdDxe: a question about the source code

 

Good question, my understanding is setting B_GMCD_REG_SRTP(BIT30= ) ONLY also means clearing B_GMCD_REG_TE (BIT31).

 

Thanks,

Star

From: Jerry Zhou(BJ-RD) [mailto:JerryZhou@zhaoxin.com]
Sent: Monday, May 13, 2019 10:59 AM
To: Zeng, Star <star.zeng@intel.com>; edk2-devel@lists.01.org
Cc: Yao, Jiewen <jiewen.yao@intel.com<= /span>>; Ni, = Ray <ray.ni@intel.com>
Subject: =B4=F0=B8=B4: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code<= o:p>

 

Hi Star,<= /p>

    &nb= sp;    I'am so interested in DMA protection in UEFI. It's a = really good design!

    &nb= sp;    But I have a question about the implemention of DisableDmar() in IntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c

    &nb= sp;    Is it a typing error in the code segment below?<= /o:p>

 

    //<= /o:p>

    // Disab= le VTd

    //<= /o:p>

    MmioWrit= e32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG, B_GMCD_REG_SRTP);

    do {

    &nb= sp; Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress = 3; R_GSTS_REG);

} while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0);

 

The software should program the B_GMCD_REG_TE field in global command register and then poll the B_GSTS_REG_TE field in global status register if the DMAR is expected = to be disabled or enabled according to Vt-d specification.

 

Thanks

Jerry Zhou

Ext:892418

 

 

 

-----=D3=CA=BC=FE=D4=AD=BC=FE-----
=B7=A2=BC=FE=C8=CB<= span lang=3D"EN-US">: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] =B4=FA=B1=ED Star Zeng
=B7=A2=CB=CD=CA=B1=BC=E4: 2018=C4=EA10=D4=C224=C8=D5 11:32
=CA=D5=BC=FE=C8=CB<= span lang=3D"EN-US">: edk2-devel@lists.01.org
=B3=AD=CB=CD: Jiewen Yao; Star Zeng
=D6=F7=CC=E2: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force no e= arly access attr request

 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272

 

To have high confidence in = usage for platform, add option (BIT2 of

PcdVTdPolicyPropertyMask) t= o force no IOMMU access attribute request

recording before DMAR table= is installed.

 

Check PcdVTdPolicyPropertyM= ask BIT2 before RequestAccessAttribute()

and ProcessRequestedAccessA= ttribute(), then RequestAccessAttribute(),

ProcessRequestedAccessAttri= bute() and mAccessRequestXXX variables

could be optimized by compi= ler when PcdVTdPolicyPropertyMask BIT2 =3D 1.

 

Test done:

1: Created case that has IO= MMU access attribute request before DMAR

   table is insta= lled, ASSERT was triggered after setting

   PcdVTdPolicyPr= opertyMask BIT2 to 1.

 

2. Confirmed RequestAccessA= ttribute(), ProcessRequestedAccessAttribute()

   and mAccessReq= uestXXX variables were optimized by compiler after

   setting PcdVTd= PolicyPropertyMask BIT2 to 1.

 

Cc: Jiewen Yao <jiewen.yao@intel.com>

Cc: Rangasai V Chaganty <= ;rangasai.v.chaganty@intel= .com>

Contributed-under: TianoCor= e Contribution Agreement 1.1

Signed-off-by: Star Zeng &l= t;star.zeng@intel.com>

---

IntelSiliconPkg/Feature/VTd= /IntelVTdDxe/DmaProtection.c | 8 +++++++-<= /o:p>

IntelSiliconPkg/Feature/VTd= /IntelVTdDxe/IntelVTdDxe.c   | 7 ++++++&#= 43;

IntelSiliconPkg/IntelSilico= nPkg.dec           &= nbsp;         | 1 +<= /span>

3 files changed, 15 inserti= ons(+), 1 deletion(-)

 

diff --git a/IntelSiliconPk= g/Feature/VTd/IntelVTdDxe/DmaProtection.c b/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/DmaProtection.c

index 86d50eb6f288..7784545= 631b3 100644

--- a/IntelSiliconPkg/Featu= re/VTd/IntelVTdDxe/DmaProtection.c

+++ b/IntelSili= conPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c

@@ -515,7 +515,13 @@ Se= tupVtd (

 

   ParseDmar= AcpiTableRmrr ();

 

-  ProcessRequestedAcc= essAttribute ();

+  if ((PcdGet8 (P= cdVTdPolicyPropertyMask) & BIT2) =3D=3D 0) {

+    //<= o:p>

+    // = Support IOMMU access attribute request recording before DMAR table is insta= lled.

+    // = Here is to process the requests.

+    //<= o:p>

+    Pro= cessRequestedAccessAttribute ();

+  }

 

   for (Inde= x =3D 0; Index < mVtdUnitNumber; Index++) {

     DE= BUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnit= Information[Index].Segment));

diff --git a/IntelSiliconPk= g/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c b/IntelSiliconPkg/Feature/VTd/Intel= VTdDxe/IntelVTdDxe.c

index 25d7c80af1d4..09948ce= 50e94 100644

--- a/IntelSiliconPkg/Featu= re/VTd/IntelVTdDxe/IntelVTdDxe.c

+++ b/IntelSili= conPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c

@@ -254,6 +254,13 @@ VT= dSetAttribute (

     //= Record the entry to driver global variable.

     //= As such once VTd is activated, the setting can be adopted.

     //=

+    if = ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) {

+   &nbs= p;  //

+   &nbs= p;  // Force no IOMMU access attribute request recording before DMAR t= able is installed.

+   &nbs= p;  //

+   &nbs= p;  ASSERT_EFI_ERROR (EFI_NOT_READY);

+   &nbs= p;  return EFI_NOT_READY;

+    }

     St= atus =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, Length, = IoMmuAccess);

   } else {<= /o:p>

     PE= RF_CODE (

diff --git a/IntelSiliconPk= g/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSiliconPkg.dec

index b9646d773b95..900e8f6= 3c64d 100644

--- a/IntelSiliconPkg/Intel= SiliconPkg.dec

+++ b/IntelSili= conPkg/IntelSiliconPkg.dec

@@ -64,6 +64,7 @@ [Pcds= FixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=

   ## The mask is= used to control VTd behavior.<BR><BR>

   #  BIT0: = Enable IOMMU during boot (If DMAR table is installed in DXE. If VTD_INFO_PP= I is installed in PEI.)

   #  BIT1: = Enable IOMMU when transfer control to OS (ExitBootService in normal boot. E= ndOfPEI in S3)

+  #  BIT2: F= orce no IOMMU access attribute request recording before DMAR table is insta= lled.

   # @Prompt The = policy for VTd driver behavior.

   gIntelSiliconP= kgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x00000002

 

--

2.7.0.windows.1<= /span>

 

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