From nobody Sun Feb 8 22:07:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88930+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88930+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1650011880; cv=none; d=zohomail.com; s=zohoarc; b=Ki2OHWHHcv7ZnGqQHeypzDH8qR1GVNQiNNkMz1qNGAdXHjnwscwp1gEUcaEDSG5LuUmCAoZTk+vOEULa4wCspKuwcx255faTbNROVF5sSSvGwbV69EJUcAVUA+XsPoPIaIHqRC44tMTIh+Z1iTPA4rFk6se6KNxzKUSzp3hRQ1A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650011880; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=TBq5KZaxgBj73STPJXZ1LVw8KOX9LIgXrL/aj1N/GMY=; b=HHSjs1VLFpIbXNBO50dIfRXFnreOwSEWG7PF/OKNAVWf2cxasc7HtUglq7KUDGOzaXHsDUGWw9KGP4KfkgEpDVVAf8QnnGrysGxRkPnW3/NrHoj452jFXf7at1h6gN+1zVapFLC7umFO3ns7jyIvLq1bzjmfOi917WjZftY/FPY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88930+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1650011880184415.42773126526527; Fri, 15 Apr 2022 01:38:00 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id HsAaYY1788612xiLu8RaUexT; Fri, 15 Apr 2022 01:37:59 -0700 X-Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.5202.1650011878251661812 for ; Fri, 15 Apr 2022 01:37:59 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10317"; a="262563802" X-IronPort-AV: E=Sophos;i="5.90,262,1643702400"; d="scan'208";a="262563802" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2022 01:37:55 -0700 X-IronPort-AV: E=Sophos;i="5.90,262,1643702400"; d="scan'208";a="700990461" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Apr 2022 01:37:53 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH v5 2/8] IntelFsp2Pkg: Add FSPx_ARCH2_UPD support for X64 Date: Fri, 15 Apr 2022 16:37:37 +0800 Message-Id: In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: Mkho9KgkcoJYf13gyMK1vu0rx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1650011879; bh=C5wwfZUuzPVL+hmReZSHRpiymwOvft6dfe9ZGOBlF/M=; h=Cc:Date:From:Reply-To:Subject:To; b=HUcZkqXE/B7ndY7rRsMXm9ugV9XnuuQ5+l+dRab1pKrnzGj5Krte+jZQeaECoghRnPL bPC4ya/iuEqUzeuU1mWW4hl+VvhaDrFM4WX2fgAN0/zWS19PD+9uB02tnIkjXok73HRJv zxwI0AJIaI2Y7rbQLN855H17rquFeHp6wBo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1650011882340100016 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 1.Added FSPx_ARCH2_UPD structures which support both IA32 and X64. 2.Added FSPx_UPD_COMMON_FSP24 structures. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm | 32 +++++- IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm | 98 ++++++++++++++--- IntelFsp2Pkg/Include/FspEas/FspApi.h | 139 +++++++++++++++++++++= +++- IntelFsp2Pkg/Tools/GenCfgOpt.py | 7 +- 4 files changed, 252 insertions(+), 24 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryM.nasm index e7261b41cd..5dada2af54 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryM.nasm @@ -1,7 +1,7 @@ ;; @file ; Provide FSP API entry points. ; -; Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; =20 @@ -32,6 +32,24 @@ struc FSPM_UPD_COMMON .size: endstruc =20 +struc FSPM_UPD_COMMON_FSP24 + ; FSP_UPD_HEADER { + .FspUpdHeader: resd 8 + ; } + ; FSPM_ARCH2_UPD { + .Revision: resb 1 + .Reserved: resb 3 + .Length resd 1 + .StackBase: resq 1 + .StackSize: resq 1 + .BootLoaderTolumSize: resd 1 + .BootMode: resd 1 + .FspEventHandler resq 1 + .Reserved1: resb 24 + ; } + .size: +endstruc + ; ; Following functions will be provided in C ; @@ -124,12 +142,22 @@ ASM_PFX(FspApiCommonContinue): pop eax =20 FspStackSetup: + mov ecx, [edx + FSPM_UPD_COMMON.Revision] + cmp ecx, 3 + jae FspmUpdCommon2 + ; ; StackBase =3D temp memory base, StackSize =3D temp memory size ; mov edi, [edx + FSPM_UPD_COMMON.StackBase] mov ecx, [edx + FSPM_UPD_COMMON.StackSize] + jmp ChkFspHeapSize + +FspmUpdCommon2: + mov edi, [edx + FSPM_UPD_COMMON_FSP24.StackBase] + mov ecx, [edx + FSPM_UPD_COMMON_FSP24.StackSize] =20 +ChkFspHeapSize: ; ; Keep using bootloader stack if heap size % is 0 ; @@ -219,7 +247,7 @@ exit: global ASM_PFX(FspPeiCoreEntryOff) ASM_PFX(FspPeiCoreEntryOff): ; - ; This value will be pached by the build script + ; This value will be patched by the build script ; DD 0x12345678 =20 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 7fd3d6d843..61030a843b 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -1,7 +1,7 @@ ;; @file ; Provide FSP API entry points. ; -; Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
+; Copyright (c) 2016 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ;; =20 @@ -84,8 +84,10 @@ struc LoadMicrocodeParamsFsp22 .FspUpdHeaderRevision: resb 1 .FspUpdHeaderReserved: resb 23 ; } - ; FSPT_ARCH_UPD{ - .FsptArchUpd: resd 8 + ; FSPT_ARCH_UPD { + .FsptArchRevision: resb 1 + .FsptArchReserved: resb 3 + .FsptArchUpd: resd 7 ; } ; FSPT_CORE_UPD { .MicrocodeCodeAddr: resd 1 @@ -96,6 +98,28 @@ struc LoadMicrocodeParamsFsp22 .size: endstruc =20 +struc LoadMicrocodeParamsFsp24 + ; FSP_UPD_HEADER { + .FspUpdHeaderSignature: resd 2 + .FspUpdHeaderRevision: resb 1 + .FspUpdHeaderReserved: resb 23 + ; } + ; FSPT_ARCH2_UPD { + .FsptArchRevision: resb 1 + .FsptArchReserved: resb 3 + .FsptArchLength: resd 1 + .FspDebugHandler resq 1 + .FsptArchUpd: resd 4 + ; } + ; FSPT_CORE_UPD { + .MicrocodeCodeAddr: resq 1 + .MicrocodeCodeSize: resq 1 + .CodeRegionBase: resq 1 + .CodeRegionSize: resq 1 + ; } + .size: +endstruc + ; ; Define SSE macros ; @@ -172,9 +196,9 @@ ASM_PFX(LoadMicrocodeDefault): ; Executed by SBSP and NBSP ; Beginning of microcode update region starts on paragraph boundary =20 - ; ; ; Save return address to EBP + ; movd ebp, mm7 =20 cmp esp, 0 @@ -188,8 +212,12 @@ ASM_PFX(LoadMicrocodeDefault): ; and report error if size is less than 2k ; first check UPD header revision cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 - jae Fsp22UpdHeader + jb Fsp20UpdHeader + cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 + je Fsp24UpdHeader + jmp Fsp22UpdHeader =20 +Fsp20UpdHeader: ; UPD structure is compliant with FSP spec 2.0/2.1 mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize] cmp eax, 0 @@ -213,6 +241,19 @@ Fsp22UpdHeader: mov esi, dword [esp + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] cmp esi, 0 jnz CheckMainHeader + jmp ParamError + +Fsp24UpdHeader: + ; UPD structure is compliant with FSP spec 2.4 + mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] + cmp eax, 0 + jz Exit2 + cmp eax, 0800h + jl ParamError + + mov esi, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] + cmp esi, 0 + jnz CheckMainHeader =20 ParamError: mov eax, 080000002h @@ -308,9 +349,13 @@ AdvanceFixedSize: =20 CheckAddress: ; Check UPD header revision - cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 - jae Fsp22UpdHeader1 + cmp byte [esp + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 + jb Fsp20UpdHeader1 + cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 + je Fsp24UpdHeader1; + jmp Fsp22UpdHeader1 =20 +Fsp20UpdHeader1: ; UPD structure is compliant with FSP spec 2.0/2.1 ; Is automatic size detection ? mov eax, dword [esp + LoadMicrocodeParams.MicrocodeCodeSize] @@ -336,6 +381,19 @@ Fsp22UpdHeader1: jae Done ;Jif address is outside of microcode region jmp CheckMainHeader =20 +Fsp24UpdHeader1: + ; UPD structure is compliant with FSP spec 2.4 + ; Is automatic size detection ? + mov eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] + cmp eax, 0ffffffffh + jz LoadMicrocodeDefault4 + + ; Address >=3D microcode region address + microcode region size? + add eax, dword [esp + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] + cmp esi, eax + jae Done ;Jif address is outside of microcode region + jmp CheckMainHeader + LoadMicrocodeDefault4: ; Is valid Microcode start point ? cmp dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh @@ -351,7 +409,7 @@ LoadCheck: mov eax, 1 cpuid mov ecx, MSR_IA32_BIOS_SIGN_ID - rdmsr ; Get current microcode signature + rdmsr ; Get current microcode signature =20 ; Verify this microcode update is not already loaded cmp dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx @@ -405,8 +463,12 @@ ASM_PFX(EstablishStackFsp): =20 ; check UPD structure revision (edx + 8) cmp byte [edx + LoadMicrocodeParamsFsp22.FspUpdHeaderRevision], 2 - jae Fsp22UpdHeader2 + jb Fsp20UpdHeader2 + cmp byte [esp + LoadMicrocodeParamsFsp22.FsptArchRevision], 2 + je Fsp24UpdHeader2 + jmp Fsp22UpdHeader2 =20 +Fsp20UpdHeader2: ; UPD structure is compliant with FSP spec 2.0/2.1 push dword [edx + LoadMicrocodeParams.CodeRegionSize] ; Code si= ze sizeof(FSPT_UPD_COMMON) + 12 push dword [edx + LoadMicrocodeParams.CodeRegionBase] ; Code ba= se sizeof(FSPT_UPD_COMMON) + 8 @@ -420,6 +482,14 @@ Fsp22UpdHeader2: push dword [edx + LoadMicrocodeParamsFsp22.CodeRegionBase] ; Co= de base sizeof(FSPT_UPD_COMMON) + 8 push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeSize] ; Mi= crocode size sizeof(FSPT_UPD_COMMON) + 4 push dword [edx + LoadMicrocodeParamsFsp22.MicrocodeCodeAddr] ; Mi= crocode base sizeof(FSPT_UPD_COMMON) + 0 + jmp ContinueAfterUpdPush + +Fsp24UpdHeader2: + ; UPD structure is compliant with FSP spec 2.4 + push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionSize] ; Co= de size sizeof(FSPT_UPD_COMMON) + 24 + push dword [edx + LoadMicrocodeParamsFsp24.CodeRegionBase] ; Co= de base sizeof(FSPT_UPD_COMMON) + 16 + push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeSize] ; Mi= crocode size sizeof(FSPT_UPD_COMMON) + 8 + push dword [edx + LoadMicrocodeParamsFsp24.MicrocodeCodeAddr] ; Mi= crocode base sizeof(FSPT_UPD_COMMON) + 0 =20 ContinueAfterUpdPush: ; @@ -517,13 +587,13 @@ ASM_PFX(TempRamInitApi): cmp eax, 0 jnz TempRamInitExit =20 - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error = from ECX-SLOT 3 in xmm6. + LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error f= rom ECX-SLOT 3 in xmm6. =20 TempRamInitExit: - mov bl, al ; save al data in bl - mov al, 07Fh ; API exit postcode 7f - out 080h, al - mov al, bl ; restore al data from bl + mov bl, al ; save al data in bl + mov al, 07Fh ; API exit postcode 7f + out 080h, al + mov al, bl ; restore al data from bl =20 ; ; Load EBP, EBX, ESI, EDI & ESP from XMM7 & XMM6 diff --git a/IntelFsp2Pkg/Include/FspEas/FspApi.h b/IntelFsp2Pkg/Include/Fs= pEas/FspApi.h index 794f94dc7a..b36bc2b9ae 100644 --- a/IntelFsp2Pkg/Include/FspEas/FspApi.h +++ b/IntelFsp2Pkg/Include/FspEas/FspApi.h @@ -2,7 +2,7 @@ Intel FSP API definition from Intel Firmware Support Package External Architecture Specification v2.0 - v2.2 =20 - Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.
+ Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -112,12 +112,12 @@ typedef struct { /// typedef struct { /// - /// Revision Revision of the structure is 1 for this version of the spec= ification. + /// Revision of the structure is 1 for this version of the specification. /// UINT8 Revision; UINT8 Reserved[3]; /// - /// Length Length of the structure in bytes. The current value for this = field is 32. + /// Length of the structure in bytes. The current value for this field i= s 32. /// UINT32 Length; /// @@ -128,6 +128,27 @@ typedef struct { UINT8 Reserved1[20]; } FSPT_ARCH_UPD; =20 +/// +/// FSPT_ARCH2_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure is 2 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length of the structure in bytes. The current value for this field i= s 32. + /// + UINT32 Length; + /// + /// FspDebugHandler Optional debug handler for the bootloader to receive= debug messages + /// occurring during FSP execution. + /// + EFI_PHYSICAL_ADDRESS FspDebugHandler; + UINT8 Reserved1[16]; +} FSPT_ARCH2_UPD; + /// /// FSPM_ARCH_UPD Configuration. /// @@ -169,14 +190,57 @@ typedef struct { UINT8 Reserved1[4]; } FSPM_ARCH_UPD; =20 +/// +/// FSPM_ARCH2_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure is 3 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length of the structure in bytes. The current value for this field i= s 64. + /// + UINT32 Length; + /// + /// Pointer to the temporary stack base address to be + /// consumed inside FspMemoryInit() API. + /// + EFI_PHYSICAL_ADDRESS StackBase; + /// + /// Temporary stack size to be consumed inside + /// FspMemoryInit() API. + /// + UINT64 StackSize; + /// + /// Size of memory to be reserved by FSP below "top + /// of low usable memory" for bootloader usage. + /// + UINT32 BootLoaderTolumSize; + /// + /// Current boot mode. + /// + UINT32 BootMode; + /// + /// Optional event handler for the bootloader to be informed of events o= ccurring during FSP execution. + /// This value is only valid if Revision is >=3D 2. + /// + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[24]; +} FSPM_ARCH2_UPD; + +/// +/// FSPS_ARCH_UPD Configuration. +/// typedef struct { /// - /// Revision Revision of the structure is 1 for this version of the spec= ification. + /// Revision of the structure is 1 for this version of the specification. /// UINT8 Revision; UINT8 Reserved[3]; /// - /// Length Length of the structure in bytes. The current value for this = field is 32. + /// Length of the structure in bytes. The current value for this field i= s 32. /// UINT32 Length; /// @@ -195,6 +259,27 @@ typedef struct { UINT8 Reserved1[19]; } FSPS_ARCH_UPD; =20 +/// +/// FSPS_ARCH2_UPD Configuration. +/// +typedef struct { + /// + /// Revision of the structure is 2 for this version of the specification. + /// + UINT8 Revision; + UINT8 Reserved[3]; + /// + /// Length of the structure in bytes. The current value for this field i= s 32. + /// + UINT32 Length; + /// + /// FspEventHandler Optional event handler for the bootloader to be info= rmed of events + /// occurring during FSP execution. + /// + EFI_PHYSICAL_ADDRESS FspEventHandler; + UINT8 Reserved1[16]; +} FSPS_ARCH2_UPD; + /// /// FSPT_UPD_COMMON Configuration. /// @@ -220,6 +305,21 @@ typedef struct { FSPT_ARCH_UPD FsptArchUpd; } FSPT_UPD_COMMON_FSP22; =20 +/// +/// FSPT_UPD_COMMON Configuration for FSP spec. 2.4 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPT_ARCH2_UPD Configuration. + /// + FSPT_ARCH2_UPD FsptArchUpd; +} FSPT_UPD_COMMON_FSP24; + /// /// FSPM_UPD_COMMON Configuration. /// @@ -234,6 +334,20 @@ typedef struct { FSPM_ARCH_UPD FspmArchUpd; } FSPM_UPD_COMMON; =20 +/// +/// FSPM_UPD_COMMON Configuration for FSP spec. 2.4 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + /// + /// FSPM_ARCH2_UPD Configuration. + /// + FSPM_ARCH2_UPD FspmArchUpd; +} FSPM_UPD_COMMON_FSP24; + /// /// FSPS_UPD_COMMON Configuration. /// @@ -259,6 +373,21 @@ typedef struct { FSPS_ARCH_UPD FspsArchUpd; } FSPS_UPD_COMMON_FSP22; =20 +/// +/// FSPS_UPD_COMMON Configuration for FSP spec. 2.4 and above. +/// +typedef struct { + /// + /// FSP_UPD_HEADER Configuration. + /// + FSP_UPD_HEADER FspUpdHeader; + + /// + /// FSPS_ARCH2_UPD Configuration. + /// + FSPS_ARCH2_UPD FspsArchUpd; +} FSPS_UPD_COMMON_FSP24; + /// /// Enumeration of FSP_INIT_PHASE for NOTIFY_PHASE. /// diff --git a/IntelFsp2Pkg/Tools/GenCfgOpt.py b/IntelFsp2Pkg/Tools/GenCfgOpt= .py index 714b2d8b1a..c4fb1f1bb2 100644 --- a/IntelFsp2Pkg/Tools/GenCfgOpt.py +++ b/IntelFsp2Pkg/Tools/GenCfgOpt.py @@ -1,6 +1,6 @@ ## @ GenCfgOpt.py # -# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.
# SPDX-License-Identifier: BSD-2-Clause-Patent # ## @@ -1398,6 +1398,7 @@ EndList UpdConfigCheck =3D ['FSP_T', 'FSP_M', 'FSP_S'] # FSP_X_CONFIG, FS= P_X_TEST_CONFIG, FSP_X_RESTRICTED_CONFIG UpdSignatureCheck =3D ['FSPT_UPD_SIGNATURE', 'FSPM_UPD_SIGNATURE',= 'FSPS_UPD_SIGNATURE'] ExcludedSpecificUpd =3D ['FSPT_ARCH_UPD', 'FSPM_ARCH_UPD', 'FSPS_A= RCH_UPD'] + ExcludedSpecificUpd1 =3D ['FSPT_ARCH2_UPD', 'FSPM_ARCH2_UPD', 'FSP= S_ARCH2_UPD'] =20 IncLines =3D [] if InputHeaderFile !=3D '': @@ -1452,7 +1453,7 @@ EndList if Match: StartIndex =3D Index - 1 Match =3D re.match("}\s([_A-Z0-9]+);", Line) - if Match and (UpdRegionCheck[item] in Match.group(1) or Up= dConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in= Match.group(1)): + if Match and (UpdRegionCheck[item] in Match.group(1) or Up= dConfigCheck[item] in Match.group(1)) and (ExcludedSpecificUpd[item] not in= Match.group(1)) and (ExcludedSpecificUpd1[item] not in Match.group(1)): EndIndex =3D Index StructStart.append(StartIndex) StructEnd.append(EndIndex) @@ -1695,7 +1696,7 @@ EndList =20 =20 def Usage(): - print ("GenCfgOpt Version 0.56") + print ("GenCfgOpt Version 0.57") print ("Usage:") print (" GenCfgOpt UPDTXT PlatformDscFile BuildFvDir = [-D Macros]") print (" GenCfgOpt HEADER PlatformDscFile BuildFvDir InputHFile = [-D Macros]") --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88930): https://edk2.groups.io/g/devel/message/88930 Mute This Topic: https://groups.io/mt/90482849/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-