From nobody Wed May 8 10:08:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+40517+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40517+1787277+3901457@groups.io ARC-Seal: i=1; a=rsa-sha256; t=1557758786; cv=none; d=zoho.com; s=zohoarc; b=n4kpFcHkE443ox0fC6fs+oCuHXfwq48u7d8gCf2tw+4srcOPVfL1JITKsMVY1rDGqc7GW0FtAEoAyB2EYCUX+ndczaw5gzc8JUfK8RasRF0XfyPDHJPCUXhG4k361ixR4ddOAx9ntSNP9MXw1pWSoU7A7AFUAoNbdyvgCHgX8c4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zoho.com; s=zohoarc; t=1557758786; h=Content-Type:Content-Transfer-Encoding:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To:ARC-Authentication-Results; bh=dIFEGXLYeGIYijCGGgE3EOXE0e/jHynkQpj2fT+46I0=; b=hlJlK0Qfq+VHMyP8lS3jWjQMaAZdUQCj+AcV4iQ9ay3nix7tW9WqB8gAvsqeIbvrVQluTXLjiHPcYZlPN16bWciEjpeReIDFjW9s5WjzccYgxf7gLFzyF1JHQufKDJSX4QTYilCznko6QaNykckyO6zG9kv+sKzHyyNIaRERLxI= ARC-Authentication-Results: i=1; mx.zoho.com; dkim=pass; spf=pass (zoho.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+40517+1787277+3901457@groups.io Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 155775878660198.24460971140877; Mon, 13 May 2019 07:46:26 -0700 (PDT) Return-Path: X-Received: from ZXSHCAS2.zhaoxin.com (ZXSHCAS2.zhaoxin.com [203.148.12.82]) by groups.io with SMTP; Mon, 13 May 2019 00:33:57 -0700 X-Received: from zxbjmbx2.zhaoxin.com (10.29.252.164) by ZXSHCAS2.zhaoxin.com (10.28.252.162) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 13 May 2019 15:35:07 +0800 X-Received: from zxbjmbx3.zhaoxin.com (10.29.252.165) by zxbjmbx2.zhaoxin.com (10.29.252.164) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1261.35; Mon, 13 May 2019 15:35:06 +0800 X-Received: from zxbjmbx3.zhaoxin.com ([fe80::57b:6f00:3193:d8a6]) by zxbjmbx3.zhaoxin.com ([fe80::57b:6f00:3193:d8a6%8]) with mapi id 15.01.1261.035; Mon, 13 May 2019 15:35:06 +0800 From: "Jerry Zhou(BJ-RD)" To: "devel@edk2.groups.io" Subject: =?UTF-8?B?W2VkazItZGV2ZWxdIOetlOWkjTogW2VkazJdIFtQQVRDSF0gSW50ZWxTaWxpY29uUGtnIFZUZER4ZTogYSBxdWVzdGlvbiBhYm91dCB0aGUgc291cmNlIGNvZGU=?= Thread-Topic: [edk2] [PATCH] IntelSiliconPkg VTdDxe: a question about the source code Thread-Index: AdUJNci9WEC63Y3xT7KjRAFsJUkP5QAKF1fw Date: Mon, 13 May 2019 07:35:06 +0000 Message-ID: Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.29.8.16] MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,JerryZhou@zhaoxin.com Content-Language: zh-CN Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1557758786; bh=dIFEGXLYeGIYijCGGgE3EOXE0e/jHynkQpj2fT+46I0=; h=Content-Type:Date:From:Reply-To:Subject:To; b=fIywlhXh+pevVX84q3mNXEHHNouBqC8iytnpMzRsTIDMnBCFe89LzVxoQJuDVtTlN+r dAFDT+isGbAsM0M0MG4MFAt5s9v6nsvICjBS5SNEzEds0YvvLYLJr/Xie9hAY4sp+W8K+ rsRWdWXqphD5K6lFkilwjVUUzwnWCd/CdY0= X-ZohoMail-DKIM: pass (identity @groups.io) Hi Star, I'am so interested in DMA protection in UEFI. It's a really good d= esign! But I have a question about the implemention of DisableDmar() in I= ntelSiliconPkg\feature\vtd\intelvtddxe\VtdReg.c Is it a typing error in the code segment below? // // Disable VTd // MmioWrite32 (mVtdUnitInformation[Index].VtdUnitBaseAddress + R_GCMD_REG= , B_GMCD_REG_SRTP); do { Reg32 =3D MmioRead32 (mVtdUnitInformation[Index].VtdUnitBaseAddress += R_GSTS_REG); =E3=80=80=E3=80=80} while((Reg32 & B_GSTS_REG_RTPS) =3D=3D 0); =E3=80=80=E3=80=80 =E3=80=80=E3=80=80The software should program the B_GMCD_REG_TE field in gl= obal command register and then poll the B_GSTS_REG_TE field in global statu= s register if the DMAR is expected to be disabled or enabled according to V= t-d specification. =E3=80=80=E3=80=80 Thanks Jerry Zhou Ext:892418 -----=E9=82=AE=E4=BB=B6=E5=8E=9F=E4=BB=B6----- =E5=8F=91=E4=BB=B6=E4=BA=BA: edk2-devel [mailto:edk2-devel-bounces@lists.01= .org] =E4=BB=A3=E8=A1=A8 Star Zeng =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2018=E5=B9=B410=E6=9C=8824=E6=97=A5 1= 1:32 =E6=94=B6=E4=BB=B6=E4=BA=BA: edk2-devel@lists.01.org =E6=8A=84=E9=80=81: Jiewen Yao; Star Zeng =E4=B8=BB=E9=A2=98: [edk2] [PATCH] IntelSiliconPkg VTdDxe: Option to force = no early access attr request REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D1272 To have high confidence in usage for platform, add option (BIT2 of PcdVTdPolicyPropertyMask) to force no IOMMU access attribute request recording before DMAR table is installed. Check PcdVTdPolicyPropertyMask BIT2 before RequestAccessAttribute() and ProcessRequestedAccessAttribute(), then RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables could be optimized by compiler when PcdVTdPolicyPropertyMask BIT2 =3D 1. Test done: 1: Created case that has IOMMU access attribute request before DMAR table is installed, ASSERT was triggered after setting PcdVTdPolicyPropertyMask BIT2 to 1. 2. Confirmed RequestAccessAttribute(), ProcessRequestedAccessAttribute() and mAccessRequestXXX variables were optimized by compiler after setting PcdVTdPolicyPropertyMask BIT2 to 1. Cc: Jiewen Yao Cc: Rangasai V Chaganty Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Star Zeng --- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c | 8 +++++++- IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c | 7 +++++++ IntelSiliconPkg/IntelSiliconPkg.dec | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c b/Inte= lSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c index 86d50eb6f288..7784545631b3 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/DmaProtection.c @@ -515,7 +515,13 @@ SetupVtd ( ParseDmarAcpiTableRmrr (); - ProcessRequestedAccessAttribute (); + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) =3D=3D 0) { + // + // Support IOMMU access attribute request recording before DMAR table = is installed. + // Here is to process the requests. + // + ProcessRequestedAccessAttribute (); + } for (Index =3D 0; Index < mVtdUnitNumber; Index++) { DEBUG ((DEBUG_INFO,"VTD Unit %d (Segment: %04x)\n", Index, mVtdUnitInf= ormation[Index].Segment)); diff --git a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c b/IntelS= iliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c index 25d7c80af1d4..09948ce50e94 100644 --- a/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c +++ b/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/IntelVTdDxe.c @@ -254,6 +254,13 @@ VTdSetAttribute ( // Record the entry to driver global variable. // As such once VTd is activated, the setting can be adopted. // + if ((PcdGet8 (PcdVTdPolicyPropertyMask) & BIT2) !=3D 0) { + // + // Force no IOMMU access attribute request recording before DMAR tab= le is installed. + // + ASSERT_EFI_ERROR (EFI_NOT_READY); + return EFI_NOT_READY; + } Status =3D RequestAccessAttribute (Segment, SourceId, DeviceAddress, L= ength, IoMmuAccess); } else { PERF_CODE ( diff --git a/IntelSiliconPkg/IntelSiliconPkg.dec b/IntelSiliconPkg/IntelSil= iconPkg.dec index b9646d773b95..900e8f63c64d 100644 --- a/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/IntelSiliconPkg/IntelSiliconPkg.dec @@ -64,6 +64,7 @@ [PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, Pc= dsDynamicEx] ## The mask is used to control VTd behavior.

# BIT0: Enable IOMMU during boot (If DMAR table is installed in DXE. If= VTD_INFO_PPI is installed in PEI.) # BIT1: Enable IOMMU when transfer control to OS (ExitBootService in no= rmal boot. EndOfPEI in S3) + # BIT2: Force no IOMMU access attribute request recording before DMAR t= able is installed. # @Prompt The policy for VTd driver behavior. gIntelSiliconPkgTokenSpaceGuid.PcdVTdPolicyPropertyMask|1|UINT8|0x000000= 02 -- 2.7.0.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel =E4=BF=9D=E5=AF=86=E5=A3=B0=E6=98=8E=EF=BC=9A =E6=9C=AC=E9=82=AE=E4=BB=B6=E5=90=AB=E6=9C=89=E4=BF=9D=E5=AF=86=E6=88=96=E4= =B8=93=E6=9C=89=E4=BF=A1=E6=81=AF=EF=BC=8C=E4=BB=85=E4=BE=9B=E6=8C=87=E5=AE= =9A=E6=94=B6=E4=BB=B6=E4=BA=BA=E4=BD=BF=E7=94=A8=E3=80=82=E4=B8=A5=E7=A6=81= =E5=AF=B9=E6=9C=AC=E9=82=AE=E4=BB=B6=E6=88=96=E5=85=B6=E5=86=85=E5=AE=B9=E5= =81=9A=E4=BB=BB=E4=BD=95=E6=9C=AA=E7=BB=8F=E6=8E=88=E6=9D=83=E7=9A=84=E6=9F= =A5=E9=98=85=E3=80=81=E4=BD=BF=E7=94=A8=E3=80=81=E5=A4=8D=E5=88=B6=E6=88=96= =E8=BD=AC=E5=8F=91=E3=80=82 CONFIDENTIAL NOTE: This email contains confidential or legally privileged information and is f= or the sole use of its intended recipient. Any unauthorized review, use, co= pying or forwarding of this email or the content of this email is strictly = prohibited. -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#40517): https://edk2.groups.io/g/devel/message/40517 Mute This Topic: https://groups.io/mt/31607817/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-