From nobody Sun Feb 8 12:14:47 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88472+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88472+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649264649; cv=none; d=zohomail.com; s=zohoarc; b=kBmFA4sQCfHdmaI8hWqESZfL+RqlbEAXc2JG+/cWMQi+4cR2DovwAVnCPpDvrJE54HbUynpSpGzr39p+XjD4Mo5cZL+oVMlOx3ZWgVAT0gHzKE2QLurAP+TnFxxyiHl5Q/iX721IQARY+/3pO3nG+DVoZWVgVIFI5WEXw6wdQGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649264649; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=yYfhdl+02I87Z95cHu3tTKtsdUW4sK5RRvGeUdHkuo8=; b=TIObNINgYNhsPIP/4249z3aKZEGiST4mit4tvqGUeppYPsRPCl2slGYp8dhkoee+2U6SV/JRBUL7cAk769Q43PS1FMVm7B2Kh31WrdfBlZYA0SOLwy/6NE52JrEkvy1/gsgp1L22r7bqQastIKckjcDA/8SukMQbl+BxYAt5KMo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88472+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649264649067510.7948789549549; Wed, 6 Apr 2022 10:04:09 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id eOgwYY1788612xWyDHiMDuqS; Wed, 06 Apr 2022 10:04:08 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web11.428.1649264645457619554 for ; Wed, 06 Apr 2022 10:04:07 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="347548654" X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="347548654" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:03:03 -0700 X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="642137821" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:03:02 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH v3 7/8] IntelFsp2WrapperPkg: BaseFspWrapperApiLib support for X64 Date: Thu, 7 Apr 2022 01:02:38 +0800 Message-Id: In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: JJ9RKvaxUk2s5Ue5Ball1mBGx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649264648; bh=nDFfBXoTL9NvRbJz6UgYY2yu5t8ON3i2Zzrtm3GV1HM=; h=Cc:Date:From:Reply-To:Subject:To; b=an6u7ryGiaCrFc3DznGo4uyFzyRH4B7Q9UlIhqJKV/9B8qYEATtaV8wBYUHrVP8a8M3 7HaT4S6HFn1csS3sWmluLnGZcsIxGzIHx8THMiRQ8/pZRnW7E3IaGa3v557vmm18HBEda znX+mPphBVqiAmYsAdN3qOjeCwgWRLS9fhU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649264650563100033 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 Add Execute64BitCode to execute 64bit code from long mode directly in PEI 64bit. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- .../BaseFspWrapperApiLib/FspWrapperApiLib.c | 42 +++++++++++++++++-= -- .../BaseFspWrapperApiLib/IA32/DispatchExecute.c | 21 ++++++++++ .../BaseFspWrapperApiLib/X64/DispatchExecute.c | 45 ++++++++++++++++++= +++- 3 files changed, 101 insertions(+), 7 deletions(-) diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApi= Lib.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c index 67faad927c..ba4fe3903e 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/FspWrapperApiLib.c @@ -13,7 +13,7 @@ #include =20 /** - Wrapper for a thunk to transition from long mode to compatibility mode = to execute 32-bit code and then transit back to + Wrapper for a thunk to transition from long mode to compatibility mode t= o execute 32-bit code and then transit back to long mode. =20 @param[in] Function The 32bit code entry to be executed. @@ -29,6 +29,22 @@ Execute32BitCode ( IN UINT64 Param2 ); =20 +/** + Wrapper to execute 64-bit code directly from long mode. + + @param[in] Function The 64bit code entry to be executed. + @param[in] Param1 The first parameter to pass to 64bit code. + @param[in] Param2 The second parameter to pass to 64bit code. + + @return EFI_STATUS. +**/ +EFI_STATUS +Execute64BitCode ( + IN UINT64 Function, + IN UINT64 Param1, + IN UINT64 Param2 + ); + /** Find FSP header pointer. =20 @@ -94,7 +110,11 @@ CallFspNotifyPhase ( =20 NotifyPhaseApi =3D (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspH= eader->NotifyPhaseEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); - Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)Notif= yPhaseParams, (UINTN)NULL); + if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) =3D= =3D FSP_IA32) { + Status =3D Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhase= Params, (UINTN)NULL); + } else { + Status =3D Execute64BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhase= Params, (UINTN)NULL); + } SetInterruptState (InterruptState); =20 return Status; @@ -127,7 +147,11 @@ CallFspMemoryInit ( =20 FspMemoryInitApi =3D (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + Fsp= Header->FspMemoryInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); - Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)F= spmUpdDataPtr, (UINTN)HobListPtr); + if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) =3D= =3D FSP_IA32) { + Status =3D Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDa= taPtr, (UINTN)HobListPtr); + } else { + Status =3D Execute64BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspmUpdDa= taPtr, (UINTN)HobListPtr); + } SetInterruptState (InterruptState); =20 return Status; @@ -158,7 +182,11 @@ CallTempRamExit ( =20 TempRamExitApi =3D (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + Fsp= Header->TempRamExitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); - Status =3D Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempR= amExitParam, (UINTN)NULL); + if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) =3D= =3D FSP_IA32) { + Status =3D Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExit= Param, (UINTN)NULL); + } else { + Status =3D Execute64BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExit= Param, (UINTN)NULL); + } SetInterruptState (InterruptState); =20 return Status; @@ -189,7 +217,11 @@ CallFspSiliconInit ( =20 FspSiliconInitApi =3D (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + F= spHeader->FspSiliconInitEntryOffset); InterruptState =3D SaveAndDisableInterrupts (); - Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN= )FspsUpdDataPtr, (UINTN)NULL); + if ((FspHeader->ImageAttribute & IMAGE_ATTRIBUTE_64BIT_MODE_SUPPORT) =3D= =3D FSP_IA32) { + Status =3D Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdD= ataPtr, (UINTN)NULL); + } else { + Status =3D Execute64BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspsUpdD= ataPtr, (UINTN)NULL); + } SetInterruptState (InterruptState); =20 return Status; diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/Dispatch= Execute.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchE= xecute.c index 4f6a8dd1a7..a22ed2d539 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute= .c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/IA32/DispatchExecute= .c @@ -49,3 +49,24 @@ Execute32BitCode ( =20 return Status; } + +/** + Wrapper for a thunk to transition from compatibility mode to long mode t= o execute 64-bit code and then transit back to + compatibility mode. + + @param[in] Function The 64bit code entry to be executed. + @param[in] Param1 The first parameter to pass to 64bit code. + @param[in] Param2 The second parameter to pass to 64bit code. + + @return EFI_STATUS. +**/ +EFI_STATUS +Execute64BitCode ( + IN UINT64 Function, + IN UINT64 Param1, + IN UINT64 Param2 + ) +{ + return EFI_UNSUPPORTED; +} + diff --git a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchE= xecute.c b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExe= cute.c index 2ee5bc3dd4..bae216f639 100644 --- a/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c +++ b/IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/X64/DispatchExecute.c @@ -1,5 +1,5 @@ /** @file - Execute 32-bit code in Long Mode. + Execute 64-bit code in Long Mode. Provide a thunk function to transition from long mode to compatibility m= ode to execute 32-bit code and then transit back to long mode. =20 @@ -12,6 +12,21 @@ #include #include =20 +/** + FSP API functions. + + @param[in] Param1 The first parameter to pass to 64bit code. + @param[in] Param2 The second parameter to pass to 64bit code. + + @return EFI_STATUS. +**/ +typedef +EFI_STATUS +(EFIAPI *FSP_FUNCTION)( + IN VOID *Param1, + IN VOID *Param2 + ); + #pragma pack(1) typedef union { struct { @@ -80,7 +95,7 @@ AsmExecute32BitCode ( ); =20 /** - Wrapper for a thunk to transition from long mode to compatibility mode = to execute 32-bit code and then transit back to + Wrapper for a thunk to transition from long mode to compatibility mode t= o execute 32-bit code and then transit back to long mode. =20 @param[in] Function The 32bit code entry to be executed. @@ -110,3 +125,29 @@ Execute32BitCode ( =20 return Status; } + +/** + Wrapper to execute 64-bit code directly from long mode. + + @param[in] Function The 64bit code entry to be executed. + @param[in] Param1 The first parameter to pass to 64bit code. + @param[in] Param2 The second parameter to pass to 64bit code. + + @return EFI_STATUS. +**/ +EFI_STATUS +Execute64BitCode ( + IN UINT64 Function, + IN UINT64 Param1, + IN UINT64 Param2 + ) +{ + FSP_FUNCTION EntryFunc; + EFI_STATUS Status; + + EntryFunc =3D (FSP_FUNCTION)(UINTN)(Function); + Status =3D EntryFunc ((VOID *)(UINTN)Param1, (VOID *)(UINTN)Param2); + + return Status; +} + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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