From nobody Sun Feb 8 22:33:42 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+55746+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55746+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1583919274; cv=none; d=zohomail.com; s=zohoarc; b=LxCTx2b1oCM2dVKBJZA4Wz69hzWk/AXpjB9bhNbF3sEmWJDRZupKfh7G+nn9Qu6IJo9pLNLfriuY9fOlfMLOQcKqGMcqXslWQeF9IuXDitXm/+5moI8zfdfjlV4Q8oMJAjGDtJr+OwWxGJl75MeID8CqZ3OQgDWTRGgtrqZlYVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583919274; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=lJnPhfntT1siUxW1N1VPBvzvzp3fEC6VL9fD74cp2/0=; b=RSUcrTOU7F7viKjKdnUGZqIP6qse/ZT8vu04kd8xM5Kk8CQscJpuZV2c+BMHv8UOL68TA/BdXGeRPH0Plv07p9fxZSYUdNzwQjoUqaHcg7LGAO1mqBlYeDufQhIaQMTvQjXua6BZhoHE0JCvZ8E2GE1bGtuf3LUcxWEHKuhuooU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+55746+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1583919274132762.8140781082344; Wed, 11 Mar 2020 02:34:34 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id BRZkYY1788612xNSSJgkkf78; Wed, 11 Mar 2020 02:34:33 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.4651.1583919272948017912 for ; Wed, 11 Mar 2020 02:34:33 -0700 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Mar 2020 02:34:32 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,540,1574150400"; d="scan'208";a="277307446" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga002.fm.intel.com with ESMTP; 11 Mar 2020 02:34:30 -0700 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Bob Feng , Liming Gao Subject: [edk2-devel] [Patch] Silicon/Intel/Tools: Add parameter for microcode alignment in FitGen. Date: Wed, 11 Mar 2020 17:34:28 +0800 Message-Id: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: MFX2ZDbROlcLgUTgbPEiDs1vx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583919273; bh=fUf3XSIBzriFTZeSvx4A2HWRcoAozi4gDIGj7EmkHpw=; h=Cc:Date:From:Reply-To:Subject:To; b=xK9hpKacmVHmZk6G+5l4JtpD9qD3vw9FRc3OeiefeGpbhWnc/otxv2yJ4GWb4u54ew9 lKU4+GpItq4P9e3ltW669jjZhUK/51PETnIHrkXS+Lfpz0tI//Ghe6ipYqTSDyv7zNNLv lfe2nHsfZ0FWPN693WYLkcFdjN3sdyOoPo4= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" The current FitGen has "-NA" parameter to indicate whether microcode is placed with an alignment, but it could only support 0x800 alignment: - With"-NA" means microcode is not aligned. - No "-NA" means Microcode is 0x800 aligned. There is no method to specify other alignment value. This patch add "-A" option to FitGen for to configure the alignment to a user specified value. The change is backward compatible as: - Only "-NA" means microcode is not aligned (same as before). - No "-NA" and No "-A" means Microcode is 0x800 aligned (same as before). - Only "-A" means microcode is aligned with specified value (new). Cc: Bob Feng Cc: Liming Gao Signed-off-by: Siyuan Fu Reviewed-by: Bob Feng --- Silicon/Intel/Tools/FitGen/FitGen.c | 35 +++++++++++++++++++---------- 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/Silicon/Intel/Tools/FitGen/FitGen.c b/Silicon/Intel/Tools/FitG= en/FitGen.c index 49ec33a7fd..75d8932d90 100644 --- a/Silicon/Intel/Tools/FitGen/FitGen.c +++ b/Silicon/Intel/Tools/FitGen/FitGen.c @@ -260,7 +260,8 @@ typedef struct { FIT_TABLE_CONTEXT_ENTRY BiosModule[MAX_BIOS_MODULE_ENTRY]; UINT32 BiosModuleVersion; FIT_TABLE_CONTEXT_ENTRY Microcode[MAX_MICROCODE_ENTRY]; - BOOLEAN MicrocodeAlignment; + BOOLEAN MicrocodeIsAligned; + UINT32 MicrocodeAlignValue; UINT32 MicrocodeVersion; FIT_TABLE_CONTEXT_ENTRY OptionalModule[MAX_OPTIONAL_ENTRY]; FIT_TABLE_CONTEXT_ENTRY PortModule[MAX_PORT_ENTRY]; @@ -325,6 +326,7 @@ Returns: "\t[-V ]\n" "\t[-F ] [-F ] [-V= ]\n" "\t[-NA]\n" + "\t[-A ]\n" "\t[-CLEAR]\n" "\t[-L ]\n" "\t[-I ]\n" @@ -357,7 +359,8 @@ Returns: printf ("\tMicrocodeGuid - Guid of Microcode Module.\n"); printf ("\tMicrocodeSlotSize - Occupied region size of each Microco= de binary.\n"); printf ("\tMicrocodeFfsGuid - Guid of FFS which is used to save Mi= crocode binary"); - printf ("\t-NA - No 0x800 aligned Microcode requireme= nt. No -NA means Microcode is 0x800 aligned.\n"); + printf ("\t-NA - No 0x800 aligned Microcode requireme= nt. No -NA means Microcode is aligned with option MicrocodeAlignment value.= \n"); + printf ("\tMicrocodeAlignment - HEX value of Microcode alignment. Ig= nored if \"-NA\" is specified. Default value is 0x800.\n"); printf ("\tRecordType - FIT entry record type. User should e= nsure it is ordered.\n"); printf ("\tRecordDataAddress - FIT entry record data address.\n"); printf ("\tRecordDataSize - FIT entry record data size.\n"); @@ -957,17 +960,25 @@ Returns: // if ((Index >=3D argc) || ((strcmp (argv[Index], "-NA") !=3D 0) && - (strcmp (argv[Index], "-na") !=3D 0)) ) { + (strcmp (argv[Index], "-na") !=3D 0) && + (strcmp (argv[Index], "-A") !=3D 0) && + (strcmp (argv[Index], "-a") !=3D 0))) { // // by pass // - gFitTableContext.MicrocodeAlignment =3D TRUE; - } else { + gFitTableContext.MicrocodeIsAligned =3D TRUE; + gFitTableContext.MicrocodeAlignValue =3D 0x800; + } else if ((strcmp (argv[Index], "-NA") =3D=3D 0) || (strcmp (argv[Index= ], "-na") =3D=3D 0)) { + gFitTableContext.MicrocodeIsAligned =3D FALSE; + gFitTableContext.MicrocodeAlignValue =3D 1; + Index +=3D 1; + } else if ((strcmp (argv[Index], "-A") =3D=3D 0) || (strcmp (argv[Index]= , "-a") =3D=3D 0)) { + gFitTableContext.MicrocodeIsAligned =3D TRUE; // - // no alignment + // Get alignment from parameter // - gFitTableContext.MicrocodeAlignment =3D FALSE; - Index +=3D 1; + gFitTableContext.MicrocodeAlignValue =3D xtoi (argv[Index + 1]);; + Index +=3D 2; } =20 // @@ -1159,8 +1170,8 @@ Returns: // // MCU might be put at 2KB alignment, if so, we need to ad= just the size as 2KB alignment. // - if (gFitTableContext.MicrocodeAlignment) { - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + M= ICROCODE_ALIGNMENT) & ~MICROCODE_ALIGNMENT; + if (gFitTableContext.MicrocodeIsAligned) { + MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + (= gFitTableContext.MicrocodeAlignValue - 1)) & ~(gFitTableContext.MicrocodeAl= ignValue - 1); } else { MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32)); } @@ -1537,8 +1548,8 @@ Returns: // // MCU might be put at 2KB alignment, if so, we need to adjust the= size as 2KB alignment. // - if (gFitTableContext.MicrocodeAlignment) { - MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + MICROCODE= _ALIGNMENT) & ~MICROCODE_ALIGNMENT; + if (gFitTableContext.MicrocodeIsAligned) { + MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32) + (gFitTabl= eContext.MicrocodeAlignValue - 1)) & ~(gFitTableContext.MicrocodeAlignValue= - 1); } else { MicrocodeSize =3D (*(UINT32 *)(MicrocodeBuffer + 32)); } --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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