From nobody Mon Feb 9 08:15:29 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88227+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88227+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1648597677; cv=none; d=zohomail.com; s=zohoarc; b=Kk8azAdEKSQxRmKwYOY1RjS4dJMuHA0BKJG2eHQCi9mI8nWRNQtmyyFoVYyFOujF3qQeePnkj0R/LGBD8miIA+baQ+YTwUy16t6LkECiospORyfMLzNKV7x370/LjEy9RCGVr+LWuFRVnYCTZG4MCaonlAUerlOjXNppenpZiyY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1648597677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=i2cPS3A1enkb6yM86QUt4ju7AQw7LgwOBAFo80HGwf8=; b=fPomg3HA3j360M6+zgYIiL8AGlnVSZV7ow2swq3W1mUsGMCrSBql6jD9S1H1uXY/t/rKZDqyDc3wHw3j35djLrooELcVAj8YQeHz/Tqlsb5bKcFu3IWaXnjmobw4MmHVjIk1aYG1hua2Xh/NRtFxKi0Jkht8rhSnuLSS8C+1t6U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88227+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1648597677844170.30205099314742; Tue, 29 Mar 2022 16:47:57 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id FaJBYY1788612xE8VxZ0BWuS; Tue, 29 Mar 2022 16:47:57 -0700 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.1145.1648597670632172204 for ; Tue, 29 Mar 2022 16:47:56 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10301"; a="259375252" X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="259375252" X-Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 16:47:55 -0700 X-IronPort-AV: E=Sophos;i="5.90,220,1643702400"; d="scan'208";a="521658671" X-Received: from zhangpen-mobl.ccr.corp.intel.com (HELO mxu9-mobl1.ccr.corp.intel.com) ([10.255.29.230]) by orsmga006-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2022 16:47:51 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V12 18/47] OvmfPkg/PlatformInitLib: Add hob functions Date: Wed, 30 Mar 2022 07:46:11 +0800 Message-Id: In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: bjJUH6jrDuxGivnkPaNQTOFcx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1648597677; bh=cn7gUlE+c2QygPPnWGoBcpmIbm4V7J6M6BK31T67ZCA=; h=Cc:Date:From:Reply-To:Subject:To; b=k/bn5MmvlopztEnGgp5+tz1yFDwEoLzzO5UpMBABCzhkUMwVmS8YA6NugcHtJokIraR meU2f6X0PadJ/IO9vtIps3RvSwUuC9jAbn4HZYhe0jF0BGD/di/0yhmSinvgQLqN8H+FS LOGl+/DVCnNW21caIvupviz0Tj48kbJK0h4= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1648597678570100001 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 In this patch of PlatformInitLib, below hob functions are introduced: - PlatformAddIoMemoryBaseSizeHob - PlatformAddIoMemoryRangeHob - PlatformAddMemoryBaseSizeHob - PlatformAddMemoryRangeHob - PlatformAddReservedMemoryBaseSizeHob They correspond the below functions in OvmfPkg/PlatformPei: - AddIoMemoryBaseSizeHob - AddIoMemoryRangeHob - AddMemoryBaseSizeHob - AddMemoryRangeHob - AddReservedMemoryBaseSizeHob After above hob functions are introduced in PlatformInitLib, OvmfPkg/PlatformPei is refactored with this library. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/Include/Library/PlatformInitLib.h | 36 ++++++ OvmfPkg/Library/PlatformInitLib/Platform.c | 106 ++++++++++++++++++ .../PlatformInitLib/PlatformInitLib.inf | 2 + OvmfPkg/PlatformPei/MemDetect.c | 20 ++-- OvmfPkg/PlatformPei/Platform.c | 101 ++--------------- OvmfPkg/PlatformPei/Platform.h | 31 ----- 6 files changed, 165 insertions(+), 131 deletions(-) create mode 100644 OvmfPkg/Library/PlatformInitLib/Platform.c diff --git a/OvmfPkg/Include/Library/PlatformInitLib.h b/OvmfPkg/Include/Li= brary/PlatformInitLib.h index 2ebac5ccb013..9b99d4c1f514 100644 --- a/OvmfPkg/Include/Library/PlatformInitLib.h +++ b/OvmfPkg/Include/Library/PlatformInitLib.h @@ -96,4 +96,40 @@ PlatformDebugDumpCmos ( VOID ); =20 +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ); + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ); + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ); + #endif // PLATFORM_INIT_LIB_H_ diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/P= latformInitLib/Platform.c new file mode 100644 index 000000000000..e41f230ff563 --- /dev/null +++ b/OvmfPkg/Library/PlatformInitLib/Platform.c @@ -0,0 +1,106 @@ +/**@file + + Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2011, Andrei Warkentin + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +// +// The package level header files this module uses +// +#include + +// +// The Library classes this module consumes +// +#include +#include +#include +#include +#include + +VOID +EFIAPI +PlatformAddIoMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddReservedMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize, + IN BOOLEAN Cacheable + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_RESERVED, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + (Cacheable ? + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : + 0 + ) | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddIoMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - Memor= yBase)); +} + +VOID +EFIAPI +PlatformAddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +VOID +EFIAPI +PlatformAddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryB= ase)); +} diff --git a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf b/OvmfPkg/= Library/PlatformInitLib/PlatformInitLib.inf index 4ea2da86274f..21813458cb59 100644 --- a/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf +++ b/OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf @@ -24,6 +24,7 @@ =20 [Sources] Cmos.c + Platform.c =20 [Packages] MdeModulePkg/MdeModulePkg.dec @@ -34,3 +35,4 @@ BaseLib DebugLib IoLib + HobLib diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 9c5bf240e3ba..e5e105f377dd 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -275,10 +275,10 @@ ScanOrAdd64BitE820Ram ( End =3D (E820Entry.BaseAddr + E820Entry.Length) & ~(UINT64)EFI_PAGE_MASK; if (Base < End) { - AddMemoryRangeHob (Base, End); + PlatformAddMemoryRangeHob (Base, End); DEBUG (( DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", + "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n", __FUNCTION__, Base, End @@ -816,8 +816,8 @@ QemuInitializeRamBelow1gb ( ) { if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); + PlatformAddReservedMemoryBaseSizeHob ( SMM_DEFAULT_SMBASE, MCH_DEFAULT_SMBASE_SIZE, TRUE /* Cacheable */ @@ -826,12 +826,12 @@ QemuInitializeRamBelow1gb ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" ); - AddMemoryRangeHob ( + PlatformAddMemoryRangeHob ( SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, BASE_512KB + BASE_128KB ); } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); + PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB); } } =20 @@ -889,14 +889,14 @@ QemuInitializeRam ( UINT32 TsegSize; =20 TsegSize =3D mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); + PlatformAddReservedMemoryBaseSizeHob ( LowerMemorySize - TsegSize, TsegSize, TRUE ); } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); + PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize); } =20 // @@ -908,7 +908,7 @@ QemuInitializeRam ( if (EFI_ERROR (Status)) { UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); if (UpperMemorySize !=3D 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 594891786440..62480c3c40e5 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -57,85 +57,6 @@ BOOLEAN mS3Supported =3D FALSE; =20 UINT32 mMaxCpuCount; =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - VOID MemMapInitialization ( VOID @@ -155,12 +76,12 @@ MemMapInitialization ( // // Video memory + Legacy BIOS region // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); + PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB); =20 if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ + PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ + PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } =20 @@ -194,20 +115,20 @@ MemMapInitialization ( // 0xFEE00000 LAPIC 1 MB // PciSize =3D 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); + PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); =20 - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); + PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); + PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); + PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); // // Note: there should be an // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); + // PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); // // call below, just like the one above for RCBA. However, Linux insists // that the MMCONFIG area be marked in the E820 or UEFI memory map as @@ -225,7 +146,7 @@ MemMapInitialization ( // is most definitely not RAM; so, as an exception, cover it with // uncacheable reserved memory right here. // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); + PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); BuildMemoryAllocationHob ( PciExBarBase, SIZE_256MB, @@ -233,7 +154,7 @@ MemMapInitialization ( ); } =20 - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); + PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), S= IZE_1MB); =20 // // On Q35, the IO Port space is available for PCI resource allocations f= rom diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..f193ff736549 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ =20 #include =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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