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14 Jun 2019 13:00:49 -0700 From: "Agyeman, Prince" To: devel@edk2.groups.io Cc: Liming Gao , David Y Wei , Michael Kubacki , Nate DeSimone , Chasel Chiu Subject: [edk2-devel] [edk2-platforms][PATCH] ClevoOpenBoardPkg: Added OS boot support Date: Fri, 14 Jun 2019 13:00:49 -0700 Message-Id: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prince.agyeman@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1560542451; bh=VBbp9JXKM7U5YtxRo9nrbGJgo2362CwwgqVEUyAiII8=; h=Cc:Date:From:Reply-To:Subject:To; b=UnLbGE1iffdFMtm1EzderG7wPj/I4WK/OwUhfNAcb6y+4TWkJ9/xX2pV+oBN1pKo/L4 H5U/RMWcd2k7T03dfFYOlrbgNN4OpfFlmffS/ScQZLRg0oQ0TSG5Z1gXhOg3tQzBhEDdm xnoZNLUb4MHoIqpxZ3DScZ3ahtJ1ORBpDqs= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" These changes add OS boot support to N1xxWU platforms Test: N1xxWU currently boots to windows 10 Cc: Liming Gao Cc: David Y Wei Cc: Michael Kubacki Cc: Nate DeSimone Cc: Chasel Chiu Co-authored-by: David Y Wei Signed-off-by: Agyeman Reviewed-by: Ankit Sinha Reviewed-by: Nate DeSimone --- .../Features/Tbt/TbtInit/Smm/TbtSmm.inf | 2 +- .../PeiPreMemSiliconPolicyNotifyLib.c | 103 +++ .../PeiPreMemSiliconPolicyNotifyLib.inf | 43 ++ .../PeiSaPolicyUpdatePreMem.c | 11 +- .../PeiSiliconPolicyUpdateLibFsp.inf | 3 + .../PeiMultiBoardInitPreMemLib.inf | 3 + .../BoardInitLib/PeiN1xxWUInitPreMemLib.c | 30 +- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc | 13 +- .../ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf | 2 +- .../N1xxWU/OpenBoardPkgPcd.dsc | 2 +- .../PlatformInitPei/PlatformInitPreMem.c | 640 ++++++++++++++++++ .../PlatformInitPei/PlatformInitPreMem.inf | 67 ++ 12 files changed, 899 insertions(+), 20 deletions(-) create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Libr= ary/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Libr= ary/PeiSiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c create mode 100644 Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platfo= rm/Intel/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf diff --git a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtS= mm.inf b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.i= nf index 3826cf589b..c08608ae76 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf +++ b/Platform/Intel/ClevoOpenBoardPkg/Features/Tbt/TbtInit/Smm/TbtSmm.inf @@ -44,7 +44,7 @@ =20 [Pcd] gBoardModuleTokenSpaceGuid.PcdSwSmiDTbtEnumerate ## CONSUMES - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength ## CONSUMES + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength ## CONSUMES =20 [FixedPcd] gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c b/Platform/Intel/C= levoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPre= MemSiliconPolicyNotifyLib.c new file mode 100644 index 0000000000..0fedd81cd0 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.c @@ -0,0 +1,103 @@ +/** @file + This library implements constructor function to register notify call back + when policy PPI installed. + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include + +/** + Callback function to update policy when policy PPI installed. + + @param[in] PeiServices General purpose services available to ev= ery PEIM. + @param[in] NotifyDescriptor The notification structure this PEIM reg= istered on install. + @param[in] Ppi The memory discovered PPI. Not used. + + @retval EFI_SUCCESS Succeeds. + @retval Others Error code returned by sub-functions. +**/ +EFI_STATUS +EFIAPI +SiPreMemPolicyPpiNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi; + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig; + + DEBUG ((DEBUG_INFO, "SiPreMemPolicyPpiNotify() Start\n")); + + Status =3D PeiServicesLocatePpi ( + &gSiPreMemPolicyPpiGuid, + 0, + NULL, + (VOID **)&SiPreMemPolicyPpi + ); + ASSERT_EFI_ERROR (Status); + if (SiPreMemPolicyPpi !=3D NULL) { + // + // Get requisite IP Config Blocks which needs to be used here + // + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig); + ASSERT_EFI_ERROR (Status); + + // + // Update SpdAddressTable policy when it is installed. + // + if (MiscPeiPreMemConfig !=3D NULL) { + MiscPeiPreMemConfig->SpdAddressTable[0] =3D PcdGet8 (PcdMrcSpdAddres= sTable0); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[0] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[0])); + MiscPeiPreMemConfig->SpdAddressTable[1] =3D PcdGet8 (PcdMrcSpdAddres= sTable1); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[1] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[1])); + MiscPeiPreMemConfig->SpdAddressTable[2] =3D PcdGet8 (PcdMrcSpdAddres= sTable2); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[2] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[2])); + MiscPeiPreMemConfig->SpdAddressTable[3] =3D PcdGet8 (PcdMrcSpdAddres= sTable3); + DEBUG ((DEBUG_INFO, "MiscPeiPreMemConfig->SpdAddressTable[3] 0x%x\n"= , MiscPeiPreMemConfig->SpdAddressTable[3])); + } + } + return Status; +} + +static EFI_PEI_NOTIFY_DESCRIPTOR mSiPreMemPolicyPpiNotifyList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMIN= ATE_LIST, + &gSiPreMemPolicyPpiGuid, + SiPreMemPolicyPpiNotify + } +}; + +/** + The library constructuor. + The function register a policy install notify callback. + + @param[in] ImageHandle The firmware allocated handle for the UEFI= image. + @param[in] SystemTable A pointer to the EFI system table. + + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now. + It will ASSERT on error for debug version. +**/ +EFI_STATUS +EFIAPI +PeiPreMemSiliconPolicyNotifyLibConstructor ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + // + // Register call back after PPI produced + // + Status =3D PeiServicesNotifyPpi (mSiPreMemPolicyPpiNotifyList); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf b/Platform/Intel= /ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiP= reMemSiliconPolicyNotifyLib.inf new file mode 100644 index 0000000000..13c12655f6 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyNotifyLib/PeiPreMemSiliconPolicyNotifyLib.inf @@ -0,0 +1,43 @@ +## @file +# Component information file for Silicon Policy Notify Library. +# This library implements constructor function to register notify call back +# when policy PPI installed. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiPreMemSiliconPolicyNotifyLib + FILE_GUID =3D 6D231E12-C088-47C8-8B16-61F07293EEF8 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D NULL + CONSTRUCTOR =3D PeiPreMemSiliconPolicyNotifyLibConstr= uctor + +[LibraryClasses] + BaseLib + +[Packages] + MdePkg/MdePkg.dec + KabylakeOpenBoardPkg/OpenBoardPkg.dec + KabylakeSiliconPkg/SiPkg.dec + +[Sources] + PeiPreMemSiliconPolicyNotifyLib.c + +[Guids] + gSaMiscPeiPreMemConfigGuid + +[Ppis] + gSiPreMemPolicyPpiGuid + +[Pcd] + # SPD Address Table + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c b/Platform/Intel/ClevoO= penBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPol= icyUpdatePreMem.c index 12d2b2cdb2..93d79c2313 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c @@ -39,8 +39,15 @@ PeiFspSaPolicyUpdatePreMem ( { VOID *Buffer; =20 - CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr00, (VOID *)(UINT= N)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); - CopyMem((VOID *)(UINTN)FspmUpd->FspmConfig.MemorySpdPtr10, (VOID *)(UINT= N)PcdGet32 (PcdMrcSpdData), PcdGet16 (PcdMrcSpdDataSize)); +// +// Update UPD:DqPinsInterleaved +// + FspmUpd->FspmConfig.DqPinsInterleaved =3D (UINT8)PcdGetBool(PcdMrcDqPins= Interleaved); + + // + // Update UPD:DqPinsInterleaved + // + FspmUpd->FspmConfig.CaVrefConfig =3D PcdGet8(PcdMrcCaVrefConfig); =20 DEBUG((DEBUG_INFO, "Updating Dq Byte Map and DQS Byte Swizzling Settings= ...\n")); Buffer =3D (VOID *) (UINTN) PcdGet32 (PcdMrcDqByteMap); diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf b/Platform/Intel= /ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/P= eiSiliconPolicyUpdateLibFsp.inf index 25531d3d7f..b9b9232692 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf @@ -96,6 +96,9 @@ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2Dram ## CONSUMES gBoardModuleTokenSpaceGuid.PcdMrcSpdData gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved =20 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable ## CONSUMES diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Lib= rary/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 8f73c2fa40..0f6be110c0 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPreMemLib.inf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiMulti= BoardInitPreMemLib.inf @@ -64,6 +64,9 @@ gBoardModuleTokenSpaceGuid.PcdMrcDqsMapCpu2DramSize gBoardModuleTokenSpaceGuid.PcdMrcSpdData gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize + gBoardModuleTokenSpaceGuid.PcdMrcCaVrefConfig + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleavedControl + gBoardModuleTokenSpaceGuid.PcdMrcDqPinsInterleaved =20 # PEG Reset By GPIO gBoardModuleTokenSpaceGuid.PcdPcie0WakeGpioNo diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/P= eiN1xxWUInitPreMemLib.c b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/B= oardInitLib/PeiN1xxWUInitPreMemLib.c index 10550baf8a..b8eb0e67c6 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UInitPreMemLib.c +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Library/BoardInitLib/PeiN1xxW= UInitPreMemLib.c @@ -44,6 +44,15 @@ GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistor= SklRvp1[SA_MRC_MAX_RCOMP // GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp1[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 40, 23, 40 }; =20 +// +// Reference RCOMP resistors on motherboard - for SKL RVP2 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompResistorSklRvp2[SA_MRC_MAX= _RCOMP] =3D { 121, 81, 100 }; +// +// RCOMP target values for RdOdt, WrDS, WrDSCmd, WrDSCtl, WrDSClk - for SK= L RVP2 +// +GLOBAL_REMOVE_IF_UNREFERENCED const UINT16 RcompTargetSklRvp2[SA_MRC_MAX_R= COMP_TARGETS] =3D { 100, 40, 20, 20, 26 }; + /** N 1XX WU board configuration init function for PEI pre-memory phase. =20 @@ -81,20 +90,17 @@ N1xxWUInitPreMem ( // PcdSet8S (PcdSaMiscUserBd, 5); =20 - PcdSet8S (PcdMrcSpdAddressTable0, 0xA2); - PcdSet8S (PcdMrcSpdAddressTable1, 0xA0); - PcdSet8S (PcdMrcSpdAddressTable2, 0xA2); - PcdSet8S (PcdMrcSpdAddressTable3, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0); + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2); + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4); + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6); =20 - PcdSet32S (PcdMrcDqByteMap, (UINTN) mDqByteMapSklRvp3); - PcdSet16S (PcdMrcDqByteMapSize, sizeof (mDqByteMapSklRvp3)); - PcdSet32S (PcdMrcDqsMapCpu2Dram, (UINTN) mDqsMapCpu2DramSklRvp3); - PcdSet16S (PcdMrcDqsMapCpu2DramSize, sizeof (mDqsMapCpu2DramSklRvp3)); - PcdSet32S (PcdMrcRcompResistor, (UINTN) RcompResistorSklRvp1); - PcdSet32S (PcdMrcRcompTarget, (UINTN) RcompTargetSklRvp1); =20 - PcdSet32S (PcdMrcSpdData, (UINTN) mSkylakeRvp3Spd110); - PcdSet16S (PcdMrcSpdDataSize, mSkylakeRvp3Spd110Size); + PcdSetBoolS(PcdMrcDqPinsInterleavedControl, TRUE); + PcdSetBoolS(PcdMrcDqPinsInterleaved, TRUE); + PcdSet32S(PcdMrcRcompResistor, (UINTN)RcompResistorSklRvp2); + PcdSet32S(PcdMrcRcompTarget, (UINTN)RcompTargetSklRvp2); + PcdSet8S(PcdMrcCaVrefConfig, 2); // DDR4 boards =20 PcdSetBoolS (PcdIoExpanderPresent, TRUE); =20 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc index 02ef06579b..f9deece846 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.dsc @@ -120,7 +120,7 @@ # # PEI phase common # - SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/PeiSerialPortLibSpiFlash= /PeiSerialPortLibSpiFlash.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLibNull= .inf DebugLib|MdeModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebug= LibReportStatusCode.inf FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrapp= erPlatformLib/PeiFspWrapperPlatformLib.inf !if $(TARGET) =3D=3D DEBUG @@ -209,7 +209,7 @@ # Platform # $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf - $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf { + $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/PlatformI= nitPei/PlatformInitPreMem.inf { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE BoardInitLib|$(PROJECT)/Library/BoardInitLib/PeiBoardInitPreMemLib.i= nf @@ -221,7 +221,14 @@ SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicy= InitLibDependency/PeiPreMemSiliconPolicyInitLibDependency.inf } - $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf{ + + # # + # Hook a library constructor to update some policy fields when policy = installed. + # + NULL|$(PROJECT)/FspWrapper/Library/PeiSiliconPolicyNotifyLib/PeiPreMem= SiliconPolicyNotifyLib.inf + } + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= { !if gBoardModuleTokenSpaceGuid.PcdMultiBoardSupport =3D=3D FALSE diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf b/Pla= tform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf index b16bf0fe4e..7d76257671 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkg.fdf @@ -234,7 +234,7 @@ INF MdeModulePkg/Core/Pei/PeiMain.inf !include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf =20 INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf -INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf +INF $(PROJECT)/Override/Platform/Intel/MinPlatformPkg/PlatformInit/Platfor= mInitPei/PlatformInitPreMem.inf INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf =20 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc b/= Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc index 7bb341a1dd..c6bce19856 100644 --- a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/OpenBoardPkgPcd.dsc @@ -43,7 +43,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1 =20 gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000 - gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gSiPkgTokenSpaceGuid.PcdSiPciExpressRegionLength|0x10000000 gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000 gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000 gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000 diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c b/Platfo= rm/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/Pl= atformInit/PlatformInitPei/PlatformInitPreMem.c new file mode 100644 index 0000000000..b784026c1b --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPl= atformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.c @@ -0,0 +1,640 @@ +/** @file + Source code file for Platform Init Pre-Memory PEI module + +Copyright (c) 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ); + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ); + +/** + + This function checks the memory range in PEI. + + @param PeiServices Pointer to PEI Services. + @param This Pei memory test PPI pointer. + @param BeginAddress Beginning of the memory address to be checked. + @param MemoryLength Bytes of memory range to be checked. + @param Operation Type of memory check operation to be performed. + @param ErrorAddress Return the address of the error memory address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. + +**/ +EFI_STATUS +EFIAPI +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ); + +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gEfiPeiMemoryDiscoveredPpiGuid, + (EFI_PEIM_NOTIFY_ENTRY_POINT) MemoryDiscoveredPpiNotifyCallback +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiListRecoveryBootM= ode =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiBootInRecoveryModePpiGuid, + NULL +}; + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_PPI_DESCRIPTOR mPpiBootMode =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gEfiPeiMasterBootModePpiGuid, + NULL +}; + +static PEI_BASE_MEMORY_TEST_PPI mPeiBaseMemoryTestPpi =3D { BaseMemory= Test }; + +static PEI_PLATFORM_MEMORY_SIZE_PPI mMemoryMemorySizePpi =3D { GetPlatfor= mMemorySize }; + +static EFI_PEI_PPI_DESCRIPTOR mMemPpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI, + &gPeiBaseMemoryTestPpiGuid, + &mPeiBaseMemoryTestPpi + }, + { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiPlatformMemorySizePpiGuid, + &mMemoryMemorySizePpi + }, +}; + +/// +/// Memory Reserved should be between 125% to 150% of the Current required= memory +/// otherwise BdsMisc.c would do a reset to make it 125% to avoid s4 resum= e issues. +/// +GLOBAL_REMOVE_IF_UNREFERENCED EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTy= peInformation[] =3D { + { EfiACPIReclaimMemory, FixedPcdGet32 (PcdPlatformEfiAcpiReclaimMemory= Size) }, // ASL + { EfiACPIMemoryNVS, FixedPcdGet32 (PcdPlatformEfiAcpiNvsMemorySize= ) }, // ACPI NVS (including S3 related) + { EfiReservedMemoryType, FixedPcdGet32 (PcdPlatformEfiReservedMemorySiz= e) }, // BIOS Reserved (including S3 related) + { EfiRuntimeServicesData, FixedPcdGet32 (PcdPlatformEfiRtDataMemorySize)= }, // Runtime Service Data + { EfiRuntimeServicesCode, FixedPcdGet32 (PcdPlatformEfiRtCodeMemorySize)= }, // Runtime Service Code + { EfiMaxMemoryType, 0 } +}; + +VOID +BuildMemoryTypeInformation ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariableServices; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + + // + // Locate system configuration variable + // + Status =3D PeiServicesLocatePpi( + &gEfiPeiReadOnlyVariable2PpiGuid, // GUID + 0, // INSTANCE + NULL, // EFI_PEI_PPI_DESCRIPTOR + (VOID **) &VariableServices // PPI + ); + ASSERT_EFI_ERROR(Status); + + DataSize =3D sizeof (MemoryData); + Status =3D VariableServices->GetVariable ( + VariableServices, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + if (EFI_ERROR(Status)) { + DataSize =3D sizeof (mDefaultMemoryTypeInformation); + CopyMem(MemoryData, mDefaultMemoryTypeInformation, DataSize); + } + + /// + /// Build the GUID'd HOB for DXE + /// + BuildGuidDataHob ( + &gEfiMemoryTypeInformationGuid, + MemoryData, + DataSize + ); +} + +EFI_STATUS +EFIAPI +GetPlatformMemorySize ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_PLATFORM_MEMORY_SIZE_PPI *This, + IN OUT UINT64 *MemorySize + ) +{ + EFI_STATUS Status; + EFI_PEI_READ_ONLY_VARIABLE2_PPI *Variable; + UINTN DataSize; + EFI_MEMORY_TYPE_INFORMATION MemoryData[EfiMaxMemoryType + 1]; + UINTN Index; + EFI_BOOT_MODE BootMode; + UINTN IndexNumber; + +#define PEI_MIN_MEMORY_SIZE (EFI_PHYSICAL_ADDRESS) ((320 * 0x1= 00000)) + + *MemorySize =3D PEI_MIN_MEMORY_SIZE; + Status =3D PeiServicesLocatePpi ( + &gEfiPeiReadOnlyVariable2PpiGuid, + 0, + NULL, + (VOID **)&Variable + ); + + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + DataSize =3D sizeof (MemoryData); + + Status =3D Variable->GetVariable ( + Variable, + EFI_MEMORY_TYPE_INFORMATION_VARIABLE_NAME, + &gEfiMemoryTypeInformationGuid, + NULL, + &DataSize, + &MemoryData + ); + IndexNumber =3D sizeof (mDefaultMemoryTypeInformation) / sizeof (EFI_MEM= ORY_TYPE_INFORMATION); + + // + // Accumulate maximum amount of memory needed + // + + DEBUG((DEBUG_ERROR, "PEI_MIN_MEMORY_SIZE:%dKB \n", DivU64x32(*MemorySize= ,1024))); + DEBUG((DEBUG_ERROR, "IndexNumber:%d MemoryDataNumber%d \n", IndexNumber,= DataSize/ sizeof (EFI_MEMORY_TYPE_INFORMATION))); + if (EFI_ERROR (Status)) { + // + // Start with minimum memory + // + for (Index =3D 0; Index < IndexNumber; Index++) { + DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,mDefaultMemoryTypeInformation[Index].Type,mDefaultMemoryTypeInformat= ion[Index].NumberOfPages)); + *MemorySize +=3D mDefaultMemoryTypeInformation[Index].NumberOfPages = * EFI_PAGE_SIZE; + } + DEBUG((DEBUG_ERROR, "No memory type, Total platform memory:%dKB \n", = DivU64x32(*MemorySize,1024))); + } else { + // + // Start with at least 0x200 pages of memory for the DXE Core and the = DXE Stack + // + for (Index =3D 0; Index < IndexNumber; Index++) { + DEBUG((DEBUG_ERROR, "Index[%d].Type =3D %d .NumberOfPages=3D0x%x\n",= Index,MemoryData[Index].Type,MemoryData[Index].NumberOfPages)); + *MemorySize +=3D MemoryData[Index].NumberOfPages * EFI_PAGE_SIZE; + + } + DEBUG((DEBUG_ERROR, "has memory type, Total platform memory:%dKB \n",= DivU64x32(*MemorySize,1024))); + } + + return EFI_SUCCESS; +} + +/** + + This function checks the memory range in PEI. + + @param PeiServices Pointer to PEI Services. + @param This Pei memory test PPI pointer. + @param BeginAddress Beginning of the memory address to be checked. + @param MemoryLength Bytes of memory range to be checked. + @param Operation Type of memory check operation to be performed. + @param ErrorAddress Return the address of the error memory address. + + @retval EFI_SUCCESS The operation completed successfully. + @retval EFI_DEVICE_ERROR Memory test failed. It's not safe to use thi= s range of memory. + +**/ +EFI_STATUS +EFIAPI +BaseMemoryTest ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_BASE_MEMORY_TEST_PPI *This, + IN EFI_PHYSICAL_ADDRESS BeginAddress, + IN UINT64 MemoryLength, + IN PEI_MEMORY_TEST_OP Operation, + OUT EFI_PHYSICAL_ADDRESS *ErrorAddress + ) +{ + UINT32 TestPattern; + UINT32 SpanSize; + EFI_PHYSICAL_ADDRESS TempAddress; + +#define MEMORY_TEST_PATTERN 0x5A5A5A5A +#define MEMORY_TEST_COVER_SPAN 0x40000 + + TestPattern =3D MEMORY_TEST_PATTERN; + SpanSize =3D 0; + + // + // Make sure we don't try and test anything above the max physical addre= ss range + // + ASSERT (BeginAddress + MemoryLength < MAX_ADDRESS); + + switch (Operation) { + case Extensive: + SpanSize =3D 0x4; + break; + + case Sparse: + case Quick: + SpanSize =3D MEMORY_TEST_COVER_SPAN; + break; + + case Ignore: + goto Done; + break; + } + // + // Write the test pattern into memory range + // + TempAddress =3D BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + (*(UINT32 *) (UINTN) TempAddress) =3D TestPattern; + TempAddress +=3D SpanSize; + } + // + // Read pattern from memory and compare it + // + TempAddress =3D BeginAddress; + while (TempAddress < BeginAddress + MemoryLength) { + if ((*(UINT32 *) (UINTN) TempAddress) !=3D TestPattern) { + *ErrorAddress =3D TempAddress; + return EFI_DEVICE_ERROR; + } + + TempAddress +=3D SpanSize; + } + +Done: + + return EFI_SUCCESS; +} + +/** + Set Cache Mtrr. +**/ +VOID +SetCacheMtrr ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_HOB_POINTERS Hob; + MTRR_SETTINGS MtrrSetting; + UINT64 MemoryBase; + UINT64 MemoryLength; + UINT64 LowMemoryLength; + UINT64 HighMemoryLength; + EFI_BOOT_MODE BootMode; + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; + UINT64 CacheMemoryLength; + + /// + /// Reset all MTRR setting. + /// + ZeroMem(&MtrrSetting, sizeof(MTRR_SETTINGS)); + + /// + /// Cache the Flash area as WP to boost performance + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + (UINTN) PcdGet32 (PcdFlashAreaBaseAddress), + (UINTN) PcdGet32 (PcdFlashAreaSize), + CacheWriteProtected + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer for Flash Region to be WP to bo= ost performance + /// + MtrrSetAllMtrrs (&MtrrSetting); + + /// + /// Set low to 1 MB. Since 1MB cacheability will always be set + /// until override by CSM. + /// Initialize high memory to 0. + /// + LowMemoryLength =3D 0x100000; + HighMemoryLength =3D 0; + ResourceAttribute =3D ( + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE + ); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + ResourceAttribute |=3D EFI_RESOURCE_ATTRIBUTE_TESTED; + } + + Status =3D PeiServicesGetHobList ((VOID **) &Hob.Raw); + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType =3D=3D EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM= _MEMORY) || + ((Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_MEMOR= Y_RESERVED) && + (Hob.ResourceDescriptor->ResourceAttribute =3D=3D ResourceAttri= bute)) + ) { + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000000ULL) { + HighMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } else if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + LowMemoryLength +=3D Hob.ResourceDescriptor->ResourceLength; + } + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + } + + DEBUG ((DEBUG_INFO, "Memory Length (Below 4GB) =3D %lx.\n", LowMemoryLen= gth)); + DEBUG ((DEBUG_INFO, "Memory Length (Above 4GB) =3D %lx.\n", HighMemoryLe= ngth)); + + /// + /// Assume size of main memory is multiple of 256MB + /// + MemoryLength =3D (LowMemoryLength + 0xFFFFFFF) & 0xF0000000; + MemoryBase =3D 0; + + CacheMemoryLength =3D MemoryLength; + /// + /// Programming MTRRs to avoid override SPI region with UC when MAX TOLU= D Length >=3D 3.5GB + /// + if (MemoryLength > 0xDC000000) { + CacheMemoryLength =3D 0xC0000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xC0000000; + CacheMemoryLength =3D MemoryLength - 0xC0000000; + if (MemoryLength > 0xE0000000) { + CacheMemoryLength =3D 0x20000000; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + MemoryBase =3D 0xE0000000; + CacheMemoryLength =3D MemoryLength - 0xE0000000; + } + } + + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + CacheMemoryLength, + CacheWriteBack + ); + ASSERT_EFI_ERROR (Status); + + if (LowMemoryLength !=3D MemoryLength) { + MemoryBase =3D LowMemoryLength; + MemoryLength -=3D LowMemoryLength; + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + MemoryBase, + MemoryLength, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + } + + /// + /// VGA-MMIO - 0xA0000 to 0xC0000 to be UC + /// + Status =3D MtrrSetMemoryAttributeInMtrrSettings ( + &MtrrSetting, + 0xA0000, + 0x20000, + CacheUncacheable + ); + ASSERT_EFI_ERROR (Status); + + /// + /// Update MTRR setting from MTRR buffer + /// + MtrrSetAllMtrrs (&MtrrSetting); + + return ; +} + +VOID +ReportCpuHob ( + VOID + ) +{ + UINT8 PhysicalAddressBits; + UINT32 RegEax; + + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); + if (RegEax >=3D 0x80000008) { + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); + PhysicalAddressBits =3D (UINT8) RegEax; + } else { + PhysicalAddressBits =3D 36; + } + + /// + /// Create a CPU hand-off information + /// + BuildCpuHob (PhysicalAddressBits, 16); +} + +/** + Install Firmware Volume Hob's once there is main memory + + @param[in] PeiServices General purpose services available to ever= y PEIM. + @param[in] NotifyDescriptor Notify that this module published. + @param[in] Ppi PPI that was installed. + + @retval EFI_SUCCESS The function completed successfully. +**/ +EFI_STATUS +EFIAPI +MemoryDiscoveredPpiNotifyCallback ( + IN CONST EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status =3D BoardInitAfterMemoryInit (); + ASSERT_EFI_ERROR (Status); + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + + ReportCpuHob (); + + TestPointMemoryDiscoveredMtrrFunctional (); + + TestPointMemoryDiscoveredMemoryResourceFunctional (); + + /// + /// If S3 resume, then we are done + /// + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + return EFI_SUCCESS; + } + + TestPointMemoryDiscoveredDmaProtectionEnabled (); + + if (PcdGetBool (PcdStopAfterMemInit)) { + CpuDeadLoop (); + } + + return Status; +} + + +/** + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p= roduced + + @param[in] PeiServices Pointer to PEI Services Table. + + @retval EFI_SUCCESS The function completes successfully + @retval others +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMem ( + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + // + // Start board detection + // + BoardDetect (); + + BoardDebugInit (); + + TestPointDebugInitDone (); + + if (PcdGetBool (PcdStopAfterDebugInit)) { + CpuDeadLoop (); + } + + BootMode =3D BoardBootModeDetect (); + Status =3D PeiServicesSetBootMode (BootMode); + ASSERT_EFI_ERROR (Status); + if (BootMode =3D=3D BOOT_IN_RECOVERY_MODE) { + Status =3D PeiServicesInstallPpi (&mPpiListRecoveryBootMode); + } + /// + /// Signal possible dependent modules that there has been a + /// final boot mode determination, it is used to build BIST + /// Hob for Dxe use. + /// + Status =3D PeiServicesInstallPpi (&mPpiBootMode); + ASSERT_EFI_ERROR (Status); + + BuildMemoryTypeInformation (); + + if (!PcdGetBool(PcdFspWrapperBootMode)) { + Status =3D PeiServicesInstallPpi (mMemPpiList); + ASSERT_EFI_ERROR (Status); + } + + Status =3D BoardInitBeforeMemoryInit (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + + +/** + Platform Init before memory PEI module entry point + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +PlatformInitPreMemEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + Status =3D PlatformInitPreMem (PeiServices); + + /// + /// After code reorangized, memorycallback will run because the PPI is a= lready + /// installed when code run to here, it is supposed that the InstallEfiM= emory is + /// done before. + /// + Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList); + + return Status; +} diff --git a/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Inte= l/MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf b/Plat= form/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPlatformPkg/= PlatformInit/PlatformInitPei/PlatformInitPreMem.inf new file mode 100644 index 0000000000..76dd67d1a8 --- /dev/null +++ b/Platform/Intel/ClevoOpenBoardPkg/N1xxWU/Override/Platform/Intel/MinPl= atformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf @@ -0,0 +1,67 @@ +### @file +# Component information file for the Platform Init Pre-Memory PEI module. +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PlatformInitPreMem + FILE_GUID =3D EEEE611D-F78F-4FB9-B868-55907F169280 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D PlatformInitPreMemEntryPoint + +[LibraryClasses] + BaseMemoryLib + BoardInitLib + DebugLib + HobLib + IoLib + MemoryAllocationLib + MtrrLib + PeimEntryPoint + PeiServicesLib + ReportFvLib + TestPointCheckLib + TimerLib + +[Packages] + MinPlatformPkg/MinPlatformPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[Pcd] + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit ## CONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit ## CONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize ## CO= NSUMES + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize ## CO= NSUMES + +[Sources] + PlatformInitPreMem.c + +[Ppis] + gEfiPeiMemoryDiscoveredPpiGuid + gEfiPeiMasterBootModePpiGuid ## PRODUCES + gEfiPeiBootInRecoveryModePpiGuid ## PRODUCES + gEfiPeiReadOnlyVariable2PpiGuid + gPeiBaseMemoryTestPpiGuid + gPeiPlatformMemorySizePpiGuid + +[Guids] + gEfiMemoryTypeInformationGuid + +[Depex] + gEfiPeiReadOnlyVariable2PpiGuid --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#42450): https://edk2.groups.io/g/devel/message/42450 Mute This Topic: https://groups.io/mt/32067747/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-