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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,lorena.r.de.leon.vazquez@intel.com X-Gm-Message-State: b9OEtka02Shp8oWV6ycssabLx1787277AA= Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1583236685; bh=9kAMZozfAbDNfUN+s/f/Gg3nhQ+tD3d3X9hxJjHRlZ0=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=Domxx6GrA/4MZFBozPMWitO9nW1POmXQxnr+w6BiaAytAiQRy2I0A5bVk9XMETm3o1y Gnt42q1PIb2oIxD6aNNA26LmvF8G1flozU1niKsviczJEmBOMeVVZO9Yw91LDPosZsYWO 1V8qg8SMuhc0HZ2KXGyIokJCDuCgggOisN0= X-ZohoMail-DKIM: pass (identity @groups.io) --_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_ Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Looks like Addresswidth is BIT wise values. Right now these values are not = used any Suggested-by: Star Zeng star.zeng@intel.com Signed-off-by: lorena.r.de.leon.vazquez@intel.com -- .../Feature/VTd/IntelVTdDxe/TranslationTable.c | 11 ++++------- .../Feature/VTd/IntelVTdDxe/TranslationTableEx.c | 11 ++++------- 2 files changed, 8 insertions(+), 14 deletions(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTable.c index cc970c0..61fbb4a 100644 Reviewed-by: jiewen.yao@intel.com Reviewed-by: jiewen.yao@intel.com --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= e.c @@ -128,14 +128,11 @@ CreateContextEntry ( DEBUG ((DEBUG_INFO,"Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInform= ation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.= Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Roo= tEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Translat= ionTableEx.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/Transl= ationTableEx.c index 0da1611..6bd31b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTabl= eEx.c @@ -78,14 +78,11 @@ CreateExtContextEntry ( DEBUG ((DEBUG_INFO,"DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInfor= mation[VtdIndex].Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId= .Bits.Function)); - switch (mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW) { - case BIT1: - ExtContextEntry->Bits.AddressWidth =3D 0x1; - break; - case BIT2: - ExtContextEntry->Bits.AddressWidth =3D 0x2; - break; + if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0)= { + DEBUG((DEBUG_ERROR, "!!!! 4-level page-table is not supported on VTD= %d !!!!\n", VtdIndex)); + return error; } + ContextEntry->Bits.AddressWidth =3D 0x2; } FlushPageTableMemory (VtdIndex, (UINTN)mVtdUnitInformation[VtdIndex].Ext= RootEntryTable, EFI_PAGES_TO_SIZE(EntryTablePages)); -- 2.21.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#55317): https://edk2.groups.io/g/devel/message/55317 Mute This Topic: https://groups.io/mt/71688474/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_SN6PR11MB2768E38BFE9F4860231C5CDAD9E70SN6PR11MB2768namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Looks like Addresswidth is BIT wise values. Right n= ow these values are not used any

 

Suggested-by: Sta= r Zeng star.zeng@intel.com<= /span>

Signed-off-by: lorena.r.de.leon.vaz= quez@intel.com

 

--

.../Feature/VTd/IntelVTdDxe/TranslationTable.c = ;       | 11 ++++-------=

.../Feature/VTd/IntelVTdDxe/TranslationTableEx.c&nb= sp;     | 11 ++++-------

2 files changed, 8 insertions(+), 14 deletions(= -)

 

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTable.c

index cc970c0..61fbb4a 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/TranslationTable.c

+++ b/Silicon/Intel/IntelSiliconPkg/Fea= ture/VTd/IntelVTdDxe/TranslationTable.c

@@ -128,14 +128,11 @@ CreateContextEntry (=

     DEBUG ((DEBUG_INFO,&q= uot;Source: S%04x B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex].= Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function));=

-    switch (mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ContextEntry->Bi= ts.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ContextEntry->Bi= ts.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vt= dIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ER= ROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n",= VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addre= ssWidth =3D 0x2;

   }

   FlushPageTableMemory (VtdIndex, (= UINTN)mVtdUnitInformation[VtdIndex].RootEntryTable, EFI_PAGES_TO_SIZE(Entry= TablePages));

diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/= VTd/IntelVTdDxe/TranslationTableEx.c b/Silicon/Intel/IntelSiliconPkg/Featur= e/VTd/IntelVTdDxe/TranslationTableEx.c

index 0da1611..6bd31b7 100644

--- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/Int= elVTdDxe/TranslationTableEx.c

+++ b/Silicon/Intel/IntelSiliconPkg/Fea= ture/VTd/IntelVTdDxe/TranslationTableEx.c

@@ -78,14 +78,11 @@ CreateExtContextEntry (

     DEBUG ((DEBUG_INFO,&q= uot;DOMAIN: S%04x, B%02x D%02x F%02x\n", mVtdUnitInformation[VtdIndex]= .Segment, SourceId.Bits.Bus, SourceId.Bits.Device, SourceId.Bits.Function))= ;

-    switch (mVtdUnitInformation[Vtd= Index].CapReg.Bits.SAGAW) {

-    case BIT1:

-      ExtContextEntry->= ;Bits.AddressWidth =3D 0x1;

-      break;

-    case BIT2:

-      ExtContextEntry->= ;Bits.AddressWidth =3D 0x2;

-      break;

+    if ((mVtdUnitInformation[Vt= dIndex].CapReg.Bits.SAGAW & BIT2) =3D=3D 0) {

+      DEBUG((DEBUG_ER= ROR, "!!!! 4-level page-table is not supported on VTD %d !!!!\n",= VtdIndex));

+      return error;

     }

+    ContextEntry->Bits.Addre= ssWidth =3D 0x2;

   }

   FlushPageTableMemory (VtdIndex, (= UINTN)mVtdUnitInformation[VtdIndex].ExtRootEntryTable, EFI_PAGES_TO_SIZE(En= tryTablePages));

--

2.21.0.windows.1

 

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