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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,zhiguang.liu@intel.com X-Gm-Message-State: jATrmQiBMpMTIYOhcSAxRv1Bx1787277AA= Content-Language: zh-CN Content-Type: multipart/alternative; boundary="_000_PH0PR11MB5048CDDC68A5506F831B204C90309PH0PR11MB5048namp_" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1623748570; bh=cAE6HzEdKB62rXQ5S0w5iIGzhnRggm6HfMtEy8N2dRQ=; h=Content-Type:Date:From:Reply-To:Subject:To; b=dsSE0Sm+e7S65JeHDkE/fctgHkJlL2rN57zLxspz0r2NkJGjow8aytRGnQsWi1V33Uc /42oBVpNy9ncishQmcFjr/HJKbR4fU8vpPoRElZYUjKtM+mSDmdfCXLmebpZjN4Zf6WaN bZD/hhDiaXV2j7SOD5HBeN4kKvof13O8QGY= X-ZohoMail-DKIM: pass (identity @groups.io) --_000_PH0PR11MB5048CDDC68A5506F831B204C90309PH0PR11MB5048namp_ Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Hi Hao, For this patch, can I keep your reviewed-by? I just added ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid C= I failure. Thanks Zhiguang ________________________________ =E5=8F=91=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io = =E4=BB=A3=E8=A1=A8 Zhiguang Liu =E5=8F=91=E9=80=81=E6=97=B6=E9=97=B4: 2021=E5=B9=B46=E6=9C=8815=E6=97=A5 17= :12 =E6=94=B6=E4=BB=B6=E4=BA=BA: devel@edk2.groups.io =E6=8A=84=E9=80=81: Kinney, Michael D ; Liming = Gao ; Wang, Jian J ; Wu, H= ao A =E4=B8=BB=E9=A2=98: [edk2-devel] [Patch V5 2/9] MdeModulePkg: Add new struc= ture for the PCI Root Bridge Info Hob V5: Add ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid open CI issue, because UID and HID are terms which are already used in current source code. Cc: Michael D Kinney Cc: Liming Gao Cc: Jian J Wang Cc: Hao A Wu Reviewed-by: Hao A Wu Signed-off-by: Zhiguang Liu Reviewed-by: Hao A Wu > --- MdeModulePkg/Include/UniversalPayload/PciRootBridges.h | 91 ++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ MdeModulePkg/MdeModulePkg.ci.yaml | 2 ++ MdeModulePkg/MdeModulePkg.dec | 6 ++++++ 3 files changed, 99 insertions(+) diff --git a/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h b/MdeMo= dulePkg/Include/UniversalPayload/PciRootBridges.h new file mode 100644 index 0000000000..3a7aae82d4 --- /dev/null +++ b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h @@ -0,0 +1,91 @@ +/** @file + This file defines the structure for the PCI Root Bridges. + + Copyright (c) 2021, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + + @par Revision Reference: + - Universal Payload Specification 0.75 (https://universalpayload.githu= b.io/documentation/) +**/ + +#ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_ +#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_ + +#include + +#pragma pack(1) + +// +// (Base > Limit) indicates an aperture is not available. +// +typedef struct { + // + // Base and Limit are the device address instead of host address when + // Translation is not zero + // + UINT64 Base; + UINT64 Limit; + // + // According to UEFI 2.7, Device Address =3D Host Address + Translation, + // so Translation =3D Device Address - Host Address. + // On platforms where Translation is not zero, the subtraction is probab= ly to + // be performed with UINT64 wrap-around semantics, for we may translate = an + // above-4G host address into a below-4G device address for legacy PCIe = device + // compatibility. + // + // NOTE: The alignment of Translation is required to be larger than any = BAR + // alignment in the same root bridge, so that the same alignment can be + // applied to both device address and host address, which simplifies the + // situation and makes the current resource allocation code in generic P= CI + // host bridge driver still work. + // + UINT64 Translation; +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE; + +/// +/// Payload PCI Root Bridge Information HOB +/// +typedef struct { + UINT32 Segment; ///< S= egment number. + UINT64 Supports; ///< S= upported attributes. + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes() + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + UINT64 Attributes; ///< I= nitial attributes. + ///< R= efer to EFI_PCI_ATTRIBUTE_xxx used by GetAttributes() + ///< a= nd SetAttributes() in EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + BOOLEAN DmaAbove4G; ///< D= MA above 4GB memory. + ///< S= et to TRUE when root bridge supports DMA above 4GB memory. + BOOLEAN NoExtendedConfigSpace; ///< W= hen FALSE, the root bridge supports + ///< E= xtended (4096-byte) Configuration Space. + ///< W= hen TRUE, the root bridge supports + ///< 2= 56-byte Configuration Space only. + UINT64 AllocationAttributes; ///< A= llocation attributes. + ///< R= efer to EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and + ///< E= FI_PCI_HOST_BRIDGE_MEM64_DECODE used by GetAllocAttributes() + ///< i= n EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus; ///< B= us aperture which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io; ///< I= O aperture which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem; ///< M= MIO aperture below 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< M= MIO aperture above 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem; ///< P= refetchable MMIO aperture below 4GB which can be used by the root bridge. + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< P= refetchable MMIO aperture above 4GB which can be used by the root bridge. + UINT32 HID; ///< P= nP hardware ID of the root bridge. This value must match the corresponding + ///< _= HID in the ACPI name space. + UINT32 UID; ///< U= nique ID that is required by ACPI if two devices have the same _HID. + ///< T= his value must also match the corresponding _UID/_HID pair in the ACPI name= space. +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE; + +typedef struct { + UNIVERSAL_PAYLOAD_GENERIC_HEADER Header; + BOOLEAN ResourceAssigned; + UINT8 Count; + UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE RootBridge[0]; +} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES; + +#pragma pack() + +#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1 + +extern GUID gUniversalPayloadPciRootBridgeInfoGuid; + +#endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_ diff --git a/MdeModulePkg/MdeModulePkg.ci.yaml b/MdeModulePkg/MdeModulePkg.= ci.yaml index 45783f12c1..4c71468bd3 100644 --- a/MdeModulePkg/MdeModulePkg.ci.yaml +++ b/MdeModulePkg/MdeModulePkg.ci.yaml @@ -16,6 +16,8 @@ ## "", "" ## ] "ExceptionList": [ + "8005", "UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE.UID", + "8005", "UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE.HID", ], ## Both file path and directory path are accepted. "IgnoreFiles": [ diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index 8d38383915..5cee4e159a 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -404,6 +404,12 @@ ## Include/Guid/MigratedFvInfo.h gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { 0xa2, 0xf4,= 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } } + # + # GUID defined in UniversalPayload + # + ## Include/UniversalPayload/PciRootBridges.h + gUniversalPayloadPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0x416e,= { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }} + [Ppis] ## Include/Ppi/AtaController.h gPeiAtaControllerPpiGuid =3D { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0,= 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x90, 0x6d }} -- 2.30.0.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76506): https://edk2.groups.io/g/devel/message/76506 Mute This Topic: https://groups.io/mt/83551777/1779286 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [zhiguang.liu@intel.com] -=3D-=3D-=3D-=3D-=3D-=3D -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#76514): https://edk2.groups.io/g/devel/message/76514 Mute This Topic: https://groups.io/mt/83551873/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- --_000_PH0PR11MB5048CDDC68A5506F831B204C90309PH0PR11MB5048namp_ Content-Type: text/html; charset="gb2312" Content-Transfer-Encoding: quoted-printable
Hi Hao,

For this patch, can I keep your reviewed-by?

I just added&n= bsp;ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid CI failure.

Thanks<= /div>
Zhiguang
=B7=A2=BC=FE=C8=CB: devel@= edk2.groups.io <devel@edk2.groups.io> =B4=FA=B1=ED Zhiguang Liu <z= higuang.liu@intel.com>
=B7=A2=CB=CD=CA=B1=BC=E4: 2021=C4=EA6=D4=C215=C8=D5 17:12
=CA=D5=BC=FE=C8=CB: devel@edk2.groups.io <devel@edk2.groups.io&g= t;
=B3=AD=CB=CD: Kinney, Michael D <michael.d.kinney@intel.com>;= Liming Gao <gaoliming@byosoft.com.cn>; Wang, Jian J <jian.j.wang@= intel.com>; Wu, Hao A <hao.a.wu@intel.com>
=D6=F7=CC=E2: [edk2-devel] [Patch V5 2/9] MdeModulePkg: Add new str= ucture for the PCI Root Bridge Info Hob
 
V5:
Add ExceptionList in MdeModulePkg\MdeModulePkg.ci.yaml, to avoid open CI issue, because UID and HID are terms which are already used in current
source code.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Reviewed-by: Hao A Wu <hao.a.wu@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
 MdeModulePkg/Include/UniversalPayload/PciRootBridges.h | 91 ++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++
 MdeModulePkg/MdeModulePkg.ci.yaml      = ;            &n= bsp;   |  2 ++
 MdeModulePkg/MdeModulePkg.dec      &nb= sp;            =        |  6 ++++++
 3 files changed, 99 insertions(+)

diff --git a/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h b/MdeM= odulePkg/Include/UniversalPayload/PciRootBridges.h
new file mode 100644
index 0000000000..3a7aae82d4
--- /dev/null
+++ b/MdeModulePkg/Include/UniversalPayload/PciRootBridges.h
@@ -0,0 +1,91 @@
+/** @file

+  This file defines the structure for the PCI Root Bridges.

+

+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR&= gt;

+  SPDX-License-Identifier: BSD-2-Clause-Patent

+

+  @par Revision Reference:

+    - Universal Payload Specification 0.75 (https://universalpayload.gi= thub.io/documentation/)

+**/

+

+#ifndef UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_

+#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_

+

+#include <UniversalPayload/UniversalPayload.h>

+

+#pragma pack(1)

+

+//

+// (Base > Limit) indicates an aperture is not available.

+//

+typedef struct {

+  //

+  // Base and Limit are the device address instead of host address w= hen

+  // Translation is not zero

+  //

+  UINT64 Base;

+  UINT64 Limit;

+  //

+  // According to UEFI 2.7, Device Address =3D Host Address + Transl= ation,

+  // so Translation =3D Device Address - Host Address.

+  // On platforms where Translation is not zero, the subtraction is = probably to

+  // be performed with UINT64 wrap-around semantics, for we may tran= slate an

+  // above-4G host address into a below-4G device address for legacy= PCIe device

+  // compatibility.

+  //

+  // NOTE: The alignment of Translation is required to be larger tha= n any BAR

+  // alignment in the same root bridge, so that the same alignment c= an be

+  // applied to both device address and host address, which simplifi= es the

+  // situation and makes the current resource allocation code in gen= eric PCI

+  // host bridge driver still work.

+  //

+  UINT64 Translation;

+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE;

+

+///

+/// Payload PCI Root Bridge Information HOB

+///

+typedef struct {

+  UINT32          =             &nb= sp;            =   Segment;          =      ///< Segment number.

+  UINT64          =             &nb= sp;            =   Supports;          = ;    ///< Supported attributes.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< Refer to EFI_PCI_ATTRIBUTE_xxx used b= y GetAttributes()

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< and SetAttributes() in EFI_PCI_ROOT_B= RIDGE_IO_PROTOCOL.

+  UINT64          =             &nb= sp;            =   Attributes;         &nb= sp;  ///< Initial attributes.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< Refer to EFI_PCI_ATTRIBUTE_xxx used b= y GetAttributes()

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< and SetAttributes() in EFI_PCI_ROOT_B= RIDGE_IO_PROTOCOL.

+  BOOLEAN          = ;            &n= bsp;            = ; DmaAbove4G;          &n= bsp; ///< DMA above 4GB memory.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< Set to TRUE when root bridge supports= DMA above 4GB memory.

+  BOOLEAN          = ;            &n= bsp;            = ; NoExtendedConfigSpace; ///< When FALSE, the root bridge supports

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< Extended (4096-byte) Configuration Sp= ace.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< When TRUE, the root bridge supports
+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< 256-byte Configuration Space only.
+  UINT64          =             &nb= sp;            =   AllocationAttributes;  ///< Allocation attributes.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< Refer to EFI_PCI_HOST_BRIDGE_COMBINE_= MEM_PMEM and

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE used= by GetAllocAttributes()

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< in EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOC= ATION_PROTOCOL.

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Bus;   &= nbsp;           &nbs= p;   ///< Bus aperture which can be used by the root bridge.
+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Io;   &n= bsp;            = ;    ///< IO aperture which can be used by the root bridg= e.

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE Mem;   &= nbsp;           &nbs= p;   ///< MMIO aperture below 4GB which can be used by the roo= t bridge.

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE MemAbove4G;  =           ///< MMIO apertur= e above 4GB which can be used by the root bridge.

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMem;   =             &nb= sp;  ///< Prefetchable MMIO aperture below 4GB which can be used by= the root bridge.

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE_APERTURE PMemAbove4G;  = ;         ///< Prefetchable MMIO= aperture above 4GB which can be used by the root bridge.

+  UINT32          =             &nb= sp;            =   HID;          &nbs= p;        ///< PnP hardware ID of the= root bridge. This value must match the corresponding

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< _HID in the ACPI name space.

+  UINT32          =             &nb= sp;            =   UID;          &nbs= p;        ///< Unique ID that is requ= ired by ACPI if two devices have the same _HID.

+            &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p;            &= nbsp;     ///< This value must also match the corres= ponding _UID/_HID pair in the ACPI name space.

+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE;

+

+typedef struct {

+  UNIVERSAL_PAYLOAD_GENERIC_HEADER   Header;

+  BOOLEAN          = ;            &n= bsp;     ResourceAssigned;

+  UINT8          &= nbsp;           &nbs= p;       Count;

+  UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE  RootBridge[0];

+} UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES;

+

+#pragma pack()

+

+#define UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_REVISION 1

+

+extern GUID gUniversalPayloadPciRootBridgeInfoGuid;

+

+#endif // UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGES_H_

diff --git a/MdeModulePkg/MdeModulePkg.ci.yaml b/MdeModulePkg/MdeModulePkg= .ci.yaml
index 45783f12c1..4c71468bd3 100644
--- a/MdeModulePkg/MdeModulePkg.ci.yaml
+++ b/MdeModulePkg/MdeModulePkg.ci.yaml
@@ -16,6 +16,8 @@
         ##    = ; "<ErrorID>", "<KeyWord>"

         ## ]

         "ExceptionList"= : [

+            "= 8005", "UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE.UID",

+            "= 8005", "UNIVERSAL_PAYLOAD_PCI_ROOT_BRIDGE.HID",

         ],

         ## Both file path and dir= ectory path are accepted.

         "IgnoreFiles": = [

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec=
index 8d38383915..5cee4e159a 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -404,6 +404,12 @@
   ## Include/Guid/MigratedFvInfo.h

   gEdkiiMigratedFvInfoGuid =3D { 0xc1ab12f7, 0x74aa, 0x408d, { = 0xa2, 0xf4, 0xc6, 0xce, 0xfd, 0x17, 0x98, 0x71 } }

 

+  #

+  # GUID defined in UniversalPayload

+  #

+  ## Include/UniversalPayload/PciRootBridges.h

+  gUniversalPayloadPciRootBridgeInfoGuid =3D { 0xec4ebacb, 0x2638, 0= x416e, { 0xbe, 0x80, 0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}

+

 [Ppis]

   ## Include/Ppi/AtaController.h

   gPeiAtaControllerPpiGuid       = = =3D { 0xa45e60d1, 0xc719, 0x44aa, { 0xb0, 0x7a, 0xaa, 0x77, 0x7f, 0x85, 0x= 90, 0x6d }}

--
2.30.0.windows.2



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