From nobody Sun Feb 8 15:42:52 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88468+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88468+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649264646; cv=none; d=zohomail.com; s=zohoarc; b=jKwPBxk8QGtFFlh3fzkIv7zVLNu+U4n4FKz0I7sqJpDQHDvaWxwS1xCfts1o6QucwK8qEFniDlIOIC+cxS0iHI4HTw60cLAu7ou8khDeFVrEhWMDC/4soWovBXhPGWnqoL+Ri51K7Ig2EUbHyjlkRsfNW5QoP1wCtyx9+TdYjqY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649264646; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=cytAE3bV+Snq2tXfqDDCDqjzTj5JKsyjXzYfHNmJYAk=; b=caXns1T5wrZ5jBBzdubC+gLLgtgu7h97HVVj1GkHa7Kf4O6HFjXc2QD2Vn6ols0otphPeXbU2tombIRe0nqYhc9OC7zHz/4dQ0IT09AQmuuzQirgtAx1AMayA1eZQiI10uuG+5uQNN90OKNcZtRZPTI/GhuXP05a6xW0QsxdaCg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88468+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649264646766782.6214844612612; Wed, 6 Apr 2022 10:04:06 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id x6jFYY1788612xbdMZHcR2Ck; Wed, 06 Apr 2022 10:04:06 -0700 X-Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by mx.groups.io with SMTP id smtpd.web09.431.1649264644096687714 for ; Wed, 06 Apr 2022 10:04:05 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10309"; a="347548612" X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="347548612" X-Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:02:58 -0700 X-IronPort-AV: E=Sophos;i="5.90,240,1643702400"; d="scan'208";a="642137751" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Apr 2022 10:02:56 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH v3 3/8] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64 Date: Thu, 7 Apr 2022 01:02:34 +0800 Message-Id: <9f8e6d30d79f5a3fbaa198eef91fdc70c151659e.1649264447.git.ted.kuo@intel.com> In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: MPbM5Ct1EvgI7RerD9MUBLNbx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649264646; bh=5/W5KJGErYzxUF7NFOL1amrAoac4x58UZOa5ZU/g3YE=; h=Cc:Date:From:Reply-To:Subject:To; b=aYjzFJ0ExMgpRAr1KnetEMkGOdb2D+/LNiCESetMbVDT3HwAVpnLalFL1OUoVap61sE x3nqRJIrqsSzS3eFHSEva62LNz4d5cqfMdxSTC2Tmm8wPFqzrtLvnfR9wqJOaEGtYCpJq qBQWEhm12w9jd2wtxLPq7lu0h8IdKDwFjk8= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649264648604100019 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support both IA32 and X64. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- IntelFsp2Pkg/Include/FspGlobalData.h | 51 +++++++++++++++++++++++++-------= ---- 2 files changed, 37 insertions(+), 16 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 85fbc7664c..1ead3c9ce6 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -130,7 +130,7 @@ FspGlobalDataInit ( ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA)); =20 PeiFspData->Signature =3D FSP_GLOBAL_DATA_SIGNATURE; - PeiFspData->Version =3D 0; + PeiFspData->Version =3D FSP_GLOBAL_DATA_VERSION; PeiFspData->CoreStack =3D BootLoaderStack; PeiFspData->PerfIdx =3D 2; PeiFspData->PerfSig =3D FSP_PERFORMANCE_DATA_SIGNATURE; diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 2b534075ae..dcfeed7501 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -10,8 +10,9 @@ =20 #include =20 -#define FSP_IN_API_MODE 0 -#define FSP_IN_DISPATCH_MODE 1 +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 +#define FSP_GLOBAL_DATA_VERSION 1 =20 #pragma pack(1) =20 @@ -28,10 +29,11 @@ typedef enum { =20 typedef struct { VOID *DataPtr; - UINT32 MicrocodeRegionBase; - UINT32 MicrocodeRegionSize; - UINT32 CodeRegionBase; - UINT32 CodeRegionSize; + UINTN MicrocodeRegionBase; + UINTN MicrocodeRegionSize; + UINTN CodeRegionBase; + UINTN CodeRegionSize; + UINTN Reserved; } FSP_PLAT_DATA; =20 #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') @@ -42,15 +44,15 @@ typedef struct { UINT32 Signature; UINT8 Version; UINT8 Reserved1[3]; + /// + /// Offset 0x08 + /// UINTN CoreStack; + UINTN Reserved2; + /// + /// IA32: Offset 0x10; X64: Offset 0x18 + /// UINT32 StatusCode; - UINT32 Reserved2[8]; - FSP_PLAT_DATA PlatformData; - FSP_INFO_HEADER *FspInfoHeader; - VOID *UpdDataPtr; - VOID *TempRamInitUpdPtr; - VOID *MemoryInitUpdPtr; - VOID *SiliconInitUpdPtr; UINT8 ApiIdx; /// /// 0: FSP in API mode; 1: FSP in DISPATCH mode @@ -60,15 +62,34 @@ typedef struct { UINT8 Reserved3; UINT32 NumberOfPhases; UINT32 PhasesExecuted; + UINT32 Reserved4[8]; /// + /// IA32: Offset 0x40; X64: Offset 0x48 + /// Start of UINTN and pointer section + /// All UINTN and pointer members must be put in this section + /// except CoreStack and Reserved2. In addition, the number of + /// UINTN and pointer members must be even for natural alignment + /// in both IA32 and X64. + /// + FSP_PLAT_DATA PlatformData; + VOID *TempRamInitUpdPtr; + VOID *MemoryInitUpdPtr; + VOID *SiliconInitUpdPtr; + /// + /// IA32: Offset 0x64; X64: Offset 0x90 /// To store function parameters pointer /// so it can be retrieved after stack switched. /// VOID *FunctionParameterPtr; - UINT8 Reserved4[16]; + FSP_INFO_HEADER *FspInfoHeader; + VOID *UpdDataPtr; + /// + /// End of UINTN and pointer section + /// + UINT8 Reserved5[16]; UINT32 PerfSig; UINT16 PerfLen; - UINT16 Reserved5; + UINT16 Reserved6; UINT32 PerfIdx; UINT64 PerfData[32]; } FSP_GLOBAL_DATA; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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