From nobody Mon Feb 9 06:50:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86372+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86372+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1643912628; cv=none; d=zohomail.com; s=zohoarc; b=bkKUhJQJ+wkhD+AMJVcjtsI/oxm2viWhGw05eWdOeGk0k/KVG+6D8LMgOsvjrWGoPxLVVZ/D6CqBE/PqCK8mtGVqscY5r+MGUd1QoxBp0G/A63maUYST1ISoxMrAmdoxGzXTjPCQLQqrFDufmep7cA4jOlxh0HwuXHvzqOO867Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1643912628; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=rQYfSGFvqAHD4VXSn2/1E0YtRWygW/O2zuXInQb4x0w=; b=PBaujGEZgsLMxVdTuzsP9x6XV0Bq8UPF0453CSld9chu2FeWKeiZZzHC0c2SQecNMqj50lCD4Lda4sS3qXyQMKKDzOoCa2Jp0DBI/k7lj3Oq+t33X+EJcjwB/hkjcdBxoakmV2sojl+EnjQSp5k4fq7YZp5Phs3Orwe+J3Pig9s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86372+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1643912628827381.52428558813256; Thu, 3 Feb 2022 10:23:48 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id w3LGYY1788612xGuTucU2Zml; Thu, 03 Feb 2022 10:23:48 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.1698.1643912626358852484 for ; Thu, 03 Feb 2022 10:23:47 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10247"; a="308943907" X-IronPort-AV: E=Sophos;i="5.88,340,1635231600"; d="scan'208";a="308943907" X-Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2022 10:17:28 -0800 X-IronPort-AV: E=Sophos;i="5.88,340,1635231600"; d="scan'208";a="631431431" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2022 10:17:26 -0800 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V2 2/2] WhitleyOpenBoardPkg/PlatformInfo: Add board ID vendor range Date: Thu, 3 Feb 2022 10:17:20 -0800 Message-Id: <9d90f627359e61a561704cd224535b4bce9e5cdb.1643911928.git.isaac.w.oram@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: 7SIe66g841ja3BgSNJsDc4ktx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1643912628; bh=/mHm8FtiLm/+Huq/VCgJZrH4Q5plpVxmjwLlZBORVI8=; h=Cc:Date:From:Reply-To:Subject:To; b=t0CMk9c/eaHgGKoaZdE0kz1W1AkhKD1+ljv5E9Ac2UWKDui3Q59tHFHD/gAqiaXYcEL k+UK/DI5oCrRFoOEilLL83imqdeBQ+Vwq0ZmlWGBRxlaobg6vuPTEKKKUmy6fgU8HLt8M c2l0uCbca7lPDKv3vthCo4UPZP5qWTfFx8M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1643912631343100007 Content-Type: text/plain; charset="utf-8" Add a vendor reserved range to avoid collisions with Intel reference board ID future use, if any. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram --- Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/PlatformInfo.= c | 3 +- Platform/Intel/WhitleyOpenBoardPkg/Readme.md = | 124 ++++++++++++++++++++ Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h = | 8 +- 3 files changed, 133 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/P= latformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInf= o/PlatformInfo.c index 87b4e57803..0065819d83 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c +++ b/Platform/Intel/WhitleyOpenBoardPkg/Platform/Pei/PlatformInfo/Platform= Info.c @@ -413,7 +413,8 @@ PdrGetPlatformInfo ( return Status; } =20 - if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax)) { + if ((PlatformInfoHob->BoardId >=3D TypePlatformMin) && (PlatformInfoHob-= >BoardId <=3D TypePlatformMax) || + (PlatformInfoHob->BoardId >=3D TypePlatformVendorMin) && (PlatformIn= foHob->BoardId <=3D TypePlatformVendorMax)) { // // Valid Platform Identified // diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Readme.md b/Platform/Intel/= WhitleyOpenBoardPkg/Readme.md new file mode 100644 index 0000000000..e8ceae858f --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Readme.md @@ -0,0 +1,124 @@ +# **Board Porting for Intel® Whitley Platform** + +## Overview +There are currently three board ports: +* WilsonCityRvp +* CooperCityRvp +* JunctionCity + +There are corresponding binaries in edk2-non-osi/WhitleyOpenBoardBinPkg. + +And there is a template for board porting, *BoardPortWhitley*. See below = for detailed instructions on creating a new board port. + +## BoardPortTemplate +This template profides basic instructions for how to customize the Whitley= OpenBoardPkg for a new system board. + +## Board Naming Conventions +The naming of boards within the filesystem is only loosely affiliated with= naming used in code. + +The convention *TypeBoardName* shows up in code in several ways: +* EFI_PLATFORM_TYPE enum, e.g. TypeJunctionCity +* UBA Protocol, e.g. gEfiPlatformTypeJunctionCityProtocolGuid +* Sometimes in an unused UBA PPI name +* Sometimes to decorate function and variable names. Consistently in UBA P= EI code to avoid name collision when multiple library class instances are s= upported. + +"BoardPortTemplate" is used in the board porting template for both board d= irectory name and within the consistent *TypeBoardName* code. + +There is no requirement for board directory naming to match code. The most= important thing is for developers to match the source code with their hard= ware. Consistency is desirable, but it is very common for one board port to= support multiple board and system products and thus consistent naming betw= een file system and code content is not required. + +## Board Porting Steps +It is desirable to pick a fairly unique name as WhitleyOpenBoardPkg UBA fe= ature is designed to make it easy to support many boards in a single binary. +For the purposes of this example, "MyBoard" is the board name in code and = filesystem. + +1. Copy WhitleyOpenBoardPkg/BoardPortTemplate to WhitleyOpenBoardPkg/MyBoa= rd +2. Rename WhitleyOpenBoardPkg/MyBoard/Uba/TypeBoardPortTemplate to Whitley= OpenBoardPkg/MyBoard/Uba/TypeMyBoard +3. Search and replace BoardPortTemplate with MyBoard in WhitleyOpenBoardPk= g/MyBoard. Do not search and replace at a higher scope as you will break t= he template examples. +4. Add a new EFI_PLATFORM_TYPE enum in edk2-platforms\Silicon\Intel\Whitle= ySiliconPkg\Include\PlatformInfoTypes.h, e.g. +``` +TypeMyBoard, // 0x80 +``` +Please update the comment for TypeBoardPortTemplate to match the new maxim= um used, e.g. +``` +TypeBoardPortTemplate // 0x81 +``` +5. Update the PcdBoardId for your board in the WhitleyOpenBoardPkg/MyBoard= /PlatformPkg.dsc, e.g. +``` +gPlatformTokenSpaceGuid.PcdBoardId|0x80 # TypeMyBoard +``` +6. Update each INF in WhitleyOpenBoardPkg/MyBoard/Uba with new GUID filena= me +7. Add a DXE UBA protocol GUID to WhitleyOpenBoardPkg/PlatformPkg.dec, *wi= th a new GUID* +``` +gEfiPlatformTypeMyBoardProtocolGuid =3D { 0xa68228c5, 0xc00f, 0x4d9a= , { 0x8d, 0xed, 0xb9, 0x6b, 0x9e, 0xef, 0xab, 0xca } } +``` +8. Add your board to the switch statement in BoardInitDxeDriverEntry (); i= n WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c +``` + case TypeMyBoard: + Status =3D gBS->InstallProtocolInterface ( + &Handle, + &gEfiPlatformTypeMyBoardProtocolGuid, + EFI_NATIVE_INTERFACE, + NULL + ); + ASSERT_EFI_ERROR (Status); + break; +``` +9. Add the gEfiPlatformTypeMyBoardProtocolGuid to the WhitleyOpenBoardPkg/= Uba/BoardInit/Dxe/BoardInitDxe.inf +10. Add a build option to edk2-platforms/Platform/Intel/build.cfg. e.g. +``` +MyBoard =3D WhitleyOpenBoardPkg/MyBoard/build_config.cfg +``` +11. At this point, you can build from edk2-platforms/Platform/Intel, e.g. +``` +build_bios.py -p MyBoard -t VS2015x86 -d +``` +12. At this point, customization is not scripted. The following are commo= n customization areas: +MyBoard/Uba/TypeBoardPortTemplate/Pei +* GPIO +* VR, IMON +* SKU info +* Board layout, sockets, memory +* Soft straps, PCH, config, USB OC +* PCI, KTI, IO port bifurcation +MyBoard/Uba/TypeBoardPortTemplate/Dxe +* IIO config update +* Slot config update +* USB overcurrent update + +## Board Builds + +**Building with the python script** + +1. Open command window, go to the workspace directory, e.g. c:\Edk2Workspa= ce or ~/Edk2Workspace in the case of a linux OS +2. If using a linux OS + * Type "cd edk2" + * Type "source edksetup.sh" + * Type "cd ../" to go back to the workspace directory +3. Type "cd edk2-platforms/Platform/Intel +4. Type "python build_bios.py -p TARGET_BOARD" + +* build_bios.py arguments: + + | Argument | Function | + | ----------------------|-------------------------------------| + | -h, --help | show this help message and exit | + | --platform, -p | the platform to build | + | --toolchain, -t | tool Chain to use in build process | + | --DEBUG, -d | debug flag | + | --RELEASE, -r | release flag | + | --TEST_RELEASE, -tr | test Release flag | + | --RELEASE_PDB, -rp | release flag | + | --list, -l | lists available platforms | + | --cleanall | cleans all | + | --clean | cleans specified platform | + | --capsule | capsule build enabled | + | --silent | silent build enabled | + | --performance | performance build enabled | + | --fsp | fsp wrapper build enabled | + | --fspapi | API mode fsp wrapper build enabled | + | --hash | Enable hash-based caching | + | --binary-destination | create cache in specified directory | + | --binary-source | Consume cache from directory | + | | + +* For more information on build options + * Type "python build_bios.py -h" diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/= Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h index fae3101336..bfc6a49138 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h @@ -65,13 +65,19 @@ typedef enum { TypeBigPineKey, TypeExperWorkStationRP, TypeJunctionCity, - EndOfEfiPlatformTypeEnum + EndOfEfiPlatformTypeEnum, + // + // Vendor board range currently starts at 0x80 + // + TypeBoardPortTemplate // 0x80 } EFI_PLATFORM_TYPE; =20 #define TypePlatformUnknown 0xFF #define TypePlatformMin StartOfEfiPlatformTypeEnum + 1 #define TypePlatformMax EndOfEfiPlatformTypeEnum - 1 #define TypePlatformDefault TypeWilsonPointRP +#define TypePlatformVendorMin 0x80 +#define TypePlatformVendorMax TypeBoardPortTemplate - 1 =20 // // CPU type: Standard (no MCP), -F, etc --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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