From nobody Thu Apr 18 08:13:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+54210+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+54210+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1581428648704310.2250323798821; Tue, 11 Feb 2020 05:44:08 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7ydsYY1788612x2GKDTNhKZB; Tue, 11 Feb 2020 05:44:07 -0800 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.10059.1581428647151793644 for ; Tue, 11 Feb 2020 05:44:07 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2020 05:44:06 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,428,1574150400"; d="scan'208";a="431961197" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga005.fm.intel.com with ESMTP; 11 Feb 2020 05:44:04 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Ray Ni , Rangasai V Chaganty Subject: [edk2-devel] [PATCH v2] IntelSiliconPkg: FIT based shadow microcode PPI support. Date: Tue, 11 Feb 2020 21:44:03 +0800 Message-Id: <98a64fcc12a49a2adfc394df7486d3737b775ce8.1581428584.git.siyuan.fu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: uCq6sJLNyiobUXpwVdCLrgpsx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1581428647; bh=EmxAKgTttHyQHUWe+uYEPeWQGymna5YWa1nKW02nT+c=; h=Cc:Date:From:Reply-To:Subject:To; b=tzl06+WVjfurXaSX24Q2LqMpeTz6xB1FBM/fdeCNIgXlGG0jQhvxjwcgRwFIICjnsOP KvL6SFoCf/ARQ+wUNw5bcrheEjYHc0TddsHKGKK6br1199ukYMW1ezttqeDQGxgmMhSxp LadUDCA2lwaqNCRpDJ6MtugkecuE5jzgK/U= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" V2 Changes: Rename EDKII_PEI_CPU_MICROCODE_ID to EDKII_PEI_MICROCODE_CPU_ID. Add missing files in V1 patch. This patch adds a platform PEIM for FIT based shadow microcode PPI support. A detailed design doc can be found here: https://edk2.groups.io/g/devel/files/Designs/2020/0214/Support%20 the%202nd%20Microcode%20FV%20Flash%20Region.pdf TEST: Tested on FIT enabled platform. BZ: https://tianocore.acgmultimedia.com/show_bug.cgi?id=3D2449 Cc: Ray Ni Cc: Rangasai V Chaganty Signed-off-by: Siyuan Fu --- .../ShadowMicrocode/ShadowMicrocodePei.c | 391 ++++++++++++++++++ .../ShadowMicrocode/ShadowMicrocodePei.h | 62 +++ .../ShadowMicrocode/ShadowMicrocodePei.inf | 46 +++ .../Include/Guid/MicrocodeShadowInfoHob.h | 57 +++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 13 + .../Intel/IntelSiliconPkg/IntelSiliconPkg.dsc | 3 +- 6 files changed, 571 insertions(+), 1 deletion(-) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/S= hadowMicrocodePei.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/S= hadowMicrocodePei.h create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/S= hadowMicrocodePei.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeSha= dowInfoHob.h diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.c b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shadow= MicrocodePei.c new file mode 100644 index 0000000000..80d71f8b09 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.c @@ -0,0 +1,391 @@ +/** @file + Source code file for Platform Init PEI module + +Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "ShadowMicrocodePei.h" + +EDKII_PEI_SHADOW_MICROCODE_PPI mPeiShadowMicrocodePpi =3D { + ShadowMicrocode +}; + + +EFI_PEI_PPI_DESCRIPTOR mPeiShadowMicrocodePpiList[] =3D { + { + EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST, + &gEdkiiPeiShadowMicrocodePpiGuid, + &mPeiShadowMicrocodePpi + } +}; + +/** + Determine if a microcode patch matchs the specific processor signature a= nd flag. + + @param[in] CpuIdCount Number of elements in MicrocodeCpuId a= rray. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MIC= ROCODE_CPU_ID + structures. + @param[in] ProcessorSignature The processor signature field value + supported by a microcode patch. + @param[in] ProcessorFlags The prcessor flags field value support= ed by + a microcode patch. + + @retval TRUE The specified microcode patch will be loaded. + @retval FALSE The specified microcode patch will not be loaded. +**/ +BOOLEAN +IsProcessorMatchedMicrocodePatch ( + IN UINTN CpuIdCount, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + IN UINT32 ProcessorSignature, + IN UINT32 ProcessorFlags + ) +{ + UINTN Index; + + for (Index =3D 0; Index < CpuIdCount; Index++) { + if ((ProcessorSignature =3D=3D MicrocodeCpuId[Index].ProcessorSignatur= e) && + (ProcessorFlags & (1 << MicrocodeCpuId[Index].PlatformId)) !=3D 0)= { + return TRUE; + } + } + + return FALSE; +} + +/** + Check the 'ProcessorSignature' and 'ProcessorFlags' of the microcode + patch header with the CPUID and PlatformID of the processors within + system to decide if it will be copied into memory. + + @param[in] CpuIdCount Number of elements in MicrocodeCpuId a= rray. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MIC= ROCODE_CPU_ID + structures. + @param[in] MicrocodeEntryPoint The pointer to the microcode patch hea= der. + + @retval TRUE The specified microcode patch need to be loaded. + @retval FALSE The specified microcode patch dosen't need to be loaded. +**/ +BOOLEAN +IsMicrocodePatchNeedLoad ( + IN UINTN CpuIdCount, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + CPU_MICROCODE_HEADER *MicrocodeEntryPoint + ) +{ + BOOLEAN NeedLoad; + UINTN DataSize; + UINTN TotalSize; + CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader; + UINT32 ExtendedTableCount; + CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable; + UINTN Index; + + // + // Check the 'ProcessorSignature' and 'ProcessorFlags' in microcode patc= h header. + // + NeedLoad =3D IsProcessorMatchedMicrocodePatch ( + CpuIdCount, + MicrocodeCpuId, + MicrocodeEntryPoint->ProcessorSignature.Uint32, + MicrocodeEntryPoint->ProcessorFlags + ); + + // + // If the Extended Signature Table exists, check if the processor is in = the + // support list + // + DataSize =3D MicrocodeEntryPoint->DataSize; + TotalSize =3D (DataSize =3D=3D 0) ? 2048 : MicrocodeEntryPoint->TotalSiz= e; + if ((!NeedLoad) && (DataSize !=3D 0) && + (TotalSize - DataSize > sizeof (CPU_MICROCODE_HEADER) + + sizeof (CPU_MICROCODE_EXTENDED_TABLE_HEADER)= )) { + ExtendedTableHeader =3D (CPU_MICROCODE_EXTENDED_TABLE_HEADER *) ((UINT= 8 *) (MicrocodeEntryPoint) + + DataSize + sizeof (CPU_MICROCODE_HEADER)); + ExtendedTableCount =3D ExtendedTableHeader->ExtendedSignatureCount; + ExtendedTable =3D (CPU_MICROCODE_EXTENDED_TABLE *) (ExtendedTabl= eHeader + 1); + + for (Index =3D 0; Index < ExtendedTableCount; Index ++) { + // + // Check the 'ProcessorSignature' and 'ProcessorFlag' of the Extended + // Signature Table entry with the CPUID and PlatformID of the proces= sors + // within system to decide if it will be copied into memory + // + NeedLoad =3D IsProcessorMatchedMicrocodePatch ( + CpuIdCount, + MicrocodeCpuId, + ExtendedTable->ProcessorSignature.Uint32, + ExtendedTable->ProcessorFlag + ); + if (NeedLoad) { + break; + } + ExtendedTable ++; + } + } + + return NeedLoad; +} + +/** + Actual worker function that shadows the required microcode patches into = memory. + + @param[in] Patches The pointer to an array of information= on + the microcode patches that will be loa= ded + into memory. + @param[in] PatchCount The number of microcode patches that w= ill + be loaded into memory. + @param[in] TotalLoadSize The total size of all the microcode pa= tches + to be loaded. + @param[out] BufferSize Pointer to receive the total size of B= uffer. + @param[out] Buffer Pointer to receive address of allocate= d memory + with microcode patches data in it. +**/ +VOID +ShadowMicrocodePatchWorker ( + IN MICROCODE_PATCH_INFO *Patches, + IN UINTN PatchCount, + IN UINTN TotalLoadSize, + OUT UINTN *BufferSize, + OUT VOID **Buffer + ) +{ + UINTN Index; + VOID *MicrocodePatchInRam; + UINT8 *Walker; + EDKII_MICROCODE_SHADOW_INFO_HOB *MicrocodeShadowHob; + UINTN HobDataLength; + UINT64 *MicrocodeAddrInMemory; + UINT64 *MicrocodeAddrInFlash; + + ASSERT ((Patches !=3D NULL) && (PatchCount !=3D 0)); + + // + // Init microcode shadow info HOB content. + // + HobDataLength =3D sizeof (EDKII_MICROCODE_SHADOW_INFO_HOB) + + sizeof (UINT64) * PatchCount * 2; + MicrocodeShadowHob =3D AllocatePool (HobDataLength); + if (MicrocodeShadowHob =3D=3D NULL) { + ASSERT (FALSE); + return; + } + MicrocodeShadowHob->MicrocodeCount =3D PatchCount; + CopyGuid ( + &MicrocodeShadowHob->StorageType, + &gEdkiiMicrocodeStorageTypeFlashGuid + ); + MicrocodeAddrInMemory =3D (UINT64 *) (MicrocodeShadowHob + 1); + MicrocodeAddrInFlash =3D MicrocodeAddrInMemory + PatchCount; + + // + // Allocate memory for microcode shadow operation. + // + MicrocodePatchInRam =3D AllocatePages (EFI_SIZE_TO_PAGES (TotalLoadSize)= ); + if (MicrocodePatchInRam =3D=3D NULL) { + ASSERT (FALSE); + return; + } + + // + // Shadow all the required microcode patches into memory + // + for (Walker =3D MicrocodePatchInRam, Index =3D 0; Index < PatchCount; In= dex++) { + CopyMem ( + Walker, + (VOID *) Patches[Index].Address, + Patches[Index].Size + ); + MicrocodeAddrInMemory[Index] =3D (UINT64) Walker; + MicrocodeAddrInFlash[Index] =3D (UINT64) Patches[Index].Address; + Walker +=3D Patches[Index].Size; + } + + // + // Update the microcode patch related fields in CpuMpData + // + *Buffer =3D (VOID *) (UINTN) MicrocodePatchInRam; + *BufferSize =3D TotalLoadSize; + + BuildGuidDataHob ( + &gEdkiiMicrocodeShadowInfoHobGuid, + MicrocodeShadowHob, + HobDataLength + ); + + DEBUG (( + DEBUG_INFO, + "%a: Required microcode patches have been loaded at 0x%lx, with size 0= x%lx.\n", + __FUNCTION__, *Buffer, *BufferSize + )); + + return; +} + +/** + Shadow the required microcode patches data into memory according + to FIT microcode entry. + +**/ +EFI_STATUS +ShadowMicrocodePatchByFit ( + IN UINTN CpuIdCount, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + OUT UINTN *BufferSize, + OUT VOID **Buffer + ) +{ + UINT64 FitPointer; + FIRMWARE_INTERFACE_TABLE_ENTRY *FitEntry; + UINT32 EntryNum; + UINT32 Index; + MICROCODE_PATCH_INFO *PatchInfoBuffer; + UINTN MaxPatchNumber; + CPU_MICROCODE_HEADER *MicrocodeEntryPoint; + UINTN PatchCount; + UINTN TotalSize; + UINTN TotalLoadSize; + + if (!FeaturePcdGet (PcdCpuShadowMicrocodeByFit)) { + return EFI_UNSUPPORTED; + } + + FitPointer =3D *(UINT64 *) (UINTN) FIT_POINTER_ADDRESS; + if ((FitPointer =3D=3D 0) || + (FitPointer =3D=3D 0xFFFFFFFFFFFFFFFF) || + (FitPointer =3D=3D 0xEEEEEEEEEEEEEEEE)) { + // + // No FIT table. + // + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + FitEntry =3D (FIRMWARE_INTERFACE_TABLE_ENTRY *) (UINTN) FitPointer; + if ((FitEntry[0].Type !=3D FIT_TYPE_00_HEADER) || + (FitEntry[0].Address !=3D FIT_TYPE_00_SIGNATURE)) { + // + // Invalid FIT table, treat it as no FIT table. + // + ASSERT (FALSE); + return EFI_NOT_FOUND; + } + + EntryNum =3D *(UINT32 *)(&FitEntry[0].Size[0]) & 0xFFFFFF; + + // + // Calculate microcode entry number + // + MaxPatchNumber =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + MaxPatchNumber++; + } + } + if (MaxPatchNumber =3D=3D 0) { + return EFI_NOT_FOUND; + } + + PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + if (PatchInfoBuffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + // + // Fill up microcode patch info buffer according to FIT table. + // + PatchCount =3D 0; + TotalLoadSize =3D 0; + for (Index =3D 0; Index < EntryNum; Index++) { + if (FitEntry[Index].Type =3D=3D FIT_TYPE_01_MICROCODE) { + MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[In= dex].Address; + TotalSize =3D (MicrocodeEntryPoint->DataSize =3D=3D 0) ? 2048 : Micr= ocodeEntryPoint->TotalSize; + if (IsMicrocodePatchNeedLoad (CpuIdCount, MicrocodeCpuId, MicrocodeE= ntryPoint)) { + PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntry= Point; + PatchInfoBuffer[PatchCount].Size =3D TotalSize; + TotalLoadSize +=3D TotalSize; + PatchCount++; + } + } + } + + if (PatchCount !=3D 0) { + DEBUG (( + DEBUG_INFO, + "%a: 0x%x microcode patches will be loaded into memory, with size 0x= %x.\n", + __FUNCTION__, PatchCount, TotalLoadSize + )); + + ShadowMicrocodePatchWorker (PatchInfoBuffer, PatchCount, TotalLoadSize= , BufferSize, Buffer); + } + + FreePool (PatchInfoBuffer); + return EFI_SUCCESS; +} + + +/** + Shadow microcode update patches to memory. + + The function is used for shadowing microcode update patches to a continu= ous memory. + It shall allocate memory buffer and only shadow the microcode patches fo= r those + processors specified by MicrocodeCpuId array. The checksum verification = may be + skiped in this function so the caller must perform checksum verification= before + using the microcode patches in returned memory buffer. + + @param[in] This The PPI instance pointer. + @param[in] CpuIdCount Number of elements in MicrocodeCpuId ar= ray. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICR= OCODE_CPU_ID + structures. + @param[out] BufferSize Pointer to receive the total size of Bu= ffer. + @param[out] Buffer Pointer to receive address of allocated= memory + with microcode patches data in it. + + @retval EFI_SUCCESS The microcode has been shadowed to memo= ry. + @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of reso= urces. + +**/ +EFI_STATUS +ShadowMicrocode ( + IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, + IN UINTN CpuIdCount, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + OUT UINTN *BufferSize, + OUT VOID **Buffer + ) +{ + if (BufferSize =3D=3D NULL || Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + return ShadowMicrocodePatchByFit (CpuIdCount, MicrocodeCpuId, BufferSize= , Buffer); +} + + +/** + Platform Init PEI module entry point + + @param[in] FileHandle Not used. + @param[in] PeiServices General purpose services available to e= very PEIM. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +ShadowMicrocodePeimInit ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + + // + // Install EDKII Shadow Microcode PPI + // + Status =3D PeiServicesInstallPpi(mPeiShadowMicrocodePpiList); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.h b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shadow= MicrocodePei.h new file mode 100644 index 0000000000..04fe7cbfd3 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.h @@ -0,0 +1,62 @@ +/** @file + Source code file for Platform Init PEI module + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __SHADOW_MICROCODE_PEI_H__ +#define __SHADOW_MICROCODE_PEI_H__ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +// +// Data structure for microcode patch information +// +typedef struct { + UINTN Address; + UINTN Size; +} MICROCODE_PATCH_INFO; + +/** + Shadow microcode update patches to memory. + + The function is used for shadowing microcode update patches to a continu= ous memory. + It shall allocate memory buffer and only shadow the microcode patches fo= r those + processors specified by MicrocodeCpuId array. The checksum verification = may be + skiped in this function so the caller must perform checksum verification= before + using the microcode patches in returned memory buffer. + + @param[in] This The PPI instance pointer. + @param[in] CpuIdCount Number of elements in MicrocodeCpuId ar= ray. + @param[in] MicrocodeCpuId A pointer to an array of EDKII_PEI_MICR= OCODE_CPU_ID + structures. + @param[out] BufferSize Pointer to receive the total size of Bu= ffer. + @param[out] Buffer Pointer to receive address of allocated= memory + with microcode patches data in it. + + @retval EFI_SUCCESS The microcode has been shadowed to memo= ry. + @retval EFI_OUT_OF_RESOURCES The operation fails due to lack of reso= urces. + +**/ +EFI_STATUS +ShadowMicrocode ( + IN EDKII_PEI_SHADOW_MICROCODE_PPI *This, + IN UINTN CpuIdCount, + IN EDKII_PEI_MICROCODE_CPU_ID *MicrocodeCpuId, + OUT UINTN *BufferSize, + OUT VOID **Buffer + ); + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMi= crocodePei.inf b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/Shad= owMicrocodePei.inf new file mode 100644 index 0000000000..fecb7c3904 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocode= Pei.inf @@ -0,0 +1,46 @@ +### @file +# Component information file for the Platform Init PEI module. +# +# Copyright (c) 2020, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D ShadowMicrocodePei + FILE_GUID =3D 8af4cf68-ebe4-4b21-a008-0cb3da277be5 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + ENTRY_POINT =3D ShadowMicrocodePeimInit + +[Sources] + ShadowMicrocodePei.c + +[LibraryClasses] + PeimEntryPoint + DebugLib + MemoryAllocationLib + BaseMemoryLib + HobLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Ppis] + gEdkiiPeiShadowMicrocodePpiGuid ## PRODUCES + +[Guids] + gEdkiiMicrocodeShadowInfoHobGuid + gEdkiiMicrocodeStorageTypeFlashGuid + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit + +[Depex] + TRUE diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfo= Hob.h b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h new file mode 100644 index 0000000000..59a38cee74 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Guid/MicrocodeShadowInfoHob.h @@ -0,0 +1,57 @@ +/** @file + The definition for VTD PMR Regions Information Hob. + + Copyright (c) 2019, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + + +#ifndef _MICROCODE_SHADOW_INFO_HOB_H_ +#define _MICROCODE_SHADOW_INFO_HOB_H_ + +/// +/// The Global ID of a GUIDed HOB used to pass microcode shadow info to DX= E Driver. +/// +#define EDKII_MICROCODE_SHADOW_INFO_HOB_GUID \ + { \ + 0x658903f9, 0xda66, 0x460d, { 0x8b, 0xb0, 0x9d, 0x2d, 0xdf, 0x65, 0x44= , 0x59 } \ + } + +extern EFI_GUID gEdkiiMicrocodeShadowInfoHobGuid; + +typedef struct { + // + // Number of the microcode patches which have been + // relocated to memory. + // + UINT64 MicrocodeCount; + // + // An EFI_GUID that defines the contents of StorageContext. + // + GUID StorageType; + // + // An array with MicrocodeCount elements that stores + // the shadowed microcode patch address in memory. + // + UINT64 MicrocodeAddrInMemory[0]; + // + // A buffer which contains details about the storage information + // specific to StorageType. + // + // UINT8 StorageContext[]; +} EDKII_MICROCODE_SHADOW_INFO_HOB; + +// +// An EDKII_MICROCODE_SHADOW_INFO_HOB with StorageType set to below GUID w= ill +// have the StorageContext of an array with MicrocodeCount of UINT64 eleme= nts +// that stores the original microcode patch address on flash. This address= is +// placed in same order as the microcode patches in MicrocodeAddrInMemory. +// +#define EFI_MICROCODE_STORAGE_TPYE_FLASH_GUID \ + { \ + 0x2cba01b3, 0xd391, 0x4598, { 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd= , 0x71 } \ + } + +extern EFI_GUID gEdkiiMicrocodeStorageTypeFlashGuid; + +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index 22ebf19c4e..ad093928b7 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -48,6 +48,12 @@ ## HOB GUID to get memory information after MRC is done. The hob data wi= ll be used to set the PMR ranges gVtdPmrInfoDataHobGuid =3D {0x6fb61645, 0xf168, 0x46be, { 0x80, 0xec, 0x= b5, 0x02, 0x38, 0x5e, 0xe7, 0xe7 } } =20 + ## Include/Guid/MicrocodeShadowInfoHob.h + gEdkiiMicrocodeShadowInfoHobGuid =3D { 0x658903f9, 0xda66, 0x460d, { 0x8= b, 0xb0, 0x9d, 0x2d, 0xdf, 0x65, 0x44, 0x59 } } + + ## Include/Guid/MicrocodeShadowInfoHob.h + gEdkiiMicrocodeStorageTypeFlashGuid =3D { 0x2cba01b3, 0xd391, 0x4598, { = 0x8d, 0x89, 0xb7, 0xfc, 0x39, 0x22, 0xfd, 0x71 } } + [Ppis] gEdkiiVTdInfoPpiGuid =3D { 0x8a59fcb3, 0xf191, 0x400c, { 0x97, 0x67, 0x6= 7, 0xaf, 0x2b, 0x25, 0x68, 0x4a } } =20 @@ -58,6 +64,13 @@ # Include/Protocol/PlatformDeviceSecurityPolicy.h gEdkiiDeviceSecurityPolicyProtocolGuid =3D {0x7ea41a99, 0x5e32, 0x4c97, = {0x88, 0xc4, 0xd6, 0xe7, 0x46, 0x84, 0x9, 0xd4}} =20 +[PcdsFeatureFlag] + ## Indicates if FIT based microcode shadowing will be enabled.

+ # TRUE - FIT base microcode shadowing will be enabled.
+ # FALSE - FIT base microcode shadowing will be disabled.
+ # @Prompt FIT based microcode shadowing. + gIntelSiliconPkgTokenSpaceGuid.PcdCpuShadowMicrocodeByFit|FALSE|BOOLEAN|= 0x00000006 + [PcdsFixedAtBuild, PcdsPatchableInModule] ## Error code for VTd error.

# EDKII_ERROR_CODE_VTD_ERROR =3D (EFI_IO_BUS_UNSPECIFIED | (EFI_OEM_SPE= CIFIC | 0x00000000)) =3D 0x02008000
diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dsc index 0a6509d8b3..f995883691 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dsc @@ -1,7 +1,7 @@ ## @file # This package provides common open source Intel silicon modules. # -# Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -84,6 +84,7 @@ IntelSiliconPkg/Feature/VTd/PlatformVTdInfoSamplePei/PlatformVTdInfoSamp= lePei.inf IntelSiliconPkg/Feature/Capsule/MicrocodeUpdateDxe/MicrocodeUpdateDxe.inf IntelSiliconPkg/Feature/Capsule/Library/MicrocodeFlashAccessLibNull/Micr= ocodeFlashAccessLibNull.inf + IntelSiliconPkg/Feature/ShadowMicrocode/ShadowMicrocodePei.inf IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/PeiFirmwareBootMediaLib.inf IntelSiliconPkg/Library/PeiDxeSmmBootMediaLib/DxeSmmFirmwareBootMediaLib= .inf =20 --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#54210): https://edk2.groups.io/g/devel/message/54210 Mute This Topic: https://groups.io/mt/71166911/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-