From nobody Mon Feb 9 00:06:56 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+86430+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86430+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1644260590; cv=none; d=zohomail.com; s=zohoarc; b=EOD88bcL2JnkpSUgvUXCXmsrGIeftiZ9c3Au9CiVcTRXKC9gBdTi1EJfwDoyk/2dmrCgp1k4g8eToxkWMoDA+Q0BQxsH+MtkvoPHkXpgg+9dx0CsDj8oxFlagIPOPPEB+WB/D6ktSaJyuUq95CFEYxpy+Ykjth6Edt8p0tUzOKU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1644260590; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uUDJSfhJFVcF8jWmsT8ebIJ5s+wDsz7gV5Ge1/xTk4k=; b=YhgoMAjIpbzaKOyWYrvCWCCLdPhxk529pzq10ACyXRNQbFKxGXF7eNPlS2CSDudRXQKDnsbdOtFJa8mCSucQWqdnuiRF2hDYonD3t6Hvm+uY6EZUJrtYdO1weIPxxUF2femOjaZ2oyWm6qeGOiM0wu0RvhY/22rWeb+CkS1Dvm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+86430+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 16442605902311001.2585215064597; Mon, 7 Feb 2022 11:03:10 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id FINuYY1788612xIURaw76U7u; Mon, 07 Feb 2022 11:03:09 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web12.444.1644260588103486600 for ; Mon, 07 Feb 2022 11:03:08 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10250"; a="248737314" X-IronPort-AV: E=Sophos;i="5.88,350,1635231600"; d="scan'208";a="248737314" X-Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2022 11:02:52 -0800 X-IronPort-AV: E=Sophos;i="5.88,350,1635231600"; d="scan'208";a="567583960" X-Received: from iworam-desk.amr.corp.intel.com ([10.7.150.79]) by orsmga001-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2022 11:02:52 -0800 From: "Oram, Isaac W" To: devel@edk2.groups.io Cc: Nate DeSimone , Chasel Chiu Subject: [edk2-devel][edk2-platforms][PATCH V1 7/8] WhitleyOpenBoardPkg/WilsonCityRvp: Generate AML offset table Date: Mon, 7 Feb 2022 11:02:44 -0800 Message-Id: <987586e418eca8caa7afd342ec344bf0897b444d.1644259969.git.isaac.w.oram@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,isaac.w.oram@intel.com X-Gm-Message-State: SBICXlVbn6FjWUw6IVmm3q65x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1644260589; bh=+Tx8NOLvPeCZmzu1fiymFYRDSDcRQDOZny0xwPXJOnU=; h=Cc:Date:From:Reply-To:Subject:To; b=nJTLKfa3EE+DFjhhI8Nc+BS7AoqLpTR4FF98nemAhBnV8VDf0YCp5PtdsKA+sHafCjW ZnU8sp8r7ckKS+CJgZnrbHvZvrSjZmuKqdfRBJFiUylQnpnn8Jr1WeNo3fX0eeiQ8jFCG tYIBB+XqiH09Z4nnlK9IHHdiSdiY0/vSN6M= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1644260592624100007 Content-Type: text/plain; charset="utf-8" Add PreBuild step to generate the AML offset table for the ACPI tables. Cc: Nate DeSimone Cc: Chasel Chiu Signed-off-by: Isaac Oram Reviewed-by: Nate DeSimone --- Platform/Intel/.gitignore = | 2 + Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc = | 41 +++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffsets.inf= | 26 ++++++++ Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py = | 63 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg = | 15 +++++ 5 files changed, 147 insertions(+) diff --git a/Platform/Intel/.gitignore b/Platform/Intel/.gitignore new file mode 100644 index 0000000000..548fee5bea --- /dev/null +++ b/Platform/Intel/.gitignore @@ -0,0 +1,2 @@ +WhitleyOpenBoardPkg/Uba/UbaMain/StaticSkuDataDxe/AmlOffsetTable.c +__init__.py diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.ds= c b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc new file mode 100644 index 0000000000..2e5ebf432a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets.dsc @@ -0,0 +1,41 @@ +## @file +# Build file for generating AML offset table +# +# @copyright +# Copyright (C) 2021 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + PLATFORM_NAME =3D $(RP_PKG) + PLATFORM_GUID =3D D7EAF54D-C9B9-4075-89F0-71943DBC= FA61 + PLATFORM_VERSION =3D 0.1 + DSC_SPECIFICATION =3D 0x00010005 + OUTPUT_DIRECTORY =3D Build/$(RP_PKG) + SUPPORTED_ARCHITECTURES =3D IA32|X64 + BUILD_TARGETS =3D DEBUG|RELEASE + PLATFORM_SI_PACKAGE =3D ClientOneSiliconPkg + DEFINE PLATFORM_SI_BIN_PACKAGE =3D WhitleySiliconBinPkg + PEI_ARCH =3D IA32 + DXE_ARCH =3D X64 + +!if $(CPUTARGET) =3D=3D "CPX" + DEFINE FSP_BIN_PKG =3D CedarIslandFspBinPkg + DEFINE IIO_INSTANCE =3D Skx +!elseif $(CPUTARGET) =3D=3D "ICX" + DEFINE FSP_BIN_PKG =3D WhitleyFspBinPkg + DEFINE IIO_INSTANCE =3D Icx +!else + DEFINE IIO_INSTANCE =3D UnknownCpu +!endif + + # + # Platform On/Off features are defined here + # + !include $(RP_PKG)/PlatformPkgConfig.dsc + +[Components.X64] + $(RP_PKG)/WilsonCityRvp/AmlOffsets/AmlOffsets.inf + +!include $(RP_PKG)/Include/Dsc/BuildOptions.dsc diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/Am= lOffsets.inf b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/= AmlOffsets.inf new file mode 100644 index 0000000000..8945f372e3 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets/AmlOffset= s.inf @@ -0,0 +1,26 @@ +## @file +# Generate AML offset table EPRPPlatform10nm.offset.h via edk2 build +# +# @copyright +# Copyright (C) 2022 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D AmlOffsets + FILE_GUID =3D d7641589-753a-44c5-91c2-bd09686205c6 + MODULE_TYPE =3D USER_DEFINED + VERSION_STRING =3D 1.0 + +[Sources] + WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt/EPRPPlatform10nm.asl + +[Packages] + MdePkg/MdePkg.dec + WhitleySiliconPkg/SiliconPkg.dec + +[BuildOptions] + # add -vr and -so to generate offset.h + *_*_*_ASL_FLAGS =3D -oi -vr -so diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.p= y b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py index a0c31e4558..5f625f5f92 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_board.py @@ -23,6 +23,7 @@ def pre_build_ex(config, functions): :returns: nothing """ print("pre_build_ex") + config["BUILD_DIR_PATH"] =3D os.path.join(config["WORKSPACE"], 'Build', config["PLATFORM_BOARD_PACKAGE= "], @@ -53,6 +54,68 @@ def pre_build_ex(config, functions): =20 if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") =3D=3D "TRUE": raise ValueError("FSP API Mode is currently unsupported on Ice Lak= e Xeon Scalable") + + # Build the ACPI AML offset table *.offset.h + print("Info: re-generating PlatformOffset header files") + + execute_script =3D functions.get("execute_script") + + command =3D ["build", "-D", "MAX_SOCKET=3D" + config["MAX_SOCKET"]] + + if config["EXT_BUILD_FLAGS"] and config["EXT_BUILD_FLAGS"] !=3D "": + ext_build_flags =3D config["EXT_BUILD_FLAGS"].split(" ") + ext_build_flags =3D [x.strip() for x in ext_build_flags] + ext_build_flags =3D [x for x in ext_build_flags if x !=3D ""] + command.extend(ext_build_flags) + + aml_offsets_split =3D os.path.split(os.path.normpath(config["AML_OFFSE= TS_PATH"])) + command.append("-p") + command.append(os.path.normpath(config["AML_OFFSETS_PATH"]) + '.dsc') + command.append("-m") + command.append(os.path.join(aml_offsets_split[0], aml_offsets_split[1]= , aml_offsets_split[1] + '.inf')) + command.append("-y") + command.append(os.path.join(config["WORKSPACE"], "PreBuildReport.txt")) + command.append("--log=3D" + os.path.join(config["WORKSPACE"], "PreBuil= d.log")) + + _, _, _, code =3D execute_script(command, config) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + # Build AmlGenOffset command to consume the *.offset.h and produce Aml= OffsetTable.c for StaticSkuDataDxe use. + + # Get destination path and filename from config + relative_file_path =3D os.path.normpath(config["STRIPPED_AML_OFFSETS_F= ILE_PATH"]) # get path relative to Platform/Intel + out_file_path =3D os.path.join(config["WORKSPACE_PLATFORM"], relative_= file_path) # full path to output file + out_file_dir =3D os.path.dirname(out_file_path) = # remove filename + + out_file_root_ext =3D os.path.splitext(os.path.basename(out_file_path)= ) # root and extension of output file + + # Get relative path for the generated offset.h file + relative_dsdt_file_path =3D os.path.normpath(config["DSDT_TABLE_FILE_P= ATH"]) # path relative to Platform/Intel + dsdt_file_root_ext =3D os.path.splitext(os.path.basename(relative_dsdt= _file_path)) # root and extension of generated offset.h file + + # Generate output directory if it doesn't exist + if not os.path.exists(out_file_dir): + os.mkdir(out_file_dir) + + command =3D ["python", + os.path.join(config["MIN_PACKAGE_TOOLS"], "AmlGenOffset", "= AmlGenOffset.py"), + "-d", "--aml_filter", config["AML_FILTER"], + "-o", out_file_path, + os.path.join(config["BUILD_X64"], aml_offsets_split[0], aml= _offsets_split[1], aml_offsets_split[1], "OUTPUT", os.path.dirname(relative= _dsdt_file_path), dsdt_file_root_ext[0] + ".offset.h")] + + # execute the command + _, _, _, code =3D execute_script(command, config) + if code !=3D 0: + print(" ".join(command)) + print("Error re-generating PlatformOffset header files") + sys.exit(1) + + print("GenOffset done") + + return None =20 def _merge_files(files, ofile): diff --git a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.= cfg b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg index 1676c08813..4cc9496153 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg +++ b/Platform/Intel/WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg @@ -34,3 +34,18 @@ FSP_BINARY_BUILD =3D FALSE FSP_TEST_RELEASE =3D FALSE SECURE_BOOT_ENABLE =3D FALSE BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807 + +# +# AML offset table generation configuration options +# All paths should use / and be relative to edk2-platforms/Platform/Intel +# +# AML_FILTER - AML filter is used to strip out unused= AML offset data +# AML_OFFSETS_PATH - Path to INF file that builds AML offse= ts C source file +# The directory name, DSC file name, INF file name, and BASE_NAME must m= atch identically +# DSDT_TABLE_FILE_PATH - Path to DSDT ASL file for the board +# STRIPPED_AML_OFFSETS_FILE_PATH - Target AML offset data file consumed b= y UBA driver +# +AML_FILTER =3D \"PSYS\" .\.DRVT\" .\.FIX[0-9,A-Z] BBI[0] BBU[0] CRCM BAR0 = .\.CCT[0-9A-Z]\" .\.CFH[0-9A-Z]\" .\.FXCD\" .\.FXST\" .\.FXIN\" .\.FXOU\" .= \.FXBS\" .\.FXFH\" .\.CENA\" .\.DRVT\" .\.CFIS\" {NULL }; +AML_OFFSETS_PATH =3D WhitleyOpenBoardPkg/WilsonCityRvp/AmlOffsets +DSDT_TABLE_FILE_PATH =3D WhitleyOpenBoardPkg/Features/Acpi/AcpiTables/Dsdt= /EPRPPlatform10nm.asl +STRIPPED_AML_OFFSETS_FILE_PATH =3D WhitleyOpenBoardPkg/Uba/UbaMain/StaticS= kuDataDxe/AmlOffsetTable.c --=20 2.27.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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