From nobody Sat Apr 20 06:13:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+96131+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+96131+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1667993481; cv=none; d=zohomail.com; s=zohoarc; b=ecKsbNQ87+G8cvDxyDYitBTVCKpKL9JBYlq2vfCKFUsQRpVkmkSSHYJtzDDtZ5zBKfaDVlfRQl3ooL+SRlbEU0D8aIIg+tdZUDLX9yDOGGEZucemmBUDvj0wrI9JAXhoA1ljZViP/XBR2Ycoq7QNzqMbmEelO7wODwo+/8Q9u40= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667993481; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=J5qlutV4ginxc8vLfxSRKm3PdFO8CCQ01WO8za5B8A0=; b=PWyEVEOHsI/CxZeDSt4eHcZEEquv158HdxSauvDyQ4il4FHcrEtjv3Id5MHmM+45EggGhT5s1+2dPmKhczva6QV4E+iRuCsuQIlNojn82akpFx2KOQcOqDFS2hRWMIoVoh/M9MUlCGbuRPzIzY/6SpGsnbTR4HiCyZcx1pvF8gg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+96131+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1667993481078909.4277315962631; Wed, 9 Nov 2022 03:31:21 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id 7QPEYY1788612xohRHF16i7K; Wed, 09 Nov 2022 03:31:20 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web11.2147.1667993479682229264 for ; Wed, 09 Nov 2022 03:31:19 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="312753426" X-IronPort-AV: E=Sophos;i="5.96,150,1665471600"; d="scan'208";a="312753426" X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 03:31:11 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10525"; a="639167475" X-IronPort-AV: E=Sophos;i="5.96,150,1665471600"; d="scan'208";a="639167475" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2022 03:31:09 -0800 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S , Chinni B Duggapu Subject: [edk2-devel][PATCH v1] IntelFsp2Pkg: Improvement of supporting null UPD pointer in FSP-T Date: Wed, 9 Nov 2022 19:30:57 +0800 Message-Id: <982993884529155a9bba1fa0a09a33301a0ded35.1667982515.git.ted.kuo@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: JRnuuqKexkke5CBtlINYwNtzx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667993480; bh=9XXpSSJtACI650CbZLUoX9OXDjUaryfQIL6pAY2+i68=; h=Cc:Date:From:Reply-To:Subject:To; b=osILRIQQCKsnQgog3rmVQhKnJ0jECuPx3P8pa65WYubAXAL1520dWRnGTPURBhYlVmH QP0Mokig3f8xjsZOL70l+dB+kr1Kz0ZCQaiWbblLNB0sRbEAf4uL5OeTXsr6GM4yC0IHA 5SxV1EoXaFN0Px9fTIvtFcSwkrvTei0BLUc= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667993481613100003 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4114 1.Use xmm5 slot 1 and xmm6 slot 3 to save ucode status and UPD pointer respectively in TempRamInitApi in IA32 FspSecCoreT. 2.Correct inappropriate description in the return value of AsmGetFspInfoHeader. 3.Replace hardcoded offset value 0x1C with FSP_HEADER_IMGBASE_OFFSET in FspHeler.nasm. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Signed-off-by: Ted Kuo Reviewed-by: Chasel Chiu Reviewed-by: Nate DeSimone --- .../FspSecCore/Ia32/FspApiEntryT.nasm | 17 +++-- IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm | 4 +- .../FspSecCore/Ia32/SaveRestoreSseNasm.inc | 74 ++++++++++--------- IntelFsp2Pkg/FspSecCore/SecFsp.h | 2 +- IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm | 4 +- 5 files changed, 55 insertions(+), 46 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/= FspSecCore/Ia32/FspApiEntryT.nasm index 73821ad22a..2cff8b3643 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm @@ -594,37 +594,38 @@ ASM_PFX(TempRamInitApi): SAVE_EAX SAVE_EDX =20 + CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + SAVE_ECX ; save UPD param to slot 3 in xmm6 + ; ; Sec Platform Init ; - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param CALL_MMX ASM_PFX(SecPlatformInit) cmp eax, 0 jnz TempRamInitExit =20 ; Load microcode LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + LOAD_ECX CALL_MMX ASM_PFX(LoadMicrocodeDefault) - SXMMN xmm6, 3, eax ;Save microcode return status in ECX-S= LOT 3 in xmm6. + SAVE_UCODE_STATUS ; Save microcode return status in slot= 1 in xmm5. ;@note If return value eax is not 0, microcode did not load, but continu= e and attempt to boot. =20 ; Call Sec CAR Init LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param + LOAD_ECX CALL_MMX ASM_PFX(SecCarInit) cmp eax, 0 jnz TempRamInitExit =20 LOAD_ESP - CALL_EBP ASM_PFX(LoadUpdPointerToECX) ; ECX for UPD param - mov edi, ecx ; Save UPD param to EDI for later= code use + LOAD_ECX + mov edi, ecx ; Save UPD param to EDI for later code= use CALL_MMX ASM_PFX(EstablishStackFsp) cmp eax, 0 jnz TempRamInitExit =20 - LXMMN xmm6, eax, 3 ;Restore microcode status if no CAR init error f= rom ECX-SLOT 3 in xmm6. - SXMMN xmm6, 3, edi ;Save FSP-T UPD parameter pointer in ECX-SLOT 3 = in xmm6. + LOAD_UCODE_STATUS ; Restore microcode status if no CAR i= nit error from slot 1 in xmm5. =20 TempRamInitExit: mov bl, al ; save al data in bl diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm b/IntelFsp2Pkg/Fsp= SecCore/Ia32/FspHelper.nasm index e3e1945473..3c63f6eea5 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspHelper.nasm @@ -7,6 +7,8 @@ =20 SECTION .text =20 +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch + global ASM_PFX(FspInfoHeaderRelativeOff) ASM_PFX(FspInfoHeaderRelativeOff): DD 0x12345678 ; This value must be patched by the buil= d script @@ -14,7 +16,7 @@ ASM_PFX(FspInfoHeaderRelativeOff): global ASM_PFX(AsmGetFspBaseAddress) ASM_PFX(AsmGetFspBaseAddress): call ASM_PFX(AsmGetFspInfoHeader) - add eax, 0x1C + add eax, FSP_HEADER_IMGBASE_OFFSET mov eax, dword [eax] ret =20 diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index 4c321cbece..a222f2e376 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; ; Abstract: @@ -16,21 +16,21 @@ ; ; Define SSE macros using SSE 4.1 instructions ; args 1:XMM, 2:IDX, 3:REG -%macro SXMMN 3 +%macro SXMMN 3 pinsrd %1, %3, (%2 & 3) %endmacro =20 ; ;args 1:XMM, 2:REG, 3:IDX ; -%macro LXMMN 3 +%macro LXMMN 3 pextrd %2, %1, (%3 & 3) %endmacro %else ; ; Define SSE macros using SSE 2 instructions ; args 1:XMM, 2:IDX, 3:REG -%macro SXMMN 3 +%macro SXMMN 3 pinsrw %1, %3, (%2 & 3) * 2 ror %3, 16 pinsrw %1, %3, (%2 & 3) * 2 + 1 @@ -38,19 +38,19 @@ %endmacro =20 ; -;args 1:XMM, 2:REG, 3:IDX +;args 1:XMM, 2:REG, 3:IDX ; %macro LXMMN 3 - pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh) + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2)) & 0FFh) movd %2, %1 - pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FF= h) + pshufd %1, %1, ((0E4E4E4h >> (%3 * 2 + (%3 & 1) * 4)) & 0FFh) %endmacro %endif =20 ; -; XMM7 to save/restore EBP, EBX, ESI, EDI +; XMM7 to save/restore EBP - slot 0, EBX - slot 1, ESI - slot 2, EDI - slo= t 3 ; -%macro SAVE_REGS 0 +%macro SAVE_REGS 0 SXMMN xmm7, 0, ebp SXMMN xmm7, 1, ebx SXMMN xmm7, 2, esi @@ -67,63 +67,67 @@ %endmacro =20 ; -; XMM6 to save/restore EAX, EDX, ECX, ESP +; XMM6 to save/restore ESP - slot 0, EAX - slot 1, EDX - slot 2, ECX - slo= t 3 ; -%macro LOAD_EAX 0 +%macro LOAD_ESP 0 + movd esp, xmm6 + %endmacro + +%macro SAVE_ESP 0 + SXMMN xmm6, 0, esp + %endmacro + +%macro LOAD_EAX 0 LXMMN xmm6, eax, 1 %endmacro =20 -%macro SAVE_EAX 0 +%macro SAVE_EAX 0 SXMMN xmm6, 1, eax %endmacro =20 -%macro LOAD_EDX 0 +%macro LOAD_EDX 0 LXMMN xmm6, edx, 2 %endmacro =20 -%macro SAVE_EDX 0 +%macro SAVE_EDX 0 SXMMN xmm6, 2, edx %endmacro =20 -%macro SAVE_ECX 0 - SXMMN xmm6, 3, ecx - %endmacro - -%macro LOAD_ECX 0 +%macro LOAD_ECX 0 LXMMN xmm6, ecx, 3 %endmacro =20 -%macro SAVE_ESP 0 - SXMMN xmm6, 0, esp +%macro SAVE_ECX 0 + SXMMN xmm6, 3, ecx %endmacro =20 -%macro LOAD_ESP 0 - movd esp, xmm6 - %endmacro ; -; XMM5 for calling stack +; XMM5 slot 0 for calling stack ; arg 1:Entry %macro CALL_XMM 1 mov esi, %%ReturnAddress - pslldq xmm5, 4 -%ifdef USE_SSE41_FLAG - pinsrd xmm5, esi, 0 -%else - pinsrw xmm5, esi, 0 - ror esi, 16 - pinsrw xmm5, esi, 1 -%endif + SXMMN xmm5, 0, esi mov esi, %1 jmp esi %%ReturnAddress: %endmacro =20 %macro RET_XMM 0 - movd esi, xmm5 - psrldq xmm5, 4 + LXMMN xmm5, esi, 0 jmp esi %endmacro =20 +; +; XMM5 slot 1 for uCode status +; +%macro LOAD_UCODE_STATUS 0 + LXMMN xmm5, eax, 1 + %endmacro + +%macro SAVE_UCODE_STATUS 0 + SXMMN xmm5, 1, eax + %endmacro + %macro ENABLE_SSE 0 ; ; Initialize floating point units diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.h index d7a5976c12..693af29f20 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h @@ -79,7 +79,7 @@ AsmGetFspBaseAddress ( /** This interface gets FspInfoHeader pointer =20 - @return FSP binary base address. + @return FSP info header. =20 **/ UINTN diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm b/IntelFsp2Pkg/FspS= ecCore/X64/FspHelper.nasm index 122fa1d174..71624a3aad 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspHelper.nasm @@ -7,10 +7,12 @@ DEFAULT REL SECTION .text =20 +FSP_HEADER_IMGBASE_OFFSET EQU 1Ch + global ASM_PFX(AsmGetFspBaseAddress) ASM_PFX(AsmGetFspBaseAddress): call ASM_PFX(AsmGetFspInfoHeader) - add rax, 0x1C + add rax, FSP_HEADER_IMGBASE_OFFSET mov eax, [rax] ret =20 --=20 2.35.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#96131): https://edk2.groups.io/g/devel/message/96131 Mute This Topic: https://groups.io/mt/94910671/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-