From nobody Sat Feb 7 05:48:45 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92924+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92924+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805428; cv=none; d=zohomail.com; s=zohoarc; b=JeVbxHSlD89Y8xGpOVgPmdxiJDdooRlvYPs+3g5EcQfvd7bmoEuFffPowZ7eXLARvVDH9ZdSpgREz3mNjG5PhMlslSF78CDe6kbxUKzBG+kTE7vxQE6mPLmJfI8hXHoYT3C/iGatX7CmbiwwSBXDUYIYVJf8RCTdf7GcBafThpc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805428; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=GsYaRvZAHdG+LqZZeUYI1gGKDUFcS/NEPNOj/aHomj0=; b=X0r9rNPXL32YdWjiQ9yC7t+8o6F9BJQqZHSs4cMSd7oWLtl1Uk6oQKXhgY58iE1+Y6BnUviSsTE2TKPsvznXvnds1nJGJVWLkRCkcQrM8OsqMjMxm4eI48Uo7UKiVPoXW9qHXDm7B0aBUZcoxm2c64hffqXqVaM9viTNShIlDuc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92924+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805428189911.8718153492415; Mon, 29 Aug 2022 13:37:08 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id y7kNYY1788612xt9Ag4p8HME; Mon, 29 Aug 2022 13:37:07 -0700 X-Received: from mail-qt1-f176.google.com (mail-qt1-f176.google.com [209.85.160.176]) by mx.groups.io with SMTP id smtpd.web11.3426.1661805426850280479 for ; Mon, 29 Aug 2022 13:37:07 -0700 X-Received: by mail-qt1-f176.google.com with SMTP id cb8so7130608qtb.0 for ; Mon, 29 Aug 2022 13:37:06 -0700 (PDT) X-Gm-Message-State: TqQzapswJiU509YOIANjd8q5x1787277AA= X-Google-Smtp-Source: AA6agR7EbTNkxlvfbbKHHvkL5R9/rg3EOZG5R7EYThiGZBz7kUMUOQGoKU4vBIbtpgfmUvnl5cGEPg== X-Received: by 2002:ac8:690b:0:b0:343:5bc0:78a0 with SMTP id bt11-20020ac8690b000000b003435bc078a0mr11665188qtb.535.1661805425589; Mon, 29 Aug 2022 13:37:05 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:05 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Chasel Chiu , Jeremy Soller , Sai Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v1 5/5] KabylakeOpenBoardPkg: Example of board S3 Date: Mon, 29 Aug 2022 16:36:20 -0400 Message-Id: <9825213b3cbe2814c9b4418570cdeca3fe49bc90.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805427; bh=gYJKzITnaJtSkXCPezwEWhNn3Lw93RA7vRWEZwiRfSY=; h=Cc:Date:From:Reply-To:Subject:To; b=PZs+5XxWb3SMcIzURBqlNicDRY/qQuzx/sBiaoAytfuxoxKOLDkk1s7rDIIiVGKnCvP HKzE4GdLoQWJIJlHG+w6+0H23s4nThNj7Ktfy6pDWt9JHqAnHuCPcZ1Li2cOghkadoI1S MPDsKeGY+vUG0tyTONt6l5JnIcehUiI9L1k= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805431518100002 Content-Type: text/plain; charset="utf-8" Use silicon code to detect S3 resume state. Apply some relevant policy modifications. PcdPeiMemSize must be in common scope, for a DXE module to allocate required memory. Libraries that produce required PPIs are defined. BootScriptExecutorDxe should only be linked against a functionally compatible debug stack. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Chasel Chiu Cc: Jeremy Soller Cc: Sai Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron --- .../PeiFspMiscUpdUpdateLib.c | 12 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../PeiAspireVn7Dash572GInitPreMemLib.c | 61 ++++++++++++++----- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 3 + .../AspireVn7Dash572G/OpenBoardPkg.dsc | 18 ++++++ .../AspireVn7Dash572G/OpenBoardPkgPcd.dsc | 7 +-- .../PeiSiliconPolicyUpdateLib.c | 11 +++- .../PeiSiliconPolicyUpdateLib.inf | 1 + .../PeiFspMiscUpdUpdateLib.c | 11 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../BoardInitLib/PeiGalagoPro3InitPreMemLib.c | 27 +++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../GalagoPro3/OpenBoardPkg.dsc | 16 +++++ .../GalagoPro3/OpenBoardPkgPcd.dsc | 2 +- .../PeiFspMiscUpdUpdateLib.c | 12 +++- .../PeiSaPolicyUpdate.c | 12 +++- .../BoardInitLib/PeiBoardInitPreMemLib.inf | 1 + .../PeiKabylakeRvp3InitPreMemLib.c | 27 +++++++- .../PeiMultiBoardInitPreMemLib.inf | 1 + .../KabylakeRvp3/OpenBoardPkg.dsc | 13 ++++ .../KabylakeRvp3/OpenBoardPkgPcd.dsc | 2 +- .../PeiSiliconPolicyUpdateLib.c | 11 +++- .../PeiSiliconPolicyUpdateLib.inf | 1 + 24 files changed, 242 insertions(+), 33 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform= /Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSilicon= PolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c index a9b7e446c8d6..7e4194bf4fe6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include + #include #include #include @@ -32,11 +34,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -70,7 +76,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapp= er/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Inte= l/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolic= yUpdateLibFsp/PeiSaPolicyUpdate.c index 4621cbd3ca3a..1299bf504fbd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -27,12 +28,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -40,7 +46,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c b/Platform/Intel/KabylakeO= penBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInit= PreMemLib.c index 1c9a65399b54..1b4c6b484b43 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GInitPreMemLib.c @@ -11,7 +11,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include +#include #include #include #include @@ -248,6 +250,8 @@ AspireVn7Dash572GBoardDebugInit ( VOID ) { + UINT16 ABase; + /// /// Do Early PCH init /// @@ -258,6 +262,16 @@ AspireVn7Dash572GBoardDebugInit ( // - Alternatively, move the preceding calls to BoardDetect() AspireVn7Dash572GBoardDetect (); =20 + // Dump relevant registers + // - TODO: Remove after debugging + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A)))); + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B)))); + + PchAcpiBaseGet (&ABase); + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase))); + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN))); + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT))); + return EFI_SUCCESS; } =20 @@ -267,25 +281,42 @@ AspireVn7Dash572GBoardBootModeDetect ( VOID ) { - UINT16 ABase; + EFI_BOOT_MODE BootMode; UINT32 SleepType; + UINT16 ABase; =20 DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); =20 - // TODO: Perform advanced detection (recovery/capsule) - // FIXME: This violates PI specification? But BOOT_WITH* would always ta= ke precedence - // over BOOT_ON_S{4,5}... - PchAcpiBaseGet (&ABase); - SleepType =3D IoRead32 (ABase + R_PCH_ACPI_PM1_CNT) & B_PCH_ACPI_PM1_CNT= _SLP_TYP; + // Known sane defaults; TODO: Consider "default"? + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; =20 - switch (SleepType) { - case V_PCH_ACPI_PM1_CNT_S3: - return BOOT_ON_S3_RESUME; - case V_PCH_ACPI_PM1_CNT_S4: - return BOOT_ON_S4_RESUME; -// case V_PCH_ACPI_PM1_CNT_S5: -// return BOOT_ON_S5_RESUME; - default: - return BOOT_WITH_FULL_CONFIGURATION; + // TODO: Perform advanced detection (capsule/recovery) + // TODO: Perform "IsFirstBoot" test with VariablePpi for "minimal"/"assu= me" + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + // Dump relevant registers + // - TODO: Remove after debugging + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_A=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_A)))); + DEBUG ((DEBUG_INFO, "PMC GEN_PMCON_B=3D 0x%x\n", PciRead32 ((UINTN)PCI_L= IB_ADDRESS (0, PCI_DEVICE_NUMBER_PCH_PMC, PCI_FUNCTION_NUMBER_PCH_PMC, R_PC= H_PMC_GEN_PMCON_B)))); + + PchAcpiBaseGet (&ABase); + DEBUG ((DEBUG_INFO, "ABase PM1_STS=3D 0x%x\n", IoRead16 (ABase))); + DEBUG ((DEBUG_INFO, "ABase PM1_EN=3D 0x%x\n", IoRead16 (ABase + R_PCH_AC= PI_PM1_EN))); + DEBUG ((DEBUG_INFO, "ABase PM1_CNT=3D 0x%x\n", IoRead32 (ABase + R_PCH_A= CPI_PM1_CNT))); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index cd9f979d313c..c53114e15450 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf @@ -25,11 +25,14 @@ TimerLib PchCycleDecodingLib PchResetLib + PciLib IoLib EcLib BoardEcLib GpioLib PeiLib + PeiServicesLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc index 261f141056f5..f4664985f947 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -150,6 +150,7 @@ ####################################### ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # @@ -238,6 +239,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -662,6 +664,22 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Library cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +# TODO: Requires testing +# - Strongly suspect DebugLibSerialPort constructor presents PeiDxeSerialP= ortLibMem dependency on services as a bug +!if FALSE # $(USE_MEMORY_LOGGING) =3D=3D TRUE + SerialPortLib|MdeModulePkg/Library/PeiDxeSerialPortLibMem/DxeSerialP= ortLibMem.inf +!endif + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkgPcd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoa= rdPkgPcd.dsc index 822040c06f32..df2cc81ae801 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd= .dsc @@ -127,10 +127,7 @@ # PcdIpmiFeatureEnable will not be enabled (no BMC) # TODO: Can be build-time (user) choice gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable = |FALSE - # TODO: Continue developing support. Broken at present. - # - PeiSmmAccessLib in IntelSiliconPkg seems like a stub - # - May require a PeiSmmControlLib to SMM communicate - gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |FALSE + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable = |TRUE # TODO: Definitions (now added SmbiosDxe) gSmbiosFeaturePkgTokenSpaceGuid.PcdSmbiosFeatureEnable = |TRUE # Requires actual hook-up @@ -360,6 +357,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|4 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -442,7 +440,6 @@ # Edk2 Configuration ###################################### gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Int= el/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUp= dateLib/PeiSiliconPolicyUpdateLib.c index 3764f7c3ac09..ab8abac6be1c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -549,6 +550,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -557,6 +559,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -571,7 +576,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/I= ntel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicy= UpdateLib/PeiSiliconPolicyUpdateLib.inf index 1ce26fc3dcec..31a45292209d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Intel/= KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLi= bFsp/PeiFspMiscUpdUpdateLib.c index dbc84631acaa..ce309bd378d2 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,6 +11,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include @@ -36,11 +37,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -75,7 +80,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Libr= ary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kabyl= akeOpenBoardPkg/GalagoPro3/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/= PeiSaPolicyUpdate.c index 133b8c963f65..48899aa63b4f 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/FspWrapper/Library/Pei= SiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Galag= oPro3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index d6c91cd2b94b..5b3a6921d0ee 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiBoardInitPreMemLib.inf @@ -23,6 +23,7 @@ PcdLib SiliconInitLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiGalagoPro3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPkg/Ga= lagoPro3/Library/BoardInitLib/PeiGalagoPro3InitPreMemLib.c index 051dac0b204d..1cd2baf4a4dd 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiGalagoPro3InitPreMemLib.c @@ -14,6 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -236,5 +237,29 @@ GalagoPro3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardIn= itLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/= GalagoPro3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index fe31f421356e..20ddac1d994d 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/Library/BoardInitLib/P= eiMultiBoardInitPreMemLib.inf @@ -25,6 +25,7 @@ SiliconInitLib MultiBoardInitSupportLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.ds= c b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc index 2e3c6d3ca506..097d20f34b4e 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkg.dsc @@ -108,6 +108,7 @@ ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf SiliconPolicyInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconPolicyInit= LibFsp/PeiSiliconPolicyInitLibFsp.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 ##################################### # Platform Package @@ -177,6 +178,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -488,6 +490,20 @@ NULL|$(PROJECT)/Library/BoardAcpiLib/DxeMultiBoardAcpiSupportLib.i= nf !endif } + +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # Reverse-ranked priority list +!if gKabylakeOpenBoardPkgTokenSpaceGuid.PcdI2cHdmiDebugPortEnable =3D=3D T= RUE + SerialPortLib|$(PLATFORM_BOARD_PACKAGE)/Library/I2cHdmiDebugSerialPo= rtLib/BootScriptExecutorDxeI2cHdmiDebugSerialPortLib.inf +!endif + } +!endif MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouter= Smm.inf { DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf diff --git a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd= .dsc b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc index 4a37d6157b95..618a70910536 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/GalagoPro3/OpenBoardPkgPcd.dsc @@ -305,6 +305,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -405,7 +406,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c b/Platform/Inte= l/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpda= teLibFsp/PeiFspMiscUpdUpdateLib.c index 699f4297fad6..71b03f2da464 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c @@ -11,11 +11,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 #include #include #include - #include #include #include @@ -36,11 +36,15 @@ PeiFspMiscUpdUpdatePreMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; UINTN VariableSize; VOID *FspNvsBufferPtr; UINT8 MorControl; VOID *MorControlPtr; =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + // // Initialize S3 Data variable (S3DataPtr). It may be used for warm and = fast boot paths. // @@ -73,7 +77,11 @@ PeiFspMiscUpdUpdatePreMem ( &VariableSize ); DEBUG ((DEBUG_INFO, "MorControl - 0x%x (%r)\n", MorControl, Status)); - if (MOR_CLEAR_MEMORY_VALUE (MorControl)) { + // + // Do not set CleanMemory on S3 resume + // TODO: Handle advanced features later - capsule update is in-memory li= st + // + if (MOR_CLEAR_MEMORY_VALUE (MorControl) && BootMode !=3D BOOT_ON_S3_RESU= ME) { FspmUpd->FspmConfig.CleanMemory =3D (BOOLEAN)(MorControl & MOR_CLEAR_M= EMORY_BIT_MASK); } =20 diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Li= brary/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c b/Platform/Intel/Kab= ylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/PeiSiliconPolicyUpdateLib= Fsp/PeiSaPolicyUpdate.c index d6ec3e38dd7e..b69abd11cbce 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/FspWrapper/Library/P= eiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c @@ -17,6 +17,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include =20 /** Performs FSP SA PEI Policy initialization. @@ -33,12 +34,17 @@ PeiFspSaPolicyUpdate ( IN OUT FSPS_UPD *FspsUpd ) { + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; =20 DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + FspsUpd->FspsConfig.PeiGraphicsPeimInit =3D 1; =20 Size =3D 0; @@ -46,7 +52,11 @@ PeiFspSaPolicyUpdate ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/Kab= ylakeRvp3/Library/BoardInitLib/PeiBoardInitPreMemLib.inf index 850fc514188b..e0022e8d6118 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiBoardInitPreMemLib.inf @@ -24,6 +24,7 @@ SiliconInitLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiKabylakeRvp3InitPreMemLib.c b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiKabylakeRvp3InitPreMemLib.c index 87ae3b531ed6..02cd37227e50 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiKabylakeRvp3InitPreMemLib.c @@ -13,6 +13,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -330,5 +331,29 @@ KabylakeRvp3BoardBootModeDetect ( VOID ) { - return BOOT_WITH_FULL_CONFIGURATION; + EFI_BOOT_MODE BootMode; + UINT32 SleepType; + + DEBUG ((DEBUG_INFO, "Performing boot mode detection\n")); + + // Known sane defaults + BootMode =3D BOOT_WITH_FULL_CONFIGURATION; + + if (GetSleepTypeAfterWakeup (&SleepType)) { + switch (SleepType) { + case V_PCH_ACPI_PM1_CNT_S3: + BootMode =3D BOOT_ON_S3_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S4: + BootMode =3D BOOT_ON_S4_RESUME; + break; + case V_PCH_ACPI_PM1_CNT_S5: + BootMode =3D BOOT_ON_S5_RESUME; + break; + } + } + + DEBUG ((DEBUG_INFO, "BootMode is 0x%x\n", BootMode)); + + return BootMode; } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/Board= InitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/KabylakeOpenBoardPk= g/KabylakeRvp3/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf index 23fe6b6f03c5..0112bf84a193 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Library/BoardInitLib= /PeiMultiBoardInitPreMemLib.inf @@ -26,6 +26,7 @@ MultiBoardInitSupportLib EcLib PchResetLib + PchPmcLib =20 [Packages] MinPlatformPkg/MinPlatformPkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.= dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc index 26a54b0dc7cc..dbffa2918df7 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkg.dsc @@ -138,6 +138,7 @@ ####################################### ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf SiliconInitLib|$(PLATFORM_SI_PACKAGE)/Library/PeiSiliconInitLib/PeiSilic= onInitLib.inf + IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLib= Kbl/BaseIntelCompatShimLibKbl.inf =20 !if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1 # @@ -201,6 +202,7 @@ # Silicon Package ####################################### ReportCpuHobLib|IntelSiliconPkg/Library/ReportCpuHobLib/ReportCpuHobLib.= inf + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibSm= ramc/PeiSmmAccessLib.inf =20 ####################################### # Platform Package @@ -505,6 +507,17 @@ !endif } =20 +!if gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =3D=3D TRUE + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf { + + # On S3 resume, RSC is in end-of-BS state + # - Moreover: Libraries cannot effectively use some end-of-BS events + DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPor= t.inf + SerialPortLib|MdePkg/Library/BaseSerialPortLibNull/BaseSerialPortLib= Null.inf + # TODO: Insert a reverse-ranked priority list of compatible librarie= s here + } +!endif + !endif =20 ####################################### diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgP= cd.dsc b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.d= sc index bdd5bc412795..82bf55f4cce1 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/OpenBoardPkgPcd.dsc @@ -305,6 +305,7 @@ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8 gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2 gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000 + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 # # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags @@ -375,7 +376,6 @@ ###################################### gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0 gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148 - gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000 =20 ###################################### # Platform Configuration diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/Pe= iSiliconPolicyUpdateLib.c index 22aadc0221df..2061efb2445c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c @@ -20,6 +20,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include +#include #include #include #include @@ -513,6 +514,7 @@ SiliconPolicyUpdatePostMem ( ) { EFI_STATUS Status; + EFI_BOOT_MODE BootMode; VOID *Buffer; VOID *MemBuffer; UINT32 Size; @@ -521,6 +523,9 @@ SiliconPolicyUpdatePostMem ( =20 DEBUG((DEBUG_INFO, "\nUpdating Policy in Post Mem\n")); =20 + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + GtConfig =3D NULL; Status =3D GetConfigBlock ((VOID *) Policy, &gGraphicsPeiConfigGuid, (VO= ID *)&GtConfig); ASSERT_EFI_ERROR (Status); @@ -535,7 +540,11 @@ SiliconPolicyUpdatePostMem ( PeiGetSectionFromAnyFv (PcdGetPtr (PcdGraphicsVbtGuid), EFI_SECTION_RA= W, 0, &Buffer, &Size); if (Buffer =3D=3D NULL) { DEBUG((DEBUG_WARN, "Could not locate VBT\n")); - } else { + // + // Graphics initialisation is unnecessary, + // OS has present framebuffer. + // + } else if (BootMode !=3D BOOT_ON_S3_RESUME) { MemBuffer =3D (VOID *)AllocatePages (EFI_SIZE_TO_PAGES ((UINTN)Size)= ); if ((MemBuffer !=3D NULL) && (Buffer !=3D NULL)) { CopyMem (MemBuffer, (VOID *)Buffer, (UINTN)Size); diff --git a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Librar= y/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf b/Platform/Intel/= KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSiliconPolicyUpdateLib/= PeiSiliconPolicyUpdateLib.inf index 25eae88f5989..e9a23593e133 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Policy/Library/PeiSi= liconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf @@ -23,6 +23,7 @@ BaseMemoryLib MemoryAllocationLib PeiLib + PeiServicesLib CpuPlatformLib PchPcieRpLib PchInfoLib --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92924): https://edk2.groups.io/g/devel/message/92924 Mute This Topic: https://groups.io/mt/93335523/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-