From nobody Mon Feb 9 02:43:31 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93257+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93257+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1662483768; cv=none; d=zohomail.com; s=zohoarc; b=Y1ON/4lao6A4RjN3YBZhOV308DBsLCDKQnd/pPT6KehkVzMEuoLwslDZ+zkcvQwHDyl9hIGJ5IgGqKwGl9NHBArug1aCORX0aio4hOLU4PfJgK+iVCWuN9+1DnqqHafhYZxPx5iPJ+xcos6m/3plA5XXGD9RmFU1JnhOPcpTo6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662483768; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=VZLCt0VVauJfO4sIIDZEVwEfn71KCkzke24dN87Ep+A=; b=GO6yy1Rp7J1GMkU93K+Jt7QvMbt/62IkTGdi+hYK4mZd1n5wJkcXXkKLKRmlRl+FuOvyACbvmlULzpEEBt/UXAZwN2SCgsX9OrLjk9kwiOYwHtIt5gw4aU0PJzkO3GlEmVN2HSYs/ip57aWRho4CDhwPX3gPFmCDZK9YJ0AQGUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93257+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662483768329254.05566416857096; Tue, 6 Sep 2022 10:02:48 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id vsQnYY1788612xEc9Vtuktr5; Tue, 06 Sep 2022 10:02:48 -0700 X-Received: from mail-qt1-f169.google.com (mail-qt1-f169.google.com [209.85.160.169]) by mx.groups.io with SMTP id smtpd.web11.1760.1662483767124653270 for ; Tue, 06 Sep 2022 10:02:47 -0700 X-Received: by mail-qt1-f169.google.com with SMTP id w28so8516892qtc.7 for ; Tue, 06 Sep 2022 10:02:47 -0700 (PDT) X-Gm-Message-State: ZcpnSZloaiNcxJ1RGfqiseZnx1787277AA= X-Google-Smtp-Source: AA6agR5aQwGGGBFm3AhApO7awHw/ZbOhvtukoZiPFm1JP754J+3WC1cqlut9TjLh05NyuFfOw63e7g== X-Received: by 2002:a05:622a:254:b0:343:55c0:1d84 with SMTP id c20-20020a05622a025400b0034355c01d84mr44111327qtx.225.1662483765927; Tue, 06 Sep 2022 10:02:45 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:46bc:db07:bbf3:df6d]) by smtp.gmail.com with ESMTPSA id bi13-20020a05620a318d00b006b59f02224asm10895809qkb.60.2022.09.06.10.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:02:45 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Ray Ni , Rangasai V Chaganty , Isaac Oram Subject: [edk2-devel][edk2-platforms][PATCH v2 3/6] IntelSiliconPkg/Feature/SmmControl: Implement PPI with chipset support Date: Tue, 6 Sep 2022 13:02:25 -0400 Message-Id: <8dffa2473dfd2871443632ab2ba32a787471dafd.1662483691.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662483768; bh=tDpwABGncjmng+wQnTjWYOYO4ry4sHPZTbCTYa+9AqY=; h=Cc:Date:From:Reply-To:Subject:To; b=UMUFDwUJOeVVccMweGpwHH8BPVSSDMsA7VJ2gmVU0Olrp+x9y5HuqAOrlX6iEu3Uq65 hDQHconhdor4CRjLGZFu22zODialmBoFOhCX1VsGexJ3DsTIBEYPzwu3zgJJk997K0SV3 tnVjnpJxyQoPtI4U5V44oEXtmzd3G41hd3s= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662483769348100008 Content-Type: text/plain; charset="utf-8" S3 resume may require communication with SMM, for which we need the SmmControl PPI. Therefore, port the DXE drivers to a library, like there is for SMM Access. Tested, working on Kabylake. Further testing required after the refactor for compatibility. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Isaac Oram Signed-off-by: Benjamin Doron Reviewed-by: Isaac Oram --- .../PeiSmmControlLib/PeiSmmControlLib.c | 309 ++++++++++++++++++ .../PeiSmmControlLib/PeiSmmControlLib.inf | 34 ++ .../Include/Library/SmmControlLib.h | 26 ++ .../Intel/IntelSiliconPkg/IntelSiliconPkg.dec | 4 + 4 files changed, 373 insertions(+) create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.c create mode 100644 Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Librar= y/PeiSmmControlLib/PeiSmmControlLib.inf create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmContro= lLib.h diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.c b/Silicon/Intel/IntelSiliconPkg/Feature/SmmC= ontrol/Library/PeiSmmControlLib/PeiSmmControlLib.c new file mode 100644 index 000000000000..cc6c7f8fe672 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.c @@ -0,0 +1,309 @@ +/** @file + This is to publish the SMM Control Ppi instance. + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include + +#include +#include + +#define SMM_CONTROL_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('i', '4', 's', '= c') + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + EFI_PEI_MM_CONTROL_PPI SmmControl; +} SMM_CONTROL_PRIVATE_DATA; + +#define SMM_CONTROL_PRIVATE_DATA_FROM_THIS(a) \ + CR (a, \ + SMM_CONTROL_PRIVATE_DATA, \ + SmmControl, \ + SMM_CONTROL_DEV_SIGNATURE \ + ) + +// +// Common registers: +// +// +// APM Registers +// +#define R_PCH_APM_CNT 0xB2 +// +// ACPI and legacy I/O register offsets from ACPIBASE +// +#define R_PCH_ACPI_PM1_STS 0x00 +#define B_PCH_ACPI_PM1_STS_PRBTNOR BIT11 + +#define R_PCH_SMI_EN 0x30 + +#define R_PCH_SMI_STS 0x34 +#define B_PCH_SMI_STS_APM BIT5 +#define B_PCH_SMI_EN_APMC BIT5 +#define B_PCH_SMI_EN_EOS BIT1 +#define B_PCH_SMI_EN_GBL_SMI BIT0 + +/** + Trigger the software SMI + + @param[in] Data The value to be set on the software SMI = data port + + @retval EFI_SUCCESS Function completes successfully +**/ +EFI_STATUS +EFIAPI +SmmTrigger ( + UINT8 Data + ) +{ + UINT16 ABase; + UINT32 OutputData; + UINT32 OutputPort; + + ABase =3D FixedPcdGet16 (PcdAcpiBaseAddress); + + /// + /// Enable the APMC SMI + /// + OutputPort =3D ABase + R_PCH_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D (B_PCH_SMI_EN_APMC | B_PCH_SMI_EN_GBL_SMI); + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + OutputPort =3D R_PCH_APM_CNT; + OutputData =3D Data; + + /// + /// Generate the APMC SMI + /// + IoWrite8 ( + (UINTN) OutputPort, + (UINT8) (OutputData) + ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_DEVICE_ERROR Something error occurred +**/ +EFI_STATUS +EFIAPI +SmmClear ( + VOID + ) +{ + UINT16 ABase; + UINT32 OutputData; + UINT32 OutputPort; + + ABase =3D FixedPcdGet16 (PcdAcpiBaseAddress); + + /// + /// Clear the Power Button Override Status Bit, it gates EOS from being = set. + /// + OutputPort =3D ABase + R_PCH_ACPI_PM1_STS; + OutputData =3D B_PCH_ACPI_PM1_STS_PRBTNOR; + DEBUG ( + (DEBUG_EVENT, + "The PM1 Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite16 ( + (UINTN) OutputPort, + (UINT16) (OutputData) + ); + + /// + /// Clear the APM SMI Status Bit + /// + OutputPort =3D ABase + R_PCH_SMI_STS; + OutputData =3D B_PCH_SMI_STS_APM; + DEBUG ( + (DEBUG_EVENT, + "The SMI Status Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// Set the EOS Bit + /// + OutputPort =3D ABase + R_PCH_SMI_EN; + OutputData =3D IoRead32 ((UINTN) OutputPort); + OutputData |=3D B_PCH_SMI_EN_EOS; + DEBUG ( + (DEBUG_EVENT, + "The SMI Control Port at address %x will be written to %x.\n", + OutputPort, + OutputData) + ); + IoWrite32 ( + (UINTN) OutputPort, + (UINT32) (OutputData) + ); + + /// + /// There is no need to read EOS back and check if it is set. + /// This can lead to a reading of zero if an SMI occurs right after the = SMI_EN port read + /// but before the data is returned to the CPU. + /// SMM Dispatcher should make sure that EOS is set after all SMI source= s are processed. + /// + return EFI_SUCCESS; +} + +/** + This routine generates an SMI + + @param[in] This The EFI SMM Control protocol insta= nce + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic Periodic or not + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI Status Describing the result of the opera= tion + @retval EFI_INVALID_PARAMETER Some parameter value passed is not= supported +**/ +EFI_STATUS +EFIAPI +Activate ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + EFI_STATUS Status; + UINT8 Data; + + if (Periodic) { + DEBUG ((DEBUG_WARN, "Invalid parameter\n")); + return EFI_INVALID_PARAMETER; + } + + // NOTE: Copied from Quark. Matches the usage in PiSmmCommunicationPei + if (ArgumentBuffer =3D=3D NULL) { + Data =3D 0xFF; + } else { + if (ArgumentBufferSize =3D=3D NULL || *ArgumentBufferSize !=3D 1) { + return EFI_INVALID_PARAMETER; + } + + Data =3D *ArgumentBuffer; + } + /// + /// Clear any pending the APM SMI + /// + Status =3D SmmClear (); + if (EFI_ERROR (Status)) { + return Status; + } + + return SmmTrigger (Data); +} + +/** + This routine clears an SMI + + @param[in] This The EFI SMM Control protocol instance + @param[in] Periodic Periodic or not + + @retval EFI Status Describing the result of the operation + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +Deactivate ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_MM_CONTROL_PPI * This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return SmmClear (); +} + +/** + This function is to install an SMM Control PPI + - Introduction \n + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard + way for other modules to trigger software SMIs. + + @retval EFI_SUCCESS - Ppi successfully started and installed. + @retval EFI_NOT_FOUND - Ppi can't be found. + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver. +**/ +EFI_STATUS +EFIAPI +PeiInstallSmmControlPpi ( + VOID + ) +{ + EFI_STATUS Status; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + SMM_CONTROL_PRIVATE_DATA *SmmControlPrivate; + + // + // Initialize private data + // + SmmControlPrivate =3D AllocateZeroPool (sizeof (*SmmControlPrivate)); + ASSERT (SmmControlPrivate !=3D NULL); + if (SmmControlPrivate =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + PpiList =3D AllocateZeroPool (sizeof (*PpiList)); + ASSERT (PpiList !=3D NULL); + if (PpiList =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + SmmControlPrivate->Signature =3D SMM_CONTROL_PRIVATE_DATA_SIGNATURE; + SmmControlPrivate->Handle =3D NULL; + + SmmControlPrivate->SmmControl.Trigger =3D Activate; + SmmControlPrivate->SmmControl.Clear =3D Deactivate; + + // + // Install PPI + // + PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR= _TERMINATE_LIST); + PpiList->Guid =3D &gEfiPeiMmControlPpiGuid; + PpiList->Ppi =3D &SmmControlPrivate->SmmControl; + + Status =3D PeiServicesInstallPpi (PpiList); + ASSERT_EFI_ERROR (Status); + + // Unlike driver, do not disable SMIs as S3 resume continues + return EFI_SUCCESS; +} diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSm= mControlLib/PeiSmmControlLib.inf b/Silicon/Intel/IntelSiliconPkg/Feature/Sm= mControl/Library/PeiSmmControlLib/PeiSmmControlLib.inf new file mode 100644 index 000000000000..91c761366446 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmContro= lLib/PeiSmmControlLib.inf @@ -0,0 +1,34 @@ +## @file +# Library description file for the SmmControl PPI +# +# Copyright (c) 2019, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D PeiSmmControlLib + FILE_GUID =3D F45D521A-C0DF-4283-A3CA-65AD01B479E7 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D PEIM + LIBRARY_CLASS =3D SmmControlLib + +[LibraryClasses] + IoLib + DebugLib + MemoryAllocationLib + PeiServicesLib + +[Packages] + MdePkg/MdePkg.dec + IntelSiliconPkg/IntelSiliconPkg.dec + +[Sources] + PeiSmmControlLib.c + +[Pcd] + gIntelSiliconPkgTokenSpaceGuid.PcdAcpiBaseAddress ## CONSUMES + +[Ppis] + gEfiPeiMmControlPpiGuid ## PRODUCES diff --git a/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h = b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h new file mode 100644 index 000000000000..b532dd13f373 --- /dev/null +++ b/Silicon/Intel/IntelSiliconPkg/Include/Library/SmmControlLib.h @@ -0,0 +1,26 @@ +/** @file + This is to publish the SMM Control Ppi instance. + + Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef _SMM_CONTROL_LIB_H_ +#define _SMM_CONTROL_LIB_H_ + +/** + This function is to install an SMM Control PPI + - Introduction \n + An API to install an instance of EFI_PEI_MM_CONTROL_PPI. This PPI prov= ides a standard + way for other modules to trigger software SMIs. + + @retval EFI_SUCCESS - Ppi successfully started and installed. + @retval EFI_NOT_FOUND - Ppi can't be found. + @retval EFI_OUT_OF_RESOURCES - Ppi does not have enough resources to = initialize the driver. +**/ +EFI_STATUS +EFIAPI +PeiInstallSmmControlPpi ( + VOID + ); +#endif diff --git a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec b/Silicon/In= tel/IntelSiliconPkg/IntelSiliconPkg.dec index deefdc55b5d6..440c7d0255ce 100644 --- a/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec +++ b/Silicon/Intel/IntelSiliconPkg/IntelSiliconPkg.dec @@ -35,6 +35,10 @@ # SmmAccessLib|Include/Library/SmmAccessLib.h =20 + ## @libraryclass Provides services to trigger SMI + # + SmmControlLib|Include/Library/SmmControlLib.h + ## @libraryclass Provides services to access config block # ConfigBlockLib|Include/Library/ConfigBlockLib.h --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#93257): https://edk2.groups.io/g/devel/message/93257 Mute This Topic: https://groups.io/mt/93506109/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-