From nobody Sun Feb 8 10:03:33 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88392+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88392+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649045704; cv=none; d=zohomail.com; s=zohoarc; b=dSumHKi+/vZYW6IXLJoInnzMt8yJPKyG9acmEM0O0cJ0kj0A0+LJ1JP/G7RDl36YoznA2ByFRjCH/d0T26hQb++jA0JJmUvhiob9gc3tl4bjg6zU6QP7nyu06AZzeRp2/QB/BFF3fi4ZfOzwB4lCKYj/1CcEUbRO6Ih7MTctHW4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649045704; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=GgE5HqJWoHaHD5OMQx3COFOekeAu1CTK/Fy46LBpXyc=; b=BohFv9zOYJbfB1D9Ben0E/dCqeqteE6xRUQCuG5INpRcVS4+1wp+M3Aqh44zdeP1cwpjjPMFDnXbSi4i7xhKIiojvKFlYwqwAhjLktC+QlE9Fr3gGL0ZkFU40twvBKB+NO5GgwuFPLy0prvD658B6HjXtL/kYXYHolJNHWaL3fk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88392+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649045704791482.34765321744203; Sun, 3 Apr 2022 21:15:04 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id pE6VYY1788612x7ka7sfX9yT; Sun, 03 Apr 2022 21:15:04 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web10.31557.1649045701897767143 for ; Sun, 03 Apr 2022 21:15:03 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="258015879" X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="258015879" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 21:14:41 -0700 X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="696444604" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 21:14:40 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH 5/5] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64 Date: Mon, 4 Apr 2022 12:14:00 +0800 Message-Id: <8bade556b0c8433a5dfc252b7b4e302e48a2b842.1649045384.git.ted.kuo@intel.com> In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: G4Rf2riAXmTU8qi5VIUMHaJVx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649045704; bh=JnCg97G84Xy/2jSZqjdIBT3YIsCVpg+4JVjJST1rAUg=; h=Cc:Date:From:Reply-To:Subject:To; b=NSYBIbBmy1HXWJXW7lvLrV+NupJH1VPrZ0NsE17UG6A/4b0fQbAoG0ZYT6sgLOF5a7g jlLJRUpeLR/NO5Tc28JWsGe9Ap+g/RdOv/12MKhxOu9t9OmMQPJUXTHE4F+cPLLxuhDya nBph1hkdh678Kvasn9BZ/CR6dk5yJs+XauY= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649045706948100003 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 +++++++++++++++++ .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++++++++++++++++++= ++++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long6= 4.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCa= rInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION =3D 0.1 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES =3D IA32 + SUPPORTED_ARCHITECTURES =3D IA32|X64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatfor= mLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatf= ormLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNul= l.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNul= l.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 +# VALID_ARCHITECTURES =3D IA32 X64 # =20 ##########################################################################= ###### @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm =20 +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + ##########################################################################= ###### # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm = b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 0000000000..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movd rsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.n= asm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 0000000000..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movd rsi, mm7 ; move ReturnAddress from MM7 to R= SI + jmp rsi + +%endmacro + +SECTION .text + +;-------------------------------------------------------------------------= ---- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and C= ode +; +;-------------------------------------------------------------------------= ---- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xor rax, rax + +SecCarInitExit: + + RET_RSI + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88392): https://edk2.groups.io/g/devel/message/88392 Mute This Topic: https://groups.io/mt/90234877/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-