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Mon, 16 May 2022 20:24:14 +0000 X-Received: from tlendack-t1.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 16 May 2022 15:24:13 -0500 From: "Lendacky, Thomas via groups.io" To: CC: Ard Biesheuvel , Jiewen Yao , Jordan Justen , "Gerd Hoffmann" , Erdem Aktas , "James Bottomley" , Michael Roth , Min Xu Subject: [edk2-devel] [PATCH] OvmfPkg: Make an Ia32/X64 hybrid build work with SEV Date: Mon, 16 May 2022 15:24:02 -0500 Message-ID: <7df5d5feedb9f95777d305a6ce3c5fbc32c6e8d1.1652732642.git.thomas.lendacky@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 3c7c5f20-a1c4-4b36-a203-08da377a0ba6 X-MS-TrafficTypeDiagnostic: MN2PR12MB3838:EE_ X-Microsoft-Antispam-PRVS: X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: LZb8aFT0f9Glfma97Z0Ho5LrNAje1KslhFbhukKkyFb/V0WvGi1SDC8Ub9AXg4mvwhboR5baUy+g4dBpI3uqz142oZIZZf02OGFmNzbciAnmU5Xipfam7qJT1NQC1oWUKYy/5q/sJfLa3OH91ydOUDnfqsqFWx+iEtSgAf3d7fbPObaqm9B5e1u4nIEWdLhC96pvnKySo/qyWwKbYlYNVOJWpNVoNZHYTocO3hVeUr7vGLsU5clAcZxnlfgkbxbQZwTs6KRlljm2VP5dKq+ST0waYuN2nvSDLmaOCvLoc0wPlufAPP1pI2sD4WL3be99ZDJZhgfkOFz5VmKjuK6+y2LtOUiQFk3dcgBAG/6uFetGw/NkjOkx2YjhWi8Sct6a/zdAlfOh4IBVfSjDdgyY1UdoJlyt74m8zI6Hroi/ewpu7cqIIgz0PbB8udmayD5kcyTQNq79e2LStQzH8C25Br0HsdgkBwV4UkHI4SKws+dsTR1+ZWAlLzusY5+2iUk3ktfG3bL8RfpV4QwuRFheK0lzLcc1i+HHwy264JJsLYQ0mQA3rOhUR9xq+i20wH7UhXGuSgqv36E3u+NqSvRQTMaKioaSBL3oRpWyECqaA6oemZck+equYSBK1KE3uItSDw7UvQuQNum9uot7lquNlVSJTUKXTk12RkZv1COPwfmqOa82iZY7co1WpXJWgHz5laOhJBgdWKvq9wp2QONtSw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 May 2022 20:24:14.6729 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c7c5f20-a1c4-4b36-a203-08da377a0ba6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB3838 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,thomas.lendacky@amd.com X-Gm-Message-State: 8sBD4uHXgXSXkVoiZawzuXwbx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652732658; bh=j+efTiOs5tiLqvu+YIaAecOY+IF33PqAgLe26ui1PEI=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=wkm1KZMW59JQkg9oFqEHWu+ZsmRuuCUk2uxo26ntOSWwK8lK4tKrRwHtRJy3RsPRAp2 xg7ZgH4lbWPTEqeVltZFFmXNPp4aXl7TavoMQuvLwTuPldPKEq3ZPhVKHkEJPbZjxR19Y xj/arXaOlHxxTqER9TNCJDank/lmCdFNwyM= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652732659666100003 Content-Type: text/plain; charset="utf-8" The BaseMemEncryptSevLib functionality was updated to rely on the use of the OVMF/SEV workarea to check for SEV guests. However, this area is only updated when running the X64 OVMF build, not the hybrid Ia32/X64 build. Base SEV support is allowed under the Ia32/X64 build, but it now fails to boot as a result of the change. Update the ResetVector code to check for SEV features when built for 32-bit mode, not just 64-bit mode (requiring updates to both the Ia32 and Ia32X64 fdf files). Fixes: f1d1c337e7c0575da7fd248b2dd9cffc755940df Cc: Ard Biesheuvel Cc: Jiewen Yao Cc: Jordan Justen Cc: Gerd Hoffmann Cc: Erdem Aktas Cc: James Bottomley Cc: Michael Roth Cc: Min Xu Signed-off-by: Tom Lendacky --- OvmfPkg/OvmfPkgIa32.fdf | 11 +++ OvmfPkg/OvmfPkgIa32X64.fdf | 8 +++ OvmfPkg/OvmfPkgX64.fdf | 3 +- OvmfPkg/ResetVector/Ia32/AmdSev.asm | 4 ++ OvmfPkg/ResetVector/Main.asm | 6 ++ OvmfPkg/ResetVector/ResetVector.nasmb | 72 ++++++++++---------- 6 files changed, 67 insertions(+), 37 deletions(-) diff --git a/OvmfPkg/OvmfPkgIa32.fdf b/OvmfPkg/OvmfPkgIa32.fdf index 3ab1755749d4..57d13b7130bc 100644 --- a/OvmfPkg/OvmfPkgIa32.fdf +++ b/OvmfPkg/OvmfPkgIa32.fdf @@ -76,6 +76,9 @@ [FD.MEMFD] 0x007000|0x001000 gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|gUefiOvmfPkgT= okenSpaceGuid.PcdGuidedExtractHandlerTableSize =20 +0x008000|0x001000 +gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfWorkAreaSize + 0x010000|0x010000 gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|gUefiOvmfPkgTokenSpace= Guid.PcdOvmfSecPeiTempRamSize =20 @@ -87,6 +90,14 @@ [FD.MEMFD] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize FV =3D DXEFV =20 +##########################################################################= ################ +# Set the SEV-ES specific work area PCDs (used for all forms of SEV since = the +# the SEV STATUS MSR is now saved in the work area) +# +SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase =3D $(MEMFD_BASE_ADDRES= S) + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpa= ceGuid.PcdOvmfConfidentialComputingWorkAreaHeader +SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize =3D gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentia= lComputingWorkAreaHeader +##########################################################################= ################ + ##########################################################################= ###### =20 [FV.SECFV] diff --git a/OvmfPkg/OvmfPkgIa32X64.fdf b/OvmfPkg/OvmfPkgIa32X64.fdf index e1638fa6ea38..ccde366887a9 100644 --- a/OvmfPkg/OvmfPkgIa32X64.fdf +++ b/OvmfPkg/OvmfPkgIa32X64.fdf @@ -90,6 +90,14 @@ [FD.MEMFD] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|gUefiOvmfPkgTokenSpaceGuid.= PcdOvmfDxeMemFvSize FV =3D DXEFV =20 +##########################################################################= ################ +# Set the SEV-ES specific work area PCDs (used for all forms of SEV since = the +# the SEV STATUS MSR is now saved in the work area) +# +SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase =3D $(MEMFD_BASE_ADDRES= S) + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpa= ceGuid.PcdOvmfConfidentialComputingWorkAreaHeader +SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize =3D gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentia= lComputingWorkAreaHeader +##########################################################################= ################ + ##########################################################################= ###### =20 [FV.SECFV] diff --git a/OvmfPkg/OvmfPkgX64.fdf b/OvmfPkg/OvmfPkgX64.fdf index aa9a83032d9b..438806fba8f1 100644 --- a/OvmfPkg/OvmfPkgX64.fdf +++ b/OvmfPkg/OvmfPkgX64.fdf @@ -106,7 +106,8 @@ [FD.MEMFD] FV =3D DXEFV =20 ##########################################################################= ################ -# Set the SEV-ES specific work area PCDs +# Set the SEV-ES specific work area PCDs (used for all forms of SEV since = the +# the SEV STATUS MSR is now saved in the work area) # SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase =3D $(MEMFD_BASE_ADDRES= S) + gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase + gUefiOvmfPkgTokenSpa= ceGuid.PcdOvmfConfidentialComputingWorkAreaHeader SET gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaSize =3D gUefiOvmfPkgTokenSp= aceGuid.PcdOvmfWorkAreaSize - gUefiOvmfPkgTokenSpaceGuid.PcdOvmfConfidentia= lComputingWorkAreaHeader diff --git a/OvmfPkg/ResetVector/Ia32/AmdSev.asm b/OvmfPkg/ResetVector/Ia32= /AmdSev.asm index 864d68385342..9350b0406833 100644 --- a/OvmfPkg/ResetVector/Ia32/AmdSev.asm +++ b/OvmfPkg/ResetVector/Ia32/AmdSev.asm @@ -150,6 +150,8 @@ BITS 32 SevEsUnexpectedRespTerminate: TerminateVmgExit TERM_UNEXPECTED_RESP_CODE =20 +%ifdef ARCH_X64 + ; If SEV-ES is enabled then initialize and make the GHCB page shared SevClearPageEncMaskForGhcbPage: ; Check if SEV is enabled @@ -209,6 +211,8 @@ GetSevCBitMaskAbove31: GetSevCBitMaskAbove31Exit: OneTimeCallRet GetSevCBitMaskAbove31 =20 +%endif + ; Check if Secure Encrypted Virtualization (SEV) features are enabled. ; ; Register usage is tight in this routine, so multiple calls for the diff --git a/OvmfPkg/ResetVector/Main.asm b/OvmfPkg/ResetVector/Main.asm index 5cfc0b5c72b1..46cfa87c4c0a 100644 --- a/OvmfPkg/ResetVector/Main.asm +++ b/OvmfPkg/ResetVector/Main.asm @@ -75,6 +75,12 @@ SearchBfv: =20 %ifdef ARCH_IA32 =20 + ; + ; SEV support can be built and run using the Ia32/X64 split environmen= t. + ; Set the OVMF/SEV work area as appropriate. + ; + OneTimeCall CheckSevFeatures + ; ; Restore initial EAX value into the EAX register ; diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/Re= setVector.nasmb index 9421f4818907..94fbb0a87b37 100644 --- a/OvmfPkg/ResetVector/ResetVector.nasmb +++ b/OvmfPkg/ResetVector/ResetVector.nasmb @@ -47,7 +47,36 @@ %include "Ia32/SearchForBfvBase.asm" %include "Ia32/SearchForSecEntry.asm" =20 -%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase)) +%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase)) +%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTables= Base) + (Offset)) + +%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTa= bleBase)) +%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) +%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) +%define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase= )) +%define SEV_ES_WORK_AREA_SIZE 25 +%define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase= )) +%define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase= ) + 8) +%define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase= ) + 16) +%define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBase= ) + 24) +%define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRam= Base) + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) +%define SEV_SNP_SECRETS_BASE (FixedPcdGet32 (PcdOvmfSnpSecretsBas= e)) +%define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSiz= e)) +%define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase)) +%define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize)) +%define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTables= Base)) +%define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) = - SNP_SEC_MEM_BASE_DESC_1) +; +; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used +; as GHCB shared page and second is used for bookkeeping to support the +; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM +; does not need to validate the shared page but it need to validate the +; bookkeeping page. +; +%define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000) +%define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_= BASE_DESC_2) +%define SNP_SEC_MEM_BASE_DESC_3 (CPUID_BASE + CPUID_SIZE) +%define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase)= - SNP_SEC_MEM_BASE_DESC_3) =20 %ifdef ARCH_X64 #include @@ -94,43 +123,14 @@ %define TDX_WORK_AREA_PGTBL_READY (FixedPcdGet32 (PcdOvmfWorkAreaBase) += 4) %define TDX_WORK_AREA_GPAW (FixedPcdGet32 (PcdOvmfWorkAreaBase) += 8) =20 - %define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Off= set)) + %include "X64/IntelTdxMetadata.asm" + %include "Ia32/Flat32ToFlat64.asm" + %include "Ia32/PageTables64.asm" + %include "Ia32/IntelTdx.asm" + %include "X64/OvmfSevMetadata.asm" +%endif =20 - %define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase)) - %define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase)) - %define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize)) - %define SEV_ES_WORK_AREA (FixedPcdGet32 (PcdSevEsWorkAreaBase)) - %define SEV_ES_WORK_AREA_SIZE 25 - %define SEV_ES_WORK_AREA_STATUS_MSR (FixedPcdGet32 (PcdSevEsWorkAreaBase= )) - %define SEV_ES_WORK_AREA_RDRAND (FixedPcdGet32 (PcdSevEsWorkAreaBase) + = 8) - %define SEV_ES_WORK_AREA_ENC_MASK (FixedPcdGet32 (PcdSevEsWorkAreaBase) = + 16) - %define SEV_ES_WORK_AREA_RECEIVED_VC (FixedPcdGet32 (PcdSevEsWorkAreaBas= e) + 24) - %define SEV_ES_VC_TOP_OF_STACK (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase)= + FixedPcdGet32 (PcdOvmfSecPeiTempRamSize)) - %define SEV_SNP_SECRETS_BASE (FixedPcdGet32 (PcdOvmfSnpSecretsBase)) - %define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSize)) - %define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase)) - %define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize)) - %define SNP_SEC_MEM_BASE_DESC_1 (FixedPcdGet32 (PcdOvmfSecPageTablesBase= )) - %define SNP_SEC_MEM_SIZE_DESC_1 (FixedPcdGet32 (PcdOvmfSecGhcbBase) - SN= P_SEC_MEM_BASE_DESC_1) - ; - ; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used - ; as GHCB shared page and second is used for bookkeeping to support the - ; nested GHCB in SEC phase. The bookkeeping page is mapped private. The = VMM - ; does not need to validate the shared page but it need to validate the - ; bookkeeping page. - ; - %define SNP_SEC_MEM_BASE_DESC_2 (GHCB_BASE + 0x1000) - %define SNP_SEC_MEM_SIZE_DESC_2 (SEV_SNP_SECRETS_BASE - SNP_SEC_MEM_BASE= _DESC_2) - %define SNP_SEC_MEM_BASE_DESC_3 (CPUID_BASE + CPUID_SIZE) - %define SNP_SEC_MEM_SIZE_DESC_3 (FixedPcdGet32 (PcdOvmfPeiMemFvBase) - S= NP_SEC_MEM_BASE_DESC_3) - -%include "X64/IntelTdxMetadata.asm" -%include "Ia32/Flat32ToFlat64.asm" %include "Ia32/AmdSev.asm" -%include "Ia32/PageTables64.asm" -%include "Ia32/IntelTdx.asm" -%include "X64/OvmfSevMetadata.asm" -%endif =20 %include "Ia16/Real16ToFlat32.asm" %include "Ia16/Init16.asm" --=20 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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