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Wed, 15 Feb 2023 08:01:57 +0000 X-Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 15 Feb 2023 02:01:57 -0600 X-Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Wed, 15 Feb 2023 00:01:57 -0800 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Wed, 15 Feb 2023 02:01:55 -0600 From: "Abdul Lateef Attar via groups.io" To: CC: Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar Subject: [edk2-devel] [PATCH v5 5/6] UefiCpuPkg: Initial implementation of AMD's SmmCpuFeaturesLib Date: Wed, 15 Feb 2023 13:31:42 +0530 Message-ID: <7c00738614ac1704c687bc0be762bb59e3205506.1676447938.git.abdattar@amd.com> In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT059:EE_|SA1PR12MB7221:EE_ X-MS-Office365-Filtering-Correlation-Id: 04b63e54-d7ed-4017-ac41-08db0f2ae932 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: QT8xCmzyFo3+sdNzH+s8+8x5JtFFyV7n/XnfFqtxShHI/UJDrzfIsC4KeMc5dZLNIDzpVqr6m1WnGjpLXQSY4VnAWXWWoni6IweVCmiwa44XmWt0/+50njOHHVUMEJ+SPR3vJ44o0xaUMnVvRFRv0+mVK7kDU5AEvT+lDROhSjTgtQ5OyrdWadRKCc5XlRBDrmyC36Tfu/NuvJhjeFP7UwJApJkKAl6keUN9BiqvBWwBp3ijp0nnmUv3bBvI4zYvlOzgIctCqDyyxQeD5GFvc9RLj2SkBMlz32+pDJB+h0tCEJL2FwecY+UdYRfHyyepGkqgmbR5WOxWroZStSkob+mIlYN5xkYIaTaqJmbndmpiFwwLpbUFI+2LenNT3wadMqExfxPzuOnNU7w6DCutlC84tnBTKwkvVAv/2gDBLd4xX5rQHJZDvaEmwUIzCH6v+drL3YRxZ5Xdbel6OfffNMTu+4AqrKU+40cRguCrfW1mcDkH5dHObH/2/OOfUy2Y6fuULgzonbQNDIn134wOqqKPANh4ztsK1w2t3kEubXLO3mcosoTqxjDELVhfTxQX2C9ZIMwaGm9FRV+nBGBs77X0GZ4oITfTCXZZ/UYzDQCj/XcaiTBnOG5895CreK8k/GCod+Gu6pe3SFJiQ7uptBBcY37DDl575JMSkZYQ6eBxX1M92UN/0UDAdJyRGTsXQV8GpqnRvb1Nc82oiASpFwrQUUoFl0HSceInCd+pff4= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Feb 2023 08:01:57.7731 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 04b63e54-d7ed-4017-ac41-08db0f2ae932 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7221 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abdattar@amd.com X-Gm-Message-State: iTJwGfU9YWTF3yYUzCOPUP3Kx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1676448122; bh=w9VpoTp1uIcskrYiVouwck3+dxfrERnuE0btr6nojOc=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=ClaY7b3KBKoeTFiWk9kyQK1nnCJT7T7dHdTC2D4ywRf0xjXa7BDl3eMG8C1VWSMpnSR AUZIiN2B/PsEaaxOXiDP6CEp3QZ9+/DOG9SsnE4T7DfQ6V7PGIhsvOfzPxhanuhYosoTc 8huMluGYpbWc5mtrLf0xBikfihb+k9tHUPo= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1676448125068100004 Content-Type: text/plain; charset="utf-8" From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Adds initial defination for AMD's SmmCpuFeaturesLib library implementation. All function's body either empty or just returns value. Its initial skeleton of library implementation. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang --- UefiCpuPkg/UefiCpuPkg.dsc | 8 + .../AmdSmmCpuFeaturesLib.inf | 33 ++ .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 345 ++++++++++++++++++ 3 files changed, 386 insertions(+) create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesL= ib.inf create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesL= ib.c diff --git a/UefiCpuPkg/UefiCpuPkg.dsc b/UefiCpuPkg/UefiCpuPkg.dsc index 99f7532ce00b..1833d35fb354 100644 --- a/UefiCpuPkg/UefiCpuPkg.dsc +++ b/UefiCpuPkg/UefiCpuPkg.dsc @@ -178,6 +178,13 @@ [Components.IA32, Components.X64] SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLibStm.inf } + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf { + + FILE_GUID =3D B7242C74-BD21-49EE-84B4-07162E8C080D + + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeat= uresLib.inf + SmmCpuPlatformHookLib|UefiCpuPkg/Library/SmmCpuPlatformHookLibNull/S= mmCpuPlatformHookLibNull.inf + } UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf UefiCpuPkg/ResetVector/Vtf0/Bin/ResetVector.inf UefiCpuPkg/Library/SmmCpuRendezvousLib/SmmCpuRendezvousLib.inf @@ -194,6 +201,7 @@ [Components.IA32, Components.X64] UnitTestResultReportLib|UnitTestFrameworkPkg/Library/UnitTestResultR= eportLib/UnitTestResultReportLibConOut.inf } UefiCpuPkg/Library/SmmSmramSaveStateLib/AmdSmmSmramSaveStateLib.inf + UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf =20 [Components.X64] UefiCpuPkg/Library/CpuExceptionHandlerLib/UnitTest/DxeCpuExceptionHandle= rLibUnitTest.inf diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf new file mode 100644 index 000000000000..4c77efc64462 --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -0,0 +1,33 @@ +## @file +# The CPU specific programming for PiSmmCpuDxeSmm module. +# +# Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SmmCpuFeaturesLib + MODULE_UNI_FILE =3D SmmCpuFeaturesLib.uni + FILE_GUID =3D 5849E964-78EC-428E-8CBD-848A7E359134 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D SmmCpuFeaturesLib + CONSTRUCTOR =3D SmmCpuFeaturesLibConstructor + +[Sources] + SmmCpuFeaturesLib.c + SmmCpuFeaturesLibCommon.c + AmdSmmCpuFeaturesLib.c + +[Packages] + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseLib + PcdLib + MemoryAllocationLib + DebugLib diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/= UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c new file mode 100644 index 000000000000..c74e1a0c0c5b --- /dev/null +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c @@ -0,0 +1,345 @@ +/** @file +Implementation specific to the SmmCpuFeatureLib library instance +for AMD based platforms. + +Copyright (c) 2010 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) Microsoft Corporation.
+Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include + +/** + Read an SMM Save State register on the target processor. If this functi= on + returns EFI_UNSUPPORTED, then the caller is responsible for reading the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to read the SMM Save State. = The + value must be between 0 and the NumberOfCpus field= in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to read. + @param[in] Width The number of bytes to read from the CPU save stat= e. + @param[out] Buffer Upon return, this holds the CPU register value read + from the save state. + + @retval EFI_SUCCESS The register was read from Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support reading Reg= ister. + +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesReadSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + OUT VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +/** + Writes an SMM Save State register on the target processor. If this func= tion + returns EFI_UNSUPPORTED, then the caller is responsible for writing the + SMM Save Sate register. + + @param[in] CpuIndex The index of the CPU to write the SMM Save State. = The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] Register The SMM Save State register to write. + @param[in] Width The number of bytes to write to the CPU save state. + @param[in] Buffer Upon entry, this holds the new CPU register value. + + @retval EFI_SUCCESS The register was written to Save State. + @retval EFI_INVALID_PARAMTER Buffer is NULL. + @retval EFI_UNSUPPORTED This function does not support writing Reg= ister. +**/ +EFI_STATUS +EFIAPI +SmmCpuFeaturesWriteSaveStateRegister ( + IN UINTN CpuIndex, + IN EFI_SMM_SAVE_STATE_REGISTER Register, + IN UINTN Width, + IN CONST VOID *Buffer + ) +{ + return EFI_SUCCESS; +} + +/** + Performs library initialization. + + This initialization function contains common functionality shared betwen= all + library instance constructors. + +**/ +VOID +CpuFeaturesLibInitialization ( + VOID + ) +{ +} + +/** + Called during the very first SMI into System Management Mode to initiali= ze + CPU features, including SMBASE, for the currently executing CPU. Since = this + is the first SMI, the SMRAM Save State Map is at the default address of + AMD_SMM_DEFAULT_SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET. The currently exe= cuting + CPU is specified by CpuIndex and CpuIndex can be used to access informat= ion + about the currently executing CPU in the ProcessorInfo array and the + HotPlugCpuData data structure. + + @param[in] CpuIndex The index of the CPU to initialize. The value + must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] IsMonarch TRUE if the CpuIndex is the index of the CPU = that + was elected as monarch during System Manageme= nt + Mode initialization. + FALSE if the CpuIndex is not the index of the= CPU + that was elected as monarch during System + Management Mode initialization. + @param[in] ProcessorInfo Pointer to an array of EFI_PROCESSOR_INFORMAT= ION + structures. ProcessorInfo[CpuIndex] contains= the + information for the currently executing CPU. + @param[in] CpuHotPlugData Pointer to the CPU_HOT_PLUG_DATA structure th= at + contains the ApidId and SmBase arrays. +**/ +VOID +EFIAPI +SmmCpuFeaturesInitializeProcessor ( + IN UINTN CpuIndex, + IN BOOLEAN IsMonarch, + IN EFI_PROCESSOR_INFORMATION *ProcessorInfo, + IN CPU_HOT_PLUG_DATA *CpuHotPlugData + ) +{ +} + +/** + This function updates the SMRAM save state on the currently executing CPU + to resume execution at a specific address after an RSM instruction. This + function must evaluate the SMRAM save state to determine the execution m= ode + the RSM instruction resumes and update the resume execution address with + either NewInstructionPointer32 or NewInstructionPoint. The auto HALT re= start + flag in the SMRAM save state must always be cleared. This function retu= rns + the value of the instruction pointer from the SMRAM save state that was + replaced. If this function returns 0, then the SMRAM save state was not + modified. + + This function is called during the very first SMI on each CPU after + SmmCpuFeaturesInitializeProcessor() to set a flag in normal execution mo= de + to signal that the SMBASE of each CPU has been updated before the default + SMBASE address is used for the first SMI to the next CPU. + + @param[in] CpuIndex The index of the CPU to hook. The v= alue + must be between 0 and the NumberOfCp= us + field in the System Management Syste= m Table + (SMST). + @param[in] CpuState Pointer to SMRAM Save State Map for = the + currently executing CPU. + @param[in] NewInstructionPointer32 Instruction pointer to use if resumi= ng to + 32-bit execution mode from 64-bit SM= M. + @param[in] NewInstructionPointer Instruction pointer to use if resumi= ng to + same execution mode as SMM. + + @retval 0 This function did modify the SMRAM save state. + @retval > 0 The original instruction pointer value from the SMRAM save = state + before it was replaced. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesHookReturnFromSmm ( + IN UINTN CpuIndex, + IN SMRAM_SAVE_STATE_MAP *CpuState, + IN UINT64 NewInstructionPointer32, + IN UINT64 NewInstructionPointer + ) +{ + return 0; +} + +/** + Return the size, in bytes, of a custom SMI Handler in bytes. If 0 is + returned, then a custom SMI handler is not provided by this library, + and the default SMI handler must be used. + + @retval 0 Use the default SMI handler. + @retval > 0 Use the SMI handler installed by SmmCpuFeaturesInstallSmiHa= ndler() + The caller is required to allocate enough SMRAM for each CP= U to + support the size of the custom SMI handler. +**/ +UINTN +EFIAPI +SmmCpuFeaturesGetSmiHandlerSize ( + VOID + ) +{ + return 0; +} + +/** + Install a custom SMI handler for the CPU specified by CpuIndex. This fu= nction + is only called if SmmCpuFeaturesGetSmiHandlerSize() returns a size is gr= eater + than zero and is called by the CPU that was elected as monarch during Sy= stem + Management Mode initialization. + + @param[in] CpuIndex The index of the CPU to install the custom SMI han= dler. + The value must be between 0 and the NumberOfCpus f= ield + in the System Management System Table (SMST). + @param[in] SmBase The SMBASE address for the CPU specified by CpuInd= ex. + @param[in] SmiStack The stack to use when an SMI is processed by the + the CPU specified by CpuIndex. + @param[in] StackSize The size, in bytes, if the stack used when an SMI = is + processed by the CPU specified by CpuIndex. + @param[in] GdtBase The base address of the GDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] GdtSize The size, in bytes, of the GDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtBase The base address of the IDT to use when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] IdtSize The size, in bytes, of the IDT used when an SMI is + processed by the CPU specified by CpuIndex. + @param[in] Cr3 The base address of the page tables to use when an= SMI + is processed by the CPU specified by CpuIndex. +**/ +VOID +EFIAPI +SmmCpuFeaturesInstallSmiHandler ( + IN UINTN CpuIndex, + IN UINT32 SmBase, + IN VOID *SmiStack, + IN UINTN StackSize, + IN UINTN GdtBase, + IN UINTN GdtSize, + IN UINTN IdtBase, + IN UINTN IdtSize, + IN UINT32 Cr3 + ) +{ +} + +/** + Determines if MTRR registers must be configured to set SMRAM cache-abili= ty + when executing in System Management Mode. + + @retval TRUE MTRR registers must be configured to set SMRAM cache-abil= ity. + @retval FALSE MTRR registers do not need to be configured to set SMRAM + cache-ability. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesNeedConfigureMtrrs ( + VOID + ) +{ + return FALSE; +} + +/** + Disable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigu= reMtrrs() + returns TRUE. +**/ +VOID +EFIAPI +SmmCpuFeaturesDisableSmrr ( + VOID + ) +{ +} + +/** + Enable SMRR register if SMRR is supported and SmmCpuFeaturesNeedConfigur= eMtrrs() + returns TRUE. +**/ +VOID +EFIAPI +SmmCpuFeaturesReenableSmrr ( + VOID + ) +{ +} + +/** + Processor specific hook point each time a CPU enters System Management M= ode. + + @param[in] CpuIndex The index of the CPU that has entered SMM. The val= ue + must be between 0 and the NumberOfCpus field in the + System Management System Table (SMST). +**/ +VOID +EFIAPI +SmmCpuFeaturesRendezvousEntry ( + IN UINTN CpuIndex + ) +{ +} + +/** + Returns the current value of the SMM register for the specified CPU. + If the SMM register is not supported, then 0 is returned. + + @param[in] CpuIndex The index of the CPU to read the SMM register. The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to read. + + @return The value of the SMM register specified by RegName from the CPU + specified by CpuIndex. +**/ +UINT64 +EFIAPI +SmmCpuFeaturesGetSmmRegister ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + return 0; +} + +/** + Sets the value of an SMM register on a specified CPU. + If the SMM register is not supported, then no action is performed. + + @param[in] CpuIndex The index of the CPU to write the SMM register. The + value must be between 0 and the NumberOfCpus field = in + the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to write. + registers are read-only. + @param[in] Value The value to write to the SMM register. +**/ +VOID +EFIAPI +SmmCpuFeaturesSetSmmRegister ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName, + IN UINT64 Value + ) +{ +} + +/** + Check to see if an SMM register is supported by a specified CPU. + + @param[in] CpuIndex The index of the CPU to check for SMM register supp= ort. + The value must be between 0 and the NumberOfCpus fi= eld + in the System Management System Table (SMST). + @param[in] RegName Identifies the SMM register to check for support. + + @retval TRUE The SMM register specified by RegName is supported by the= CPU + specified by CpuIndex. + @retval FALSE The SMM register specified by RegName is not supported by= the + CPU specified by CpuIndex. +**/ +BOOLEAN +EFIAPI +SmmCpuFeaturesIsSmmRegisterSupported ( + IN UINTN CpuIndex, + IN SMM_REG_NAME RegName + ) +{ + return FALSE; +} --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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