From nobody Sat Dec 21 14:20:49 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+109603+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109603+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=163.com ARC-Seal: i=1; a=rsa-sha256; t=1697216170; cv=none; d=zohomail.com; s=zohoarc; b=j9v3uHsMh7na0hvoegGt6m7Ef4LSk8FE2zitbsoM1O3CchZnSguIc8XBsZK484FU/XlhdmFfTwLzn2Rr6xu8Aw+Ig09Vz20X9f8LsI/qpcKeWC0KIC9s+UlRaiOvNGGR1+m7Tnyj2k8yn/9Kc+yAa3pDAcnnkK0yoir/rCDdoR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1697216170; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Reply-To:References:Sender:Subject:Subject:To:To:Message-Id; bh=Jpv3StbutOUbIVyZyfLdxmHpIc8BlQWaSQ3v9VwNRYQ=; b=LWfq/NtgkGyWpIpw14Ql9Ct4ZJWWtgPc8dB1JRJW+RLe18lkpv6Bv+tB0K2SD0z7fIihhRWx2CyZX+wjH5Svbb13CfmlGOK1JW9n5wGMUGY2Dh+wV8Lh1uhW2R+T9Sy4HTJJI8ruEecM2xhV4klBTZyPBOrMJ2XknJGG30FvzlI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+109603+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1697216170181635.0744994377885; Fri, 13 Oct 2023 09:56:10 -0700 (PDT) Return-Path: DKIM-Signature: a=rsa-sha256; bh=OkcGRgXMntZoeHj0S+mNE4t/X72WLX1qFgTriBSsFqU=; c=relaxed/simple; d=groups.io; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding; s=20140610; t=1697216169; v=1; b=e9fYk4P4ZE76HUjpkBi2lX4c+rUf0/XGKQwdTGwtOJ9O+B1iykNfXPln4rB8tOEmvdU+U3Kd K8fDBPqpeWXHJtOdNR2Jy+p1+G1TsWaatsXObJVj9TOJGP25cneuycXsNN8ITHPWROmvbkYNatl 9dWFPlrfixe0u7FBv+Oth5JI= X-Received: by 127.0.0.2 with SMTP id EabLYY1788612xTbxDmzrOK6; Fri, 13 Oct 2023 09:56:09 -0700 X-Received: from m15.mail.163.com (m15.mail.163.com [45.254.50.219]) by mx.groups.io with SMTP id smtpd.web10.30859.1697166168677821682 for ; Thu, 12 Oct 2023 20:02:49 -0700 X-Received: from rv-uefi.. (unknown [211.87.236.31]) by zwqz-smtp-mta-g0-2 (Coremail) with SMTP id _____wD3v6FTsyhlo02nAQ--.33906S2; Fri, 13 Oct 2023 11:02:43 +0800 (CST) From: caiyuqing_hz@163.com To: devel@edk2.groups.io Cc: USER0FISH , sunilvl@ventanamicro.com, Leif Lindholm , Michael D Kinney , Inochi Amaoto Subject: [edk2-devel] [PATCH edk2-platforms v5 4/7] Sophgo/SG2042Pkg: Add SEC module. Date: Fri, 13 Oct 2023 11:02:43 +0800 Message-Id: <73f493046d9ec69a4a29a5d06d0dbd648fbc1360.1697120122.git.caiyuqing_hz@outlook.com> In-Reply-To: References: MIME-Version: 1.0 X-CM-TRANSID: _____wD3v6FTsyhlo02nAQ--.33906S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfWF43urW8JFWUWr18Xr17Awb_yoW8tw47to Z7KFZ2yr48Gws8ur1IkwnrGw47WFnIgay3Xr1rtFWqvF4vvrnIvayxXa45G3s8Ar18G3yD Ww4fX3s7JFZIqrykn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxUcSdyUUUUU X-Originating-IP: [211.87.236.31] X-CM-SenderInfo: 5fdl535tlqwslk26il2tof0z/1tbiKAYIxV7WNZtyPAABsK Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,caiyuqing_hz@163.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: dMhon8EPNOj9cwWUHQbIrk14x1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1697216172204100018 Content-Type: text/plain; charset="utf-8" From: caiyuqing379 This module supports Sophgo SG2042 EVB platform. It uses the PEI less design. Add this module in SG2042Pkg leveraging the one from OvmfPkg/RiscVVirt. Add only lowest memory node in SEC module. Currently, RISC-V with a multi-range memory layout hits relocation overflow problems, so only one DDR can be inserted if you want to boot the Linux OS via GRUB2. Referring to [1], this seems to be an issue with GRUB2. When using the no-map attribute in dt, OpenSBI 1.3/1.3.1 should be used which fixed its no-map issue. Otherwise, maybe get into some issues in linux kernel. [1]https://lore.kernel.org/all/55d68176-bbf4-4310-e718-6127c3de497e@intel.c= om/T/ Signed-off-by: caiyuqing379 Co-authored-by: USER0FISH Cc: dahogn Cc: meng-cz Cc: yli147 Cc: ChaiEvan Cc: Leif Lindholm Cc: Michael D Kinney Cc: Sunil V L --- Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf | 68 +++++ Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h | 104 +++++++ Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c | 29 ++ Silicon/Sophgo/SG2042Pkg/Sec/Memory.c | 327 +++++++++++++++++++++++ Silicon/Sophgo/SG2042Pkg/Sec/Platform.c | 130 +++++++++ Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c | 115 ++++++++ Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S | 18 ++ 7 files changed, 791 insertions(+) create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Memory.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/Platform.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c create mode 100644 Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf b/Silicon/Sophgo/SG20= 42Pkg/Sec/SecMain.inf new file mode 100644 index 000000000000..3b4d6d6b86bc --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.inf @@ -0,0 +1,68 @@ +## @file +# SEC Driver for RISC-V +# +# Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+# Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Univers= iy, China.P.R. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x0001001B + BASE_NAME =3D SecMainRiscV64 + FILE_GUID =3D 125E1236-9D4F-457B-BF7E-6311C88A1621 + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SecMain + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D RISCV64 +# + +[Sources] + SecEntry.S + SecMain.c + SecMain.h + Cpu.c + Memory.c + Platform.c + +[Packages] + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + Silicon/Sophgo/SG2042Pkg/SG2042Pkg.dec + Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec + +[LibraryClasses] + BaseLib + DebugLib + PcdLib + IoLib + PeCoffLib + LzmaDecompressLib + RiscVSbiLib + PrePiLib + FdtLib + MemoryAllocationLib + HobLib + SerialPortLib + +[FixedPcd] + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvBase = ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdRiscVDxeFvSize = ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionBaseAddress= ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdVariableFirmwareRegionSize = ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamBase = ## CONSUMES + gUefiRiscVPlatformPkgTokenSpaceGuid.PcdTemporaryRamSize = ## CONSUMES + +[Guids] + gFdtHobGuid ## PRODUCES + +[BuildOptions] + GCC:*_*_*_PP_FLAGS =3D -D__ASSEMBLY__ + diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h b/Silicon/Sophgo/SG2042= Pkg/Sec/SecMain.h new file mode 100644 index 000000000000..9d615e9fa6a1 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.h @@ -0,0 +1,104 @@ +/** @file + Master header file for SecCore. + + Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universi= y, China.P.R. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef SEC_MAIN_H_ +#define SEC_MAIN_H_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + @param SizeOfRam Size of the temporary memory available for us= e. + @param TempRamBase Base address of temporary ram + @param BootFirmwareVolume Base address of the Boot Firmware Volume. +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ); + +/** + Auto-generated function that calls the library constructors for all of t= he module's + dependent libraries. This function must be called by the SEC Core once = a stack has + been established. + +**/ +VOID +EFIAPI +ProcessLibraryConstructorList ( + VOID + ); + +/** + Perform Platform PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + IN VOID *DeviceTreeAddress + ); + +/** + Perform Memory PEIM initialization. + + @param DeviceTreeAddress Pointer to FDT. + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +MemoryPeimInitialization ( + IN VOID *DeviceTreeAddress + ); + +/** + Perform CPU PEIM initialization. + + @return EFI_SUCCESS The platform initialized successfully. + @retval Others - As the error code indicates + +**/ +EFI_STATUS +EFIAPI +CpuPeimInitialization ( + VOID + ); + +#endif diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c b/Silicon/Sophgo/SG2042Pkg/= Sec/Cpu.c new file mode 100644 index 000000000000..c72bafdcc478 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Cpu.c @@ -0,0 +1,29 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include + +/** + Cpu Peim initialization. + +**/ +EFI_STATUS +CpuPeimInitialization ( + VOID + ) +{ + // + // for MMU type >=3D sv39 + // + BuildCpuHob (40, 39); + + return EFI_SUCCESS; +} diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c b/Silicon/Sophgo/SG2042P= kg/Sec/Memory.c new file mode 100644 index 000000000000..e2b624000987 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Memory.c @@ -0,0 +1,327 @@ +/** @file + Memory Detection for SG2042 EVB. + + Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right= s reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universi= y, China.P.R. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +Module Name: + + MemDetect.c + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +/** + Create memory range resource HOB using the memory base + address and size. + + @param MemoryBase Memory range base address. + @param MemorySize Memory range size. + +**/ +STATIC +VOID +AddMemoryBaseSizeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN UINT64 MemorySize + ) +{ + BuildResourceDescriptorHob ( + EFI_RESOURCE_SYSTEM_MEMORY, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Create memory range resource HOB using memory base + address and top address of the memory range. + + @param MemoryBase Memory range base address. + @param MemoryLimit Memory range size. + +**/ +STATIC +VOID +AddMemoryRangeHob ( + IN EFI_PHYSICAL_ADDRESS MemoryBase, + IN EFI_PHYSICAL_ADDRESS MemoryLimit + ) +{ + AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); +} + +/** + Publish system RAM and reserve memory regions. + +**/ +STATIC +VOID +InitializeRamRegions ( + IN EFI_PHYSICAL_ADDRESS SystemMemoryBase, + IN UINT64 SystemMemorySize + ) +{ + AddMemoryRangeHob ( + SystemMemoryBase, + SystemMemoryBase + SystemMemorySize + ); +} + +/** Get the number of cells for a given property + + @param[in] Fdt Pointer to Device Tree (DTB) + @param[in] Node Node + @param[in] Name Name of the property + + @return Number of cells. +**/ +STATIC +INT32 +GetNumCells ( + IN VOID *Fdt, + IN INT32 Node, + IN CONST CHAR8 *Name + ) +{ + CONST INT32 *Prop; + INT32 Len; + UINT32 Val; + + Prop =3D fdt_getprop (Fdt, Node, Name, &Len); + if (Prop =3D=3D NULL) { + return Len; + } + + if (Len !=3D sizeof (*Prop)) { + return -FDT_ERR_BADNCELLS; + } + + Val =3D fdt32_to_cpu (*Prop); + if (Val > FDT_MAX_NCELLS) { + return -FDT_ERR_BADNCELLS; + } + + return (INT32)Val; +} + +/** Mark reserved memory ranges in the EFI memory map + + * As per DT spec v0.4 Section 3.5.4, + * "Reserved regions with the no-map property must be listed in the + * memory map with type EfiReservedMemoryType. All other reserved + * regions must be listed with type EfiBootServicesData." + + @param FdtPointer Pointer to FDT + +**/ +STATIC +VOID +AddReservedMemoryMap ( + IN VOID *FdtPointer + ) +{ + CONST INT32 *RegProp; + INT32 Node; + INT32 SubNode; + INT32 Len; + EFI_PHYSICAL_ADDRESS Addr; + UINT64 Size; + INTN NumRsv, i; + INT32 NumAddrCells, NumSizeCells; + + NumRsv =3D fdt_num_mem_rsv (FdtPointer); + + /* Look for an existing entry and add it to the efi mem map. */ + for (i =3D 0; i < NumRsv; i++) { + if (fdt_get_mem_rsv (FdtPointer, i, &Addr, &Size) !=3D 0) { + continue; + } + + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } + + /* process reserved-memory */ + Node =3D fdt_subnode_offset (FdtPointer, 0, "reserved-memory"); + if (Node >=3D 0) { + NumAddrCells =3D GetNumCells (FdtPointer, Node, "#address-cells"); + if (NumAddrCells <=3D 0) { + return; + } + + NumSizeCells =3D GetNumCells (FdtPointer, Node, "#size-cells"); + if (NumSizeCells <=3D 0) { + return; + } + + fdt_for_each_subnode (SubNode, FdtPointer, Node) { + RegProp =3D fdt_getprop (FdtPointer, SubNode, "reg", &Len); + + if ((RegProp !=3D 0) && (Len =3D=3D ((NumAddrCells + NumSizeCells) *= sizeof (INT32)))) { + Addr =3D fdt32_to_cpu (RegProp[0]); + + if (NumAddrCells > 1) { + Addr =3D (Addr << 32) | fdt32_to_cpu (RegProp[1]); + } + + RegProp +=3D NumAddrCells; + Size =3D fdt32_to_cpu (RegProp[0]); + + if (NumSizeCells > 1) { + Size =3D (Size << 32) | fdt32_to_cpu (RegProp[1]); + } + + DEBUG (( + DEBUG_INFO, + "%a: Adding Reserved Memory Addr =3D 0x%llx, Size =3D 0x%llx\n", + __func__, + Addr, + Size + )); + + // OpenSBI 1.3/1.3.1 should be used which fixed its no-map issue. + if (fdt_getprop (FdtPointer, SubNode, "no-map", &Len)) { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiReservedMemoryType + ); + } else { + BuildMemoryAllocationHob ( + Addr, + Size, + EfiBootServicesData + ); + } + } + } + } +} + +/** + Initialize memory hob based on the DTB information. + + NOTE: The memory space size of SG2042 EVB is determined by the number + and size of DDRs inserted on the board. There is an error with initializ= ing + the system ram space of each memory node separately using InitializeRamR= egions, + so InitializeRamRegions is only called once for total system ram initial= ization. + + @param DeviceTreeAddress Pointer to FDT. + @return EFI_SUCCESS The memory hob added successfully. + +**/ +EFI_STATUS +MemoryPeimInitialization ( + IN VOID *DeviceTreeAddress + ) +{ + CONST UINT64 *RegProp; + CONST CHAR8 *Type; + UINT64 UefiMemoryBase; + UINT64 CurBase; + UINT64 CurSize; + UINT64 LowestMemBase; + UINT64 LowestMemSize; + INT32 Node; + INT32 Prev; + INT32 Len; + + UefiMemoryBase =3D (UINT64)FixedPcdGet32 (PcdTemporaryRamBase) + FixedPc= dGet32 (PcdTemporaryRamSize) - SIZE_32MB; + LowestMemBase =3D 0; + LowestMemSize =3D 0; + + // Look for the lowest memory node + for (Prev =3D 0; ; Prev =3D Node) { + Node =3D fdt_next_node (DeviceTreeAddress, Prev, NULL); + if (Node < 0) { + break; + } + + // Check for memory node + Type =3D fdt_getprop (DeviceTreeAddress, Node, "device_type", &Len); + if (Type && (AsciiStrnCmp (Type, "memory", Len) =3D=3D 0)) { + // Get the 'reg' property of this node. For now, we will assume + // two 8 byte quantities for base and size, respectively. + RegProp =3D fdt_getprop (DeviceTreeAddress, Node, "reg", &Len); + if ((RegProp !=3D 0) && (Len =3D=3D (2 * sizeof (UINT64)))) { + CurBase =3D fdt64_to_cpu (ReadUnaligned64 (RegProp)); + CurSize =3D fdt64_to_cpu (ReadUnaligned64 (RegProp + 1)); + + DEBUG (( + DEBUG_INFO, + "%a: System RAM @ 0x%lx - 0x%lx\n", + __func__, + CurBase, + CurBase + CurSize - 1 + )); + + if ((LowestMemBase =3D=3D 0) || (CurBase <=3D LowestMemBase)) { + LowestMemBase =3D CurBase; + LowestMemSize =3D CurSize; + } + + } else { + DEBUG (( + DEBUG_ERROR, + "%a: Failed to parse FDT memory node\n", + __func__ + )); + } + } + } + + if (UefiMemoryBase > LowestMemBase) { + LowestMemBase =3D UefiMemoryBase; + LowestMemSize -=3D UefiMemoryBase; + } + + DEBUG (( + DEBUG_INFO, + "%a: Total System RAM @ 0x%lx - 0x%lx\n", + __func__, + LowestMemBase, + LowestMemBase + LowestMemSize - 1 + )); + + InitializeRamRegions (LowestMemBase, LowestMemSize); + + AddReservedMemoryMap (DeviceTreeAddress); + + /* Make sure SEC is booting with bare mode */ + ASSERT ((RiscVGetSupervisorAddressTranslationRegister () & SATP64_MODE) = =3D=3D (SATP_MODE_OFF << SATP64_MODE_SHIFT)); + + BuildMemoryTypeInformationHob (); + + return EFI_SUCCESS; +} diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/Platform.c b/Silicon/Sophgo/SG204= 2Pkg/Sec/Platform.c new file mode 100644 index 000000000000..21885a956088 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/Platform.c @@ -0,0 +1,130 @@ +/** @file +The library call to pass the device tree to DXE via HOB. + +Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights = reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Build memory map I/O range resource HOB using the + base address and size. + + @param MemoryBase Memory map I/O base. + @param MemorySize Memory map I/O size. + +**/ +STATIC +VOID +AddIoMemoryBaseSizeHob ( + EFI_PHYSICAL_ADDRESS MemoryBase, + UINT64 MemorySize + ) +{ + /* Align to EFI_PAGE_SIZE */ + MemorySize =3D ALIGN_VALUE (MemorySize, EFI_PAGE_SIZE); + BuildResourceDescriptorHob ( + EFI_RESOURCE_MEMORY_MAPPED_IO, + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED, + MemoryBase, + MemorySize + ); +} + +/** + Populate IO resources from FDT that not added to GCD by its + driver in the DXE phase. + + @param FdtBase Fdt base address + @param Compatible Compatible string + +**/ +STATIC +VOID +PopulateIoResources ( + VOID *FdtBase, + CONST CHAR8 *Compatible + ) +{ + UINT64 *Reg; + INT32 Node, LenP; + + Node =3D fdt_node_offset_by_compatible (FdtBase, -1, Compatible); + while (Node !=3D -FDT_ERR_NOTFOUND) { + Reg =3D (UINT64 *)fdt_getprop (FdtBase, Node, "reg", &LenP); + if (Reg) { + ASSERT (LenP =3D=3D (2 * sizeof (UINT64))); + AddIoMemoryBaseSizeHob (SwapBytes64 (Reg[0]), SwapBytes64 (Reg[1])); + } + + Node =3D fdt_node_offset_by_compatible (FdtBase, Node, Compatible); + } +} + +/** + @param DeviceTreeAddress Pointer to FDT. + @retval EFI_SUCCESS The address of FDT is passed in HOB. + EFI_UNSUPPORTED Can't locate FDT. +**/ +EFI_STATUS +EFIAPI +PlatformPeimInitialization ( + IN VOID *DeviceTreeAddress + ) +{ + VOID *Base; + VOID *NewBase; + UINTN FdtSize; + UINTN FdtPages; + UINT64 *FdtHobData; + + if (DeviceTreeAddress =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Invalid FDT pointer\n", __func__)); + return EFI_UNSUPPORTED; + } + + DEBUG ((DEBUG_INFO, "%a: Build FDT HOB - FDT at address: 0x%x \n", __fun= c__, DeviceTreeAddress)); + Base =3D DeviceTreeAddress; + if (fdt_check_header (Base) !=3D 0) { + DEBUG ((DEBUG_ERROR, "%a: Corrupted DTB\n", __func__)); + return EFI_UNSUPPORTED; + } + + FdtSize =3D fdt_totalsize (Base); + FdtPages =3D EFI_SIZE_TO_PAGES (FdtSize); + NewBase =3D AllocatePages (FdtPages); + if (NewBase =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not allocate memory for DTB\n", __func= __)); + return EFI_UNSUPPORTED; + } + + fdt_open_into (Base, NewBase, EFI_PAGES_TO_SIZE (FdtPages)); + + FdtHobData =3D BuildGuidHob (&gFdtHobGuid, sizeof *FdtHobData); + if (FdtHobData =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "%a: Could not build FDT Hob\n", __func__)); + return EFI_UNSUPPORTED; + } + + *FdtHobData =3D (UINTN)NewBase; + + BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)); + + PopulateIoResources (Base, "bitmain,bm-sd"); + PopulateIoResources (Base, "snps,dw-apb-uart"); + + return EFI_SUCCESS; +} diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c b/Silicon/Sophgo/SG2042= Pkg/Sec/SecMain.c new file mode 100644 index 000000000000..a75b8b819737 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecMain.c @@ -0,0 +1,115 @@ +/** @file + RISC-V SEC phase module for SG2042 EVB. + + Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
+ Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
+ Copyright (c) 2023, Academy of Intelligent Innovation, Shandong Universi= y, China.P.R. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "SecMain.h" + +/** + Initialize the memory and CPU, setting the boot mode, and platform + initialization. It also builds the core information HOB. + + @return EFI_SUCCESS Status. +**/ +STATIC +EFI_STATUS +EFIAPI +SecInitializePlatform ( + IN VOID *DeviceTreeAddress + ) +{ + EFI_STATUS Status; + + MemoryPeimInitialization (DeviceTreeAddress); + + CpuPeimInitialization (); + + // Set the Boot Mode + SetBootMode (BOOT_WITH_FULL_CONFIGURATION); + + Status =3D PlatformPeimInitialization (DeviceTreeAddress); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + + Entry point to the C language phase of SEC. After the SEC assembly + code has initialized some temporary memory and set up the stack, + the control is transferred to this function. + + + @param[in] BootHartId Hardware thread ID of boot hart. + @param[in] DeviceTreeAddress Pointer to Device Tree (DTB) +**/ +VOID +NORETURN +EFIAPI +SecStartup ( + IN UINTN BootHartId, + IN VOID *DeviceTreeAddress + ) +{ + EFI_HOB_HANDOFF_INFO_TABLE *HobList; + EFI_RISCV_FIRMWARE_CONTEXT FirmwareContext; + EFI_STATUS Status; + UINT64 UefiMemoryBase; + UINT64 StackBase; + UINT32 StackSize; + + SerialPortInitialize (); + + // + // Report Status Code to indicate entering SEC core + // + DEBUG (( + DEBUG_INFO, + "%a() BootHartId: 0x%x, DeviceTreeAddress=3D0x%x\n", + __func__, + BootHartId, + DeviceTreeAddress + )); + + FirmwareContext.BootHartId =3D BootHartId; + SetFirmwareContextPointer (&FirmwareContext); + + StackBase =3D (UINT64)FixedPcdGet32 (PcdTemporaryRamBase); + StackSize =3D FixedPcdGet32 (PcdTemporaryRamSize); + UefiMemoryBase =3D StackBase + StackSize - SIZE_32MB; + + // Declare the PI/UEFI memory region + HobList =3D HobConstructor ( + (VOID *)UefiMemoryBase, + SIZE_32MB, + (VOID *)UefiMemoryBase, + (VOID *)StackBase // The top of the UEFI Memory is reserved = for the stacks + ); + PrePeiSetHobList (HobList); + + SecInitializePlatform (DeviceTreeAddress); + + BuildStackHob (StackBase, StackSize); + + // + // Process all libraries constructor function linked to SecMain. + // + ProcessLibraryConstructorList (); + + // Assume the FV that contains the SEC (our code) also contains a compre= ssed FV. + Status =3D DecompressFirstFv (); + ASSERT_EFI_ERROR (Status); + + // Load the DXE Core and transfer control to it + Status =3D LoadDxeCoreFromFv (NULL, 0); + ASSERT_EFI_ERROR (Status); + // + // Should not come here. + // + UNREACHABLE (); +} diff --git a/Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S b/Silicon/Sophgo/SG204= 2Pkg/Sec/SecEntry.S new file mode 100644 index 000000000000..ee02317a6bc8 --- /dev/null +++ b/Silicon/Sophgo/SG2042Pkg/Sec/SecEntry.S @@ -0,0 +1,18 @@ +/* + Copyright (c) 2022 Ventana Micro Systems Inc. + + SPDX-License-Identifier: BSD-2-Clause-Patent + + */ + +#include "SecMain.h" + +ASM_FUNC (_ModuleEntryPoint) + /* Use Temp memory as the stack for calling to C code */ + li a4, FixedPcdGet32 (PcdTemporaryRamBase) + li a5, FixedPcdGet32 (PcdTemporaryRamSize) + + /* Use Temp memory as the stack for calling to C code */ + add sp, a4, a5 + + call SecStartup -- 2.34.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#109603): https://edk2.groups.io/g/devel/message/109603 Mute This Topic: https://groups.io/mt/101944467/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-