From nobody Mon Feb 9 11:32:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+85993+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85993+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1642901978; cv=none; d=zohomail.com; s=zohoarc; b=i3Bjy0XAFDG0LaypkLCui9exuAAd7x+F99nNWz2mR6ls3Hp9LGwnog+kmcW9W/1/960CCipdddAwgY8lSKJbC8qqKpZkLWYQ3CdPAWpy9IL4qOHihlC7P5BmMQ7eMIHztd++N75I1BeYbXxeCgaxdr4tLuuWPwMtUl1Gz18x6ps= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1642901978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=cdeE8gnvV1NpOFoCspXcY//yKOI8fKpTZRJoiZxBR4w=; b=iRQPy6L8JxCLsfOT3Qu3L8QqZUWFTMKHPxkuyFkpCXSEF3x2Y6HJJXDJzoZuM7lYVa4An5FxE7FurO3Xr/SJG8IuNii1c0PMOa+eVUUstjuWMK1KzFEZs9ivEmG+4tC8KUpx6JX2Rx15/CyDGEHbgbIx6YUySwLKJst357VRDDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+85993+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1642901978569419.37326008521984; Sat, 22 Jan 2022 17:39:38 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id zTDPYY1788612xFMclIC0Xld; Sat, 22 Jan 2022 17:39:38 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web08.4550.1642901975552765292 for ; Sat, 22 Jan 2022 17:39:36 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10235"; a="244686094" X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="244686094" X-Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:22 -0800 X-IronPort-AV: E=Sophos;i="5.88,309,1635231600"; d="scan'208";a="695033261" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.255.30.84]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Jan 2022 17:39:19 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V5 23/33] OvmfPkg: Refactor PlatformPei with PlatformInitLib Date: Sun, 23 Jan 2022 09:36:54 +0800 Message-Id: <69f38db6daff718e3d5a1856cb9e7b1eb2b2ff8e.1642899774.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: lztr7D99INAXJ26XEABDXiP2x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1642901978; bh=BvT0WzZWo1o3gnceDwWVD7HHy/mdl4x62s+17oUyQKU=; h=Cc:Date:From:Reply-To:Subject:To; b=jOmUC9pPEDzS8/bSxWzHwMcgE5r/QI2hg1mNIoCxl6Gf1/c8HSg9PeCOtBw4ru7E9nn HalAaHeHJJpdUyOz87U3eZ3BU9PxYgv+UvF4yYYooZuVdsVZoi9LBBD2JmMmqYBELLKjo mPvjenk7lGMkAyFQjXkIZg2ucs/76DG5IhQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1642901980420100006 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 PlatformInitLib wraps the common functions in OvmfPkg/PlatformPei. After it is introduced, OvmfPkg/PlatformPei is refactored with it. Other variants of PlatformPei will be refactored in the future as the next stages. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/AmdSev/AmdSevX64.dsc | 1 + OvmfPkg/CloudHv/CloudHvX64.dsc | 1 + OvmfPkg/Microvm/MicrovmX64.dsc | 1 + OvmfPkg/OvmfPkgIa32.dsc | 1 + OvmfPkg/OvmfPkgIa32X64.dsc | 1 + OvmfPkg/OvmfPkgX64.dsc | 1 + OvmfPkg/PlatformPei/Cmos.c | 55 --- OvmfPkg/PlatformPei/Cmos.h | 48 -- OvmfPkg/PlatformPei/MemDetect.c | 657 ++-------------------------- OvmfPkg/PlatformPei/Platform.c | 507 ++------------------- OvmfPkg/PlatformPei/Platform.h | 36 -- OvmfPkg/PlatformPei/PlatformPei.inf | 3 +- 12 files changed, 78 insertions(+), 1234 deletions(-) delete mode 100644 OvmfPkg/PlatformPei/Cmos.c delete mode 100644 OvmfPkg/PlatformPei/Cmos.h diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc index 648d3accd95c..53464f3a54b9 100644 --- a/OvmfPkg/AmdSev/AmdSevX64.dsc +++ b/OvmfPkg/AmdSev/AmdSevX64.dsc @@ -277,6 +277,7 @@ QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoad= ImageLib.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/CloudHv/CloudHvX64.dsc b/OvmfPkg/CloudHv/CloudHvX64.dsc index 191dd2c5053f..ddd2d67025e1 100644 --- a/OvmfPkg/CloudHv/CloudHvX64.dsc +++ b/OvmfPkg/CloudHv/CloudHvX64.dsc @@ -304,6 +304,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/Microvm/MicrovmX64.dsc b/OvmfPkg/Microvm/MicrovmX64.dsc index c45e37dc7da0..a09f542c83fb 100644 --- a/OvmfPkg/Microvm/MicrovmX64.dsc +++ b/OvmfPkg/Microvm/MicrovmX64.dsc @@ -301,6 +301,7 @@ QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf =20 MemEncryptSevLib|OvmfPkg/Library/BaseMemEncryptSevLib/PeiMemEncryptSevLi= b.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 [LibraryClasses.common.DXE_CORE] HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc index 085cc7ece15d..3f52939ab6d2 100644 --- a/OvmfPkg/OvmfPkgIa32.dsc +++ b/OvmfPkg/OvmfPkgIa32.dsc @@ -300,6 +300,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc index 57e8bfb6b80f..30e01feeb539 100644 --- a/OvmfPkg/OvmfPkgIa32X64.dsc +++ b/OvmfPkg/OvmfPkgIa32X64.dsc @@ -306,6 +306,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc index 843f7a2e7bf6..5fc6d14ee011 100644 --- a/OvmfPkg/OvmfPkgX64.dsc +++ b/OvmfPkg/OvmfPkgX64.dsc @@ -307,6 +307,7 @@ QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/PeiQemuFwCfgS3LibFwCfg.inf PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf QemuFwCfgLib|OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgPeiLib.inf + PlatformInitLib|OvmfPkg/Library/PlatformInitLib/PlatformInitLib.inf =20 !include OvmfPkg/OvmfTpmLibsPeim.dsc.inc =20 diff --git a/OvmfPkg/PlatformPei/Cmos.c b/OvmfPkg/PlatformPei/Cmos.c deleted file mode 100644 index a01b3866bee4..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.c +++ /dev/null @@ -1,55 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#include "Cmos.h" -#include "Library/IoLib.h" - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ) -{ - IoWrite8 (0x70, (UINT8)Index); - return IoRead8 (0x71); -} - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ) -{ - IoWrite8 (0x70, (UINT8)Index); - IoWrite8 (0x71, Value); - return Value; -} diff --git a/OvmfPkg/PlatformPei/Cmos.h b/OvmfPkg/PlatformPei/Cmos.h deleted file mode 100644 index 2b3124d7ba36..000000000000 --- a/OvmfPkg/PlatformPei/Cmos.h +++ /dev/null @@ -1,48 +0,0 @@ -/** @file - PC/AT CMOS access routines - - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
- SPDX-License-Identifier: BSD-2-Clause-Patent - -**/ - -#ifndef __CMOS_H__ -#define __CMOS_H__ - -/** - Reads 8-bits of CMOS data. - - Reads the 8-bits of CMOS data at the location specified by Index. - The 8-bit read value is returned. - - @param Index The CMOS location to read. - - @return The value read. - -**/ -UINT8 -EFIAPI -CmosRead8 ( - IN UINTN Index - ); - -/** - Writes 8-bits of CMOS data. - - Writes 8-bits of CMOS data to the location specified by Index - with the value specified by Value and returns Value. - - @param Index The CMOS location to write. - @param Value The value to write to CMOS. - - @return The value written to CMOS. - -**/ -UINT8 -EFIAPI -CmosWrite8 ( - IN UINTN Index, - IN UINT8 Value - ); - -#endif diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 1bcb5a08bca6..0c930ab1d70e 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -36,9 +36,8 @@ Module Name: #include #include #include - +#include #include "Platform.h" -#include "Cmos.h" =20 UINT8 mPhysMemAddressWidth; =20 @@ -50,6 +49,7 @@ STATIC UINT16 mQ35TsegMbytes; BOOLEAN mQ35SmramAtDefaultSmbase; =20 UINT32 mQemuUc32Base; +UINT32 mLowerMemorySize =3D 0; =20 VOID Q35TsegMbytesInitialization ( @@ -140,406 +140,11 @@ QemuUc32BaseInitialization ( VOID ) { - UINT32 LowerMemorySize; - UINT32 Uc32Size; - if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { return; } =20 - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // On q35, the 32-bit area that we'll mark as UC, through variable MTR= Rs, - // starts at PcdPciExpressBaseAddress. The platform DSC is responsible= for - // setting PcdPciExpressBaseAddress such that describing the - // [PcdPciExpressBaseAddress, 4GB) range require a very small number of - // variable MTRRs (preferably 1 or 2). - // - ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <=3D MAX_UINT32); - mQemuUc32Base =3D (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress); - return; - } - - if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { - Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; - mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; - return; - } - - ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); - // - // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one - // variable MTRR suffices by truncating the size to a whole power of two, - // while keeping the end affixed to 4GB. This will round the base up. - // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - Uc32Size =3D GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize= )); - mQemuUc32Base =3D (UINT32)(SIZE_4GB - Uc32Size); - // - // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most= 2GB. - // Therefore mQemuUc32Base is at least 2GB. - // - ASSERT (mQemuUc32Base >=3D BASE_2GB); - - if (mQemuUc32Base !=3D LowerMemorySize) { - DEBUG (( - DEBUG_VERBOSE, - "%a: rounded UC32 base from 0x%x up to 0x%x, for " - "an UC32 size of 0x%x\n", - __FUNCTION__, - LowerMemorySize, - mQemuUc32Base, - Uc32Size - )); - } -} - -/** - Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start ou= tside - of the 32-bit address range. - - Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce - descriptor HOBs for RAM entries that start at or above 4GB. - - @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ra= m() - produces memory resource descriptor HOBs for RAM - entries that start at or above 4GB. - - Otherwise, MaxAddress holds the highest exclusive - >=3D4GB RAM address on output. If QEMU's fw_cfg = E820 - RAM map contains no RAM entry that starts outsid= e of - the 32-bit address range, then MaxAddress is exa= ctly - 4GB on output. - - @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and proces= sed. - - @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a - whole multiple of sizeof(EFI_E820_ENTRY64). = No - RAM entry was processed. - - @return Error codes from QemuFwCfgFindFile(). No RAM - entry was processed. -**/ -STATIC -EFI_STATUS -ScanOrAdd64BitE820Ram ( - IN BOOLEAN AddHighHob, - OUT UINT64 *LowMemory OPTIONAL, - OUT UINT64 *MaxAddress OPTIONAL - ) -{ - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - EFI_E820_ENTRY64 E820Entry; - UINTN Processed; - - Status =3D QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); - if (EFI_ERROR (Status)) { - return Status; - } - - if (FwCfgSize % sizeof E820Entry !=3D 0) { - return EFI_PROTOCOL_ERROR; - } - - if (LowMemory !=3D NULL) { - *LowMemory =3D 0; - } - - if (MaxAddress !=3D NULL) { - *MaxAddress =3D BASE_4GB; - } - - QemuFwCfgSelectItem (FwCfgItem); - for (Processed =3D 0; Processed < FwCfgSize; Processed +=3D sizeof E820E= ntry) { - QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry); - DEBUG (( - DEBUG_VERBOSE, - "%a: Base=3D0x%Lx Length=3D0x%Lx Type=3D%u\n", - __FUNCTION__, - E820Entry.BaseAddr, - E820Entry.Length, - E820Entry.Type - )); - if (E820Entry.Type =3D=3D EfiAcpiAddressRangeMemory) { - if (AddHighHob && (E820Entry.BaseAddr >=3D BASE_4GB)) { - UINT64 Base; - UINT64 End; - - // - // Round up the start address, and round down the end address. - // - Base =3D ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE); - End =3D (E820Entry.BaseAddr + E820Entry.Length) & - ~(UINT64)EFI_PAGE_MASK; - if (Base < End) { - AddMemoryRangeHob (Base, End); - DEBUG (( - DEBUG_VERBOSE, - "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n", - __FUNCTION__, - Base, - End - )); - } - } - - if (MaxAddress || LowMemory) { - UINT64 Candidate; - - Candidate =3D E820Entry.BaseAddr + E820Entry.Length; - if (MaxAddress && (Candidate > *MaxAddress)) { - *MaxAddress =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: MaxAddress=3D0x%Lx\n", - __FUNCTION__, - *MaxAddress - )); - } - - if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB= )) { - *LowMemory =3D Candidate; - DEBUG (( - DEBUG_VERBOSE, - "%a: LowMemory=3D0x%Lx\n", - __FUNCTION__, - *LowMemory - )); - } - } - } - } - - return EFI_SUCCESS; -} - -UINT32 -GetSystemMemorySizeBelow4gb ( - VOID - ) -{ - EFI_STATUS Status; - UINT64 LowerMemorySize =3D 0; - UINT8 Cmos0x34; - UINT8 Cmos0x35; - - Status =3D ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); - if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { - return (UINT32)LowerMemorySize; - } - - // - // CMOS 0x34/0x35 specifies the system memory above 16 MB. - // * CMOS(0x35) is the high byte - // * CMOS(0x34) is the low byte - // * The size is specified in 64kb chunks - // * Since this is memory above 16MB, the 16MB must be added - // into the calculation to get the total memory size. - // - - Cmos0x34 =3D (UINT8)CmosRead8 (0x34); - Cmos0x35 =3D (UINT8)CmosRead8 (0x35); - - return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB); -} - -STATIC -UINT64 -GetSystemMemorySizeAbove4gb ( - ) -{ - UINT32 Size; - UINTN CmosIndex; - - // - // CMOS 0x5b-0x5d specifies the system memory above 4GB MB. - // * CMOS(0x5d) is the most significant size byte - // * CMOS(0x5c) is the middle size byte - // * CMOS(0x5b) is the least significant size byte - // * The size is specified in 64kb chunks - // - - Size =3D 0; - for (CmosIndex =3D 0x5d; CmosIndex >=3D 0x5b; CmosIndex--) { - Size =3D (UINT32)(Size << 8) + (UINT32)CmosRead8 (CmosIndex); - } - - return LShiftU64 (Size, 16); -} - -/** - Return the highest address that DXE could possibly use, plus one. -**/ -STATIC -UINT64 -GetFirstNonAddress ( - VOID - ) -{ - UINT64 FirstNonAddress; - UINT64 Pci64Base, Pci64Size; - UINT32 FwCfgPciMmio64Mb; - EFI_STATUS Status; - FIRMWARE_CONFIG_ITEM FwCfgItem; - UINTN FwCfgSize; - UINT64 HotPlugMemoryEnd; - RETURN_STATUS PcdStatus; - - // - // set FirstNonAddress to suppress incorrect compiler/analyzer warnings - // - FirstNonAddress =3D 0; - - // - // If QEMU presents an E820 map, then get the highest exclusive >=3D4GB = RAM - // address from it. This can express an address >=3D 4GB+1TB. - // - // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich - // can only express a size smaller than 1TB), and add it to 4GB. - // - Status =3D ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); - if (EFI_ERROR (Status)) { - FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb (); - } - - // - // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO - // resources to 32-bit anyway. See DegradeResource() in - // "PciResourceSupport.c". - // - #ifdef MDE_CPU_IA32 - if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { - return FirstNonAddress; - } - - #endif - - // - // Otherwise, in order to calculate the highest address plus one, we must - // consider the 64-bit PCI host aperture too. Fetch the default size. - // - Pci64Size =3D PcdGet64 (PcdPciMmio64Size); - - // - // See if the user specified the number of megabytes for the 64-bit PCI = host - // aperture. Accept an aperture size up to 16TB. - // - // As signaled by the "X-" prefix, this knob is experimental, and might = go - // away at any time. - // - Status =3D QemuFwCfgParseUint32 ( - "opt/ovmf/X-PciMmio64Mb", - FALSE, - &FwCfgPciMmio64Mb - ); - switch (Status) { - case EFI_UNSUPPORTED: - case EFI_NOT_FOUND: - break; - case EFI_SUCCESS: - if (FwCfgPciMmio64Mb <=3D 0x1000000) { - Pci64Size =3D LShiftU64 (FwCfgPciMmio64Mb, 20); - break; - } - - // - // fall through - // - default: - DEBUG (( - DEBUG_WARN, - "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\= n", - __FUNCTION__ - )); - break; - } - - if (Pci64Size =3D=3D 0) { - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - DEBUG (( - DEBUG_INFO, - "%a: disabling 64-bit PCI host aperture\n", - __FUNCTION__ - )); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); - ASSERT_RETURN_ERROR (PcdStatus); - } - - // - // There's nothing more to do; the amount of memory above 4GB fully - // determines the highest address plus one. The memory hotplug area (s= ee - // below) plays no role for the firmware in this case. - // - return FirstNonAddress; - } - - // - // The "etc/reserved-memory-end" fw_cfg file, when present, contains an - // absolute, exclusive end address for the memory hotplug area. This area - // starts right at the end of the memory above 4GB. The 64-bit PCI host - // aperture must be placed above it. - // - Status =3D QemuFwCfgFindFile ( - "etc/reserved-memory-end", - &FwCfgItem, - &FwCfgSize - ); - if (!EFI_ERROR (Status) && (FwCfgSize =3D=3D sizeof HotPlugMemoryEnd)) { - QemuFwCfgSelectItem (FwCfgItem); - QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd); - DEBUG (( - DEBUG_VERBOSE, - "%a: HotPlugMemoryEnd=3D0x%Lx\n", - __FUNCTION__, - HotPlugMemoryEnd - )); - - ASSERT (HotPlugMemoryEnd >=3D FirstNonAddress); - FirstNonAddress =3D HotPlugMemoryEnd; - } - - // - // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB= , so - // that the host can map it with 1GB hugepages. Follow suit. - // - Pci64Base =3D ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB); - Pci64Size =3D ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB); - - // - // The 64-bit PCI host aperture should also be "naturally" aligned. The - // alignment is determined by rounding the size of the aperture down to = the - // next smaller or equal power of two. That is, align the aperture by the - // largest BAR size that can fit into it. - // - Pci64Base =3D ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size)); - - if (mBootMode !=3D BOOT_ON_S3_RESUME) { - // - // The core PciHostBridgeDxe driver will automatically add this range = to - // the GCD memory space map through our PciHostBridgeLib instance; her= e we - // only need to set the PCDs. - // - PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size); - ASSERT_RETURN_ERROR (PcdStatus); - - DEBUG (( - DEBUG_INFO, - "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", - __FUNCTION__, - Pci64Base, - Pci64Size - )); - } - - // - // The useful address space ends with the 64-bit PCI host aperture. - // - FirstNonAddress =3D Pci64Base + Pci64Size; - return FirstNonAddress; + mQemuUc32Base =3D PlatformQemuUc32BaseInitialization (mHostBridgeDevId, = mLowerMemorySize); } =20 /** @@ -550,36 +155,19 @@ AddressWidthInitialization ( VOID ) { - UINT64 FirstNonAddress; - - // - // As guest-physical memory size grows, the permanent PEI RAM requiremen= ts - // are dominated by the identity-mapping page tables built by the DXE IP= L. - // The DXL IPL keys off of the physical address bits advertized in the C= PU - // HOB. To conserve memory, we calculate the minimum address width here. - // - FirstNonAddress =3D GetFirstNonAddress (); - mPhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); - - // - // If FirstNonAddress is not an integral power of two, then we need an - // additional bit. - // - if ((FirstNonAddress & (FirstNonAddress - 1)) !=3D 0) { - ++mPhysMemAddressWidth; - } - - // - // The minimum address width is 36 (covers up to and excluding 64 GB, wh= ich - // is the maximum for Ia32 + PAE). The theoretical architecture maximum = for - // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits= . We - // can simply assert that here, since 48 bits are good enough for 256 TB. - // - if (mPhysMemAddressWidth <=3D 36) { - mPhysMemAddressWidth =3D 36; - } - - ASSERT (mPhysMemAddressWidth <=3D 48); + UINT64 Pci64Base; + UINT64 Pci64Size; + UINT64 FirstNonAddress; + RETURN_STATUS PcdStatus; + + Pci64Base =3D 0; + Pci64Size =3D 0; + FirstNonAddress =3D PlatformGetFirstNonAddress (&Pci64Base, &Pci64S= ize, PcdGet64 (PcdPciMmio64Size)); + mPhysMemAddressWidth =3D PlatformAddressWidthInitialization (FirstNonAdd= ress); + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, Pci64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, Pci64Size); + ASSERT_RETURN_ERROR (PcdStatus); } =20 /** @@ -664,7 +252,7 @@ PublishPeiMemory ( UINT32 LowerMemorySize; UINT32 PeiMemoryCap; =20 - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); + LowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (); if (FeaturePcdGet (PcdSmmSmramRequire)) { // // TSEG is chipped from the end of low RAM @@ -736,162 +324,6 @@ PublishPeiMemory ( return Status; } =20 -STATIC -VOID -QemuInitializeRamBelow1gb ( - VOID - ) -{ - if (FeaturePcdGet (PcdSmmSmramRequire) && mQ35SmramAtDefaultSmbase) { - AddMemoryRangeHob (0, SMM_DEFAULT_SMBASE); - AddReservedMemoryBaseSizeHob ( - SMM_DEFAULT_SMBASE, - MCH_DEFAULT_SMBASE_SIZE, - TRUE /* Cacheable */ - ); - STATIC_ASSERT ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128= KB, - "end of SMRAM at default SMBASE ends at, or exceeds, 640KB" - ); - AddMemoryRangeHob ( - SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE, - BASE_512KB + BASE_128KB - ); - } else { - AddMemoryRangeHob (0, BASE_512KB + BASE_128KB); - } -} - -/** - Peform Memory Detection for QEMU / KVM - -**/ -STATIC -VOID -QemuInitializeRam ( - VOID - ) -{ - UINT64 LowerMemorySize; - UINT64 UpperMemorySize; - MTRR_SETTINGS MtrrSettings; - EFI_STATUS Status; - - DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__)); - - // - // Determine total memory size available - // - LowerMemorySize =3D GetSystemMemorySizeBelow4gb (); - - if (mBootMode =3D=3D BOOT_ON_S3_RESUME) { - // - // Create the following memory HOB as an exception on the S3 boot path. - // - // Normally we'd create memory HOBs only on the normal boot path. Howe= ver, - // CpuMpPei specifically needs such a low-memory HOB on the S3 path as - // well, for "borrowing" a subset of it temporarily, for the AP startup - // vector. - // - // CpuMpPei saves the original contents of the borrowed area in perman= ent - // PEI RAM, in a backup buffer allocated with the normal PEI services. - // CpuMpPei restores the original contents ("returns" the borrowed are= a) at - // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before - // transferring control to the OS's wakeup vector in the FACS. - // - // We expect any other PEIMs that "borrow" memory similarly to CpuMpPe= i to - // restore the original contents. Furthermore, we expect all such PEIMs - // (CpuMpPei included) to claim the borrowed areas by producing memory - // allocation HOBs, and to honor preexistent memory allocation HOBs wh= en - // looking for an area to borrow. - // - QemuInitializeRamBelow1gb (); - } else { - // - // Create memory HOBs - // - QemuInitializeRamBelow1gb (); - - if (FeaturePcdGet (PcdSmmSmramRequire)) { - UINT32 TsegSize; - - TsegSize =3D mQ35TsegMbytes * SIZE_1MB; - AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize); - AddReservedMemoryBaseSizeHob ( - LowerMemorySize - TsegSize, - TsegSize, - TRUE - ); - } else { - AddMemoryRangeHob (BASE_1MB, LowerMemorySize); - } - - // - // If QEMU presents an E820 map, then create memory HOBs for the >=3D4= GB RAM - // entries. Otherwise, create a single memory HOB with the flat >=3D4GB - // memory size read from the CMOS. - // - Status =3D ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); - if (EFI_ERROR (Status)) { - UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); - if (UpperMemorySize !=3D 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); - } - } - } - - // - // We'd like to keep the following ranges uncached: - // - [640 KB, 1 MB) - // - [LowerMemorySize, 4 GB) - // - // Everything else should be WB. Unfortunately, programming the inverse = (ie. - // keeping the default UC, and configuring the complement set of the abo= ve as - // WB) is not reliable in general, because the end of the upper RAM can = have - // practically any alignment, and we may not have enough variable MTRRs = to - // cover it exactly. - // - if (IsMtrrSupported () && (mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID)) { - MtrrGetAllMtrrs (&MtrrSettings); - - // - // MTRRs disabled, fixed MTRRs disabled, default type is uncached - // - ASSERT ((MtrrSettings.MtrrDefType & BIT11) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & BIT10) =3D=3D 0); - ASSERT ((MtrrSettings.MtrrDefType & 0xFF) =3D=3D 0); - - // - // flip default type to writeback - // - SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06); - ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables); - MtrrSettings.MtrrDefType |=3D BIT11 | BIT10 | 6; - MtrrSetAllMtrrs (&MtrrSettings); - - // - // Set memory range from 640KB to 1MB to uncacheable - // - Status =3D MtrrSetMemoryAttribute ( - BASE_512KB + BASE_128KB, - BASE_1MB - (BASE_512KB + BASE_128KB), - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - - // - // Set the memory range from the start of the 32-bit MMIO area (32-bit= PCI - // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable. - // - Status =3D MtrrSetMemoryAttribute ( - mQemuUc32Base, - SIZE_4GB - mQemuUc32Base, - CacheUncacheable - ); - ASSERT_EFI_ERROR (Status); - } -} - /** Publish system RAM and reserve memory regions =20 @@ -901,7 +333,15 @@ InitializeRamRegions ( VOID ) { - QemuInitializeRam (); + PlatformInitializeRamRegions ( + mQemuUc32Base, + mHostBridgeDevId, + FeaturePcdGet (PcdSmmSmramRequire), + mBootMode, + mS3Supported, + mLowerMemorySize, + mQ35TsegMbytes + ); =20 SevInitializeRam (); =20 @@ -979,28 +419,6 @@ InitializeRamRegions ( } =20 if (mBootMode !=3D BOOT_ON_S3_RESUME) { - if (!FeaturePcdGet (PcdSmmSmramRequire)) { - // - // Reserve the lock box storage area - // - // Since this memory range will be used on S3 resume, it must be - // reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // LockBox area. We ought to prevent DXE from serving allocation req= uests - // such that they would overlap the LockBox storage. - // - ZeroMem ( - (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize) - ); - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase), - (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData - ); - } - if (FeaturePcdGet (PcdSmmSmramRequire)) { UINT32 TsegSize; =20 @@ -1010,7 +428,7 @@ InitializeRamRegions ( // TsegSize =3D mQ35TsegMbytes * SIZE_1MB; BuildMemoryAllocationHob ( - GetSystemMemorySizeBelow4gb () - TsegSize, + PlatformGetSystemMemorySizeBelow4gb () - TsegSize, TsegSize, EfiReservedMemoryType ); @@ -1026,26 +444,5 @@ InitializeRamRegions ( ); } } - - #ifdef MDE_CPU_X64 - if (FixedPcdGet32 (PcdOvmfWorkAreaSize) !=3D 0) { - // - // Reserve the work area. - // - // Since this memory range will be used by the Reset Vector on S3 - // resume, it must be reserved as ACPI NVS. - // - // If S3 is unsupported, then various drivers might still write to t= he - // work area. We ought to prevent DXE from serving allocation reques= ts - // such that they would overlap the work area. - // - BuildMemoryAllocationHob ( - (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase), - (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize), - mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData - ); - } - - #endif } } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index d0323c645162..05a5c94ce80a 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -37,9 +37,8 @@ #include #include #include - +#include #include "Platform.h" -#include "Cmos.h" =20 EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[] =3D { { @@ -57,84 +56,7 @@ BOOLEAN mS3Supported =3D FALSE; =20 UINT32 mMaxCpuCount; =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_MAPPED_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_MEMORY_RESERVED, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - (Cacheable ? - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE : - 0 - ) | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ) -{ - BuildResourceDescriptorHob ( - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | - EFI_RESOURCE_ATTRIBUTE_TESTED, - MemoryBase, - MemorySize - ); -} - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ) -{ - AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase)); -} +extern UINT32 mLowerMemorySize; =20 VOID MemMapInitialization ( @@ -144,117 +66,19 @@ MemMapInitialization ( UINT64 PciIoBase; UINT64 PciIoSize; RETURN_STATUS PcdStatus; - UINT32 TopOfLowRam; - UINT64 PciExBarBase; UINT32 PciBase; UINT32 PciSize; =20 - PciIoBase =3D 0xC000; - PciIoSize =3D 0x4000; - - // - // Video memory + Legacy BIOS region - // - AddIoMemoryRangeHob (0x0A0000, BASE_1MB); - + PlatformMemMapInitialization (mHostBridgeDevId, mQemuUc32Base, &PciBase,= &PciSize, &PciIoBase, &PciIoSize); if (mHostBridgeDevId =3D=3D 0xffff /* microvm */) { - AddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */ - AddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */ return; } =20 - TopOfLowRam =3D GetSystemMemorySizeBelow4gb (); - PciExBarBase =3D 0; - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // The MMCONFIG area is expected to fall between the top of low RAM and - // the base of the 32-bit PCI host aperture. - // - PciExBarBase =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT (TopOfLowRam <=3D PciExBarBase); - ASSERT (PciExBarBase <=3D MAX_UINT32 - SIZE_256MB); - PciBase =3D (UINT32)(PciExBarBase + SIZE_256MB); - } else { - ASSERT (TopOfLowRam <=3D mQemuUc32Base); - PciBase =3D mQemuUc32Base; - } - - // - // address purpose size - // ------------ -------- ------------------------- - // max(top, 2g) PCI MMIO 0xFC000000 - max(top, 2g) - // 0xFC000000 gap 44 MB - // 0xFEC00000 IO-APIC 4 KB - // 0xFEC01000 gap 1020 KB - // 0xFED00000 HPET 1 KB - // 0xFED00400 gap 111 KB - // 0xFED1C000 gap (PIIX4) / RCRB (ICH9) 16 KB - // 0xFED20000 gap 896 KB - // 0xFEE00000 LAPIC 1 MB - // - PciSize =3D 0xFC000000 - PciBase; - AddIoMemoryBaseSizeHob (PciBase, PciSize); PcdStatus =3D PcdSet64S (PcdPciMmio32Base, PciBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciMmio32Size, PciSize); ASSERT_RETURN_ERROR (PcdStatus); =20 - AddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); - AddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB); - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - AddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB); - // - // Note: there should be an - // - // AddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB); - // - // call below, just like the one above for RCBA. However, Linux insists - // that the MMCONFIG area be marked in the E820 or UEFI memory map as - // "reserved memory" -- Linux does not content itself with a simple gap - // in the memory map wherever the MCFG ACPI table points to. - // - // This appears to be a safety measure. The PCI Firmware Specification - // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources c= an - // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory - // [...]". (Emphasis added here.) - // - // Normally we add memory resource descriptor HOBs in - // QemuInitializeRam(), and pre-allocate from those with memory - // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG ar= ea - // is most definitely not RAM; so, as an exception, cover it with - // uncacheable reserved memory right here. - // - AddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE); - BuildMemoryAllocationHob ( - PciExBarBase, - SIZE_256MB, - EfiReservedMemoryType - ); - } - - AddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB); - - // - // On Q35, the IO Port space is available for PCI resource allocations f= rom - // 0x6000 up. - // - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - PciIoBase =3D 0x6000; - PciIoSize =3D 0xA000; - ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase); - } - - // - // Add PCI IO Port space available for PCI resource allocations. - // - BuildResourceDescriptorHob ( - EFI_RESOURCE_IO, - EFI_RESOURCE_ATTRIBUTE_PRESENT | - EFI_RESOURCE_ATTRIBUTE_INITIALIZED, - PciIoBase, - PciIoSize - ); PcdStatus =3D PcdSet64S (PcdPciIoBase, PciIoBase); ASSERT_RETURN_ERROR (PcdStatus); PcdStatus =3D PcdSet64S (PcdPciIoSize, PciIoSize); @@ -281,47 +105,6 @@ NoexecDxeInitialization ( UPDATE_BOOLEAN_PCD_FROM_FW_CFG (PcdSetNxForStack); } =20 -VOID -PciExBarInitialization ( - VOID - ) -{ - union { - UINT64 Uint64; - UINT32 Uint32[2]; - } PciExBarBase; - - // - // We only support the 256MB size for the MMCONFIG area: - // 256 buses * 32 devices * 8 functions * 4096 bytes config space. - // - // The masks used below enforce the Q35 requirements that the MMCONFIG a= rea - // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 G= B. - // - // Note that (b) also ensures that the minimum address width we have - // determined in AddressWidthInitialization(), i.e., 36 bits, will suffi= ce - // for DXE's page tables to cover the MMCONFIG area. - // - PciExBarBase.Uint64 =3D FixedPcdGet64 (PcdPciExpressBaseAddress); - ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) =3D=3D 0); - ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) =3D=3D 0); - - // - // Clear the PCIEXBAREN bit first, before programming the high register. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0); - - // - // Program the high register. Then program the low register, setting the - // MMCONFIG area size and enabling decoding at once. - // - PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[= 1]); - PciWrite32 ( - DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), - PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN - ); -} - static const UINT8 EmptyFdt[] =3D { 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x48, @@ -383,19 +166,23 @@ MicrovmInitialization ( *FdtHobData =3D (UINTN)NewBase; } =20 +/** + * Misc initialization for Microvm and Cloud-Hypervisor + * + * @return VOID + */ VOID -MiscInitialization ( +MiscInitialization2 ( VOID ) { - UINTN PmCmd; - UINTN Pmba; - UINT32 PmbaAndVal; - UINT32 PmbaOrVal; - UINTN AcpiCtlReg; - UINT8 AcpiEnBit; RETURN_STATUS PcdStatus; =20 + if ((mHostBridgeDevId !=3D 0xffff) && (mHostBridgeDevId !=3D CLOUDHV_DEV= ICE_ID)) { + ASSERT (FALSE); + return; + } + // // Disable A20 Mask // @@ -408,26 +195,7 @@ MiscInitialization ( // BuildCpuHob (mPhysMemAddressWidth, 16); =20 - // - // Determine platform type and save Host Bridge DID to PCD - // switch (mHostBridgeDevId) { - case INTEL_82441_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA); - PmbaAndVal =3D ~(UINT32)PIIX4_PMBA_MASK; - PmbaOrVal =3D PIIX4_PMBA_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC); - AcpiEnBit =3D PIIX4_PMREGMISC_PMIOSE; - break; - case INTEL_Q35_MCH_DEVICE_ID: - PmCmd =3D POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET); - Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); - PmbaAndVal =3D ~(UINT32)ICH9_PMBASE_MASK; - PmbaOrVal =3D ICH9_PMBASE_VALUE; - AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); - AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; - break; case 0xffff: /* microvm */ DEBUG ((DEBUG_INFO, "%a: microvm\n", __FUNCTION__)); MicrovmInitialization (); @@ -447,7 +215,7 @@ MiscInitialization ( return; default: DEBUG (( - DEBUG_ERROR, + DEBUG_INFO, "%a: Unknown Host Bridge Device ID: 0x%04x\n", __FUNCTION__, mHostBridgeDevId @@ -455,47 +223,24 @@ MiscInitialization ( ASSERT (FALSE); return; } +} + +VOID +MiscInitialization ( + VOID + ) +{ + RETURN_STATUS PcdStatus; + + if ((mHostBridgeDevId =3D=3D 0xffff) || (mHostBridgeDevId =3D=3D CLOUDHV= _DEVICE_ID)) { + MiscInitialization2 (); + return; + } + + PlatformMiscInitialization (mHostBridgeDevId, mPhysMemAddressWidth); =20 PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, mHostBridgeDevId); ASSERT_RETURN_ERROR (PcdStatus); - - // - // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has - // been configured and skip the setup here. This matches the logic in - // AcpiTimerLibConstructor (). - // - if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) =3D=3D 0) { - // - // The PEI phase should be exited with fully accessibe ACPI PM IO spac= e: - // 1. set PMBA - // - PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal); - - // - // 2. set PCICMD/IOSE - // - PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE); - - // - // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN) - // - PciOr8 (AcpiCtlReg, AcpiEnBit); - } - - if (mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) { - // - // Set Root Complex Register Block BAR - // - PciWrite32 ( - POWER_MGMT_REGISTER_Q35 (ICH9_RCBA), - ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN - ); - - // - // Set PCI Express Register Range Base Address - // - PciExBarInitialization (); - } } =20 VOID @@ -505,11 +250,11 @@ BootModeInitialization ( { EFI_STATUS Status; =20 - if (CmosRead8 (0xF) =3D=3D 0xFE) { + if (PlatformCmosRead8 (0xF) =3D=3D 0xFE) { mBootMode =3D BOOT_ON_S3_RESUME; } =20 - CmosWrite8 (0xF, 0x00); + PlatformCmosWrite8 (0xF, 0x00); =20 Status =3D PeiServicesSetBootMode (mBootMode); ASSERT_EFI_ERROR (Status); @@ -546,27 +291,6 @@ ReserveEmuVariableNvStore ( ASSERT_RETURN_ERROR (PcdStatus); } =20 -VOID -DebugDumpCmos ( - VOID - ) -{ - UINT32 Loop; - - DEBUG ((DEBUG_INFO, "CMOS:\n")); - - for (Loop =3D 0; Loop < 0x80; Loop++) { - if ((Loop % 0x10) =3D=3D 0) { - DEBUG ((DEBUG_INFO, "%02x:", Loop)); - } - - DEBUG ((DEBUG_INFO, " %02x", CmosRead8 (Loop))); - if ((Loop % 0x10) =3D=3D 0xf) { - DEBUG ((DEBUG_INFO, "\n")); - } - } -} - VOID S3Verification ( VOID @@ -629,160 +353,12 @@ MaxCpuCountInitialization ( UINT16 BootCpuCount; RETURN_STATUS PcdStatus; =20 - // - // Try to fetch the boot CPU count. - // - QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount); - BootCpuCount =3D QemuFwCfgRead16 (); - if (BootCpuCount =3D=3D 0) { - // - // QEMU doesn't report the boot CPU count. (BootCpuCount =3D=3D 0) wil= l let - // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or - // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reach= ed - // first). - // - DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__)); - mMaxCpuCount =3D PcdGet32 (PcdCpuMaxLogicalProcessorNumber); - } else { - // - // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs = up to - // (BootCpuCount - 1) precisely, regardless of timeout. - // - // Now try to fetch the possible CPU count. - // - UINTN CpuHpBase; - UINT32 CmdData2; - - CpuHpBase =3D ((mHostBridgeDevId =3D=3D INTEL_Q35_MCH_DEVICE_ID) ? - ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE); - - // - // If only legacy mode is available in the CPU hotplug register block,= or - // the register block is completely missing, then the writes below are - // no-ops. - // - // 1. Switch the hotplug register block to modern mode. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 2. Select a valid CPU for deterministic reading of - // QEMU_CPUHP_R_CMD_DATA2. - // - // CPU#0 is always valid; it is the always present and non-removable - // BSP. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0); - // - // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to - // read as zero, and which does not invalidate the selector. (The - // selector may change, but it must not become invalid.) - // - // Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later. - // - IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING); - // - // 4. Read QEMU_CPUHP_R_CMD_DATA2. - // - // If the register block is entirely missing, then this is an unass= igned - // IO read, returning all-bits-one. - // - // If only legacy mode is available, then bit#0 stands for CPU#0 in= the - // "CPU present bitmap". CPU#0 is always present. - // - // Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (retu= rning - // all-bits-zero), or it is specified to read as zero after the abo= ve - // steps. Both cases confirm modern mode. - // - CmdData2 =3D IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2); - DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=3D0x%x\n", __FUNCTION__, CmdData2= )); - if (CmdData2 !=3D 0) { - // - // QEMU doesn't support the modern CPU hotplug interface. Assume tha= t the - // possible CPU count equals the boot CPU count (precluding hotplug). - // - DEBUG (( - DEBUG_WARN, - "%a: modern CPU hotplug interface unavailable\n", - __FUNCTION__ - )); - mMaxCpuCount =3D BootCpuCount; - } else { - // - // Grab the possible CPU count from the modern CPU hotplug interface. - // - UINT32 Present, Possible, Selected; - - Present =3D 0; - Possible =3D 0; - - // - // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures - // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However, - // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pe= nding - // hotplug events; therefore, select CPU#0 forcibly. - // - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - - do { - UINT8 CpuStatus; - - // - // Read the status of the currently selected CPU. This will help w= ith a - // sanity check against "BootCpuCount". - // - CpuStatus =3D IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT); - if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) !=3D 0) { - ++Present; - } - - // - // Attempt to select the next CPU. - // - ++Possible; - IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible); - // - // If the selection is successful, then the following read will re= turn - // the selector (which we know is positive at this point). Otherwi= se, - // the read will return 0. - // - Selected =3D IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA); - ASSERT (Selected =3D=3D Possible || Selected =3D=3D 0); - } while (Selected > 0); - - // - // Sanity check: fw_cfg and the modern CPU hotplug interface should - // return the same boot CPU count. - // - if (BootCpuCount !=3D Present) { - DEBUG (( - DEBUG_WARN, - "%a: QEMU v2.7 reset bug: BootCpuCount=3D%d " - "Present=3D%u\n", - __FUNCTION__, - BootCpuCount, - Present - )); - // - // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug pl= us - // platform reset (including S3), was corrected in QEMU commit - // e3cadac073a9 ("pc: fix FW_CFG_NB_CPUS to account for -device ad= ded - // CPUs", 2016-11-16), part of release v2.8.0. - // - BootCpuCount =3D (UINT16)Present; - } - - mMaxCpuCount =3D Possible; - } - } - - DEBUG (( - DEBUG_INFO, - "%a: BootCpuCount=3D%d mMaxCpuCount=3D%u\n", - __FUNCTION__, - BootCpuCount, - mMaxCpuCount - )); - ASSERT (BootCpuCount <=3D mMaxCpuCount); + PlatformMaxCpuCountInitialization ( + mHostBridgeDevId, + PcdGet32 (PcdCpuMaxLogicalProcessorNumber), + &mMaxCpuCount, + &BootCpuCount + ); =20 PcdStatus =3D PcdSet32S (PcdCpuBootLogicalProcessorNumber, BootCpuCount); ASSERT_RETURN_ERROR (PcdStatus); @@ -810,7 +386,7 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 - DebugDumpCmos (); + PlatformDebugDumpCmos (); =20 if (QemuFwCfgS3Enabled ()) { DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n")); @@ -836,6 +412,11 @@ InitializePlatform ( Q35SmramAtDefaultSmbaseInitialization (); } =20 + // + // Fetch the lower memory size (Below 4G) + // + mLowerMemorySize =3D PlatformGetSystemMemorySizeBelow4gb (); + PublishPeiMemory (); =20 QemuUc32BaseInitialization (); diff --git a/OvmfPkg/PlatformPei/Platform.h b/OvmfPkg/PlatformPei/Platform.h index 24e4da4e1d93..64af9cde1002 100644 --- a/OvmfPkg/PlatformPei/Platform.h +++ b/OvmfPkg/PlatformPei/Platform.h @@ -11,37 +11,6 @@ =20 #include =20 -VOID -AddIoMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddIoMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize - ); - -VOID -AddMemoryRangeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - EFI_PHYSICAL_ADDRESS MemoryLimit - ); - -VOID -AddReservedMemoryBaseSizeHob ( - EFI_PHYSICAL_ADDRESS MemoryBase, - UINT64 MemorySize, - BOOLEAN Cacheable - ); - VOID AddressWidthInitialization ( VOID @@ -62,11 +31,6 @@ PublishPeiMemory ( VOID ); =20 -UINT32 -GetSystemMemorySizeBelow4gb ( - VOID - ); - VOID QemuUc32BaseInitialization ( VOID diff --git a/OvmfPkg/PlatformPei/PlatformPei.inf b/OvmfPkg/PlatformPei/Plat= formPei.inf index 8ef404168c45..65e417b2f254 100644 --- a/OvmfPkg/PlatformPei/PlatformPei.inf +++ b/OvmfPkg/PlatformPei/PlatformPei.inf @@ -25,8 +25,6 @@ [Sources] AmdSev.c ClearCache.c - Cmos.c - Cmos.h FeatureControl.c Fv.c MemDetect.c @@ -64,6 +62,7 @@ MemEncryptSevLib PcdLib VmgExitLib + PlatformInitLib =20 [Pcd] gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#85993): https://edk2.groups.io/g/devel/message/85993 Mute This Topic: https://groups.io/mt/88617548/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-