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Mon, 10 Apr 2023 11:10:39 +0000 X-Received: from SATLEXMB07.amd.com (10.181.41.45) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 06:10:38 -0500 X-Received: from SATLEXMB04.amd.com (10.181.40.145) by SATLEXMB07.amd.com (10.181.41.45) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Mon, 10 Apr 2023 04:10:13 -0700 X-Received: from BLR-LAB-SFW01.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.34 via Frontend Transport; Mon, 10 Apr 2023 06:10:11 -0500 From: "Abdul Lateef Attar via groups.io" To: CC: Abdul Lateef Attar , Paul Grimes , Garrett Kirkendall , Abner Chang , Eric Dong , Ray Ni , Rahul Kumar , Abdul Lateef Attar Subject: [edk2-devel] [PATCH v8 6/9] UefiCpuPkg: Implements SmmCpuFeaturesLib for AMD Family Date: Mon, 10 Apr 2023 16:39:45 +0530 Message-ID: <66120dc1cddbfa0a67f98e1387ac6151bc9c78e4.1681121324.git.abdattar@amd.com> In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT067:EE_|PH0PR12MB7095:EE_ X-MS-Office365-Filtering-Correlation-Id: fd0aeaa3-3ad4-42c8-0675-08db39b437a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: EnY/F+PFXReCOOPx6yBvLNy7r+oeySu4GK+Jw8vzjuPeQugCoNCKLWj1L/P2iLTJIbB2G3SGykPyzRvmVtmBy0MVClQ45rbht+zdaM3AoAN3CbcQzNLbGqy1ARmhTbeVP8PwcvnAuqp7B4dijGulGT998qbcDaAvm/dDSio4pVYUoXXd34NuTiyPdSbWZHar8oCm2mKO/GcEH7uMkk9kBm3oNUKLX8giyLhdUX8oxkJolUDl+uDiJMky7e1nGaCX/Bh/tc0ZmZWjNi5PoCUdKhbIHPgT2WhabpjfajzoEx4L6WrHC5lcszcS4vcMGQ3VqFFE5Iq3PWf++63SJqCFTRfN0qN6YScdQQzSygsBpgpQD8+VGeR50xPJ8XP1xZe1OAZKp5A17qAgazvXI9yN8MVwo3kTC0JbDtKFD+CIKAjqAiNFOWFj/IfgGY/yAmp3sF9qJ9SxeWQ/XPieSfyR9t4JR0zDDK2qcFEyIrCi1R0KAmrm+OGQNYo+XOoEdItRofah3QjrIZrvqD8sClYxPk8Ue1JOOlevehIIcW4wZHE7ja792tMIXcEBwH/8gmpWIZSuKFNuS3iybCpTaU3tM8KFGk9B/2enB0SLJpYVAJKtkVRPXgi7pCkDbQzngZchgVUOJztUaFurOfbgDNgU8Z6aMVTHK9fS8zj9fwVcvx3CyeUM0KkJzRjNldbN3iUngCzMgtxNPyHzT99Tj0O7oVLBFYzTZKKfQjIuPwWcD7k= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Apr 2023 11:10:39.2734 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fd0aeaa3-3ad4-42c8-0675-08db39b437a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7095 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,abdattar@amd.com X-Gm-Message-State: uTfpIdtUYcNOutlABTmQlRv7x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1681125043; bh=xFfbi62fcb73V0u6Ajt13FPwYgcy/9dhphgtXQwJWUE=; h=CC:Content-Type:Date:From:Reply-To:Subject:To; b=UKE/Q/szmUeP9FKTkc1JiMjywzCnI1+mTYpHRItA4UoVqwU7WkcD/5zs9l9CXpQlgFC Pp7PwPHd1sZ31etdB9HaDPjUV6xjNCxpHphTXuQZ48uHHtayOpU9dK2DyGdxP2jRnmjOs LC4vB+3QNG/sJllGQEK1m5uqAtRSxGtMC0g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1681125045981100009 Content-Type: text/plain; charset="utf-8" From: Abdul Lateef Attar BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4182 Implements interfaces to read and write save state registers of AMD's processor family. Initializes processor SMMADDR and MASK depends on PcdSmrrEnable flag. Program or corrects the IP once control returns from SMM. Cc: Paul Grimes Cc: Garrett Kirkendall Cc: Abner Chang Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Signed-off-by: Abdul Lateef Attar Reviewed-by: Abner Chang Acked-by: Ray Ni --- .../AmdSmmCpuFeaturesLib.inf | 5 + .../SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c | 106 +++++++++++++++++- 2 files changed, 108 insertions(+), 3 deletions(-) diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf = b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf index 4c77efc64462..6d6f879e2a43 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.inf @@ -31,3 +31,8 @@ [LibraryClasses] PcdLib MemoryAllocationLib DebugLib + SmmSmramSaveStateLib + +[FeaturePcd] + gUefiCpuPkgTokenSpaceGuid.PcdSmrrEnable ## CONSUMES + gUefiCpuPkgTokenSpaceGuid.PcdSmmFeatureControlEnable ## CONSUMES diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c b/= UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c index c74e1a0c0c5b..af45be3e265a 100644 --- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c +++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/AmdSmmCpuFeaturesLib.c @@ -11,6 +11,21 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #include #include +#include +#include +#include +#include + +// EFER register LMA bit +#define LMA BIT10 + +// Machine Specific Registers (MSRs) +#define SMMADDR_ADDRESS 0xC0010112ul +#define SMMMASK_ADDRESS 0xC0010113ul +#define EFER_ADDRESS 0XC0000080ul + +// The mode of the CPU at the time an SMI occurs +STATIC UINT8 mSmmSaveStateRegisterLma; =20 /** Read an SMM Save State register on the target processor. If this functi= on @@ -39,7 +54,7 @@ SmmCpuFeaturesReadSaveStateRegister ( OUT VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateReadRegister (CpuIndex, Register, Width, Buffer); } =20 /** @@ -67,7 +82,7 @@ SmmCpuFeaturesWriteSaveStateRegister ( IN CONST VOID *Buffer ) { - return EFI_SUCCESS; + return SmramSaveStateWriteRegister (CpuIndex, Register, Width, Buffer); } =20 /** @@ -82,6 +97,13 @@ CpuFeaturesLibInitialization ( VOID ) { + UINT32 LMAValue; + + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } } =20 /** @@ -117,6 +139,52 @@ SmmCpuFeaturesInitializeProcessor ( IN CPU_HOT_PLUG_DATA *CpuHotPlugData ) { + AMD_SMRAM_SAVE_STATE_MAP *CpuState; + UINT32 LMAValue; + + // + // Configure SMBASE. + // + CpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)(UINTN)(SMM_DEFAULT= _SMBASE + SMRAM_SAVE_STATE_MAP_OFFSET); + CpuState->x64.SMBASE =3D (UINT32)CpuHotPlugData->SmBase[CpuIndex]; + + // Re-initialize the value of mSmmSaveStateRegisterLma flag which might = have been changed in PiCpuSmmDxeSmm Driver + // Entry point, to make sure correct value on AMD platform is assigned t= o be used by SmmCpuFeaturesLib. + LMAValue =3D (UINT32)AsmReadMsr64 (EFER_ADDRESS) & LMA; + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BIT; + if (LMAValue) { + mSmmSaveStateRegisterLma =3D EFI_SMM_SAVE_STATE_REGISTER_LMA_64BIT; + } + + // + // If SMRR is supported, then program SMRR base/mask MSRs. + // The EFI_MSR_SMRR_PHYS_MASK_VALID bit is not set until the first norma= l SMI. + // The code that initializes SMM environment is running in normal mode + // from SMRAM region. If SMRR is enabled here, then the SMRAM region + // is protected and the normal mode code execution will fail. + // + if (FeaturePcdGet (PcdSmrrEnable)) { + // + // SMRR size cannot be less than 4-KBytes + // SMRR size must be of length 2^n + // SMRR base alignment cannot be less than SMRR length + // + if ((CpuHotPlugData->SmrrSize < SIZE_4KB) || + (CpuHotPlugData->SmrrSize !=3D GetPowerOfTwo32 (CpuHotPlugData->Sm= rrSize)) || + ((CpuHotPlugData->SmrrBase & ~(CpuHotPlugData->SmrrSize - 1)) !=3D= CpuHotPlugData->SmrrBase)) + { + // + // Print message and halt if CPU is Monarch + // + if (IsMonarch) { + DEBUG ((DEBUG_ERROR, "SMM Base/Size does not meet alignment/size r= equirement!\n")); + CpuDeadLoop (); + } + } else { + AsmWriteMsr64 (SMMADDR_ADDRESS, CpuHotPlugData->SmrrBase); + AsmWriteMsr64 (SMMMASK_ADDRESS, ((~(UINT64)(CpuHotPlugData->SmrrSize= - 1)) | 0x6600)); + } + } } =20 /** @@ -159,7 +227,39 @@ SmmCpuFeaturesHookReturnFromSmm ( IN UINT64 NewInstructionPointer ) { - return 0; + UINT64 OriginalInstructionPointer; + AMD_SMRAM_SAVE_STATE_MAP *AmdCpuState; + + AmdCpuState =3D (AMD_SMRAM_SAVE_STATE_MAP *)CpuState; + + if (mSmmSaveStateRegisterLma =3D=3D EFI_SMM_SAVE_STATE_REGISTER_LMA_32BI= T) { + OriginalInstructionPointer =3D (UINT64)AmdCpuState->x86._EIP; + AmdCpuState->x86._EIP =3D (UINT32)NewInstructionPointer; + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x86.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x86.AutoHALTRestart &=3D ~BIT0; + } + } else { + OriginalInstructionPointer =3D AmdCpuState->x64._RIP; + if ((AmdCpuState->x64.EFER & LMA) =3D=3D 0) { + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer32; + } else { + AmdCpuState->x64._RIP =3D (UINT32)NewInstructionPointer; + } + + // + // Clear the auto HALT restart flag so the RSM instruction returns + // program control to the instruction following the HLT instruction. + // + if ((AmdCpuState->x64.AutoHALTRestart & BIT0) !=3D 0) { + AmdCpuState->x64.AutoHALTRestart &=3D ~BIT0; + } + } + + return OriginalInstructionPointer; } =20 /** --=20 2.25.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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