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02 Jan 2024 01:40:53 -0800 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Sai Chaganty , Chasel Chiu , Nate DeSimone , Eric Dong , Ashraf Ali S , Chinni B Duggapu , Liming Gao Subject: [edk2-devel][edk2-platforms][PATCH v4] MinPlatformPkg: Support SecFspWrapperPlatformSecLib in X64 Date: Tue, 2 Jan 2024 17:40:36 +0800 Message-Id: <588d6f17d0a4ac8ea2353d027829c1993da3dd0a.1704183832.git.ted.kuo@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: FpRi7DwmCIHXD5O6b5LkrCbBx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1704188470542100001 Content-Type: text/plain; charset="utf-8" https://bugzilla.tianocore.org/show_bug.cgi?id=3D4623 1.Added PeiCoreEntry.nasm, SecEntry.nasm and Stack.nasm for X64. 2.Made changes in common files to support both IA32 and X64. 3.Added the PCDs below for FSP-T UPD revisions and reset vector in FSP. - PcdFspWrapperBfvforResetVectorInFsp - PcdFsptUpdHeaderRevision - PcdFsptArchUpdRevision Cc: Sai Chaganty Cc: Chasel Chiu Cc: Nate DeSimone Cc: Eric Dong Cc: Ashraf Ali S Cc: Chinni B Duggapu Cc: Liming Gao Signed-off-by: Ted Kuo Reviewed-by: Sai Chaganty --- .../SecFspWrapperPlatformSecLib/FsptCoreUpd.h | 25 ++- .../Ia32/SecEntry.nasm | 4 +- .../SecFspWrapperPlatformSecLib.inf | 9 +- ...pWrapperPlatformSecLibResetVectorInFsp.inf | 101 +++++++++ .../SecGetPerformance.c | 11 +- .../SecPlatformInformation.c | 8 +- .../SecRamInitData.c | 73 +++++-- .../X64/PeiCoreEntry.nasm | 202 ++++++++++++++++++ .../X64/SecEntry.nasm | 71 ++++++ .../X64/Stack.nasm | 72 +++++++ .../Ia32 =3D> Include}/Fsp.h | 6 +- .../Intel/MinPlatformPkg/MinPlatformPkg.dec | 17 +- 12 files changed, 565 insertions(+), 34 deletions(-) create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/PeiCoreEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/SecEntry.nasm create mode 100644 Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFsp= WrapperPlatformSecLib/X64/Stack.nasm rename Platform/Intel/MinPlatformPkg/{FspWrapper/Library/SecFspWrapperPlat= formSecLib/Ia32 =3D> Include}/Fsp.h (79%) diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/FsptCoreUpd.h b/Platform/Intel/MinPlatformPkg/FspWrapper/Lib= rary/SecFspWrapperPlatformSecLib/FsptCoreUpd.h index 7c0f605b92..24c18f25b8 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FsptCoreUpd.h +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/FsptCoreUpd.h @@ -1,6 +1,6 @@ /** @file =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 #pragma pack(1) =20 +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <=3D 1 /** Fsp T Core UPD **/ typedef struct { @@ -34,6 +35,28 @@ typedef struct { **/ UINT8 Reserved[16]; } FSPT_CORE_UPD; +#else +/** Fsp T Core UPD +**/ +typedef struct { + +/** Offset 0x0040 +**/ + EFI_PHYSICAL_ADDRESS MicrocodeRegionBase; + +/** Offset 0x0048 +**/ + UINT64 MicrocodeRegionSize; + +/** Offset 0x0050 +**/ + EFI_PHYSICAL_ADDRESS CodeRegionBase; + +/** Offset 0x0058 +**/ + UINT64 CodeRegionSize; +} FSPT_CORE_UPD; +#endif =20 #pragma pack() =20 diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrappe= r/Library/SecFspWrapperPlatformSecLib/Ia32/SecEntry.nasm index 7f6d771e41..0b3f343991 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/SecEntry.nasm +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/SecEntry.nasm @@ -1,6 +1,6 @@ ;-------------------------------------------------------------------------= ----- ; -; Copyright (c) 2019, Intel Corporation. All rights reserved.
+; Copyright (c) 2019 - 2024, Intel Corporation. All rights reserved.
; SPDX-License-Identifier: BSD-2-Clause-Patent ; Module Name: ; @@ -13,7 +13,7 @@ ; ;-------------------------------------------------------------------------= ----- =20 -#include "Fsp.h" +#include =20 SECTION .text =20 diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLib.inf b/Platform/Intel/MinPlatform= Pkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSec= Lib.inf index 2e0d67eae4..6806e000ce 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLib.inf @@ -1,7 +1,7 @@ ## @file -# Provide FSP wrapper platform sec related function. +# Provide FSP wrapper platform sec related function for IA32. # -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,7 +25,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 X64 +# VALID_ARCHITECTURES =3D IA32 # =20 ##########################################################################= ###### @@ -47,7 +47,6 @@ Ia32/SecEntry.nasm Ia32/PeiCoreEntry.nasm Ia32/Stack.nasm - Ia32/Fsp.h =20 ##########################################################################= ###### # @@ -96,3 +95,5 @@ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision ## C= ONSUMES diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf b/Platform/I= ntel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatformSecLib/SecFspWr= apperPlatformSecLibResetVectorInFsp.inf new file mode 100644 index 0000000000..ea062cfad1 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecFspWrapperPlatformSecLibResetVectorInFsp.inf @@ -0,0 +1,101 @@ +## @file +# Provide FSP wrapper platform sec related function for X64. +# +# Copyright (c) 2024, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D SecFspWrapperPlatformSecLib + FILE_GUID =3D 94D8AA5C-5BAE-421F-B2C7-DD1A93BB4D3D + MODULE_TYPE =3D SEC + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D PlatformSecLib + + +# +# The following information is for reference only and not required by the = build tools. +# This library is only supported in X64 when reset vector is in FSP. +# +# VALID_ARCHITECTURES =3D X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources] + FspWrapperPlatformSecLib.c + SecRamInitData.c + SecPlatformInformation.c + SecGetPerformance.c + SecTempRamDone.c + PlatformInit.c + FsptCoreUpd.h + +[Sources.X64] + X64/SecEntry.nasm + X64/PeiCoreEntry.nasm + X64/Stack.nasm + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + IntelFsp2Pkg/IntelFsp2Pkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + MinPlatformPkg/MinPlatformPkg.dec + +[LibraryClasses] + LocalApicLib + SerialPortLib + FspWrapperPlatformLib + FspWrapperApiLib + SecBoardInitLib + TestPointCheckLib + PeiServicesTablePointerLib + +[Ppis] + gEfiSecPlatformInformationPpiGuid ## CONSUMES + gPeiSecPerformancePpiGuid ## CONSUMES + gTopOfTemporaryRamPpiGuid ## PRODUCES + gEfiPeiFirmwareVolumeInfoPpiGuid ## PRODUCES + gFspTempRamExitPpiGuid ## CONSUMES + gPlatformInitTempRamExitPpiGuid ## CONSUMES + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress ## C= ONSUMES + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdSecSerialPortDebugEnable ## C= ONSUMES + +[FixedPcd] + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## C= ONSUMES + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision ## C= ONSUMES + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision ## C= ONSUMES diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecGetPerformance.c b/Platform/Intel/MinPlatformPkg/FspWrapp= er/Library/SecFspWrapperPlatformSecLib/SecGetPerformance.c index ac2deeabec..1699bd9710 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecGetPerformance.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecGetPerformance.c @@ -1,7 +1,7 @@ /** @file Sample to provide SecGetPerformance function. =20 -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -58,6 +58,7 @@ SecGetPerformance ( if (EFI_ERROR (Status)) { return EFI_NOT_FOUND; } + // // |--------------| <- TopOfTemporaryRam - BL // | List Ptr | @@ -77,12 +78,12 @@ SecGetPerformance ( // | TSC[31:00] | // |--------------| // - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); - TopOfTemporaryRam -=3D sizeof (UINT32) * 2; - Count =3D *(UINT32 *)(TopOfTemporaryRam - sizeof (UINT32)); + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN); + TopOfTemporaryRam -=3D sizeof(UINTN) * 2; + Count =3D *(UINT32 *) (UINTN) (TopOfTemporaryRam - sizeof (U= INT32)); Size =3D Count * sizeof (UINT32); =20 - Ticker =3D *(UINT64 *) (TopOfTemporaryRam - sizeof (UINT32) - Size - siz= eof (UINT32) * 2); + Ticker =3D *(UINT64 *) (UINTN) (TopOfTemporaryRam - sizeof (UINT32) - Si= ze - sizeof (UINT64)); Performance->ResetEnd =3D GetTimeInNanoSecond (Ticker); =20 return EFI_SUCCESS; diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecPlatformInformation.c b/Platform/Intel/MinPlatformPkg/Fsp= Wrapper/Library/SecFspWrapperPlatformSecLib/SecPlatformInformation.c index 24d55ed838..4cbde95c2d 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecPlatformInformation.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecPlatformInformation.c @@ -1,7 +1,7 @@ /** @file Provide SecPlatformInformation function. =20 -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -59,9 +59,9 @@ SecPlatformInformation ( // This routine copies the BIST information to the buffer pointed by // PlatformInformationRecord for output. // - TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINT32); - TopOfTemporaryRam -=3D sizeof (UINT32) * 2; - Count =3D *((UINT32 *)(TopOfTemporaryRam - sizeof (UINT32))); + TopOfTemporaryRam =3D (UINTN) TopOfTemporaryRamPpi - sizeof (UINTN); + TopOfTemporaryRam -=3D sizeof (UINTN) * 2; + Count =3D *((UINT32 *)(UINTN) (TopOfTemporaryRam - sizeof (U= INT32))); Size =3D Count * sizeof (IA32_HANDOFF_STATUS); =20 if ((*StructureSize) < (UINT64) Size) { diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/SecRamInitData.c b/Platform/Intel/MinPlatformPkg/FspWrapper/= Library/SecFspWrapperPlatformSecLib/SecRamInitData.c index 355d1e6509..49d5302a7b 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/SecRamInitData.c @@ -1,7 +1,7 @@ /** @file Provide TempRamInitParams data. =20 -Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -12,25 +12,70 @@ SPDX-License-Identifier: BSD-2-Clause-Patent =20 typedef struct { FSP_UPD_HEADER FspUpdHeader; +#if FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 1 + FSPT_ARCH_UPD FsptArchUpd; +#elif FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2 + FSPT_ARCH2_UPD FsptArchUpd; +#endif FSPT_CORE_UPD FsptCoreUpd; -} FSPT_UPD_CORE_DATA; + UINT16 UpdTerminator; +} FSPT_UPD_DATA; =20 -GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_CORE_DATA FsptUpdDataPtr =3D { +GLOBAL_REMOVE_IF_UNREFERENCED CONST FSPT_UPD_DATA FsptUpdDataPtr =3D { { - 0x4450555F54505346, - 0x00, - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + 0x4450555F54505346, // FSP-T= UPD Header Signature - FSPT_UPD + FixedPcdGet8 (PcdFsptUpdHeaderRevision), // FSP-T= UPD Header Revision + { // Reser= ved[23] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00 } }, +#if FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 1 { - FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), - FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), - 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(C= odeRegionSize > LLCSize ? LLCSize : CodeRegionSize) will be used. - FixedPcdGet32 (PcdFlashCodeCacheSize), - { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, // FSP-T= ARCH UPD Revision + { // Reser= ved[3] + 0x00, 0x00, 0x00 + }, + 0x00000020, // Lengt= h of FSP-T ARCH UPD + 0, // FspDe= bugHandler + { // Reser= ved1[20] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, +#elif FixedPcdGet8 (PcdFsptArchUpdRevision) =3D=3D 2 + { + 0x02, // FSP-T= ARCH2 UPD Revision + { // Reser= ved[3] + 0x00, 0x00, 0x00 + }, + 0x00000020, // Lengt= h of FSP-T ARCH2 UPD + 0, // FspDe= bugHandler + { // Reser= ved1[16] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } - } + }, +#endif +#if FixedPcdGet8 (PcdFsptArchUpdRevision) <=3D 1 + { + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionBase + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionSize + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegion= Size > LLCSize ? LLCSize : CodeRegionSize) will be used. + FixedPcdGet32 (PcdFlashCodeCacheSize), = // CodeRegionSize + { = // Reserved[16] + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 + } + }, +#else + { + FixedPcdGet32 (PcdFlashFvMicrocodeBase) + FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionBase + FixedPcdGet32 (PcdFlashFvMicrocodeSize) - FixedPcdGet32 (PcdMicrocodeO= ffsetInFv), // MicrocodeRegionSize + 0, // Set CodeRegionBase as 0, so that caching will be 4GB-(CodeRegion= Size > LLCSize ? LLCSize : CodeRegionSize) will be used. + FixedPcdGet32 (PcdFlashCodeCacheSize) = // CodeRegionSize + }, +#endif + 0x55AA }; - diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/PeiCoreEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWra= pper/Library/SecFspWrapperPlatformSecLib/X64/PeiCoreEntry.nasm new file mode 100644 index 0000000000..af3affcf7f --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/PeiCoreEntry.nasm @@ -0,0 +1,202 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; +; Module Name: +; +; PeiCoreEntry.nasm +; +; Abstract: +; +; Find and call SecStartup +; +;-------------------------------------------------------------------------= ----- + +SECTION .text + +extern ASM_PFX(SecStartup) +extern ASM_PFX(PlatformInit) +extern ASM_PFX(PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp)) + +;-------------------------------------------------------------------------= ---- +; Macro: PUSHA_64 +; +; Description: Saves all registers on stack +; +; Input: None +; +; Output: None +;-------------------------------------------------------------------------= ---- +%macro PUSHA_64 0 + push r8 + push r9 + push r10 + push r11 + push r12 + push r13 + push r14 + push r15 + push rax + push rcx + push rdx + push rbx + push rsp + push rbp + push rsi + push rdi +%endmacro + +;-------------------------------------------------------------------------= ---- +; Macro: POPA_64 +; +; Description: Restores all registers from stack +; +; Input: None +; +; Output: None +;-------------------------------------------------------------------------= ---- +%macro POPA_64 0 + pop rdi + pop rsi + pop rbp + pop rsp + pop rbx + pop rdx + pop rcx + pop rax + pop r15 + pop r14 + pop r13 + pop r12 + pop r11 + pop r10 + pop r9 + pop r8 +%endmacro + +global ASM_PFX(CallPeiCoreEntryPoint) +ASM_PFX(CallPeiCoreEntryPoint): + ; + ; Per X64 calling convention, make sure RSP is 16-byte aligned. + ; + mov rax, rsp + and rax, 0fh + sub rsp, rax + + ; + ; Platform init + ; + PUSHA_64 + sub rsp, 20h + call ASM_PFX(PlatformInit) + add rsp, 20h + POPA_64 + + ; + ; Set stack top pointer + ; + mov rsp, r8 + + ; + ; Push the hob list pointer + ; + push rcx + + ; + ; RBP holds start of BFV passed from Vtf0. Save it to r10. + ; + mov r10, rbp + + ; + ; Save the value + ; RDX: start of range + ; r8: end of range + ; + mov rbp, rsp + push rdx + push r8 + mov r14, rdx + mov r15, r8 + + ; + ; Push processor count to stack first, then BIST status (AP then BSP) + ; + mov eax, 1 + cpuid + shr ebx, 16 + and ebx, 0000000FFh + cmp bl, 1 + jae PushProcessorCount + + ; + ; Some processors report 0 logical processors. Effectively 0 =3D 1. + ; So we fix up the processor count + ; + inc ebx + +PushProcessorCount: + sub rsp, 4 + mov rdi, rsp + mov DWORD [rdi], ebx + + ; + ; We need to implement a long-term solution for BIST capture. For now, = we just copy BSP BIST + ; for all processor threads + ; + xor ecx, ecx + mov cl, bl +PushBist: + sub rsp, 4 + mov rdi, rsp + movd eax, mm0 + mov DWORD [rdi], eax + loop PushBist + + ; + ; FSP saves the timestamp of the beginning of firmware execution in mm5. + ; Get the timestamp from mm5 and then push to stack. + ; + movq rax, mm5 + push rax + + ; + ; Per X64 calling convention, make sure RSP is 16-byte aligned. + ; + mov rax, rsp + and rax, 0fh + sub rsp, rax + + ; + ; Pass entry point of the PEI core + ; + mov rdi, 0FFFFFFE0h + mov edi, DWORD [rdi] + mov r9, rdi + + ; + ; Pass BFV into the PEI Core + ; + ; Reset Vector and initial SEC core (to initialize Temp Ram) is part of = FSP-O. + ; Default UefiCpuPkg Reset Vector locates FSP-O as BFV. However the actu= al + ; SEC core that launches PEI is part of another FV. We need to pass that= FV + ; as BFV to PEI core. + ; + mov r8, ASM_PFX (PcdGet64 (PcdFspWrapperBfvforResetVectorInFsp)) + mov rcx, QWORD[r8] + mov r8, rcx + + ; + ; Pass stack size into the PEI Core + ; + mov rcx, r15 ; Start of TempRam + mov rdx, r14 ; End of TempRam + + sub rcx, rdx ; Size of TempRam + + ; + ; Pass Control into the PEI Core + ; + sub rsp, 20h + call ASM_PFX(SecStartup) + diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/SecEntry.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper= /Library/SecFspWrapperPlatformSecLib/X64/SecEntry.nasm new file mode 100644 index 0000000000..de8ba83d52 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/SecEntry.nasm @@ -0,0 +1,71 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Module Name: +; +; SecEntry.nasm +; +; Abstract: +; +; This is the code that passes control to PEI core. +; +;-------------------------------------------------------------------------= ----- + +#include + +SECTION .text + +extern ASM_PFX(CallPeiCoreEntryPoint) +extern ASM_PFX(FsptUpdDataPtr) +; Pcds +extern ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) + +;-------------------------------------------------------------------------= --- +; +; Procedure: _ModuleEntryPoint +; +; Input: None +; +; Output: None +; +; Destroys: Assume all registers +; +; Description: +; +; After TempRamInit done, pass control to PEI core. +; +; Return: None +; +; MMX Usage: +; MM0 =3D BIST State +; +;-------------------------------------------------------------------------= --- + +BITS 64 +align 16 +global ASM_PFX(_ModuleEntryPoint) +ASM_PFX(_ModuleEntryPoint): + push rax + mov rax, ASM_PFX(FsptUpdDataPtr) ; This is dummy code to include Te= mpRamInitParams in SecCore for FSP-O. +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1 + mov rax, ASM_PFX(PcdGet32 (PcdFspTemporaryRamSize)) + sub edx, dword [rax] ; TemporaryRam for FSP +#endif + pop rax + + mov r8, rdx + mov rdx, rcx + xor ecx, ecx ; zero - no Hob List Yet + mov rsp, r8 + + ; + ; Per X64 calling convention, make sure RSP is 16-byte aligned. + ; + mov rax, rsp + and rax, 0fh + sub rsp, rax + + call ASM_PFX(CallPeiCoreEntryPoint) + + jmp $ diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/X64/Stack.nasm b/Platform/Intel/MinPlatformPkg/FspWrapper/Li= brary/SecFspWrapperPlatformSecLib/X64/Stack.nasm new file mode 100644 index 0000000000..21010bf4ef --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/X64/Stack.nasm @@ -0,0 +1,72 @@ +;-------------------------------------------------------------------------= ----- +; +; Copyright (c) 2024, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +; Abstract: +; +; Switch the stack from temporary memory to permanent memory. +; +;-------------------------------------------------------------------------= ----- + + SECTION .text + +;-------------------------------------------------------------------------= ----- +; VOID +; EFIAPI +; SecSwitchStack ( +; UINT32 TemporaryMemoryBase, +; UINT32 PermanentMemoryBase +; ); +;-------------------------------------------------------------------------= ----- +global ASM_PFX(SecSwitchStack) +ASM_PFX(SecSwitchStack): + ; + ; Save four register: rax, rbx, rcx, rdx + ; + push rax + push rbx + push rcx + push rdx + + ; + ; !!CAUTION!! this function address's is pushed into stack after + ; migration of whole temporary memory, so need save it to permanent + ; memory at first! + ; + + mov rbx, rcx ; Save the first parameter + mov rcx, rdx ; Save the second parameter + + ; + ; Save this function's return address into permanent memory at first. + ; Then, Fixup the esp point to permanent memory + ; + mov rax, rsp + sub rax, rbx + add rax, rcx + mov rdx, qword [rsp] ; copy pushed register's value to perma= nent memory + mov qword [rax], rdx + mov rdx, qword [rsp + 8] + mov qword [rax + 8], rdx + mov rdx, qword [rsp + 16] + mov qword [rax + 16], rdx + mov rdx, qword [rsp + 24] + mov qword [rax + 24], rdx + mov rdx, qword [rsp + 32] ; Update this function's return address= into permanent memory + mov qword [rax + 32], rdx + mov rsp, rax ; From now, rsp is pointed to permanent= memory + + ; + ; Fixup the rbp point to permanent memory + ; + mov rax, rbp + sub rax, rbx + add rax, rcx + mov rbp, rax ; From now, rbp is pointed to permanent= memory + + pop rdx + pop rcx + pop rbx + pop rax + ret + diff --git a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapper= PlatformSecLib/Ia32/Fsp.h b/Platform/Intel/MinPlatformPkg/Include/Fsp.h similarity index 79% rename from Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperP= latformSecLib/Ia32/Fsp.h rename to Platform/Intel/MinPlatformPkg/Include/Fsp.h index 9f6cdcf476..319e1e3372 100644 --- a/Platform/Intel/MinPlatformPkg/FspWrapper/Library/SecFspWrapperPlatfor= mSecLib/Ia32/Fsp.h +++ b/Platform/Intel/MinPlatformPkg/Include/Fsp.h @@ -1,7 +1,7 @@ /** @file Fsp related definitions =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -36,7 +36,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent // // Fsp Header // -#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C -#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 +#define FSP_HEADER_IMAGEBASE_OFFSET 0x1C +#define FSP_HEADER_TEMPRAMINIT_OFFSET 0x30 =20 #endif diff --git a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec b/Platform/In= tel/MinPlatformPkg/MinPlatformPkg.dec index a14c6b2db5..12f86585ad 100644 --- a/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec +++ b/Platform/Intel/MinPlatformPkg/MinPlatformPkg.dec @@ -6,7 +6,7 @@ # INF files to generate AutoGen.c and AutoGen.h files # for the build infrastructure. # -# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2024, Intel Corporation. All rights reserved.
# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent @@ -393,6 +393,21 @@ # gMinPlatformPkgTokenSpaceGuid.PcdFspDispatchModeUseFspPeiMain|TRUE|BOOLE= AN|0xF00000A8 =20 + ## BFV Location for Reset Vector in FSP + # The default of BFV Location for Reset Vector in FSP is 0x00000000FFFF0= 000. + # + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBfvforResetVectorInFsp|0x0000= 0000FFFF0000|UINT64|0xF00000A9 + + ## FSP-T UPD Header Revision + # The default of FSP-T UPD Header Revision is 0. + # + gMinPlatformPkgTokenSpaceGuid.PcdFsptUpdHeaderRevision|0x0|UINT8|0xF0000= 0AA + + ## FSP-T ARCH UPD Revision + # The default of FSP-T ARCH UPD Revision is 0. + # + gMinPlatformPkgTokenSpaceGuid.PcdFsptArchUpdRevision|0x0|UINT8|0xF00000AC + [PcdsFeatureFlag] =20 gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE|BOOLEAN|0= xF00000A1 --=20 2.40.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113032): https://edk2.groups.io/g/devel/message/113032 Mute This Topic: https://groups.io/mt/103478590/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-