From nobody Sun Feb 8 21:29:02 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+93291+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93291+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1662486198; cv=none; d=zohomail.com; s=zohoarc; b=cRJ0LkjuqEgI9eFiK2A9oxbz26/1MW+cUR8j3YaHWYlJjLZQ5TDB37uL/raPAvD6OaXrzCvf0OMKb0CZAPCF0uanF9dtZdUeFpb0PCjtBNtL4FO3Q5rSH2DWi5NtQx02BPk34K5JvPAn2SrIwFqzRpmz44ByG0f47Z24PpmgPnI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1662486198; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=D/M0jl1sqfXdr5TOPd7mhiRxQKmWqi1Ft40cHdtcAEo=; b=fZh8FH5yeuBLFLxaIDKbyXw/cvtSRFYEoMZfWoaYm3xdemiRyFpTZqgwkh3O5k97VRZAC+eLyxtl+woLoeGnKWiH1QRZ58L/fqAI+jLPUfvIJEH2jZvE7bZjXHeD8C1zGC9BBC6+/uT/Li/Kv7atVp+JL3A0zr8FeoEKG4KSc3k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+93291+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1662486198335784.3842627147044; Tue, 6 Sep 2022 10:43:18 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 70TCYY1788612xvaMP6eihFN; Tue, 06 Sep 2022 10:43:17 -0700 X-Received: from mail-qk1-f178.google.com (mail-qk1-f178.google.com [209.85.222.178]) by mx.groups.io with SMTP id smtpd.web11.2278.1662486191733097155 for ; Tue, 06 Sep 2022 10:43:16 -0700 X-Received: by mail-qk1-f178.google.com with SMTP id b2so8700852qkh.12 for ; Tue, 06 Sep 2022 10:43:16 -0700 (PDT) X-Gm-Message-State: IFON3OS2LHofOrzCpy7a0v4ax1787277AA= X-Google-Smtp-Source: AA6agR57TXmCp0c2XX8508DqiGQ8nqZ0EqFoRXywA9PJGVZEOUt++GMn7SX6qSbN0yzabhjj0ky7mw== X-Received: by 2002:a05:620a:3ce:b0:6c4:5e42:2813 with SMTP id r14-20020a05620a03ce00b006c45e422813mr11367010qkm.212.1662486195529; Tue, 06 Sep 2022 10:43:15 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:b132:3785:fa38:a51]) by smtp.gmail.com with ESMTPSA id bi3-20020a05620a318300b006b61b2cb1d2sm11221482qkb.46.2022.09.06.10.43.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:43:15 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Sai Chaganty , Isaac Oram , Chasel Chiu , Nate DeSimone , Ankit Sinha Subject: [edk2-devel][edk2-platforms][PATCH v1 6/7] KabylakeOpenBoardPkg/AspireVn7Dash572G: Improve board detection Date: Tue, 6 Sep 2022 13:42:57 -0400 Message-Id: <5694ab4b9ffb94132360bf216e9ad962fee0cfce.1662485273.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1662486197; bh=da0Qa2WkWasn7+H7sHjn4BBDHnCGXagUt5E6vjx5sOU=; h=Cc:Date:From:Reply-To:Subject:To; b=K87wNbpWwc6iSEwn8dRJjginZ827/qdV70pDVj118hQlaKUrGFD4kkEc6GFHJKviY0J ILWItfsCHqqH0dqXfWl9h7AlXqSK1EJCeV89nDNEC0Xftl9WvIAxPn+PI+bYSvjT4PRBr Z0n77Wk2+6aawH3NqvWsJixmmJxbXcq/5+o= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1662486200128100025 Content-Type: text/plain; charset="utf-8" Improvements based on ENE KB9012Q datasheet. Values read from EC ADC are much more consistent now. Some improvement still necessary before this is reliable, as my Rayleigh-SL (PCH-LP) is now consistently detected as a Newgate-SLS (PCH-H). Cc: Sai Chaganty Cc: Isaac Oram Cc: Chasel Chiu Cc: Nate DeSimone Cc: Ankit Sinha Signed-off-by: Benjamin Doron --- .../Include/Library/BoardEcLib.h | 5 +- .../Library/BoardEcLib/BoardEcLib.inf | 1 + .../Library/BoardEcLib/EcCommands.c | 36 ++++++++++---- .../BoardInitLib/PeiAspireVn7Dash572GDetect.c | 47 +++++++++++-------- .../AspireVn7Dash572G/OpenBoardPkg.dsc | 5 +- .../PeiBoardPolicyUpdate.c | 2 +- .../Include/PlatformBoardId.h | 5 +- 7 files changed, 65 insertions(+), 36 deletions(-) diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/= Library/BoardEcLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572= G/Include/Library/BoardEcLib.h index 8bb4cccb8f19..56fdd4ed756c 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library= /BoardEcLib.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library= /BoardEcLib.h @@ -82,8 +82,9 @@ EcIdxWrite ( ); =20 /** - Read EC analog-digital converter. - TODO: Check if ADC is valid. + Read an analog-digital converter from the EC. + TODO: There are actually 8 ADCs, but those can remain unused. + - Handling port enable bits and pin IE could get complicated. =20 @param[in] Adc @param[out] DataBuffer diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardEcLib/BoardEcLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Da= sh572G/Library/BoardEcLib/BoardEcLib.inf index 56527c3b9a3c..7287301583e0 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/BoardEcLib.inf +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/BoardEcLib.inf @@ -18,6 +18,7 @@ DebugLib EcLib IoLib + TimerLib =20 [Packages] MdePkg/MdePkg.dec diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardEcLib/EcCommands.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash= 572G/Library/BoardEcLib/EcCommands.c index 54cfaba47b1b..182cda6f1933 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/EcCommands.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEc= Lib/EcCommands.c @@ -9,9 +9,11 @@ =20 #include #include +#include #include #include #include +#include =20 /* * Notes: @@ -193,8 +195,9 @@ EcIdxWrite ( } =20 /** - Read EC analog-digital converter. - TODO: Check if ADC is valid. + Read an analog-digital converter from the EC. + TODO: There are actually 8 ADCs, but those can remain unused. + - Handling port enable bits and pin IE could get complicated. =20 @param[in] Adc @param[out] DataBuffer @@ -205,23 +208,36 @@ ReadEcAdcConverter ( OUT UINT16 *DataBuffer ) { - UINT8 AdcConvertersEnabled; // Contains some ADCs and some D= ACs + UINT8 LowAdcsEnabled; // Contains some ADCs and some DACs UINT8 IdxData; =20 if (DataBuffer =3D=3D NULL) { return; } =20 + if (Adc >=3D 4) { + DEBUG ((DEBUG_ERROR, "Handling ADC%d is unsupported!\n", Adc)); + return; + } + // Backup enabled ADCs - EcIdxRead (0xff15, &AdcConvertersEnabled); // ADDAEN + EcIdxRead (0xff15, &LowAdcsEnabled); // ADDAEN =20 - // Enable desired ADC in bitmask (not enabled by EC FW, not used by vend= or FW) - EcIdxWrite (0xff15, AdcConvertersEnabled | ((1 << Adc) & 0xf)); // ADDA= EN + /* 1. Clear IE of the related pin - ADC0: "GPIOIE38[0] (0xFC67[0]) =3D 0= b" */ + EcIdxRead (0xfc67, &IdxData); + IdxData &=3D ~(1 << Adc); + EcIdxWrite (0xfc67, IdxData); =20 - // Sample the desired ADC in binary field; OR the start bit - EcIdxWrite (0xff18, ((Adc << 1) & 0xf) | 1); // ADCTRL + /* 2. Enable desired ADC function in bitmask */ + EcIdxWrite (0xff15, (1 << Adc) & 0xf); // ADDAEN =20 - // Read the desired ADC + /* 3. Enable control of desired ADC in bit field, OR the start bit */ + EcIdxWrite (0xff18, ((Adc << 1) & 7) | 1); // ADCTRL + + /* TODO: Await ADC interrupt */ + MicroSecondDelay (256); // Wait "Voltage Conversion Time" + + /* 4. Read the desired ADC */ EcIdxRead (0xff19, &IdxData); // ADCDAT *DataBuffer =3D (IdxData << 2); // Lower 2-bits of 10-bit ADC are in high bits of next register @@ -229,5 +245,5 @@ ReadEcAdcConverter ( *DataBuffer |=3D ((IdxData & 0xc0) >> 6); =20 // Restore enabled ADCs - EcIdxWrite (0xff15, AdcConvertersEnabled); // ADDAEN + EcIdxWrite (0xff15, LowAdcsEnabled); // ADDAEN } diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/= BoardInitLib/PeiAspireVn7Dash572GDetect.c b/Platform/Intel/KabylakeOpenBoar= dPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c index 344e06859e9b..0ce747bb67c6 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GDetect.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardIn= itLib/PeiAspireVn7Dash572GDetect.c @@ -1,6 +1,7 @@ /** @file =20 Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
+Copyright (c) 2021, Baruch Binyamin Doron
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -10,14 +11,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include =20 -#define ADC_3V_10BIT_GRANULARITY_MAX (3005/1023) +#define ADC_3V_10BIT_GRANULARITY_MAX (3005 / 1023) #define PCB_VER_AD 1 #define MODEL_ID_AD 3 =20 /** - Get Aspire V Nitro (Skylake) board ID. - There are 2 different boards having different ID. - This function will return board ID to caller. + Get Aspire V Nitro (Skylake) board ID. There are 3 different boards + having different PCH (therefore, ID). This function will return board ID= to caller. + - TODO/NB: Detection is still unreliable. Likely must await interrupt. =20 @param[out] DataBuffer =20 @@ -32,34 +33,42 @@ GetAspireVn7Dash572GBoardId ( UINT16 DataBuffer; =20 ReadEcAdcConverter (MODEL_ID_AD, &DataBuffer); - DEBUG ((DEBUG_INFO, "BoardId (raw) =3D 0x%X\n", DataBuffer)); + DEBUG ((DEBUG_INFO, "BoardId (raw) =3D %d\n", DataBuffer)); // Board by max millivoltage range (of 10-bit, 3.005 V ADC) - if (DataBuffer <=3D (1374/ADC_3V_10BIT_GRANULARITY_MAX)) { + if (DataBuffer <=3D (1374 / ADC_3V_10BIT_GRANULARITY_MAX)) { // Consider returning an error DEBUG ((DEBUG_ERROR, "BoardId is reserved?\n")); - } else if (DataBuffer <=3D (2017/ADC_3V_10BIT_GRANULARITY_MAX)) { - *BoardId =3D BoardIdNewgateSLx_dGPU; + *BoardId =3D 0; + } else if (DataBuffer <=3D (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) { + *BoardId =3D BoardIdNewgateSLS_dGPU; + } else if (DataBuffer <=3D (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) { + *BoardId =3D BoardIdRayleighSLS_960M; } else { - *BoardId =3D BoardIdRayleighSLx_dGPU; + *BoardId =3D BoardIdRayleighSL_dGPU; } DEBUG ((DEBUG_INFO, "BoardId =3D 0x%X\n", *BoardId)); =20 ReadEcAdcConverter (PCB_VER_AD, &DataBuffer); - DEBUG ((DEBUG_INFO, "PCB version (raw) =3D 0x%X\n", DataBuffer)); + DEBUG ((DEBUG_INFO, "PCB version (raw) =3D %d\n", DataBuffer)); DEBUG ((DEBUG_INFO, "PCB version: ")); // PCB by max millivoltage range (of 10-bit, 3.005 V ADC) - if (DataBuffer <=3D (2017/ADC_3V_10BIT_GRANULARITY_MAX)) { + if (DataBuffer <=3D (2017 / ADC_3V_10BIT_GRANULARITY_MAX)) { // Consider returning an error DEBUG ((DEBUG_ERROR, "Reserved?\n")); - } else if (DataBuffer <=3D (2259/ADC_3V_10BIT_GRANULARITY_MAX)) { - DEBUG ((DEBUG_ERROR, "-1\n")); - } else if (DataBuffer <=3D (2493/ADC_3V_10BIT_GRANULARITY_MAX)) { - DEBUG ((DEBUG_ERROR, "SC\n")); - } else if (DataBuffer <=3D (2759/ADC_3V_10BIT_GRANULARITY_MAX)) { - DEBUG ((DEBUG_ERROR, "SB\n")); + } else if (DataBuffer <=3D (2259 / ADC_3V_10BIT_GRANULARITY_MAX)) { + DEBUG ((DEBUG_INFO, "-1\n")); + } else if (DataBuffer <=3D (2493 / ADC_3V_10BIT_GRANULARITY_MAX)) { + DEBUG ((DEBUG_INFO, "SC\n")); + } else if (DataBuffer <=3D (2759 / ADC_3V_10BIT_GRANULARITY_MAX)) { + DEBUG ((DEBUG_INFO, "SB\n")); } else { - DEBUG ((DEBUG_ERROR, "SA\n")); + DEBUG ((DEBUG_INFO, "SA\n")); } + + // FIXME + DEBUG ((DEBUG_WARN, "OVERRIDE: Detection is unreliable and other boards = unsupported!\n")); + DEBUG ((DEBUG_INFO, "Setting board SKU to Rayleigh-SL\n")); + *BoardId =3D BoardIdRayleighSL_dGPU; } =20 EFI_STATUS @@ -76,7 +85,7 @@ AspireVn7Dash572GBoardDetect ( =20 DEBUG ((DEBUG_INFO, "AspireVn7Dash572GDetectionCallback\n")); GetAspireVn7Dash572GBoardId (&BoardId); - if (BoardId =3D=3D BoardIdNewgateSLx_dGPU || BoardId =3D=3D BoardIdRayle= ighSLx_dGPU) { + if (BoardId =3D=3D BoardIdNewgateSLS_dGPU || BoardId =3D=3D BoardIdRayle= ighSLS_960M || BoardId =3D=3D BoardIdRayleighSL_dGPU) { LibPcdSetSku (BoardId); ASSERT (LibPcdGetSku() =3D=3D BoardId); } else { diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoar= dPkg.dsc b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardP= kg.dsc index 75c537f1253f..4458e7b75118 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc @@ -88,8 +88,9 @@ [SkuIds] 0x00|DEFAULT # 0|DEFAULT is reserved and always required. # For further details on specific SKUs (which dGPU installed), see EC pa= ge of schematics - 0x41|RayleighSLx_dGPU # Detect the UMA board by GPIO - 0x42|NewgateSLx_dGPU + 0x41|NewgateSLS_dGPU + 0x42|RayleighSLS_960M + 0x43|RayleighSL_dGPU # Detect the UMA board by GPIO =20 ##########################################################################= ###### # diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/L= ibrary/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c b/Platform/Intel/Ka= bylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateL= ib/PeiBoardPolicyUpdate.c index 95b7c4ad5f77..54c742147b19 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c +++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/= PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c @@ -175,7 +175,7 @@ PeiFspBoardPolicyUpdate ( // that it does - this appears to be static text?) and is UART0 me= rely supporting // the UART2 devfn? =20 - // Acer IDs (TODO: "Newgate" IDs) + // Acer IDs (TODO: "Newgate" and "RayleighSLS" IDs) //FIXME FspsUpd->FspsConfig.DefaultSvid =3D 0x1025; //FIXME FspsUpd->FspsConfig.DefaultSid =3D 0x1037; PchGeneralConfig->SubSystemVendorId =3D 0x1025; diff --git a/Platform/Intel/KabylakeOpenBoardPkg/Include/PlatformBoardId.h = b/Platform/Intel/KabylakeOpenBoardPkg/Include/PlatformBoardId.h index 0db4fb23583e..78ea0dea88df 100644 --- a/Platform/Intel/KabylakeOpenBoardPkg/Include/PlatformBoardId.h +++ b/Platform/Intel/KabylakeOpenBoardPkg/Include/PlatformBoardId.h @@ -22,8 +22,9 @@ Kaby Lake Platform Board Identifiers =20 #define BoardIdSkylakeRvp3 0x4 #define BoardIdGalagoPro3 0x20 -#define BoardIdRayleighSLx_dGPU 0x41 -#define BoardIdNewgateSLx_dGPU 0x42 +#define BoardIdNewgateSLS_dGPU 0x41 +#define BoardIdRayleighSLS_960M 0x42 +#define BoardIdRayleighSL_dGPU 0x43 #define BoardIdKabyLakeYLpddr3Rvp3 0x60 =20 #define BoardIdUnknown1 0xffff --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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