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d="scan'208";a="268226389" X-Received: from paagyema-desk2.amr.corp.intel.com ([10.7.159.148]) by orsmga001.jf.intel.com with ESMTP; 09 Sep 2019 16:15:10 -0700 From: "Agyeman, Prince" To: devel@edk2.groups.io Cc: David Wei , Liming Gao , Ankit Sinha , Agyeman Prince , Kubacki Michael A , Nate DeSimone Subject: [edk2-devel] [edk2-platforms] [PATCH 3/3] SimicsIch10Pkg: Fix GCC build issues Date: Mon, 9 Sep 2019 16:15:09 -0700 Message-Id: <53c8ae3dc3621bf64abfe21ceff0d04831df787e.1568070575.git.prince.agyeman@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,prince.agyeman@intel.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1568070913; bh=SKMBllBvIq4N2UNFkukANF+UIwF9vO6J58duRW7sPqk=; h=Cc:Date:From:Reply-To:Subject:To; b=aDZlu9/Zeaque5SnGaPDA6scrzI1YJcEDRWXyemCtZILwxAm1JgZUv15+9T29cSzKw2 TT+cyQCJkPVZmetQYZ9eWRJDpT1FGB/58vulAQzyzYJIVdQFwwUiZCpZWufl7FMhHue0P RnNn3Xw8/3oy5uilihPxz0t7+aPNFJlMwqU= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" Cc: David Wei Cc: Liming Gao Cc: Ankit Sinha Cc: Agyeman Prince Cc: Kubacki Michael A Cc: Nate DeSimone Signed-off-by: Prince Agyeman Reviewed-by: Nate DeSimone --- .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c | 3 --- .../SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c | 7 ++----- 2 files changed, 2 insertions(+), 8 deletions(-) diff --git a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLi= b/SpiCommon.c b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommo= nLib/SpiCommon.c index bd08b2453b..3e7dffedfb 100644 --- a/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCo= mmon.c +++ b/Silicon/Intel/SimicsIch10Pkg/LibraryPrivate/BasePchSpiCommonLib/SpiCo= mmon.c @@ -637,7 +637,6 @@ SendSpiCmd ( EFI_STATUS Status; UINT32 Index; SPI_INSTANCE *SpiInstance; - UINTN SpiBaseAddress; UINTN PchSpiBar0; UINT32 HardwareSpiAddr; UINT32 FlashRegionSize; @@ -648,9 +647,7 @@ SendSpiCmd ( =20 Status =3D EFI_SUCCESS; SpiInstance =3D SPI_INSTANCE_FROM_SPIPROTOCOL (This); - SpiBaseAddress =3D SpiInstance->PchSpiBase; PchSpiBar0 =3D AcquireSpiBar0 (SpiInstance); - SpiBaseAddress =3D SpiInstance->PchSpiBase; ABase =3D SpiInstance->PchAcpiBase; =20 // diff --git a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2= Dxe.c b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c index 268b04d25a..cc2d00b785 100644 --- a/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c +++ b/Silicon/Intel/SimicsIch10Pkg/SmmControl/RuntimeDxe/SmmControl2Dxe.c @@ -131,7 +131,6 @@ SmmControl2DxeTrigger ( IN UINTN ActivationInterval OPTIONAL ) { - EFI_STATUS Status; // // No support for queued or periodic activation. // @@ -141,7 +140,7 @@ SmmControl2DxeTrigger ( /// /// Clear any pending the APM SMI /// - Status =3D SmmClear(); + SmmClear(); // // The so-called "Advanced Power Management Status Port Register" is in = fact // a generic data passing register, between the caller and the SMI @@ -181,8 +180,6 @@ SmmControl2DxeClear ( IN BOOLEAN Periodic OPTIONAL ) { - EFI_STATUS Status; - if (Periodic) { return EFI_INVALID_PARAMETER; } @@ -201,7 +198,7 @@ SmmControl2DxeClear ( // // So, nothing to do here. // - Status =3D SmmClear(); + SmmClear(); =20 return EFI_SUCCESS; } --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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