From nobody Sun Feb 8 19:24:21 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88112+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88112+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1648454994; cv=none; d=zohomail.com; s=zohoarc; b=lCrspLVrZFzuDJoH8+jOVpi3AI0x9rXrwElgZfuXZCfB019EAv3/DUtDy9okn2eqRHAcXZ5djDPTBE5CjXXHxFyOFEv3geQNgFMggGXPQgjNmfzfF6r01M9pEeKAoGvdaFXOgyZrzLGTy6+JVH2Ybr2lYq5O/7mHLjPDptcTrO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1648454994; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=w952owuW6Qx7M9b6mg4SMb9aOI7Lu+1+Us9YTof5UTc=; b=nRNy6IjydyFb6nY2INiYX+PnZTyypjnvveSsD3PSBqlcdGWxAyGFs2NaEjIE6eW005wsfx9ed2649fAiBfzA6y3xD5hgJgVWDkJ2J363/T6BlbHE0+cICdwA5pblqCTafeywt13pIDUc7gyrnuRouvu21eBpktXFM36pmF4Q/rg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88112+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 164845499426798.10855803664231; Mon, 28 Mar 2022 01:09:54 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id g6BDYY1788612xkYLxeYHBfd; Mon, 28 Mar 2022 01:09:53 -0700 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web12.8480.1648454962517853012 for ; Mon, 28 Mar 2022 01:09:52 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10299"; a="257771024" X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="257771024" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:51 -0700 X-IronPort-AV: E=Sophos;i="5.90,216,1643702400"; d="scan'208";a="563427537" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.175.167]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Mar 2022 01:09:48 -0700 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Ard Biesheuvel , Jordan Justen , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann , Sebastien Boeuf Subject: [edk2-devel] [PATCH V11 22/47] OvmfPkg/PlatformPei: Refactor AddressWidthInitialization Date: Mon, 28 Mar 2022 16:08:01 +0800 Message-Id: <4fcf2fdf74b0c474341b22ca113544dabb284314.1648454441.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: g1Tgrx2fz8CpO2eSYsOoMEvUx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1648454993; bh=hYxdcBhRcMsDL7qsDWn2oCsr56N9lTtjyQKMeIUv0ck=; h=Cc:Date:From:Reply-To:Subject:To; b=WRw8hLKcQb1IbtcUJ+OTidTiQu35TTqo0qxp+waASODtNBsbNwCgezFEGwIuO6T58tc 0mxuSBjpsohaBrwfnjrylIR/b0ozHb6cLTxiaNkBfYNeR05BJB3/ec0bsKDnpvGHUWlIi 3+AaC+CQ3V/V3ZkG7D5P4BfooRY91xRCO0g= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1648454995603100003 Content-Type: text/plain; charset="utf-8" BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3863 From this patch we start to restruct the functions which set PCDs into two, one for PlatformInitLib, one for PlatformPei. AddressWidthInitialization is the first one. It is splitted into two: - PlatformAddressWidthInitialization is for PlatformInitLib - AddressWidthInitialization is for PlatformPei. It calls PlatformAddressWidthInitialization then set PCDs. Below functions are also refined for PlatformInitLib: - PlatformScanOrAdd64BitE820Ram - PlatformGetSystemMemorySizeAbove4gb - PlatformGetFirstNonAddress All the SetPcd codes are removed from above functions. Cc: Ard Biesheuvel Cc: Jordan Justen Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Cc: Sebastien Boeuf Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- OvmfPkg/PlatformPei/MemDetect.c | 117 ++++++++++++++++++++------------ OvmfPkg/PlatformPei/Platform.c | 6 +- 2 files changed, 78 insertions(+), 45 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index f3819b997b3b..5507d9585bab 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -189,7 +189,7 @@ QemuUc32BaseInitialization ( Find the highest exclusive >=3D4GB RAM address, or produce memory resour= ce descriptor HOBs for RAM entries that start at or above 4GB. =20 - @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ra= m() + @param[out] MaxAddress If MaxAddress is NULL, then PlatformScanOrAdd64B= itE820Ram() produces memory resource descriptor HOBs for RAM entries that start at or above 4GB. =20 @@ -210,7 +210,7 @@ QemuUc32BaseInitialization ( **/ STATIC EFI_STATUS -ScanOrAdd64BitE820Ram ( +PlatformScanOrAdd64BitE820Ram ( IN BOOLEAN AddHighHob, OUT UINT64 *LowMemory OPTIONAL, OUT UINT64 *MaxAddress OPTIONAL @@ -385,7 +385,7 @@ GetSystemMemorySizeBelow4gb ( return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE); } =20 - Status =3D ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); if ((Status =3D=3D EFI_SUCCESS) && (LowerMemorySize > 0)) { return (UINT32)LowerMemorySize; } @@ -407,7 +407,7 @@ GetSystemMemorySizeBelow4gb ( =20 STATIC UINT64 -GetSystemMemorySizeAbove4gb ( +PlatformGetSystemMemorySizeAbove4gb ( ) { UINT32 Size; @@ -434,7 +434,7 @@ GetSystemMemorySizeAbove4gb ( **/ STATIC UINT64 -GetFirstNonAddress ( +PlatformGetFirstNonAddress ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -444,7 +444,6 @@ GetFirstNonAddress ( FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; UINT64 HotPlugMemoryEnd; - RETURN_STATUS PcdStatus; =20 // // set FirstNonAddress to suppress incorrect compiler/analyzer warnings @@ -458,9 +457,9 @@ GetFirstNonAddress ( // Otherwise, get the flat size of the memory above 4GB from the CMOS (w= hich // can only express a size smaller than 1TB), and add it to 4GB. // - Status =3D ScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); + Status =3D PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress); if (EFI_ERROR (Status)) { - FirstNonAddress =3D BASE_4GB + GetSystemMemorySizeAbove4gb (); + FirstNonAddress =3D BASE_4GB + PlatformGetSystemMemorySizeAbove4gb (); } =20 // @@ -475,12 +474,6 @@ GetFirstNonAddress ( =20 #endif =20 - // - // Otherwise, in order to calculate the highest address plus one, we must - // consider the 64-bit PCI host aperture too. Fetch the default size. - // - PlatformInfoHob->PcdPciMmio64Size =3D PcdGet64 (PcdPciMmio64Size); - // // See if the user specified the number of megabytes for the 64-bit PCI = host // aperture. Accept an aperture size up to 16TB. @@ -522,8 +515,6 @@ GetFirstNonAddress ( "%a: disabling 64-bit PCI host aperture\n", __FUNCTION__ )); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); - ASSERT_RETURN_ERROR (PcdStatus); } =20 // @@ -574,26 +565,6 @@ GetFirstNonAddress ( // PlatformInfoHob->PcdPciMmio64Base =3D ALIGN_VALUE (PlatformInfoHob->PcdP= ciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size)); =20 - if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { - // - // The core PciHostBridgeDxe driver will automatically add this range = to - // the GCD memory space map through our PciHostBridgeLib instance; her= e we - // only need to set the PCDs. - // - PcdStatus =3D PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio= 64Base); - ASSERT_RETURN_ERROR (PcdStatus); - PcdStatus =3D PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio= 64Size); - ASSERT_RETURN_ERROR (PcdStatus); - - DEBUG (( - DEBUG_INFO, - "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", - __FUNCTION__, - PlatformInfoHob->PcdPciMmio64Base, - PlatformInfoHob->PcdPciMmio64Size - )); - } - // // The useful address space ends with the 64-bit PCI host aperture. // @@ -602,10 +573,11 @@ GetFirstNonAddress ( } =20 /** - Initialize the mPhysMemAddressWidth variable, based on guest RAM size. + Initialize the PhysMemAddressWidth field in PlatformInfoHob based on gue= st RAM size. **/ VOID -AddressWidthInitialization ( +EFIAPI +PlatformAddressWidthInitialization ( IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob ) { @@ -618,7 +590,7 @@ AddressWidthInitialization ( // The DXL IPL keys off of the physical address bits advertized in the C= PU // HOB. To conserve memory, we calculate the minimum address width here. // - FirstNonAddress =3D GetFirstNonAddress (PlatformInfoHob); + FirstNonAddress =3D PlatformGetFirstNonAddress (PlatformInfoHob); PhysMemAddressWidth =3D (UINT8)HighBitSet64 (FirstNonAddress); =20 // @@ -645,6 +617,65 @@ AddressWidthInitialization ( PlatformInfoHob->PhysMemAddressWidth =3D PhysMemAddressWidth; } =20 +/** + Initialize the PhysMemAddressWidth field in PlatformInfoHob based on gue= st RAM size. +**/ +VOID +AddressWidthInitialization ( + IN OUT EFI_HOB_PLATFORM_INFO *PlatformInfoHob + ) +{ + RETURN_STATUS PcdStatus; + + PlatformAddressWidthInitialization (PlatformInfoHob); + + // + // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO + // resources to 32-bit anyway. See DegradeResource() in + // "PciResourceSupport.c". + // + #ifdef MDE_CPU_IA32 + if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { + return; + } + + #endif + + if (PlatformInfoHob->PcdPciMmio64Size =3D=3D 0) { + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + DEBUG (( + DEBUG_INFO, + "%a: disabling 64-bit PCI host aperture\n", + __FUNCTION__ + )); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, 0); + ASSERT_RETURN_ERROR (PcdStatus); + } + + return; + } + + if (PlatformInfoHob->BootMode !=3D BOOT_ON_S3_RESUME) { + // + // The core PciHostBridgeDxe driver will automatically add this range = to + // the GCD memory space map through our PciHostBridgeLib instance; her= e we + // only need to set the PCDs. + // + PcdStatus =3D PcdSet64S (PcdPciMmio64Base, PlatformInfoHob->PcdPciMmio= 64Base); + ASSERT_RETURN_ERROR (PcdStatus); + PcdStatus =3D PcdSet64S (PcdPciMmio64Size, PlatformInfoHob->PcdPciMmio= 64Size); + ASSERT_RETURN_ERROR (PcdStatus); + + DEBUG (( + DEBUG_INFO, + "%a: Pci64Base=3D0x%Lx Pci64Size=3D0x%Lx\n", + __FUNCTION__, + PlatformInfoHob->PcdPciMmio64Base, + PlatformInfoHob->PcdPciMmio64Size + )); + } +} + /** Calculate the cap for the permanent PEI memory. **/ @@ -704,7 +735,7 @@ GetPeiMemoryCap ( =20 // // Add 64 MB for miscellaneous allocations. Note that for - // mPhysMemAddressWidth values close to 36, the cap will actually be + // PhysMemAddressWidth values close to 36, the cap will actually be // dominated by this increment. // return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB); @@ -763,7 +794,7 @@ PublishPeiMemory ( PeiMemoryCap =3D GetPeiMemoryCap (); DEBUG (( DEBUG_INFO, - "%a: mPhysMemAddressWidth=3D%d PeiMemoryCap=3D%u KB\n", + "%a: PhysMemAddressWidth=3D%d PeiMemoryCap=3D%u KB\n", __FUNCTION__, mPlatformInfoHob.PhysMemAddressWidth, PeiMemoryCap >> 10 @@ -902,9 +933,9 @@ QemuInitializeRam ( // entries. Otherwise, create a single memory HOB with the flat >=3D4GB // memory size read from the CMOS. // - Status =3D ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); + Status =3D PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL); if (EFI_ERROR (Status)) { - UpperMemorySize =3D GetSystemMemorySizeAbove4gb (); + UpperMemorySize =3D PlatformGetSystemMemorySizeAbove4gb (); if (UpperMemorySize !=3D 0) { PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); } diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3e0c56db57ed..7d370c9b8fa8 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -734,8 +734,10 @@ InitializePlatform ( =20 DEBUG ((DEBUG_INFO, "Platform PEIM Loaded\n")); =20 - mPlatformInfoHob.SmmSmramRequire =3D FeaturePcdGet (PcdSmmSmramRequire); - mPlatformInfoHob.SevEsIsEnabled =3D MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.SmmSmramRequire =3D FeaturePcdGet (PcdSmmSmramRequi= re); + mPlatformInfoHob.SevEsIsEnabled =3D MemEncryptSevEsIsEnabled (); + mPlatformInfoHob.PcdPciMmio64Size =3D PcdGet64 (PcdPciMmio64Size); + mPlatformInfoHob.DefaultMaxCpuNumber =3D PcdGet32 (PcdCpuMaxLogicalProce= ssorNumber); =20 PlatformDebugDumpCmos (); =20 --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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