From nobody Mon Feb 9 21:20:59 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+84628+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84628+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1639128942; cv=none; d=zohomail.com; s=zohoarc; b=e0ANk+p2tlEq8xw3xBOVIrAWCCValdBLIafceRAvPqlD4dubEQlYmN8lJqiOu9Fx9Xoevu2Ka8qdTMQwOtS6ZUEGbxWtWKtulfsgo8/BGcSkb5gKNQsxMhWHjemZt7didniYH9hk2G6JWQ1azRyMYk75Yp4i0uIAFG8aUrZ5A8o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639128942; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=YCWUH1PJ9QpJW4JPEwxanKCiBggvR4rpNY6ySti+xXA=; b=AOq4pU1NsDM4U1iG7FFDMsc9mtnA/FhtSuxmChdRSu1ywgB4wnbgqRjm8OQZDFVQmtoNFk5w1a1en+S71gDMH5sjc3ExnxPVKZt+XNvMMpEQSogRCxE382ZyxxKmieEeHEhlNndg1CZLKhNYbejAsZc9LjsRhFXECKdTzWATtQM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84628+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1639128941812898.990373146438; Fri, 10 Dec 2021 01:35:41 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id Kr84YY1788612xSXNdC1qiaB; Fri, 10 Dec 2021 01:35:41 -0800 X-Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by mx.groups.io with SMTP id smtpd.web11.5152.1639128940418296817 for ; Fri, 10 Dec 2021 01:35:40 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10193"; a="237051210" X-IronPort-AV: E=Sophos;i="5.88,195,1635231600"; d="scan'208";a="237051210" X-Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2021 01:35:39 -0800 X-IronPort-AV: E=Sophos;i="5.88,195,1635231600"; d="scan'208";a="503862746" X-Received: from gmarti2-mobl1.amr.corp.intel.com (HELO sboeuf-mobl.home) ([10.252.20.4]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Dec 2021 01:35:37 -0800 From: sebastien.boeuf@intel.com To: devel@edk2.groups.io Cc: jiewen.yao@intel.com, jordan.l.justen@intel.com, kraxel@redhat.com, sebastien.boeuf@intel.com Subject: [edk2-devel] [PATCH v6 1/5] OvmfPkg: Handle Cloud Hypervisor host bridge Date: Fri, 10 Dec 2021 10:35:09 +0100 Message-Id: <4eb05aa3684aa635d686cd2e45eafe2fcc120565.1639128828.git.sebastien.boeuf@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,sebastien.boeuf@intel.com X-Gm-Message-State: f4DgmWF2au2bqZp5q6a9LIpIx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1639128941; bh=Pr7m4xDrMS1I2oLor+paUcN/ritr/1Q40+BTItKFJnY=; h=Cc:Content-Type:Date:From:Reply-To:Subject:To; b=E43kkV7UrmoiZUP9UqRBXWo75VR2TEFuI19kpac9rQBZzXVgDBhz8Fk96N4QmYWTACU Jxh2SMQUjgmgjBtEwEJxuFEclLl3b7dDa59124ba35O58xiwvWBJpheq62lmG8QmB5l+Y BPUr3F08ShEJ/0zz9qacZatLwrCZEebAgsI= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1639128943571100004 Content-Type: text/plain; charset="utf-8" From: Sebastien Boeuf Handle things differently when the detected host bridge matches the Cloud Hypervisor PCI host bridge identifier. Reviewed-by: Gerd Hoffmann Reviewed-by: Jiewen Yao Signed-off-by: Rob Bradford Signed-off-by: Sebastien Boeuf --- OvmfPkg/Include/IndustryStandard/CloudHv.h | 35 +++++++++++++++++++ OvmfPkg/Include/OvmfPlatforms.h | 1 + .../Library/AcpiTimerLib/BaseAcpiTimerLib.c | 3 ++ .../AcpiTimerLib/BaseRomAcpiTimerLib.c | 4 +++ .../Library/AcpiTimerLib/DxeAcpiTimerLib.c | 3 ++ .../PlatformBootManagerLib/BdsPlatform.c | 1 + .../ResetSystemLib/BaseResetShutdown.c | 3 ++ .../Library/ResetSystemLib/DxeResetShutdown.c | 12 +++++-- OvmfPkg/PlatformPei/MemDetect.c | 9 ++++- OvmfPkg/PlatformPei/Platform.c | 6 ++++ 10 files changed, 74 insertions(+), 3 deletions(-) create mode 100644 OvmfPkg/Include/IndustryStandard/CloudHv.h diff --git a/OvmfPkg/Include/IndustryStandard/CloudHv.h b/OvmfPkg/Include/I= ndustryStandard/CloudHv.h new file mode 100644 index 0000000000..6ab18ad50d --- /dev/null +++ b/OvmfPkg/Include/IndustryStandard/CloudHv.h @@ -0,0 +1,35 @@ +/** @file + Various defines related to Cloud Hypervisor + + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#ifndef __CLOUDHV_H__ +#define __CLOUDHV_H__ + +// +// Host Bridge Device ID +// +#define CLOUDHV_DEVICE_ID 0x0d57 + +// +// ACPI timer address +// +#define CLOUDHV_ACPI_TIMER_IO_ADDRESS 0xb008 + +// +// ACPI shutdown device address +// +#define CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS 0x03c0 + +// +// 32-bit MMIO memory hole base address +// +#define CLOUDHV_MMIO_HOLE_ADDRESS 0xc0000000 + +// +// 32-bit MMIO memory hole size +// +#define CLOUDHV_MMIO_HOLE_SIZE 0x38000000 + +#endif // __CLOUDHV_H__ diff --git a/OvmfPkg/Include/OvmfPlatforms.h b/OvmfPkg/Include/OvmfPlatform= s.h index de5d7663b4..f613dd7e2d 100644 --- a/OvmfPkg/Include/OvmfPlatforms.h +++ b/OvmfPkg/Include/OvmfPlatforms.h @@ -16,6 +16,7 @@ #include #include #include +#include =20 // // OVMF Host Bridge DID Address diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c b/OvmfPkg/Libr= ary/AcpiTimerLib/BaseAcpiTimerLib.c index 1d33c86313..6d1e1cb05e 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseAcpiTimerLib.c @@ -55,6 +55,9 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c b/OvmfPkg/L= ibrary/AcpiTimerLib/BaseRomAcpiTimerLib.c index 54a288d52f..c771997a2a 100644 --- a/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/BaseRomAcpiTimerLib.c @@ -53,6 +53,8 @@ AcpiTimerLibConstructor ( AcpiCtlReg =3D POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL); AcpiEnBit =3D ICH9_ACPI_CNTL_ACPI_EN; break; + case CLOUDHV_DEVICE_ID: + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, @@ -111,6 +113,8 @@ InternalAcpiGetTimerTick ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + return IoRead32 (CLOUDHV_ACPI_TIMER_IO_ADDRESS); default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c b/OvmfPkg/Libra= ry/AcpiTimerLib/DxeAcpiTimerLib.c index 01f28b2916..1158461874 100644 --- a/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c +++ b/OvmfPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.c @@ -50,6 +50,9 @@ AcpiTimerLibConstructor ( case INTEL_Q35_MCH_DEVICE_ID: Pmba =3D POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE); break; + case CLOUDHV_DEVICE_ID: + mAcpiTimerIoAddr =3D CLOUDHV_ACPI_TIMER_IO_ADDRESS; + return RETURN_SUCCESS; default: DEBUG (( DEBUG_ERROR, diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg= /Library/PlatformBootManagerLib/BdsPlatform.c index f73c59dfff..5feadc51d7 100644 --- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c +++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c @@ -1390,6 +1390,7 @@ PciAcpiInitialization ( PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), PciHostIrqs[3]); // H break; case MICROVM_PSEUDO_DEVICE_ID: + case CLOUDHV_DEVICE_ID: return; default: if (XenDetected ()) { diff --git a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c b/OvmfPkg/L= ibrary/ResetSystemLib/BaseResetShutdown.c index 29abd57fa7..c21d3c89cf 100644 --- a/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/BaseResetShutdown.c @@ -40,6 +40,9 @@ ResetShutdown ( case INTEL_Q35_MCH_DEVICE_ID: AcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + IoWrite8 (CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS, 5 << 2 | 1 << 5); + CpuDeadLoop (); default: ASSERT (FALSE); CpuDeadLoop (); diff --git a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c b/OvmfPkg/Li= brary/ResetSystemLib/DxeResetShutdown.c index a0db8b50bf..96d93e295f 100644 --- a/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c +++ b/OvmfPkg/Library/ResetSystemLib/DxeResetShutdown.c @@ -16,6 +16,7 @@ #include // PIIX4_PMBA_VALUE =20 STATIC UINT16 mAcpiPmBaseAddress; +STATIC UINT16 mAcpiHwReducedSleepCtl; =20 EFI_STATUS EFIAPI @@ -34,6 +35,9 @@ DxeResetInit ( case INTEL_Q35_MCH_DEVICE_ID: mAcpiPmBaseAddress =3D ICH9_PMBASE_VALUE; break; + case CLOUDHV_DEVICE_ID: + mAcpiHwReducedSleepCtl =3D CLOUDHV_ACPI_SHUTDOWN_IO_ADDRESS; + break; default: ASSERT (FALSE); CpuDeadLoop (); @@ -56,7 +60,11 @@ ResetShutdown ( VOID ) { - IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); - IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + if (mAcpiHwReducedSleepCtl) { + IoWrite8 (mAcpiHwReducedSleepCtl, 5 << 2 | 1 << 5); + } else { + IoBitFieldWrite16 (mAcpiPmBaseAddress + 4, 10, 13, 0); + IoOr16 (mAcpiPmBaseAddress + 4, BIT13); + } CpuDeadLoop (); } diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetec= t.c index 738ed0c208..25bbe92862 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -16,6 +16,7 @@ Module Name: #include #include #include +#include #include #include =20 @@ -159,6 +160,12 @@ QemuUc32BaseInitialization ( return; } =20 + if (mHostBridgeDevId =3D=3D CLOUDHV_DEVICE_ID) { + Uc32Size =3D CLOUDHV_MMIO_HOLE_SIZE; + mQemuUc32Base =3D CLOUDHV_MMIO_HOLE_ADDRESS; + return; + } + ASSERT (mHostBridgeDevId =3D=3D INTEL_82441_DEVICE_ID); // // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one @@ -819,7 +826,7 @@ QemuInitializeRam ( // practically any alignment, and we may not have enough variable MTRRs = to // cover it exactly. // - if (IsMtrrSupported ()) { + if (IsMtrrSupported () && mHostBridgeDevId !=3D CLOUDHV_DEVICE_ID) { MtrrGetAllMtrrs (&MtrrSettings); =20 // diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 3000176efd..3b364c088e 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -374,6 +374,12 @@ MiscInitialization ( ); ASSERT_RETURN_ERROR (PcdStatus); return; + case CLOUDHV_DEVICE_ID: + DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor host bridge\n", __FUNCTION= __)); + PcdStatus =3D PcdSet16S (PcdOvmfHostBridgePciDevId, + CLOUDHV_DEVICE_ID); + ASSERT_RETURN_ERROR (PcdStatus); + return; default: DEBUG (( DEBUG_ERROR, --=20 2.30.2 --------------------------------------------------------------------- Intel Corporation SAS (French simplified joint stock company) Registered headquarters: "Les Montalets"- 2, rue de Paris,=20 92196 Meudon Cedex, France Registration Number: 302 456 199 R.C.S. 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