From nobody Sat Feb 7 08:45:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88398+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88398+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649053409; cv=none; d=zohomail.com; s=zohoarc; b=etwOKdCtwJifxPzB1e1k0H3vxuqa2X6Bb1p4W9Ll49VtrUi3xH5F9mnlPmI1++zhUWEUsgt13PddCQZLV/DgscKJJ4o80Nmeq9XQ6+D1bkHyrdj0oDALplFqArcBHCuyhLDxHFtQ06pkAUnK7IuN0r8PqgfChcAIqG4kQf8/e7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649053409; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=ABf5S0VcIutAl/23d7YfSkaAFO3MkMugINno1WzXDzo=; b=E3iUkryUW2BXbAeQjl6wNbrT8KT7YoxssvvXplQKFdvfk1HKXoUP32vXtdKuYZi9E2hRKBZ39OXxmphizM2VXql478w3iXMWG0rlmll1MN8cde1p1Vo4Sl+M7WnamulvzQjWpjAEn/PP4RH8pVJbtWm/TEUm8XrMS/nRB3mwPWQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88398+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649053409845316.4923911005835; Sun, 3 Apr 2022 23:23:29 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id LCZLYY1788612xfQ4ZnzAkFE; Sun, 03 Apr 2022 23:23:29 -0700 X-Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web10.32299.1649053407401800519 for ; Sun, 03 Apr 2022 23:23:28 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="321143221" X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="321143221" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 23:23:27 -0700 X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="696468699" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 23:23:26 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH v2 5/8] IntelFsp2Pkg: SecFspSecPlatformLibNull support for X64 Date: Mon, 4 Apr 2022 14:23:08 +0800 Message-Id: <4c164ed51d9b1ed06d9f5ee4e32142bd15528be8.1649053236.git.ted.kuo@intel.com> In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: jzcHSZdRHC7ZssjsalG0TiZWx1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649053409; bh=yDCtijdJalwGpSKaW6WcRbmD8iAhocwgVBLugXs9XP8=; h=Cc:Date:From:Reply-To:Subject:To; b=lcdPhkTzXIRnk6OcY1G37+hrDE2hsTmxWq+yxXBc78mlIJVE2S3xwL0DLR1Ozd8tb4T LUYY6NH1VajeOsNWJimNjY13LPRfUZfU3J9lQR44frblw062AMp0op0FymyqtBOjhurXR w5rDLa2zvaHXBS1ipChJk2CSj108hdMgKYU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649053411180100023 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 1.Added SecFspSecPlatformLibNull support for X64. 2.Added X64 support to IntelFsp2Pkg.dsc. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 +- .../SecFspSecPlatformLibNull.inf | 6 +++- .../SecFspSecPlatformLibNull/X64/Long64.nasm | 31 +++++++++++++++++ .../SecFspSecPlatformLibNull/X64/SecCarInit.nasm | 40 ++++++++++++++++++= ++++ 4 files changed, 77 insertions(+), 2 deletions(-) create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long6= 4.nasm create mode 100644 IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCa= rInit.nasm diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index c1414f7e75..1284aa042c 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -12,7 +12,7 @@ PLATFORM_VERSION =3D 0.1 DSC_SPECIFICATION =3D 0x00010005 OUTPUT_DIRECTORY =3D Build/IntelFsp2Pkg - SUPPORTED_ARCHITECTURES =3D IA32 + SUPPORTED_ARCHITECTURES =3D IA32|X64 BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT SKUID_IDENTIFIER =3D DEFAULT =20 diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatfor= mLibNull.inf b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatf= ormLibNull.inf index 42e7d83c32..ef859d5ea5 100644 --- a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNul= l.inf +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNul= l.inf @@ -23,7 +23,7 @@ # # The following information is for reference only and not required by the = build tools. # -# VALID_ARCHITECTURES =3D IA32 +# VALID_ARCHITECTURES =3D IA32 X64 # =20 ##########################################################################= ###### @@ -39,6 +39,10 @@ Ia32/Flat32.nasm Ia32/SecCarInit.nasm =20 +[Sources.X64] + X64/Long64.nasm + X64/SecCarInit.nasm + ##########################################################################= ###### # # Package Dependency Section - list of Package files that are required for diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm = b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm new file mode 100644 index 0000000000..836257f962 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/Long64.nasm @@ -0,0 +1,31 @@ +;; @file +; This is the code that performs early platform initialization. +; It consumes the reset vector, configures the stack. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +extern ASM_PFX(TempRamInitApi) + +SECTION .text + +%macro RET_RSI 0 + + movd rsi, mm7 ; restore RSI from MM7 + jmp rsi + +%endmacro + +; +; Perform early platform initialization +; +global ASM_PFX(SecPlatformInit) +ASM_PFX(SecPlatformInit): + + RET_RSI + diff --git a/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.n= asm b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm new file mode 100644 index 0000000000..e64c77ed18 --- /dev/null +++ b/IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/X64/SecCarInit.nasm @@ -0,0 +1,40 @@ +;; @file +; SEC CAR function +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + +; +; Define assembler characteristics +; + +%macro RET_RSI 0 + + movd rsi, mm7 ; move ReturnAddress from MM7 to R= SI + jmp rsi + +%endmacro + +SECTION .text + +;-------------------------------------------------------------------------= ---- +; +; Section: SecCarInit +; +; Description: This function initializes the Cache for Data, Stack, and C= ode +; +;-------------------------------------------------------------------------= ---- +global ASM_PFX(SecCarInit) +ASM_PFX(SecCarInit): + + ; + ; Set up CAR + ; + + xor rax, rax + +SecCarInitExit: + + RET_RSI + --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#88398): https://edk2.groups.io/g/devel/message/88398 Mute This Topic: https://groups.io/mt/90235998/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-