From nobody Tue Nov 26 10:36:29 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) client-ip=66.175.222.12; envelope-from=bounce+27952+53140+1787277+3901457@groups.io; helo=web01.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53140+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1578640103; cv=none; d=zohomail.com; s=zohoarc; b=ixzJz99rrmhPq1J7yNmdkFEcYSkfsrfoGAs6xTdIwO/EjCeqFrmlYCkOma3z+c2Kdied2EWXeNZuGEZ4msUNy9wFSZBYFXS4nSx+IPhcdBwVxh85ZJ3tHVb6PfrWXBPCBWIi26huwiTbgaTxvGcEzD26oKx/+uqrMptIlgXG2bs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578640103; h=Content-Transfer-Encoding:Cc:Date:From:List-Id:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=5akqJTxkQ0VKhBzX0kPEim2e2jcXQbHK7WsXSL9juvI=; b=K7RKh5IFl/3CbxR9faU6/tZQpxsyv0qkrUfXwOW0H+z6gN3+CSqb97LjiTluRcb1imNNMHMegfeOhR8c+ogWjzuqJGN7aGfyTV5PXtiwx77Kzv7ZGCXqXfkqRkKVqggOcwTnTS8uoTwjFn7kG37/uhZ9nS609xQPoaG8mJLSbSs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.12 as permitted sender) smtp.mailfrom=bounce+27952+53140+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) header.from= Received: from web01.groups.io (web01.groups.io [66.175.222.12]) by mx.zohomail.com with SMTPS id 1578640103234395.8312823316812; Thu, 9 Jan 2020 23:08:23 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id yEoiYY1788612xJ22xBApgDf; Thu, 09 Jan 2020 23:08:22 -0800 X-Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by mx.groups.io with SMTP id smtpd.web12.6970.1578640102385744209 for ; Thu, 09 Jan 2020 23:08:22 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Jan 2020 23:08:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,415,1571727600"; d="scan'208";a="217995000" X-Received: from shwdeopenpsi787.ccr.corp.intel.com ([10.239.158.56]) by fmsmga007.fm.intel.com with ESMTP; 09 Jan 2020 23:08:19 -0800 From: "Siyuan, Fu" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek Subject: [edk2-devel] [Patch] UefiCpuPkg: Add microcode flash address to EDKII microcode patch HOB. Date: Fri, 10 Jan 2020 15:08:17 +0800 Message-Id: <33c518f2a59d52a9c78bf1ed3f96eb5e0195a5ba.1578639982.git.siyuan.fu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,siyuan.fu@intel.com X-Gm-Message-State: eV49Tv2AoQvwusLPdfiIkGugx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1578640102; bh=6pjL3szWZRiE8jmJyiEielHQ1kiPeifkV+bEiMta+8k=; h=Cc:Date:From:Reply-To:Subject:To; b=AdcgUt0w7FaMf+HTCh237/6d0BfH6lNMchAx6CRk1ZPQg0U3gA7iakC9aYwQijp/dzx VG/qdctayXJr996wEaWvhvDJ1+M7EkdrlCK30FVZgox12btso+E8ePgnNE9axcTQdvN9m HhBGxbUpkDTXpPUH1okpxN9W4L43BcdoFHE= X-ZohoMail-DKIM: pass (identity @groups.io) Content-Type: text/plain; charset="utf-8" This patch adds the original microcode flash address to EDKII microcode patch HOB after the microcode loaded by processor. This information can be used to check if a microcode slot has been used by existing processor or not. BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D2454 Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Signed-off-by: Siyuan Fu --- UefiCpuPkg/Include/Guid/MicrocodePatchHob.h | 12 ++++- UefiCpuPkg/Library/MpInitLib/Microcode.c | 24 +++++---- UefiCpuPkg/Library/MpInitLib/MpLib.h | 9 ++++ UefiCpuPkg/Library/MpInitLib/PeiMpLib.c | 54 +++++++++++++++++++-- 4 files changed, 84 insertions(+), 15 deletions(-) diff --git a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h b/UefiCpuPkg/Inclu= de/Guid/MicrocodePatchHob.h index 2d307fbffb..bbf6f2c66b 100644 --- a/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h +++ b/UefiCpuPkg/Include/Guid/MicrocodePatchHob.h @@ -3,7 +3,7 @@ A. Base address and size of the loaded microcode patches data; B. Detected microcode patch for each processor within system. =20 - Copyright (c) 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -38,7 +38,15 @@ typedef struct { // If no microcode patch is detected for certain processor, the relating // element will be set to MAX_UINT64. // - UINT64 ProcessorSpecificPatchOffset[0]; + //UINT64 ProcessorSpecificPatchOffset[]; + // + // An array with 'ProcessorCount' elements that stores the original + // microcode patch address in flash if the patch has been shadowed to + // memory. This address will be the same one as specified by + // "MicrocodePatchAddress" with "PatchOffset" if the patch wasn't + // shadowed to memory. + // + //UINT64 ProcessorSpecificPatchAddrInRom[]; } EDKII_MICROCODE_PATCH_HOB; =20 #endif diff --git a/UefiCpuPkg/Library/MpInitLib/Microcode.c b/UefiCpuPkg/Library/= MpInitLib/Microcode.c index 9389e52ae5..3af5b8495f 100644 --- a/UefiCpuPkg/Library/MpInitLib/Microcode.c +++ b/UefiCpuPkg/Library/MpInitLib/Microcode.c @@ -460,6 +460,7 @@ ShadowMicrocodePatchWorker ( (VOID *) Patches[Index].Address, Patches[Index].Size ); + Patches[Index].AddressInRam =3D (UINTN) Walker; Walker +=3D Patches[Index].Size; } =20 @@ -519,7 +520,7 @@ ShadowMicrocodePatchByPcd ( PatchCount =3D 0; MaxPatchNumber =3D DEFAULT_MAX_MICROCODE_PATCH_NUM; TotalLoadSize =3D 0; - PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + PatchInfoBuffer =3D AllocateZeroPool (MaxPatchNumber * sizeof (MICROCODE= _PATCH_INFO)); if (PatchInfoBuffer =3D=3D NULL) { return; } @@ -563,7 +564,7 @@ ShadowMicrocodePatchByPcd ( // // Overflow check for MaxPatchNumber // - goto OnExit; + goto OnError; } =20 PatchInfoBuffer =3D ReallocatePool ( @@ -572,7 +573,7 @@ ShadowMicrocodePatchByPcd ( PatchInfoBuffer ); if (PatchInfoBuffer =3D=3D NULL) { - goto OnExit; + goto OnError; } MaxPatchNumber =3D MaxPatchNumber * 2; } @@ -581,7 +582,7 @@ ShadowMicrocodePatchByPcd ( // Store the information of this microcode patch // PatchInfoBuffer[PatchCount - 1].Address =3D (UINTN) MicrocodeEntryPo= int; - PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; + PatchInfoBuffer[PatchCount - 1].Size =3D TotalSize; TotalLoadSize +=3D TotalSize; } =20 @@ -601,7 +602,11 @@ ShadowMicrocodePatchByPcd ( ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, To= talLoadSize); } =20 -OnExit: + CpuMpData->PatchCount =3D PatchCount; + CpuMpData->PatchInfoBuffer =3D PatchInfoBuffer; + return; + +OnError: if (PatchInfoBuffer !=3D NULL) { FreePool (PatchInfoBuffer); } @@ -674,7 +679,7 @@ ShadowMicrocodePatchByFit ( return EFI_NOT_FOUND; } =20 - PatchInfoBuffer =3D AllocatePool (MaxPatchNumber * sizeof (MICROCODE_PAT= CH_INFO)); + PatchInfoBuffer =3D AllocateZeroPool (MaxPatchNumber * sizeof (MICROCODE= _PATCH_INFO)); if (PatchInfoBuffer =3D=3D NULL) { return EFI_OUT_OF_RESOURCES; } @@ -689,8 +694,8 @@ ShadowMicrocodePatchByFit ( MicrocodeEntryPoint =3D (CPU_MICROCODE_HEADER *) (UINTN) FitEntry[In= dex].Address; TotalSize =3D (MicrocodeEntryPoint->DataSize =3D=3D 0) ? 2048 : Micr= ocodeEntryPoint->TotalSize; if (IsMicrocodePatchNeedLoad (CpuMpData, MicrocodeEntryPoint)) { - PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntry= Point; - PatchInfoBuffer[PatchCount].Size =3D TotalSize; + PatchInfoBuffer[PatchCount].Address =3D (UINTN) MicrocodeEntryPoin= t; + PatchInfoBuffer[PatchCount].Size =3D TotalSize; TotalLoadSize +=3D TotalSize; PatchCount++; } @@ -707,7 +712,8 @@ ShadowMicrocodePatchByFit ( ShadowMicrocodePatchWorker (CpuMpData, PatchInfoBuffer, PatchCount, To= talLoadSize); } =20 - FreePool (PatchInfoBuffer); + CpuMpData->PatchCount =3D PatchCount; + CpuMpData->PatchInfoBuffer =3D PatchInfoBuffer; return EFI_SUCCESS; } =20 diff --git a/UefiCpuPkg/Library/MpInitLib/MpLib.h b/UefiCpuPkg/Library/MpIn= itLib/MpLib.h index 7c62d75acc..51c71ad38e 100644 --- a/UefiCpuPkg/Library/MpInitLib/MpLib.h +++ b/UefiCpuPkg/Library/MpInitLib/MpLib.h @@ -29,6 +29,8 @@ #include #include =20 +#include + #include =20 =20 @@ -56,6 +58,7 @@ // typedef struct { UINTN Address; + UINTN AddressInRam; UINTN Size; } MICROCODE_PATCH_INFO; =20 @@ -273,6 +276,12 @@ struct _CPU_MP_DATA { // driver. // BOOLEAN WakeUpByInitSipiSipi; + + // + // Shadow infomation of the microcode patch data. + // + UINTN PatchCount; + MICROCODE_PATCH_INFO *PatchInfoBuffer; }; =20 extern EFI_GUID mCpuInitMpLibHobGuid; diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c b/UefiCpuPkg/Library/M= pInitLib/PeiMpLib.c index 06e3f5d0d3..07fc05124c 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpLib.c @@ -1,7 +1,7 @@ /** @file MP initialize support functions for PEI phase. =20 - Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -291,6 +291,40 @@ CheckAndUpdateApsStatus ( { } =20 +/** + Find the corresponding microcode patch address in ROM before the shadow + operation. + + @param[in] CpuMpData Pointer to the CPU_MP_DATA structure. + @param[in] MicrocodeEntryAddr Loaded microcode address to be checked. + + @return Microcode address in ROM, or MAX_UINT64 if this microcode was + not been shadowed. +**/ +UINT64 +RomAddrOfShadowedMicrocode ( + IN CPU_MP_DATA *CpuMpData, + IN UINT64 MicrocodeEntryAddr + ) +{ + UINT32 Index; + + if (CpuMpData->PatchInfoBuffer =3D=3D NULL) { + // + // No shadow. + // + return MicrocodeEntryAddr; + } + + for (Index =3D 0; Index < CpuMpData->PatchCount; Index++) { + if (CpuMpData->PatchInfoBuffer[Index].AddressInRam =3D=3D MicrocodeEnt= ryAddr) { + return CpuMpData->PatchInfoBuffer[Index].Address; + } + } + + return MicrocodeEntryAddr; +} + /** Build the microcode patch HOB that contains the base address and size of= the microcode patch stored in the memory. @@ -306,8 +340,11 @@ BuildMicrocodeCacheHob ( EDKII_MICROCODE_PATCH_HOB *MicrocodeHob; UINTN HobDataLength; UINT32 Index; + UINT64 *ProcessorSpecificPatchOffset; + UINT64 *ProcessorSpecificPatchAddrInRom; =20 HobDataLength =3D sizeof (EDKII_MICROCODE_PATCH_HOB) + + sizeof (UINT64) * CpuMpData->CpuCount + sizeof (UINT64) * CpuMpData->CpuCount; =20 MicrocodeHob =3D AllocatePool (HobDataLength); @@ -317,10 +354,14 @@ BuildMicrocodeCacheHob ( } =20 // - // Store the information of the memory region that holds the microcode p= atches. + // Store information of the memory region that holds the microcode patch= es. // MicrocodeHob->MicrocodePatchAddress =3D CpuMpData->MicrocodePatchAddr= ess; MicrocodeHob->MicrocodePatchRegionSize =3D CpuMpData->MicrocodePatchRegi= onSize; + ProcessorSpecificPatchOffset =3D + (UINT64*) ((UINTN )MicrocodeHob + sizeof (EDKII_MICROCODE_PATCH_HOB)); + ProcessorSpecificPatchAddrInRom =3D + (UINT64*) ((UINTN )ProcessorSpecificPatchOffset + sizeof (UINT64) * Cp= uMpData->CpuCount); =20 // // Store the detected microcode patch for each processor as well. @@ -328,10 +369,15 @@ BuildMicrocodeCacheHob ( MicrocodeHob->ProcessorCount =3D CpuMpData->CpuCount; for (Index =3D 0; Index < CpuMpData->CpuCount; Index++) { if (CpuMpData->CpuData[Index].MicrocodeEntryAddr !=3D 0) { - MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D + ProcessorSpecificPatchOffset[Index] =3D CpuMpData->CpuData[Index].MicrocodeEntryAddr - CpuMpData->Microcod= ePatchAddress; + ProcessorSpecificPatchAddrInRom[Index] =3D RomAddrOfShadowedMicrocod= e ( + CpuMpData, + CpuMpData->CpuData[Index]= .MicrocodeEntryAddr + ); } else { - MicrocodeHob->ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; + ProcessorSpecificPatchOffset[Index] =3D MAX_UINT64; + ProcessorSpecificPatchAddrInRom[Index] =3D MAX_UINT64; } } =20 --=20 2.19.1.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#53140): https://edk2.groups.io/g/devel/message/53140 Mute This Topic: https://groups.io/mt/69596254/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-