From nobody Mon Feb 9 10:50:11 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+84718+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84718+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1639400284; cv=none; d=zohomail.com; s=zohoarc; b=Nyn6Pbkiu6R0/Bnw9yk8ZQ9K5iZdhdebpg7ZydkodGlf70Pgk16/BLP9JDuYiRvwhx/QJyQNmXSKYmRXolJjS0jSX0F/aHuZnH1MpF37fNU89ckTSRK75bik701G6bizoPNpJvSs35xr/38RXjH9SkPGqpd0aOzfc068C6qrssg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1639400284; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=AsakmNmlFXD0xyG7rgJK52zmH8cj4ds8a7BobDfQ8aE=; b=fyzwtHfhRgy1u3g4l9CPpVlQ8Ae6aljOTnmxsu/LvvHjIWo/rsdLi55ZEwpZLsMwlRTIeB8tJ+Dy6K+mkro9dscEVE6ZM/ef7acz9/lMv18MyQlVM/gYMTvU7G6z8zXE5h1v/ImHUwy0674/Rh8esQMzBAMjrIxA8ozvwEWGuzA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+84718+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1639400284740536.0542487196802; Mon, 13 Dec 2021 04:58:04 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id sTCbYY1788612xrdBSQ0H2kg; Mon, 13 Dec 2021 04:58:04 -0800 X-Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web10.10693.1639400242692099801 for ; Mon, 13 Dec 2021 04:58:04 -0800 X-IronPort-AV: E=McAfee;i="6200,9189,10196"; a="238669395" X-IronPort-AV: E=Sophos;i="5.88,202,1635231600"; d="scan'208";a="238669395" X-Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2021 04:58:03 -0800 X-IronPort-AV: E=Sophos;i="5.88,202,1635231600"; d="scan'208";a="517738478" X-Received: from mxu9-mobl1.ccr.corp.intel.com ([10.249.173.142]) by orsmga008-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Dec 2021 04:57:59 -0800 From: "Min Xu" To: devel@edk2.groups.io Cc: Min Xu , Eric Dong , Ray Ni , Rahul Kumar , Brijesh Singh , Erdem Aktas , James Bottomley , Jiewen Yao , Tom Lendacky , Gerd Hoffmann Subject: [edk2-devel] [PATCH V4 11/31] UefiCpuPkg: Support TDX in BaseXApicX2ApicLib Date: Mon, 13 Dec 2021 20:56:42 +0800 Message-Id: <33a01241acd8f1f251dd8cf4a69f5d4c3e2d1551.1639399598.git.min.m.xu@intel.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,min.m.xu@intel.com X-Gm-Message-State: fMKN7XNGzdM34AgUmol5dpF9x1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1639400284; bh=hiVa2P2u/Xp62iduHlGJ4IfM8poJ1+syE9RGJnCGvZQ=; h=Cc:Date:From:Reply-To:Subject:To; b=M/4zsONVAQswS7plMrpxcUiWSqQbsxI9CTLatWkXa+Jguk++QYqnSwu7bln0jFBDdPP dDSFLuAdw3u3J+EYI/yTOHLBvk72z5x0urPfiFoMCzotOSSZhfI9ZBn0du96DKMzW9Jz3 OHPNtk3egRnauq2KNq1xPHi+CFvlyh/8xyg= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1639400286463100002 Content-Type: text/plain; charset="utf-8" RFC: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3429 MSR is accessed in BaseXApicX2ApicLib. In TDX some MSRs are accessed directly from/to CPU. Some should be accessed via explicit requests from the host VMM using TDCALL(TDG.VP.VMCALL). This is done by the help of TdxLib. Please refer to [TDX] Section 18.1 TDX: https://software.intel.com/content/dam/develop/external/us/en/ documents/tdx-module-1.0-public-spec-v0.931.pdf Cc: Eric Dong Cc: Ray Ni Cc: Rahul Kumar Cc: Brijesh Singh Cc: Erdem Aktas Cc: James Bottomley Cc: Jiewen Yao Cc: Tom Lendacky Cc: Gerd Hoffmann Acked-by: Gerd Hoffmann Signed-off-by: Min Xu --- .../BaseXApicX2ApicLib/BaseXApicX2ApicLib.c | 160 +++++++++++++++++- 1 file changed, 152 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/U= efiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c index aaa42ff8450b..2d17177df12b 100644 --- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c +++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c @@ -23,11 +23,155 @@ #include #include #include +#include =20 // // Library internal functions // =20 +/** + Some MSRs in TDX are accessed via TdCall. + Some are directly read/write from/to CPU. + + @param MsrIndex Index of the MSR + @retval TRUE MSR accessed via TdCall. + @retval FALSE MSR accessed not via TdCall. + +**/ +BOOLEAN +AccessMsrTdxCall ( + IN UINT32 MsrIndex + ) +{ + if (!TdIsEnabled ()) { + return FALSE; + } + + switch (MsrIndex) { + case MSR_IA32_X2APIC_TPR: + case MSR_IA32_X2APIC_PPR: + case MSR_IA32_X2APIC_EOI: + case MSR_IA32_X2APIC_ISR0: + case MSR_IA32_X2APIC_ISR1: + case MSR_IA32_X2APIC_ISR2: + case MSR_IA32_X2APIC_ISR3: + case MSR_IA32_X2APIC_ISR4: + case MSR_IA32_X2APIC_ISR5: + case MSR_IA32_X2APIC_ISR6: + case MSR_IA32_X2APIC_ISR7: + case MSR_IA32_X2APIC_TMR0: + case MSR_IA32_X2APIC_TMR1: + case MSR_IA32_X2APIC_TMR2: + case MSR_IA32_X2APIC_TMR3: + case MSR_IA32_X2APIC_TMR4: + case MSR_IA32_X2APIC_TMR5: + case MSR_IA32_X2APIC_TMR6: + case MSR_IA32_X2APIC_TMR7: + case MSR_IA32_X2APIC_IRR0: + case MSR_IA32_X2APIC_IRR1: + case MSR_IA32_X2APIC_IRR2: + case MSR_IA32_X2APIC_IRR3: + case MSR_IA32_X2APIC_IRR4: + case MSR_IA32_X2APIC_IRR5: + case MSR_IA32_X2APIC_IRR6: + case MSR_IA32_X2APIC_IRR7: + return FALSE; + default: + break; + } + + return TRUE; +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 64-bit Value of MSR. + +**/ +UINT64 +LocalApicReadMsrReg64 ( + IN UINT32 MsrIndex + ) +{ + UINT64 Val; + UINT64 Status; + + if (AccessMsrTdxCall (MsrIndex)) { + Status =3D TdVmCall (TDVMCALL_RDMSR, (UINT64)MsrIndex, 0, 0, 0, &Val); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + Val =3D AsmReadMsr64 (MsrIndex); + } + + return Val; +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Value Value to be written to the MSR + + @return Value + +**/ +UINT64 +LocalApicWriteMsrReg64 ( + IN UINT32 MsrIndex, + IN UINT64 Value + ) +{ + UINT64 Status; + + if (AccessMsrTdxCall (MsrIndex)) { + Status =3D TdVmCall (TDVMCALL_WRMSR, (UINT64)MsrIndex, Value, 0, 0, 0); + if (Status !=3D 0) { + TdVmCall (TDVMCALL_HALT, 0, 0, 0, 0, 0); + } + } else { + AsmWriteMsr64 (MsrIndex, Value); + } + + return Value; +} + +/** + Read MSR value. + + @param MsrIndex Index of the MSR to read + @retval 32-bit Value of MSR. + +**/ +UINT32 +LocalApicReadMsrReg32 ( + IN UINT32 MsrIndex + ) +{ + return (UINT32)LocalApicReadMsrReg64 (MsrIndex); +} + +/** + Write to MSR. + + @param MsrIndex Index of the MSR to write to + @param Value Value to be written to the MSR + + @return Value + +**/ +UINT32 +LocalApicWriteMsrReg32 ( + IN UINT32 MsrIndex, + IN UINT32 Value + ) +{ + return (UINT32)LocalApicWriteMsrReg64 (MsrIndex, Value); +} + /** Determine if the CPU supports the Local APIC Base Address MSR. =20 @@ -78,7 +222,7 @@ GetLocalApicBaseAddress ( return PcdGet32 (PcdCpuLocalApicBaseAddress); } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); =20 return (UINTN)(LShiftU64 ((UINT64)ApicBaseMsr.Bits.ApicBaseHi, 32)) + (((UINTN)ApicBaseMsr.Bits.ApicBase) << 12); @@ -109,12 +253,12 @@ SetLocalApicBaseAddress ( return; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); =20 ApicBaseMsr.Bits.ApicBase =3D (UINT32)(BaseAddress >> 12); ApicBaseMsr.Bits.ApicBaseHi =3D (UINT32)(RShiftU64 ((UINT64)BaseAddress,= 32)); =20 - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); } =20 /** @@ -154,7 +298,7 @@ ReadLocalApicReg ( ASSERT (MmioOffset !=3D XAPIC_ICR_HIGH_OFFSET); =20 MsrIndex =3D (UINT32)(MmioOffset >> 4) + X2APIC_MSR_BASE_ADDRESS; - return AsmReadMsr32 (MsrIndex); + return LocalApicReadMsrReg32 (MsrIndex); } } =20 @@ -203,7 +347,7 @@ WriteLocalApicReg ( // Use memory fence here to force the serializing semantics to be cons= isent with xAPIC mode. // MemoryFence (); - AsmWriteMsr32 (MsrIndex, Value); + LocalApicWriteMsrReg32 (MsrIndex, Value); } } =20 @@ -309,7 +453,7 @@ GetApicMode ( return LOCAL_APIC_MODE_XAPIC; } =20 - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BASE); // // Local APIC should have been enabled // @@ -354,9 +498,9 @@ SetApicMode ( case LOCAL_APIC_MODE_XAPIC: break; case LOCAL_APIC_MODE_X2APIC: - ApicBaseMsr.Uint64 =3D AsmReadMsr64 (MSR_IA32_APIC_BASE); + ApicBaseMsr.Uint64 =3D LocalApicReadMsrReg64 (MSR_IA32_APIC_BAS= E); ApicBaseMsr.Bits.EXTD =3D 1; - AsmWriteMsr64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); + LocalApicWriteMsrReg64 (MSR_IA32_APIC_BASE, ApicBaseMsr.Uint64); break; default: ASSERT (FALSE); --=20 2.29.2.windows.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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