From nobody Sun Feb 8 14:07:05 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+88390+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88390+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1649045681; cv=none; d=zohomail.com; s=zohoarc; b=PCqM4AbozGC2XrP701Khob8wV2yUANMZFB/YnMxuIK2wgJSabMprfY0EG+sVg+0ajrlj8a3YBmhvAjL11Fh7MZz4zA7l/lkBrTtGuYE8+B2KWkreaAdjeIkPBDZF6e/CnaiFpyb5Mm1bQ2IaKMOFaP0H+Iqdm2tVJkXhUXQMltk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649045681; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:Message-ID:Reply-To:References:Sender:Subject:To; bh=vc7jdlNnMtrso4ZADHin4UoEYfz4yfanmNTTUlVPDzw=; b=GykLtpq1FPd+bgghaeuYVrR7Qo4zVV4R8qwhtDCKhNrQCGRUDQVnzlya1JS2oIb24/UUvFbwXiCWEYa1V6LLGwaHAUAXX8w8PX+DouYRtRCIYUyoSvjcPmtFhlarEoOj2yhM33ESmmJr053766pI88hsfiKL6jREERPynjvw0LA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+88390+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1649045681546232.71801107677243; Sun, 3 Apr 2022 21:14:41 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 6lzwYY1788612xnHbj4iPMQE; Sun, 03 Apr 2022 21:14:40 -0700 X-Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by mx.groups.io with SMTP id smtpd.web08.31244.1649045679565934493 for ; Sun, 03 Apr 2022 21:14:40 -0700 X-IronPort-AV: E=McAfee;i="6200,9189,10306"; a="258015856" X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="258015856" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 21:14:39 -0700 X-IronPort-AV: E=Sophos;i="5.90,233,1643702400"; d="scan'208";a="696444584" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Apr 2022 21:14:38 -0700 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel][PATCH 3/5] IntelFsp2Pkg: Update FSP_GLOBAL_DATA and FSP_PLAT_DATA for X64 Date: Mon, 4 Apr 2022 12:13:58 +0800 Message-Id: <2a584ced41f2d4157674e7748edcdb257d3e42a0.1649045384.git.ted.kuo@intel.com> In-Reply-To: References: In-Reply-To: References: Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: XiF9WEhOTHAbmp84mPo4ivP2x1787277AA= DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1649045680; bh=VQYRNssGK1vsufMW5aAHyegrYUoKZRtU+wCFCvsVXBI=; h=Cc:Date:From:Reply-To:Subject:To; b=BULF7B4R8eY5UBIpafiyLnsbE+k2/jkEFXYAWI/VnUNlRtn6Xpgnuxe8Q7Rj7egq8je Pcp6HT7aCJL7fVPPe+x3RRdDk+xFGSjs9U5KsE5JlGjjjm83vMyfrnI9Su6qnEE8Oj81W aMI/wPiEsAvXc14T2N0oVLLLEzQVcHXBFME= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1649046583496100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3893 Updated FSP_GLOBAL_DATA and FSP_PLAT_DATA structures to support both IA32 and X64. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/SecFsp.c | 2 +- IntelFsp2Pkg/Include/FspGlobalData.h | 51 +++++++++++++++++++++++++-------= ---- 2 files changed, 37 insertions(+), 16 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.c b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.c index 85fbc7664c..1ead3c9ce6 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.c +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.c @@ -130,7 +130,7 @@ FspGlobalDataInit ( ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA)); =20 PeiFspData->Signature =3D FSP_GLOBAL_DATA_SIGNATURE; - PeiFspData->Version =3D 0; + PeiFspData->Version =3D FSP_GLOBAL_DATA_VERSION; PeiFspData->CoreStack =3D BootLoaderStack; PeiFspData->PerfIdx =3D 2; PeiFspData->PerfSig =3D FSP_PERFORMANCE_DATA_SIGNATURE; diff --git a/IntelFsp2Pkg/Include/FspGlobalData.h b/IntelFsp2Pkg/Include/Fs= pGlobalData.h index 2b534075ae..dcfeed7501 100644 --- a/IntelFsp2Pkg/Include/FspGlobalData.h +++ b/IntelFsp2Pkg/Include/FspGlobalData.h @@ -10,8 +10,9 @@ =20 #include =20 -#define FSP_IN_API_MODE 0 -#define FSP_IN_DISPATCH_MODE 1 +#define FSP_IN_API_MODE 0 +#define FSP_IN_DISPATCH_MODE 1 +#define FSP_GLOBAL_DATA_VERSION 1 =20 #pragma pack(1) =20 @@ -28,10 +29,11 @@ typedef enum { =20 typedef struct { VOID *DataPtr; - UINT32 MicrocodeRegionBase; - UINT32 MicrocodeRegionSize; - UINT32 CodeRegionBase; - UINT32 CodeRegionSize; + UINTN MicrocodeRegionBase; + UINTN MicrocodeRegionSize; + UINTN CodeRegionBase; + UINTN CodeRegionSize; + UINTN Reserved; } FSP_PLAT_DATA; =20 #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D') @@ -42,15 +44,15 @@ typedef struct { UINT32 Signature; UINT8 Version; UINT8 Reserved1[3]; + /// + /// Offset 0x08 + /// UINTN CoreStack; + UINTN Reserved2; + /// + /// IA32: Offset 0x10; X64: Offset 0x18 + /// UINT32 StatusCode; - UINT32 Reserved2[8]; - FSP_PLAT_DATA PlatformData; - FSP_INFO_HEADER *FspInfoHeader; - VOID *UpdDataPtr; - VOID *TempRamInitUpdPtr; - VOID *MemoryInitUpdPtr; - VOID *SiliconInitUpdPtr; UINT8 ApiIdx; /// /// 0: FSP in API mode; 1: FSP in DISPATCH mode @@ -60,15 +62,34 @@ typedef struct { UINT8 Reserved3; UINT32 NumberOfPhases; UINT32 PhasesExecuted; + UINT32 Reserved4[8]; /// + /// IA32: Offset 0x40; X64: Offset 0x48 + /// Start of UINTN and pointer section + /// All UINTN and pointer members must be put in this section + /// except CoreStack and Reserved2. In addition, the number of + /// UINTN and pointer members must be even for natural alignment + /// in both IA32 and X64. + /// + FSP_PLAT_DATA PlatformData; + VOID *TempRamInitUpdPtr; + VOID *MemoryInitUpdPtr; + VOID *SiliconInitUpdPtr; + /// + /// IA32: Offset 0x64; X64: Offset 0x90 /// To store function parameters pointer /// so it can be retrieved after stack switched. /// VOID *FunctionParameterPtr; - UINT8 Reserved4[16]; + FSP_INFO_HEADER *FspInfoHeader; + VOID *UpdDataPtr; + /// + /// End of UINTN and pointer section + /// + UINT8 Reserved5[16]; UINT32 PerfSig; UINT16 PerfLen; - UINT16 Reserved5; + UINT16 Reserved6; UINT32 PerfIdx; UINT64 PerfData[32]; } FSP_GLOBAL_DATA; --=20 2.16.2.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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