From nobody Wed May 8 08:25:52 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+96024+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+96024+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1667810640; cv=none; d=zohomail.com; s=zohoarc; b=E9l/i1u9PQbYRmJAYzUGhLFbRzJasNUrDDUnqo8ILAP1C6r+/JpT8Gnde8DeoZNmew4vWYuBc1knwuuYs8Ijrj6UBWY0VmHFG2gK0rfZMo1TLs9pNu48x7F+KeorN4+6RG36Rvpl/pc7A7Vi9gFdBjb8F9t/ZsXOhvtA0VpwDGQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1667810640; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=YESuuJh6rADenlJ/Hv+Y9SkOuiEGeUC8zX7yLW3UHXg=; b=NArkTXD0aLGpCZ058alRHnNxN6LuTvHjZI28QYMF5S36sxu0kIIS8MC3ItIg9pesrRQVU6lf5qm7ydjNwWdwcSbDklnIPE97wxOv9yk2iw6DpeuZpfUUDZQpgwxuBZXh8qWW1NmqrY0ZLK+Y9pgTAqD6ZmSPrHCy7YEWJAYkjkg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+96024+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 166781064056087.18401920034194; Mon, 7 Nov 2022 00:44:00 -0800 (PST) Return-Path: X-Received: by 127.0.0.2 with SMTP id tbDsYY1788612xH2wmz9sgyE; Mon, 07 Nov 2022 00:44:00 -0800 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.1226.1667810639235532695 for ; Mon, 07 Nov 2022 00:43:59 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="374612396" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="374612396" X-Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 00:43:58 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="778406228" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="778406228" X-Received: from tedkuo1-win10.gar.corp.intel.com ([10.5.215.13]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Nov 2022 00:43:56 -0800 From: "Kuo, Ted" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S , Chinni B Duggapu , Amy Chan Subject: [edk2-devel][PATCH v1] IntelFsp2Pkg: Adding FspHelperLib Date: Mon, 7 Nov 2022 16:43:30 +0800 Message-Id: <28da0d3ce6289e39e542990fdabd3002a4c665a2.1667810598.git.ted.kuo@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,ted.kuo@intel.com X-Gm-Message-State: 0xWA2lp0GiloAdFvJEFePw4qx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1667810640; bh=0XEGdbWo66GRGjnGJs4maHcmoDyFrv2RjXCUUIy92DM=; h=Cc:Date:From:Reply-To:Subject:To; b=mf931wDce9cBJBIoHryXSNy1XdtMaEMu3J7UrnoWPWvQ9e9gVQ8qd8eNjew20rb9iyg X7bqEuCdc1/Z5F6nDAUsoA2qmUDqy6DDlhHdNGEnBZg6GVOcuUrL32dySc9u8tQM6eUC4 Dp+wHFWP1cDQNogmh/UWKiglUMDIWmOR6ZU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1667810642364100001 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D4128 Adding FspHelperLib for platform code to consume. There will be another patch raised later for FspSecCore to consume FspHelperLib. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Cc: Chinni B Duggapu Cc: Amy Chan Signed-off-by: Ted Kuo --- IntelFsp2Pkg/FspSecCore/SecFsp.h | 25 +--------- IntelFsp2Pkg/Include/Library/FspHelperLib.h | 35 +++++++++++++ IntelFsp2Pkg/IntelFsp2Pkg.dsc | 2 + .../BaseFspHelperLib/BaseFspHelperLib.inf | 50 +++++++++++++++++++ .../BaseFspHelperLib/Ia32/FspHelper.nasm | 35 +++++++++++++ .../BaseFspHelperLib/X64/FspHelper.nasm | 34 +++++++++++++ 6 files changed, 157 insertions(+), 24 deletions(-) create mode 100644 IntelFsp2Pkg/Include/Library/FspHelperLib.h create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.= inf create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.na= sm create mode 100644 IntelFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm diff --git a/IntelFsp2Pkg/FspSecCore/SecFsp.h b/IntelFsp2Pkg/FspSecCore/Sec= Fsp.h index d7a5976c12..f12769890f 100644 --- a/IntelFsp2Pkg/FspSecCore/SecFsp.h +++ b/IntelFsp2Pkg/FspSecCore/SecFsp.h @@ -17,6 +17,7 @@ #include #include #include +#include =20 #define FSP_MCUD_SIGNATURE SIGNATURE_32 ('M', 'C', 'U', 'D') #define FSP_PER0_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', '0') @@ -64,28 +65,4 @@ FspDataPointerFixUp ( IN UINTN OffsetGap ); =20 -/** - This interface returns the base address of FSP binary. - - @return FSP binary base address. - -**/ -UINTN -EFIAPI -AsmGetFspBaseAddress ( - VOID - ); - -/** - This interface gets FspInfoHeader pointer - - @return FSP binary base address. - -**/ -UINTN -EFIAPI -AsmGetFspInfoHeader ( - VOID - ); - #endif diff --git a/IntelFsp2Pkg/Include/Library/FspHelperLib.h b/IntelFsp2Pkg/Inc= lude/Library/FspHelperLib.h new file mode 100644 index 0000000000..84b74fa7aa --- /dev/null +++ b/IntelFsp2Pkg/Include/Library/FspHelperLib.h @@ -0,0 +1,35 @@ +/** @file + Header file for FSP Helper Library. + + Copyright (c) 2022, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef _FSP_HELPER_LIB_H_ +#define _FSP_HELPER_LIB_H_ + +/** + This interface returns the base address of FSP binary. + + @return FSP binary base address. + +**/ +UINTN +EFIAPI +AsmGetFspBaseAddress ( + VOID + ); + +/** + This interface gets FspInfoHeader pointer + + @return FSP info header. +**/ +UINTN +EFIAPI +AsmGetFspInfoHeader ( + VOID + ); + +#endif // _FSP_HELPER_LIB_H_ diff --git a/IntelFsp2Pkg/IntelFsp2Pkg.dsc b/IntelFsp2Pkg/IntelFsp2Pkg.dsc index 0713f0028d..09893d70e8 100644 --- a/IntelFsp2Pkg/IntelFsp2Pkg.dsc +++ b/IntelFsp2Pkg/IntelFsp2Pkg.dsc @@ -46,6 +46,7 @@ FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwit= chStackLib.inf FspSecPlatformLib|IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSe= cPlatformLibNull.inf FspMultiPhaseLib|IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiP= haseLib.inf + FspHelperLib|IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf =20 [LibraryClasses.common.PEIM] PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf @@ -66,6 +67,7 @@ IntelFsp2Pkg/Library/BaseDebugDeviceLibNull/BaseDebugDeviceLibNull.inf IntelFsp2Pkg/Library/SecFspSecPlatformLibNull/SecFspSecPlatformLibNull.i= nf IntelFsp2Pkg/Library/BaseFspMultiPhaseLib/BaseFspMultiPhaseLib.inf + IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf =20 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf diff --git a/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf b/I= ntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf new file mode 100644 index 0000000000..318ad65330 --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspHelperLib/BaseFspHelperLib.inf @@ -0,0 +1,50 @@ +## @file +# FSP Helper Library. +# +# Copyright (c) 2022, Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +##########################################################################= ###### +# +# Defines Section - statements that will be processed to create a Makefile. +# +##########################################################################= ###### + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D FspHelperLib + FILE_GUID =3D 65746991-8a41-4b89-b0f4-eb4e24b5b471 + MODULE_TYPE =3D BASE + VERSION_STRING =3D 1.0 + LIBRARY_CLASS =3D FspHelperLib + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 +# + +##########################################################################= ###### +# +# Sources Section - list of files that are required for the build to succe= ed. +# +##########################################################################= ###### + +[Sources.IA32] + Ia32/FspHelper.nasm + +[Sources.X64] + X64/FspHelper.nasm + +##########################################################################= ###### +# +# Package Dependency Section - list of Package files that are required for +# this module. +# +##########################################################################= ###### + +[Packages] + MdePkg/MdePkg.dec diff --git a/IntelFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.nasm b/In= telFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.nasm new file mode 100644 index 0000000000..e3e1945473 --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspHelperLib/Ia32/FspHelper.nasm @@ -0,0 +1,35 @@ +;; @file +; Provide FSP helper function. +; +; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + + SECTION .text + +global ASM_PFX(FspInfoHeaderRelativeOff) +ASM_PFX(FspInfoHeaderRelativeOff): + DD 0x12345678 ; This value must be patched by the buil= d script + +global ASM_PFX(AsmGetFspBaseAddress) +ASM_PFX(AsmGetFspBaseAddress): + call ASM_PFX(AsmGetFspInfoHeader) + add eax, 0x1C + mov eax, dword [eax] + ret + +global ASM_PFX(AsmGetFspInfoHeader) +ASM_PFX(AsmGetFspInfoHeader): + call ASM_PFX(NextInstruction) +ASM_PFX(NextInstruction): + pop eax + sub eax, ASM_PFX(NextInstruction) + add eax, ASM_PFX(AsmGetFspInfoHeader) + sub eax, dword [eax - ASM_PFX(AsmGetFspInfoHeader) + ASM_PFX(FspInfoH= eaderRelativeOff)] + ret + +global ASM_PFX(AsmGetFspInfoHeaderNoStack) +ASM_PFX(AsmGetFspInfoHeaderNoStack): + mov eax, ASM_PFX(AsmGetFspInfoHeader) + sub eax, dword [ASM_PFX(FspInfoHeaderRelativeOff)] + jmp edi diff --git a/IntelFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm b/Int= elFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm new file mode 100644 index 0000000000..122fa1d174 --- /dev/null +++ b/IntelFsp2Pkg/Library/BaseFspHelperLib/X64/FspHelper.nasm @@ -0,0 +1,34 @@ +;; @file +; Provide FSP helper function. +; +; Copyright (c) 2022, Intel Corporation. All rights reserved.
+; SPDX-License-Identifier: BSD-2-Clause-Patent +;; + DEFAULT REL + SECTION .text + +global ASM_PFX(AsmGetFspBaseAddress) +ASM_PFX(AsmGetFspBaseAddress): + call ASM_PFX(AsmGetFspInfoHeader) + add rax, 0x1C + mov eax, [rax] + ret + +global ASM_PFX(AsmGetFspInfoHeader) +ASM_PFX(AsmGetFspInfoHeader): + lea rax, [ASM_PFX(AsmGetFspInfoHeader)] + DB 0x48, 0x2d ; sub rax, 0x???????? +global ASM_PFX(FspInfoHeaderRelativeOff) +ASM_PFX(FspInfoHeaderRelativeOff): + DD 0x12345678 ; This value must be patched by the buil= d script + and rax, 0xffffffff + ret + +global ASM_PFX(AsmGetFspInfoHeaderNoStack) +ASM_PFX(AsmGetFspInfoHeaderNoStack): + lea rax, [ASM_PFX(AsmGetFspInfoHeader)] + lea rcx, [ASM_PFX(FspInfoHeaderRelativeOff)] + mov ecx, [rcx] + sub rax, rcx + and rax, 0xffffffff + jmp rdi --=20 2.35.3.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#96024): https://edk2.groups.io/g/devel/message/96024 Mute This Topic: https://groups.io/mt/94862155/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-