From nobody Sat May 4 20:29:51 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+89763+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89763+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1652698455; cv=none; d=zohomail.com; s=zohoarc; b=jkINJ+cs71crxZu/57PnqpPQCtm+vhJ8mkG7F4YXjxPComZ6AwiqPAkBN5L6Vqg3ayh2Onk6ZKYnMa7xzL/4AqKu1QEEURuyh74qv+DLivU2zMFnMaK6fTod+9lKMBekYNknT3YANbW2zO0lagkHOK4mQqg0w6MozO7KTqKNxBk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652698455; h=Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:Sender:Subject:To; bh=2fcDlLvZ50Fn71KWkyNGKqWOCRQnvVFQCO19icsc0Ho=; b=VNpDxG5K8hgsB66iCGFFDPA1YMOtc60JposaIkIN8m+g2+Kb7Q9KIVGNAPIKWOsokfvsdwmKNhHFYNyIZnJ50wMyfr6o321HoLnwiWpPc+CoQr+WuqXkrgmcP9xwbSmYS4+6fZ0xqeNGRNfmtmNDM49LwHZPSw9jufmZjKN4YCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+89763+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1652698455276639.0331745438639; Mon, 16 May 2022 03:54:15 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id 3MV8YY1788612xLHfPAKxta4; Mon, 16 May 2022 03:54:14 -0700 X-Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by mx.groups.io with SMTP id smtpd.web08.27199.1652698453329994886 for ; Mon, 16 May 2022 03:54:13 -0700 X-IronPort-AV: E=McAfee;i="6400,9594,10348"; a="333854180" X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="333854180" X-Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 03:54:04 -0700 X-IronPort-AV: E=Sophos;i="5.91,229,1647327600"; d="scan'208";a="555196386" X-Received: from cbduggap-mobl1.gar.corp.intel.com ([10.215.115.78]) by orsmga002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 May 2022 03:54:02 -0700 From: "cbduggap" To: devel@edk2.groups.io Cc: Chasel Chiu , Nate DeSimone , Star Zeng , Ashraf Ali S Subject: [edk2-devel] [PATCH v3] IntelFsp2Pkg: FSP_TEMP_RAM_INIT call must follow X64 Calling Convention Date: Mon, 16 May 2022 16:23:42 +0530 Message-Id: <254311d0ac264a325dfe65d7c3b47950c374a604.1652698395.git.chinni.b.duggapu@intel.com> MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,chinni.b.duggapu@intel.com X-Gm-Message-State: IpqlkpdXSuEOgZbFSrcZX0pFx1787277AA= Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1652698454; bh=g9XI/sBoCJ/fUrQinUXLjYTXqcUlSBwBEvkgmmOv5Xg=; h=Cc:Date:From:Reply-To:Subject:To; b=wBne+G/gQ6oMeXak4ZlYA3u6VQbPaCPLs4FLwXsO6dxTUEJwGOsi6HMs9fK9iVnraxG nZvyMtFGuGHqe2O7T3GBWNpbLO27byxHeN1SJCyBZ8VlowDdHlFJUATk4lWImK6zkKu71 XvGDkf+Gp23iiwwIdnbDri2LEanWUUjObjQ= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1652698457456100003 Content-Type: text/plain; charset="utf-8" REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3926 This API accept one parameter using RCX and this is consumed in mutiple sub functions. Cc: Chasel Chiu Cc: Nate DeSimone Cc: Star Zeng Cc: Ashraf Ali S Signed-off-by: cbduggap --- IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm | 26 ++++++++--------- .../Include/SaveRestoreSseAvxNasm.inc | 28 +++++++++++++++++++ 2 files changed, 41 insertions(+), 13 deletions(-) diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/F= spSecCore/X64/FspApiEntryT.nasm index a9f5f28ed7..9504c96b81 100644 --- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm +++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm @@ -114,7 +114,7 @@ endstruc global ASM_PFX(LoadMicrocodeDefault) ASM_PFX(LoadMicrocodeDefault): ; Inputs: - ; rsp -> LoadMicrocodeParams pointer + ; rcx -> LoadMicrocodeParams pointer ; Register Usage: ; rsp Preserved ; All others destroyed @@ -130,10 +130,9 @@ ASM_PFX(LoadMicrocodeDefault): =20 cmp rsp, 0 jz ParamError - mov eax, dword [rsp + 8] ; Parameter pointer - cmp eax, 0 + cmp ecx, 0 jz ParamError - mov esp, eax + mov esp, ecx =20 ; skip loading Microcode if the MicrocodeCodeSize is zero ; and report error if size is less than 2k @@ -321,8 +320,7 @@ ASM_PFX(EstablishStackFsp): ; ; Save parameter pointer in rdx ; - mov rdx, qword [rsp + 8] - + mov rdx, rcx ; ; Enable FSP STACK ; @@ -420,7 +418,10 @@ ASM_PFX(TempRamInitApi): ; ENABLE_SSE ENABLE_AVX - + ; + ; Save Input Parameter in YMM10 + ; + SAVE_RCX ; ; Save RBP, RBX, RSI, RDI and RSP in YMM7, YMM8 and YMM6 ; @@ -442,9 +443,8 @@ ASM_PFX(TempRamInitApi): ; ; Check Parameter ; - mov rax, qword [rsp + 8] - cmp rax, 0 - mov rax, 08000000000000002h + cmp rcx, 0 + mov rcx, 08000000000000002h jz TempRamInitExit =20 ; @@ -455,18 +455,18 @@ ASM_PFX(TempRamInitApi): jnz TempRamInitExit =20 ; Load microcode - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(LoadMicrocodeDefault) SAVE_UCODE_STATUS rax ; Save microcode return status in SLOT= 0 in YMM9 (upper 128bits). ; @note If return value rax is not 0, microcode did not load, but contin= ue and attempt to boot. =20 ; Call Sec CAR Init - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(SecCarInit) cmp rax, 0 jnz TempRamInitExit =20 - LOAD_RSP + LOAD_RCX CALL_YMM ASM_PFX(EstablishStackFsp) cmp rax, 0 jnz TempRamInitExit diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index e8bd91669d..38c807a311 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -177,6 +177,30 @@ LXMMN xmm5, %1, 1 %endmacro =20 +; +; Upper half of YMM10 to save/restore RCX +; +; +; Save RCX to YMM10[128:191] +; Modified: XMM5 and YMM10 +; + +%macro SAVE_RCX 0 + LYMMN ymm10, xmm5, 1 + SXMMN xmm5, 0, rcx + SYMMN ymm10, 1, xmm5 + %endmacro + +; +; Restore RCX from YMM10[128:191] +; Modified: XMM5 and RCX +; + +%macro LOAD_RCX 0 + LYMMN ymm10, xmm5, 1 + movq rcx, xmm5 + %endmacro + ; ; YMM7[128:191] for calling stack ; arg 1:Entry @@ -231,6 +255,7 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est ; whether the processor supports SSE instruction. ; + mov r10, rcx mov rax, 1 cpuid bt rdx, 25 @@ -241,6 +266,7 @@ NextAddress: ; bt ecx, 19 jnc SseError + mov rcx, r10 =20 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) @@ -258,6 +284,7 @@ NextAddress: %endmacro =20 %macro ENABLE_AVX 0 + mov r10, rcx mov eax, 1 cpuid and ecx, 10000000h @@ -280,5 +307,6 @@ EnableAvx: xgetbv ; result in edx:eax or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state xsetbv + mov rcx, r10 %endmacro =20 --=20 2.36.0.windows.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#89763): https://edk2.groups.io/g/devel/message/89763 Mute This Topic: https://groups.io/mt/91136907/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-