From nobody Sat Feb 7 05:49:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+92922+1787277+3901457@groups.io; helo=mail02.groups.io; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92922+1787277+3901457@groups.io; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1661805425; cv=none; d=zohomail.com; s=zohoarc; b=ne2RFfbk5u86fEXDxU4/9bSq52n4eRNAcqIkF/1ZYwD0O8k31wfvy1gEdpryMCYmEnwfa391c97o6HZNLCDZFkMVDpW0GvllBwSQdk2nA8xPAQ8kXEZEvgZV9a8VjCPeTfNRnh+kd5Tc7ZBSz8WmIK6Zn3ty0V8WCvbhrYm8Oq8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1661805425; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Id:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=sqZi2rPqxFywukJjQrlm7ak/QkqBUYbVHASXqGLCNqk=; b=AbPI6GckAYPD7PvmsW/ffV7O57a2zrJP4YCV38AF3y4DR7RagGZIYYaLNqxo8s1GAVqg33xuowe7+8CBXcVJLAJMHly6NZelHeX+6gSP8VcPRJVInSsBDod0mJixPqOuDoDkzh/TRuCUlcOqgY81HcjvRMIsUNzflfSkYkU4Ro0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+92922+1787277+3901457@groups.io; dmarc=fail header.from= (p=none dis=none) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1661805425492557.206502923825; Mon, 29 Aug 2022 13:37:05 -0700 (PDT) Return-Path: X-Received: by 127.0.0.2 with SMTP id X8icYY1788612xdOAnNbQ02S; Mon, 29 Aug 2022 13:37:05 -0700 X-Received: from mail-qk1-f180.google.com (mail-qk1-f180.google.com [209.85.222.180]) by mx.groups.io with SMTP id smtpd.web09.3365.1661805424342333299 for ; Mon, 29 Aug 2022 13:37:04 -0700 X-Received: by mail-qk1-f180.google.com with SMTP id f14so7009879qkm.0 for ; Mon, 29 Aug 2022 13:37:04 -0700 (PDT) X-Gm-Message-State: GyH0gMThfi22eYR8jrICr5vjx1787277AA= X-Google-Smtp-Source: AA6agR6q9I89pA3Dq5OCBqY1uJUu+N+cO9ChT/HtQbEoeyYfVLKQcXU4lMWfVlc70kOCxsGVtcUXgw== X-Received: by 2002:a05:620a:408a:b0:6bb:584a:fb49 with SMTP id f10-20020a05620a408a00b006bb584afb49mr9905236qko.468.1661805423114; Mon, 29 Aug 2022 13:37:03 -0700 (PDT) X-Received: from aturtleortwo-benjamindomain.. ([2607:f2c0:e98c:e:da1:4180:8030:1a92]) by smtp.gmail.com with ESMTPSA id bp6-20020a05620a458600b006bbda80595asm6846218qkb.5.2022.08.29.13.37.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 13:37:02 -0700 (PDT) From: "Benjamin Doron" To: devel@edk2.groups.io Cc: Nate DeSimone , Ankit Sinha , Sai Chaganty , Isaac Oram , Liming Gao Subject: [edk2-devel][edk2-platforms][PATCH v1 3/5] S3FeaturePkg: Implement working S3 resume Date: Mon, 29 Aug 2022 16:36:18 -0400 Message-Id: <23fd6d63ba743cfbfa994dda115437719dbc2b4f.1661799519.git.benjamin.doron00@gmail.com> In-Reply-To: References: MIME-Version: 1.0 Precedence: Bulk List-Unsubscribe: List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,benjamin.doron00@gmail.com Content-Transfer-Encoding: quoted-printable DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=groups.io; q=dns/txt; s=20140610; t=1661805425; bh=LDfiHMBLb/2Q1WtO/skG/t8XZpCk2jJhsHjeIjdsZOc=; h=Cc:Date:From:Reply-To:Subject:To; b=JK4j50EyzIFv5Fo8rVEC9cN8kU2671rwnVHcW9/AIc+tk12SZTW6NpkBkmhbV1OgkcX dLZDAWN/O7Ff5HxeboIwk9Wcc9znLKEaj3mpZj9F9TFk13DYMl2Z8y19a7lC+oaIS2sP8 CagajNO6hYk89l9TUkclbovpyRRV0eXIpBU= X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1661805427383100014 Content-Type: text/plain; charset="utf-8" Follow-up commits to MinPlatform (PeiFspWrapperHobProcessLib for memory) and FSP-related board libraries (policy overrides) required for successful S3 resume. Factored allocation logic into new module to avoid MinPlatform dependency on S3Feature package. TODO: Can optimise required size. Cc: Nate DeSimone Cc: Ankit Sinha Cc: Sai Chaganty Cc: Isaac Oram Cc: Liming Gao Signed-off-by: Benjamin Doron --- .../S3FeaturePkg/Include/PostMemory.fdf | 15 ++ .../S3FeaturePkg/Include/PreMemory.fdf | 8 +- .../S3FeaturePkg/Include/S3Feature.dsc | 42 ++++- .../S3FeaturePkg/S3Dxe/S3Dxe.c | 156 ++++++++++++++++++ .../S3FeaturePkg/S3Dxe/S3Dxe.inf | 49 ++++++ .../S3FeaturePkg/S3Pei/S3Pei.c | 83 +++++++++- .../S3FeaturePkg/S3Pei/S3Pei.inf | 8 +- .../Include/AcpiS3MemoryNvData.h | 22 +++ 8 files changed, 375 insertions(+), 8 deletions(-) create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .c create mode 100644 Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe= .inf create mode 100644 Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvDat= a.h diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory= .fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf index 9e17f853c630..5d3d96f4f317 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PostMemory.fdf @@ -2,7 +2,22 @@ # FDF file for post-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +## Dependencies + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + +## Save-state module stack + INF S3FeaturePkg/S3Dxe/S3Dxe.inf + INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + # FSP may perform CPU finalisation, requires CpuInitDxe from closed code + # - Presently, PiSmmCpuDxeSmm shall perform finalisation with this data + INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + +## Restore-state module stack + INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutor= Dxe.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.= fdf b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf index fdd16a4e0356..e130fa5f098d 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/PreMemory.fdf @@ -2,9 +2,15 @@ # FDF file for pre-memory S3 advanced feature modules. # # Copyright (c) 2019, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # ## =20 -INF S3FeaturePkg/S3Pei/S3Pei.inf +## Dependencies + INF S3FeaturePkg/S3Pei/S3Pei.inf + INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + +## Restore-state module stack + INF UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.= dsc b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc index cc34e785076a..bf45b56258ff 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc +++ b/Features/Intel/PowerManagement/S3FeaturePkg/Include/S3Feature.dsc @@ -7,6 +7,7 @@ # for the build infrastructure. # # Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.
+# Copyright (c) 2022, Baruch Binyamin Doron.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -25,6 +26,10 @@ !error "DXE_ARCH must be specified to build this feature!" !endif =20 +[PcdsFixedAtBuild] + # Attempts to improve performance at the cost of more DRAM usage + gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE + ##########################################################################= ###### # # Library Class section - list of all Library Classes needed by this featu= re. @@ -32,7 +37,15 @@ ##########################################################################= ###### =20 [LibraryClasses.common.PEIM] - SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf + #SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLibS= mramc/PeiSmmAccessLib.inf + SmmControlLib|IntelSiliconPkg/Feature/SmmControl/Library/PeiSmmControlLi= b/PeiSmmControlLib.inf + #IntelCompatShimLib|$(PLATFORM_SI_PACKAGE)/Library/BaseIntelCompatShimLi= bKbl/BaseIntelCompatShimLibKbl.inf + +[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_SMM_DRIVER] + ####################################### + # Edk2 Packages + ####################################### + S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScrip= tLib.inf =20 ##########################################################################= ###### # @@ -65,3 +78,30 @@ =20 # Add components here that should be included in the package build. S3FeaturePkg/S3Pei/S3Pei.inf + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf + UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf + +# +# Feature DXE Components +# + +# @todo: Change below line to [Components.$(DXE_ARCH)] after https://bugzi= lla.tianocore.org/show_bug.cgi?id=3D2308 +# is completed. +[Components.X64] + ##################################### + # S3 Feature Package + ##################################### + + # Add library instances here that are not included in package components= and should be tested + # in the package build. + + # Add components here that should be included in the package build. + UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf + MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf + S3FeaturePkg/S3Dxe/S3Dxe.inf + MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf + # NOTE: RSC will be after end-of-BS, use DebugLibSerialPort + # - No gBS in SerialPortInitialize() + # - No global assigns after ReadyToLock possible, due to LockBox copy + MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.= inf diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c new file mode 100644 index 000000000000..b3fb63e2bc33 --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.c @@ -0,0 +1,156 @@ +/** @file + Source code file for S3 DXE module + +Copyright (c) 2022, Baruch Binyamin Doron.
+SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + Get the mem size in memory type infromation table. + + @return the mem size in memory type infromation table. +**/ +UINT64 +EFIAPI +GetMemorySizeInMemoryTypeInformation ( + VOID + ) +{ + EFI_STATUS Status; + EFI_MEMORY_TYPE_INFORMATION *MemoryData; + UINT8 Index; + UINTN TempPageNum; + + Status =3D EfiGetSystemConfigurationTable (&gEfiMemoryTypeInformationGui= d, (VOID **) &MemoryData); + + if (EFI_ERROR (Status) || MemoryData =3D=3D NULL) { + return 0; + } + + TempPageNum =3D 0; + for (Index =3D 0; MemoryData[Index].Type !=3D EfiMaxMemoryType; Index++)= { + // + // Accumulate default memory size requirements + // + TempPageNum +=3D MemoryData[Index].NumberOfPages; + } + + return TempPageNum * EFI_PAGE_SIZE; +} + +/** + Get the mem size need to be consumed and reserved for PEI phase resume. + + @return the mem size to be reserved for PEI phase resume. +**/ +UINT64 +EFIAPI +GetPeiMemSize ( + VOID + ) +{ + #define PEI_ADDITIONAL_MEMORY_SIZE (16 * EFI_PAGE_SIZE) + + UINT64 Size; + + Size =3D GetMemorySizeInMemoryTypeInformation (); + + return PcdGet32 (PcdPeiMinMemSize) + Size + PEI_ADDITIONAL_MEMORY_SIZE; +} + +/** + Allocate EfiACPIMemoryNVS below 4G memory address. + + This function allocates EfiACPIMemoryNVS below 4G memory address. + + @param Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID * +EFIAPI +AllocateAcpiNvsMemoryBelow4G ( + IN UINTN Size + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + VOID *Buffer; + + Pages =3D EFI_SIZE_TO_PAGES (Size); + Address =3D 0xffffffff; + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + ASSERT_EFI_ERROR (Status); + + Buffer =3D (VOID *)(UINTN)Address; + ZeroMem (Buffer, Size); + + return Buffer; +} + +/** + Allocates memory to use on S3 resume. + + @param[in] ImageHandle Not used. + @param[in] SystemTable General purpose services available to e= very DXE driver. + + @retval EFI_SUCCESS The function completes successfully + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create databa= se +**/ +EFI_STATUS +EFIAPI +S3DxeEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + UINT64 S3PeiMemSize; + UINT64 S3PeiMemBase; + ACPI_S3_MEMORY S3MemoryInfo; + EFI_STATUS Status; + + DEBUG ((DEBUG_INFO, "%a() Start\n", __FUNCTION__)); + + S3PeiMemSize =3D GetPeiMemSize (); + S3PeiMemBase =3D (UINTN) AllocateAcpiNvsMemoryBelow4G (S3PeiMemSize); + ASSERT (S3PeiMemBase !=3D 0); + + S3MemoryInfo.S3PeiMemBase =3D S3PeiMemBase; + S3MemoryInfo.S3PeiMemSize =3D S3PeiMemSize; + + DEBUG ((DEBUG_INFO, "S3PeiMemBase: 0x%x\n", S3PeiMemBase)); + DEBUG ((DEBUG_INFO, "S3PeiMemSize: 0x%x\n", S3PeiMemSize)); + + // TODO: LockBox is potentially superior, though requires static location + Status =3D gRT->SetVariable ( + ACPI_S3_MEMORY_NV_NAME, + &gEfiAcpiVariableGuid, + EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACC= ESS, + sizeof (S3MemoryInfo), + &S3MemoryInfo + ); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "%a() End\n", __FUNCTION__)); + return EFI_SUCCESS; +} diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf new file mode 100644 index 000000000000..28589c2c869b --- /dev/null +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Dxe/S3Dxe.inf @@ -0,0 +1,49 @@ +### @file +# Component information file for the S3 DXE module. +# +# Copyright (c) 2022, Baruch Binyamin Doron.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +### + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D S3Dxe + FILE_GUID =3D 30926F92-CC83-4381-9F70-AC96EDB5BEE0 + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D DXE_DRIVER + ENTRY_POINT =3D S3DxeEntryPoint + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + BaseMemoryLib + DebugLib + PcdLib + UefiLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + MinPlatformPkg/MinPlatformPkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec + S3FeaturePkg/S3FeaturePkg.dec + +[Sources] + S3Dxe.c + +[Pcd] + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize + +[FeaturePcd] + gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable + +[Guids] + gEfiMemoryTypeInformationGuid ## CONSUMES + gEfiAcpiVariableGuid ## CONSUMES + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiVariableWriteArchProtocolGuid diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c b/Fe= atures/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c index b0aaa04962c8..6acb894b6fc9 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.c @@ -2,12 +2,87 @@ Source code file for S3 PEI module =20 Copyright (c) 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2022, Baruch Binyamin Doron.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 +#include +#include +#include #include #include +#include + +// TODO: Finalise implementation factoring +#define R_SA_PAM0 (0x80) +#define R_SA_PAM5 (0x85) +#define R_SA_PAM6 (0x86) + +/** + This function is called after FspSiliconInitDone installed PPI. + For FSP API mode, this is when FSP-M HOBs are installed into EDK2. + + @param[in] PeiServices Pointer to PEI Services Table. + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that + caused this function to execute. + @param[in] Ppi Pointer to the PPI data associated with this f= unction. + + @retval EFI_STATUS Always return EFI_SUCCESS +**/ +EFI_STATUS +EFIAPI +FspSiliconInitDoneNotify ( + IN EFI_PEI_SERVICES **PeiServices, + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDesc, + IN VOID *Ppi + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINT64 MchBaseAddress; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + // Enable PAM regions for AP wakeup vector (resume) + // - CPU is finalised by PiSmmCpuDxeSmm, not FSP. So, it's safe here? + // TODO/TEST: coreboot does this unconditionally, vendor FWs may not (te= st resume). Should we? + // - It is certainly interesting that only PAM0, PAM5 and PAM6 are defin= ed for KabylakeSiliconPkg. + // - Also note that 0xA0000-0xFFFFF is marked "reserved" in FSP HOB - th= is does not mean + // that the memory is unusable, perhaps this is precisely because it w= ill contain + // the AP wakeup vector. + if (BootMode =3D=3D BOOT_ON_S3_RESUME) { + MchBaseAddress =3D PCI_LIB_ADDRESS (0, 0, 0, 0); + PciWrite8 (MchBaseAddress + R_SA_PAM0, 0x30); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 1), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 2), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 3), 0x33); + PciWrite8 (MchBaseAddress + (R_SA_PAM0 + 4), 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM5, 0x33); + PciWrite8 (MchBaseAddress + R_SA_PAM6, 0x33); + } + + // + // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case + // + Status =3D PeiInstallSmmAccessPpi (); + ASSERT_EFI_ERROR (Status); + + // + // Install EFI_PEI_MM_CONTROL_PPI for S3 resume case + // + Status =3D PeiInstallSmmControlPpi (); + ASSERT_EFI_ERROR (Status); + + return Status; +} + +EFI_PEI_NOTIFY_DESCRIPTOR mFspSiliconInitDoneNotifyDesc =3D { + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST), + &gFspSiliconInitDonePpiGuid, + FspSiliconInitDoneNotify +}; =20 /** S3 PEI module entry point @@ -25,12 +100,10 @@ S3PeiEntryPoint ( IN CONST EFI_PEI_SERVICES **PeiServices ) { - EFI_STATUS Status; + EFI_STATUS Status; =20 - // - // Install EFI_PEI_MM_ACCESS_PPI for S3 resume case - // - Status =3D PeiInstallSmmAccessPpi (); + Status =3D PeiServicesNotifyPpi (&mFspSiliconInitDoneNotifyDesc); + ASSERT_EFI_ERROR (Status); =20 return Status; } diff --git a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf b/= Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf index e485eac9521f..173919bb881e 100644 --- a/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf +++ b/Features/Intel/PowerManagement/S3FeaturePkg/S3Pei/S3Pei.inf @@ -18,10 +18,13 @@ [LibraryClasses] PeimEntryPoint PeiServicesLib + DebugLib SmmAccessLib + SmmControlLib =20 [Packages] MdePkg/MdePkg.dec + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec S3FeaturePkg/S3FeaturePkg.dec =20 @@ -31,5 +34,8 @@ [FeaturePcd] gS3FeaturePkgTokenSpaceGuid.PcdS3FeatureEnable =20 +[Ppis] + gFspSiliconInitDonePpiGuid + [Depex] - gEfiPeiMemoryDiscoveredPpiGuid + TRUE diff --git a/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h b/P= latform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h new file mode 100644 index 000000000000..0d75af8e9a03 --- /dev/null +++ b/Platform/Intel/MinPlatformPkg/Include/AcpiS3MemoryNvData.h @@ -0,0 +1,22 @@ +/** @file + Header file for NV data structure definition. + +Copyright (c) 2021, Baruch Binyamin Doron +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef __ACPI_S3_MEMORY_NV_DATA_H__ +#define __ACPI_S3_MEMORY_NV_DATA_H__ + +// +// NV data structure +// +typedef struct { + UINT64 S3PeiMemBase; + UINT64 S3PeiMemSize; +} ACPI_S3_MEMORY; + +#define ACPI_S3_MEMORY_NV_NAME L"S3MemoryInfo" + +#endif --=20 2.37.2 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#92922): https://edk2.groups.io/g/devel/message/92922 Mute This Topic: https://groups.io/mt/93335521/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-