[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Add MinnowBorad3Module EEPROM binary

Guo, Mang posted 1 patch 16 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/edk2 tags/patchew/22D2C85ED001C54AA20BFE3B0E4751D1526D140D@SHSMSX103.ccr.corp.intel.com
z=eJjVt-1SS{!@o;Iezi=oqzb<J^yz5bI)HnzIFD)SN<dv`P2vQ{Nm4IZL7XD_?GW|

[edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900] Add MinnowBorad3Module EEPROM binary

Posted by Guo, Mang 16 weeks ago
Add MinnowBorad3Module EEPROM binary and related code for generating binary.
Correct code format.

Cc: David Wei <david.wei@intel.com>
Cc: Mike Wu  <mike.wu@intel.com>

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Kelly Steele <kelly.steele@intel.com>
Signed-off-by: Guo Mang <mang.guo@intel.com>
---
 .../EepromAsl/Audio/Audio_codec_10EC5645.asl       |   47 +
 .../EepromAsl/Audio/Audio_codec_10EC5651.asl       |   47 +
 .../EepromAsl/Audio/Audio_codec_1AEC8731.asl       |   47 +
 .../EepromAsl/Audio/Audio_codec_DLGS7212.asl       |   47 +
 .../Eeprom/EepromAsl/Audio/Audio_codec_INT34C1.asl |   81 +
 .../Eeprom/EepromAsl/Audio/Audio_codec_INT34E0.asl |   81 +
 .../Eeprom/EepromAsl/Audio/Vibra_INT34E1.asl       |   45 +
 .../Eeprom/EepromAsl/Charger/Charger_BQ258900.asl  |   46 +
 .../Eeprom/EepromAsl/EepromSsdt0.asl               |   65 +
 .../Eeprom/EepromAsl/I2C/Eeprom_M24M02.asl         |   41 +
 .../Eeprom/EepromAsl/I2C/I2C_Bus2_TestDevice.asl   |   62 +
 .../Eeprom/EepromAsl/SPI/SPI1_CS0_TestDevice.asl   |   35 +
 .../Eeprom/EepromAsl/SPI/SPI2_CS0_TestDevice.asl   |   35 +
 .../Eeprom/EepromAsl/Touch/Touch_ATML1000.asl      |  124 ++
 .../Board/MinnowBoard3Module/Eeprom/EepromStruct.h |  169 ++
 .../MinnowBoard3Module/Eeprom/GenerateBinary.py    |   94 +
 .../Board/MinnowBoard3Module/Eeprom/Logo/Intel.bmp |  Bin 0 -> 16126 bytes
 .../Board/MinnowBoard3Module/Eeprom/Logo/blank.bmp |  Bin 0 -> 1198 bytes
 .../Board/MinnowBoard3Module/Eeprom/MB3-Defs.cfg   |  200 ++
 .../Board/MinnowBoard3Module/Eeprom/MB3-Eeprom.bin |  Bin 0 -> 32688 bytes
 .../Board/MinnowBoard3Module/Eeprom/MB3-Prj.cfg    | 2252 ++++++++++++++++++++
 .../Eeprom/RSA-keys/MB3-private.pem                |   27 +
 .../Eeprom/RSA-keys/MB3-public.bin                 |  Bin 0 -> 256 bytes
 .../Eeprom/RSA-keys/MB3-public.pem                 |    9 +
 .../Eeprom/VBT/Vbt_bxt_t_TianmaMipi.bin            |  Bin 0 -> 6656 bytes
 .../Eeprom/VBT/Vbt_bxt_t_fab_b.bin                 |  Bin 0 -> 7168 bytes
 .../Eeprom/VBT/Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin   |  Bin 0 -> 6656 bytes
 27 files changed, 3554 insertions(+)
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5645.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5651.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_1AEC8731.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_DLGS7212.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34C1.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34E0.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Vibra_INT34E1.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Charger/Charger_BQ258900.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/EepromSsdt0.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/Eeprom_M24M02.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/I2C_Bus2_TestDevice.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI1_CS0_TestDevice.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI2_CS0_TestDevice.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Touch/Touch_ATML1000.asl
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromStruct.h
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/GenerateBinary.py
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/Intel.bmp
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/blank.bmp
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Defs.cfg
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Eeprom.bin
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Prj.cfg
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-private.pem
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.bin
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.pem
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_TianmaMipi.bin
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b.bin
 create mode 100644 Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5645.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5645.asl
new file mode 100644
index 0000000..e3a8e19
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5645.asl
@@ -0,0 +1,47 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (RT45) {
+        Name (_ADR, 0x1A)  // _ADR: Address
+        Name (_HID, "10EC5645")  // _HID: Hardware ID
+        Name (_CID, "10EC5645")  // _CID: Compatible ID
+        Name (_DDN, "Realtek RT5645 Audio Codec")  // _DDN: DOS Device Name
+        Name (_UID, One)  // _UID: Unique ID
+
+        Name (SBUF, ResourceTemplate () {
+          I2CSerialBus (
+            0x1A,               // SlaveAddress: bus address
+            ControllerInitiated,// SlaveMode: default to ControllerInitiated
+            400000,             // ConnectionSpeed: in Hz
+            AddressingMode7Bit, // Addressing Mode: default to 7 bit
+            "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+            ,                   // Descriptor Name: creates name for offset of resource descriptor
+          )  // VendorData
+          GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO0") {20} //  AUD_INT
+        })
+
+        Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+          Return (SBUF)
+        }
+
+        Method (_STA, 0, NotSerialized) { // _STA: Status
+          Return (0x0F)
+        }
+
+        Method (_DIS, 0, NotSerialized) { // _DIS: Disable Device
+        }
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5651.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5651.asl
new file mode 100644
index 0000000..b82d360
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_10EC5651.asl
@@ -0,0 +1,47 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (RT51) {
+        Name (_ADR, 0x1A)  // _ADR: Address
+        Name (_HID, "10EC5651")  // _HID: Hardware ID
+        Name (_CID, "10EC5651")  // _CID: Compatible ID
+        Name (_DDN, "Realtek RT5651 Audio Codec")  // _DDN: DOS Device Name
+        Name (_UID, One)  // _UID: Unique ID
+
+        Name (SBUF, ResourceTemplate () {
+          I2CSerialBus (
+            0x1A,               // SlaveAddress: bus address
+            ControllerInitiated,// SlaveMode: default to ControllerInitiated
+            400000,             // ConnectionSpeed: in Hz
+            AddressingMode7Bit, // Addressing Mode: default to 7 bit
+            "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+            ,                   // Descriptor Name: creates name for offset of resource descriptor
+          )  // VendorData
+          GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO0") {20} //  AUD_INT
+        })
+
+        Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+          Return (SBUF)
+        }
+
+        Method (_STA, 0, NotSerialized) { // _STA: Status
+          Return (0x0F)
+        }
+
+        Method (_DIS, 0, NotSerialized) { // _DIS: Disable Device
+        }
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_1AEC8731.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_1AEC8731.asl
new file mode 100644
index 0000000..eb373c7
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_1AEC8731.asl
@@ -0,0 +1,47 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (WLFC) {
+        Name (_ADR, 0x1A)  // _ADR: Address
+        Name (_HID, "1AEC8731")  // _HID: Hardware ID
+        Name (_CID, "1AEC8731")  // _CID: Compatible ID
+        Name (_DDN, "Wolfson WM8731 Audio Codec")  // _DDN: DOS Device Name
+        Name (_UID, One)  // _UID: Unique ID
+
+        Name (SBUF, ResourceTemplate () {
+          I2CSerialBus (
+            0x1A,               // SlaveAddress: bus address
+            ControllerInitiated,// SlaveMode: default to ControllerInitiated
+            400000,             // ConnectionSpeed: in Hz
+            AddressingMode7Bit, // Addressing Mode: default to 7 bit
+            "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+            ,                   // Descriptor Name: creates name for offset of resource descriptor
+          )  // VendorData
+          GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO0") {20} //  AUD_INT
+        })
+
+        Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+          Return (SBUF)
+        }
+
+        Method (_STA, 0, NotSerialized) { // _STA: Status
+          Return (0x0F)
+        }
+
+        Method (_DIS, 0, NotSerialized) { // _DIS: Disable Device
+        }
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_DLGS7212.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_DLGS7212.asl
new file mode 100644
index 0000000..28200d9
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_DLGS7212.asl
@@ -0,0 +1,47 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (DLGS) {
+        Name (_ADR, 0x1A)  // _ADR: Address
+        Name (_HID, "DLGS7212")  // _HID: Hardware ID
+        Name (_CID, "DLGS7212")  // _CID: Compatible ID
+        Name (_DDN, "Dialog 7212 I2S Audio Codec")  // _DDN: DOS Device Name
+        Name (_UID, One)  // _UID: Unique ID
+
+        Name (SBUF, ResourceTemplate () {
+          I2CSerialBus (
+            0x1A,               // SlaveAddress: bus address
+            ControllerInitiated,// SlaveMode: default to ControllerInitiated
+            400000,             // ConnectionSpeed: in Hz
+            AddressingMode7Bit, // Addressing Mode: default to 7 bit
+            "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+            ,                   // Descriptor Name: creates name for offset of resource descriptor
+          )  // VendorData
+          GpioInt (Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0,"\\_SB.GPO0") {20} //  AUD_INT
+        })
+
+        Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+          Return (SBUF)
+        }
+
+        Method (_STA, 0, NotSerialized) { // _STA: Status
+          Return (0x0F)
+        }
+
+        Method (_DIS, 0, NotSerialized) { // _DIS: Disable Device
+        }
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34C1.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34C1.asl
new file mode 100644
index 0000000..86f97d2
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34C1.asl
@@ -0,0 +1,81 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (ACD0) { // Audio Codec driver I2C
+      Name (_ADR, 0x1A)
+      Name (_HID, "INT34C1")
+      Name (_CID, "INT34C1")
+      Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec" )
+      Name (_UID, 1)
+
+      Name (SBUF, ResourceTemplate () {
+        I2CSerialBus (
+          0x1A,               // SlaveAddress: bus address
+          ,                   // SlaveMode: default to ControllerInitiated
+          400000,             // ConnectionSpeed: in Hz
+          ,                   // Addressing Mode: default to 7 bit
+          "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+          ,                   // Descriptor Name: creates name for offset of resource descriptor
+        )  // VendorData
+        GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0,"\\_SB.GPO0") {20} //  AUD_INT
+      })
+
+      Method (_CRS, 0x0, NotSerialized) {
+        Return (SBUF)
+      }
+
+      Method (_STA, 0x0, NotSerialized) {
+        If (LEqual (ADOS, 1)) {  // 1-WM8281
+          Return (0x0F)
+        }
+        Return (0x0)
+      }
+
+      Method (_DIS, 0x0, NotSerialized) {
+      }
+
+      Method (DEVS) {
+        Return (88)
+      }
+
+      Method (DEVC) {
+        Return (Buffer () {
+            0x54, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x10, 0xFF, 0xFF, 0xFF,
+            0x32, 0xFF, 0xFF, 0xFF,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x37, 0x03, 0xD0, 0x83,
+            0x00, 0x00, 0x70, 0xC0,
+            0x00, 0x00, 0x00, 0x00,
+            0x04, 0x00, 0x01, 0x02,
+            0x0F, 0x00, 0x00, 0x00,
+            0x0F, 0x00, 0x00, 0x00,
+            0x02, 0x40, 0x00, 0x00,
+            0x04, 0x00, 0x00, 0x00,
+            0x00, 0x0F, 0x07, 0x07,
+            0x20, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00
+        })
+      }
+    } // Device (ACD0)
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34E0.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34E0.asl
new file mode 100644
index 0000000..3314799
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Audio_codec_INT34E0.asl
@@ -0,0 +1,81 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+    Device (ACD1) {
+        Name (_ADR, 0x1A)  // _ADR: Address
+        Name (_HID, "INT34E0")  // _HID: Hardware ID
+        Name (_CID, "INT34E0")  // _CID: Compatible ID
+        Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec")  // _DDN: DOS Device Name
+        Name (_UID, One)  // _UID: Unique ID
+
+        Name (SBUF, ResourceTemplate () {
+          I2CSerialBus (
+            0x1A,               // SlaveAddress: bus address
+            ,                   // SlaveMode: default to ControllerInitiated
+            400000,             // ConnectionSpeed: in Hz
+            ,                   // Addressing Mode: default to 7 bit
+            "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+            ,                   // Descriptor Name: creates name for offset of resource descriptor
+          )  // VendorData
+          GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0,"\\_SB.GPO0") {64} //  AUD_INT
+        })
+
+        Method (_CRS, 0, Serialized) { // _CRS: Current Resource Settings
+          Return (SBUF)
+        }
+
+        Method (_STA, 0, NotSerialized) { // _STA: Status
+            If (LEqual (ADOS, 0x02)) {
+                Return (0x0F)
+            }
+            Return (Zero)
+        }
+
+        Method (_DIS, 0, NotSerialized) { // _DIS: Disable Device
+        }
+
+        Method (DEVS) {
+            Return (88)
+        }
+
+        Method (DEVC) {
+            Return (Buffer () {
+            0x54, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x10, 0xFF, 0xFF, 0xFF,
+            0x32, 0xFF, 0xFF, 0xFF,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x37, 0x03, 0xD0, 0x83,
+            0x00, 0x00, 0x70, 0xC0,
+            0x00, 0x00, 0x00, 0x00,
+            0x04, 0x00, 0x01, 0x02,
+            0x0F, 0x00, 0x00, 0x00,
+            0x0F, 0x00, 0x00, 0x00,
+            0x02, 0x40, 0x00, 0x00,
+            0x04, 0x00, 0x00, 0x00,
+            0x00, 0x0F, 0x07, 0x07,
+            0x20, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00,
+            0x00, 0x00, 0x00, 0x00
+            })
+        }
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Vibra_INT34E1.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Vibra_INT34E1.asl
new file mode 100644
index 0000000..978b5c8
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Audio/Vibra_INT34E1.asl
@@ -0,0 +1,45 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB) {
+  Device (VIBR) {
+    Name (_ADR, Zero)                               // _ADR: Address
+    Name (_HID, "INT34E1")                          // _HID: Hardware ID
+    Name (_CID, "INT34E1")                          // _CID: Compatible ID
+    Name (_DDN, "Intel(R) Vibra Driver - VIB8601")  // _DDN: DOS Device Name
+    Name (_UID, One)                                // _UID: Unique ID
+    Name (RBUF, ResourceTemplate () {
+      // SOC GPIO_35
+      GpioIo (Exclusive, PullDefault, , , IoRestrictionOutputOnly,
+             "\\_SB.GPO0", , ResourceConsumer, ,
+             )
+          { // Pin list
+            0x0023
+          }
+    })
+
+    Method (_CRS, 0, NotSerialized) {                // _CRS: Current Resource Settings
+      Return (RBUF)
+    }
+
+    Method (_STA, 0x0, NotSerialized) {
+      //If (LNotEqual (OSSL, 1)) {                      // Android only
+      //    Return (0xF)
+      //}
+      Return (0xF)
+    }
+
+  } // Device (VIBR)
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Charger/Charger_BQ258900.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Charger/Charger_BQ258900.asl
new file mode 100644
index 0000000..f1314d2
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Charger/Charger_BQ258900.asl
@@ -0,0 +1,46 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+  Device (ANCH) {
+    Name (_ADR, 0x6B)
+    Name (_HID, "BQ258900")           // _HID: Hardware ID
+    Name (_CID, "BQ258900")           // _CID: Compatible ID
+    Name (_DDN, "Charger Controller") // _DDN: DOS Device Name
+    Name (RBUF, ResourceTemplate () {
+      I2CSerialBus(
+        0x6B,               // SlaveAddress: bus address
+        ,                   // SlaveMode: default to ControllerInitiated
+        400000,             // ConnectionSpeed: in Hz
+        ,                   // Addressing Mode: default to 7 bit
+        "\\_SB.PCI0.I2C1",  // ResourceSource: I2C bus controller name
+        ,                   // Descriptor Name: creates name for offset of resource descriptor
+      )  // VendorData
+      GpioInt (Level, ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GPO0") {19} //  CHARGER_INT
+      GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO0", 0x00, ResourceConsumer, ,) {15}
+    })
+
+    Method (_CRS, 0, NotSerialized) { // _CRS: Current Resource Settings
+      Return (RBUF) /* \_SB_.PCI0.I2C1.ANCH.RBUF */
+    }
+
+    Method (_STA, 0, NotSerialized) { // _STA: Status
+      If (LEqual(OSSL, One))          // Linux
+        {Return (0x0F)}
+      Else
+        {Return (Zero)}
+    }
+  }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/EepromSsdt0.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/EepromSsdt0.asl
new file mode 100644
index 0000000..e21f7a6
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/EepromSsdt0.asl
@@ -0,0 +1,65 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+DefinitionBlock (
+    "EepromSsdt1.aml",
+    "SSDT",
+    1,
+    "INTEL",
+    "EprmSdt0",
+    0x1000
+    )
+{
+  External (ADOS, IntObj)
+  External (OSSL, IntObj)
+  External (VTKB, IntObj)
+  External (\_SB.GPO0, DeviceObj)
+  External (\_SB.GPO2, DeviceObj)
+  External (\_SB.IPC1, DeviceObj)
+  External (\_SB.IPC1.PMIC, DeviceObj)
+  External (\_SB.IPC1.PMIC.AVBG, IntObj)
+  External (\_SB.IPC1.PMIC.AVBL, IntObj)
+  External (\_SB.IPC1.PMIC.GP3B, IntObj)
+  External (\_SB.IPC1.PMIC.GP6B, IntObj)
+  External (\_SB.IPC1.PMIC.VP3B, IntObj)
+  External (\_SB.IPC1.PMIC.VP6B, IntObj)
+  External (\_SB.PCI0, DeviceObj)
+  External (\_SB.PCI0.I2C1, DeviceObj)
+  External (\_SB.PCI0.I2C2, DeviceObj)
+  External (\_SB.PCI0.I2C3, DeviceObj)
+  External (\_SB.PCI0.SPI1, DeviceObj)
+  External (\_SB.PCI0.SPI2, DeviceObj)
+
+  // include ("Charger/Charger_BQ258900.asl")
+  include ("I2C/Eeprom_M24M02.asl")
+
+  // These are 6 examples of audio codecs
+  // include ("Audio/Audio_codec_10EC5645.asl")
+  // include ("Audio/Audio_codec_10EC5651.asl")
+  // include ("Audio/Audio_codec_1AEC8731.asl")
+  // include ("Audio/Audio_codec_INT34C1.asl")
+  // include ("Audio/Audio_codec_INT34E0.asl")
+  // include ("Audio/Audio_codec_DLGS7212.asl")
+
+  // This is an example of how to add an I2C device and set the speed
+  // include ("I2C/I2C_Bus2_TestDevice.asl")
+
+  // This is an example of how to add a SPI device
+  // include ("SPI/SPI1_CS0_TestDevice.asl")
+  // include ("SPI/SPI2_CS0_TestDevice.asl")
+
+  // This is an example of how to add a touch panel
+  // include ("Touch/Touch_ATML1000.asl")
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/Eeprom_M24M02.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/Eeprom_M24M02.asl
new file mode 100644
index 0000000..c6c8658
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/Eeprom_M24M02.asl
@@ -0,0 +1,41 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C1) {
+  Device (EEP0) {
+    Name (_ADR, 0x50)      // _ADR: Address
+    Name (_HID, "INT3500") // _HID: Hardware ID
+    Name (_CID, "24m02")   // _CID: Compatible ID
+    Name (_DDN, "EEPROM")  // _DDN: DOS Device Name
+    Name (RBUF, ResourceTemplate () {
+       I2cSerialBus (
+           0x0050,                // SlaveAddress: bus address
+       ControllerInitiated,   // SlaveMode: default to ControllerInitiated
+       400000,                // ConnectionSpeed: in Hz
+       AddressingMode7Bit,    // Addressing Mode: default to 7 bit
+       "\\_SB.PCI0.I2C1",     // ResourceSource: I2C bus controller name
+       0x00                   // Descriptor Name: creates name for offset of resource descriptor
+   ) // Vendor Data
+    })
+
+    Method (_CRS, 0, NotSerialized) { // _CRS: Current Resource Settings
+      Return (RBUF) /* \_SB_.PCI0.I2C1.EEP0.RBUF */
+    }
+
+    Method (_STA, 0, NotSerialized) { // _STA: Status
+      Return (0x0F)
+    }
+  }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/I2C_Bus2_TestDevice.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/I2C_Bus2_TestDevice.asl
new file mode 100644
index 0000000..7f30ac2
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/I2C/I2C_Bus2_TestDevice.asl
@@ -0,0 +1,62 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C2)
+{
+    Name (_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package () {
+            Package () {"clock-frequency", 100000},
+        }
+    })
+}
+
+Scope (\_SB.PCI0.I2C2)
+{
+    Device (ACCL) {
+        Name (_HID, "PRP0001")
+        Name (_DDN, "ADXL345 Three-Axis Digital Accelerometer")
+        Name (_CRS, ResourceTemplate () {
+            I2cSerialBus (
+                0x53,                   // Bus address
+                ControllerInitiated,    // Don't care
+                400000,                 // Max speed of the chip
+                AddressingMode7Bit,     // 7-bit addressing
+                "\\_SB.PCI0.I2C2",      // I2C host controller
+                0                       // Must be 0
+            )
+                GpioInt (
+                    Edge,
+                    ActiveHigh,
+                    ExclusiveAndWake,
+                    PullNone,
+                    0x0000,
+                    "\\_SB.GPO2",
+                    0x00,
+                    ResourceConsumer, ,
+                )
+                {   // Pin list
+                    28                  // ISH_GPIO_6_LS
+                }
+        })
+
+        Name (_DSD, Package () {
+            ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"compatible", Package () {"adi,adxl34x"}},
+            }
+        })
+    }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI1_CS0_TestDevice.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI1_CS0_TestDevice.asl
new file mode 100644
index 0000000..9037abd
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI1_CS0_TestDevice.asl
@@ -0,0 +1,35 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.SPI1) {
+  Device (TP0) {
+    Name (_HID, "SPT0001")
+    Name (_DDN, "SPI test device connected to CS0")
+    Name (_CRS, ResourceTemplate () {
+      SpiSerialBus (
+        0,                      // Chip select (0, 1, 2)
+        PolarityLow,            // Chip select is active low
+        FourWireMode,           // Full duplex
+        8,                      // Bits per word is 8 (byte)
+        ControllerInitiated,    // Don't care
+        1000000,                // 1 MHz
+        ClockPolarityLow,       // SPI mode 0
+        ClockPhaseFirst,        // SPI mode 0
+        "\\_SB.PCI0.SPI1",      // SPI host controller
+        0                       // Must be 0
+      )
+    })
+  }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI2_CS0_TestDevice.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI2_CS0_TestDevice.asl
new file mode 100644
index 0000000..b1c3b62
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/SPI/SPI2_CS0_TestDevice.asl
@@ -0,0 +1,35 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.SPI2) {
+  Device (TP0) {
+    Name (_HID, "SPT0001")
+    Name (_DDN, "SPI test device connected to CS0")
+    Name (_CRS, ResourceTemplate () {
+      SpiSerialBus (
+        0,                      // Chip select (0, 1, 2)
+        PolarityLow,            // Chip select is active low
+        FourWireMode,           // Full duplex
+        8,                      // Bits per word is 8 (byte)
+        ControllerInitiated,    // Don't care
+        1000000,                // 1 MHz
+        ClockPolarityLow,       // SPI mode 0
+        ClockPhaseFirst,        // SPI mode 0
+        "\\_SB.PCI0.SPI2",      // SPI host controller
+        0                       // Must be 0
+      )
+    })
+  }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Touch/Touch_ATML1000.asl b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Touch/Touch_ATML1000.asl
new file mode 100644
index 0000000..14f1811
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromAsl/Touch/Touch_ATML1000.asl
@@ -0,0 +1,124 @@
+/** @file
+
+Copyright (c) 2017 - 2018 Intel Corporation.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD License
+which accompanies this distribution.  The full text of the license may be found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope (\_SB.PCI0.I2C3)
+{
+  Device (TCS0)
+  {
+    Name (_ADR, 0x0)
+    Name (_HID, "ATML0001")
+    Name (_CID, "PNP0C50")
+    Name (_S0W, 0)
+
+    Method (_PS3, 0, Serialized) {
+      If(LEqual (\_SB.IPC1.PMIC.AVBL, 1)){
+//        Store(0x00, \_SB.IPC1.PMIC.VP6B)  // Tianma - 0 put the device to power saving state
+        Store(0x00, \_SB.IPC1.PMIC.VP3B)  // Truly  - 0 put the device to power saving state
+
+        If(LEqual (\_SB.IPC1.PMIC.AVBG, 1)){
+//           Store(0x01, \_SB.IPC1.PMIC.GP6B)  // Tianma
+           Store(0x01, \_SB.IPC1.PMIC.GP3B)  // Truly
+        }
+        Sleep(120)
+      }
+    }
+
+    Method (_PS0, 0, Serialized) {
+      If(LEqual (\_SB.IPC1.PMIC.AVBL, 1)){
+//        Store(0x01, \_SB.IPC1.PMIC.VP6B) // Tianma
+        Store(0x01, \_SB.IPC1.PMIC.VP3B) // Truly
+
+        If(LEqual (\_SB.IPC1.PMIC.AVBG, 1)){
+//          Store(0x01, \_SB.IPC1.PMIC.GP6B)   // Tianma - 1 put the device to normal state
+          Store(0x01, \_SB.IPC1.PMIC.GP3B)   // Truly  - 1 put the device to normal state
+        }
+        Sleep(120)
+      }
+    }
+
+    Name (XBUF, ResourceTemplate (){ // resource fot HR16 truly panel Windows
+      I2CSerialBus(0x4A, //SlaveAddress: bus address 1386->1664
+                       , //SlaveMode: default to ControllerInitiated
+                 400000, //400000 ConnectionSpeed: in Hz
+                       , //Addressing Mode: default to 7 bit
+      "\\_SB.PCI0.I2C3", //ResourceSource: I2C bus controller name
+                       , //Descriptor Name: creates name for offset of resource descriptor
+                     ) //VendorData
+      GpioInt(Edge,  ActiveLow, ExclusiveAndWake, PullUp, 0, "\\_SB.GPO0", ) {22}  // GPIO_22 TOUCH_INT
+      GpioIo(Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.GPO2", ) {28} // GPIO_152 RESET
+    })
+
+    Method(_CRS, 0x0, NotSerialized){
+      Return (XBUF)
+    }
+
+    Method(_DSM, 0x4, Serialized){
+      // BreakPoint
+      Store ("Method _DSM begin", Debug)
+
+      If(LEqual(Arg0, ToUUID("3CDFF6F7-4267-4555-AD05-B30A3D8938DE")))
+      {
+        // DSM Function
+        switch(ToInteger(Arg2))
+        {
+          // Function 0: Query function, return based on revision
+          case(0)
+          {
+            // DSM Revision
+            switch(ToInteger(Arg1))
+            {
+              // Revision 1: Function 1 supported
+              case(1)
+              {
+                Store ("Method _DSM Function Query", Debug)
+                Return(Buffer(One) { 0x03 })
+              }
+
+              default
+              {
+                // Revision 2+: no functions supported
+                Return(Buffer(One) { 0x00 })
+              }
+            }
+          }
+
+          // Function 1 : HID Function
+          case(1)
+          {
+            Store ("Method _DSM Function HID", Debug)
+
+            // HID Descriptor Address
+            Return(0x0000)
+          }
+
+          default
+          {
+            // Functions 2+: not supported
+            Return(0x0000)
+          }
+        }
+      }else{
+        // No other GUIDs supported
+        Return(Buffer(One) { 0x00 })
+      }
+    }
+    Method(_STA, 0x0, NotSerialized){
+    If (LEqual(VTKB,2)){ // hide discrete touch when integrated touch is enabled
+       Return(0x0)
+    }
+      Return(0xF)
+    }
+  }
+}
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromStruct.h b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromStruct.h
new file mode 100644
index 0000000..316f5b2
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/EepromStruct.h
@@ -0,0 +1,169 @@
+#ifndef _EEPROM_LAYOUT_H_
+#define _EEPROM_LAYOUT_H_
+
+#pragma pack(1)
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    UINT32  structlength;
+    UINT32  crc32;
+    UINT32  crclength;
+    UINT32  version;
+    CHAR8   reserved[16];
+}EEPROM_HEADER;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   acpitbl[0];
+}ACPI_TABLE;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   manuname[16];
+    CHAR8   brdname[16];
+    CHAR8   brdserial[16];
+    UINT32  boardid;
+    UINT32  fabid;
+    UINT32  ecid;
+    UINT8   boardtype;
+    CHAR8   reserved[19];
+}BOARD_INFO_TABLE;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   partlabel[16];
+    UINT32  blklength;
+    UINT16  pagesize;
+    UINT32  partsize;
+    UINT8   busnumber;
+    UINT8   master;
+    UINT8   speed;
+    CHAR8   reserved[3];
+//  UINT8   mapdata[0];
+}EEPROM_MAP;
+
+
+typedef struct {
+    CHAR8   maplabel[16];
+    UINT32  length;
+    UINT32  offset;
+    UINT8   address;
+    CHAR8   reserved[7];
+}EEPROM_MAP_RECORD;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   gpiodata[0];
+}GPIO_DATA_HEADER;
+
+
+typedef struct {
+    CHAR8   gpiolabel[16];
+    UINT32  length;
+    UINT32  offset;
+    UINT32  anddata;
+    UINT32  ordata;
+    UINT8   datasize;
+    UINT8   datatype;
+    CHAR8   reserved[14];
+}GPIO_DATA_RECORD;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   hdacodec[0];
+}HDA_CODEC;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    UINT16  spdslot;
+    CHAR8   reserved[14];
+//  UINT8   spddata[0];
+}MEMORY_DATA;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   nicid[8];
+    CHAR8   macaddr[6];
+    UINT16  nicnum;
+    CHAR8   reserved[16];
+//  UINT8   nicdata[0];
+}NIC_INFO;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    UINT16  hashtype;
+    CHAR8   reserved[14];
+//  UINT8   eepromsig[0];
+}SIGNATURE_DATA;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   ucodedata[0];
+}MICROCODE;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   videodata[0];
+}VIDEO_DATA;
+
+
+typedef struct {
+    CHAR8   signature[8];
+    UINT16  vermajor;
+    UINT16  verminor;
+    UINT32  length;
+    CHAR8   reserved[16];
+//  UINT8   logodata[0];
+}LOGO_DATA;
+
+#pragma pack()
+#endif
+
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/GenerateBinary.py b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/GenerateBinary.py
new file mode 100644
index 0000000..92b0cc9
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/GenerateBinary.py
@@ -0,0 +1,94 @@
+#  @file
+#  Script file to generate the EEPROM binary
+#
+#  Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php.
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+import glob
+import os
+import subprocess
+import sys
+
+# Version defines
+__version__   = '0.1.0.2'
+VerString     = 'EEPROM binary generation tool, Version #{0}'.format(__version__)
+PythonVersion = 'Python version = {0:X}'.format(sys.hexversion)
+
+def Main():
+  # Set return code to error
+  ReturnCode = 1
+
+  try:
+    # Get paths
+    ThisUtilityPath   = os.path.dirname(os.path.abspath(sys.argv[0]))
+    ParentUtilityPath = os.path.dirname(ThisUtilityPath)
+    UtilityPath       = ParentUtilityPath + '\\Utilities'
+    ProjectName       = 'MB3'
+
+    # MinnowBoard 3 specific defines
+    EepromBinaryUtility  = UtilityPath     + '\\eeprom.py'
+    EepromHashUtility    = UtilityPath     + '\\HashBinary.py'
+    EepromDefinitionFile = ThisUtilityPath + '\\' + ProjectName + '-Defs.cfg'
+    EepromProjectFile    = ThisUtilityPath + '\\' + ProjectName + '-Prj.cfg'
+    EepromBinaryFile     = ThisUtilityPath + '\\' + ProjectName + '-Eeprom.bin'
+    EepromHeaderFile     = ThisUtilityPath + '\\EepromStruct.h'
+    EepromPrivatePemFile = ThisUtilityPath + '\\RSA-keys\\' + ProjectName + '-private.pem'
+    OpenSslPath          = UtilityPath     + '\\OpenSsl\\openssl.exe'
+
+    # Debug prints
+    if False:
+      print('sys.argv[0]          = {0}'.format(sys.argv[0]))
+      print('ThisUtilityPath      = {0}'.format(ThisUtilityPath))
+      print('ParentUtilityPath    = {0}'.format(ParentUtilityPath))
+      print('UtilityPath          = {0}'.format(UtilityPath))
+      print('EepromBinaryFile     = {0}'.format(EepromBinaryFile))
+      print('EepromBinaryUtility  = {0}'.format(EepromBinaryUtility))
+      print('EepromDefinitionFile = {0}'.format(EepromDefinitionFile))
+      print('EepromHashUtility    = {0}'.format(EepromHashUtility))
+      print('EepromHeaderFile     = {0}'.format(EepromHeaderFile))
+      print('EepromPrivatePemFile = {0}'.format(EepromPrivatePemFile))
+      print('EepromProjectFile    = {0}'.format(EepromProjectFile))
+      print('OpenSslPath          = {0}'.format(OpenSslPath))
+
+    # Delete any previous files
+    RemoveFile(EepromBinaryFile)
+    RemoveFile(EepromHeaderFile)
+    for file in glob.glob(ThisUtilityPath + '\\*.aml'):
+      RemoveFile(file)
+
+    # Generate unhashed binary
+    #   eeprom.py -d EepromDefinitionFile -p EepromProjectFile -b EepromBinaryFile --header EepromHeaderFile
+    subprocess.call(['python.exe', EepromBinaryUtility, '-d', EepromDefinitionFile, '-p', EepromProjectFile, '-b', EepromBinaryFile, '--header', EepromHeaderFile])
+
+    # Add hashing/signature
+    #   HashBinary.py OpenSSL EepromBinaryFile [PrivateKey]
+    subprocess.call(['python.exe', EepromHashUtility, OpenSslPath, EepromBinaryFile, EepromPrivatePemFile])
+
+    # Delete temporary files
+    for file in glob.glob(ThisUtilityPath + '\\*.aml'):
+      RemoveFile(file)
+
+    # Clear error code
+    ReturnCode = 0
+
+  finally:
+    return ReturnCode
+
+def RemoveFile(FileName):
+  if os.path.exists(FileName):
+    os.remove(FileName)
+  return
+
+if __name__ == "__main__":
+  print('')
+  print(VerString)
+  print(PythonVersion)
+  sys.exit(Main())
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/Intel.bmp b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/Intel.bmp
new file mode 100644
index 0000000000000000000000000000000000000000..4bbd88512488238d5cd81dbd8e5a856ee784ce2e
GIT binary patch
literal 16126
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ze~F47KyLfDF6YsA$p>#HM2!vVj7kqJoA@K1sopMc@7Da(!W{>*vVFe3$JEdfsgB5I
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SFx`JF#Yul_zP#?)yZ#T1f9$*f

literal 0
HcmV?d00001

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/blank.bmp b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/Logo/blank.bmp
new file mode 100644
index 0000000000000000000000000000000000000000..2f6df34d17a94cf815dc7f01520aec5a6a357c96
GIT binary patch
literal 1198
zcmc)Iv5^!p5QX8U3WEZZ1llA5?5^|4p~Jv@p|n9^62r4EhBG>Z^UqlR8C{VAqxtl-
z+O3_D)K5SDe2n}0PJUzb`Q3;3bkF~!|N7;)C;oMc;11~oJ;SgaesR1$|BlE)gD-Mm
zY(xbT45}dvjE(3(qQHk12FAWWH_1Xn7#JJDFeXuG2m@nz$v~pe5C+CZaK|PJ4Pjtx
zRPdUSxLQLP7<-nMNfsKyz}U0wO0v)p2F9K(=_CscVPNdpE+tuL2m@o!R!)+IhA=Sp
zY_pRrG=zb%_Yu@4S!f6YV?(T8k+@dgxZ1$jPzDl(hA=Sp99tz>Xb1yi&yjYLg@!ON
z_8d14kqQlAVC*S{NwUxo2F9K;agv3GFfjHmA#IX{hA=QT%=#UPLPHo_ZBJ=sl7)sa
zF!q#PC0S?)17lA~c9MmLFfjI%tCB1<gn_ZAlqbnTLl_u)%G^m78p6cu+arGQJMn)J
SkNb|t;~If>O<mo8y8Z&MfJZ_A

literal 0
HcmV?d00001

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Defs.cfg b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Defs.cfg
new file mode 100644
index 0000000..621b7d3
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Defs.cfg
@@ -0,0 +1,200 @@
+; @file
+;  EEPROM structure definitions for Intel Test Platform
+;
+;  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+;
+;  This program and the accompanying materials
+;  are licensed and made available under the terms and conditions of the BSD License
+;  which accompanies this distribution.  The full text of the license may be found at
+;  http://opensource.org/licenses/bsd-license.php.
+;
+;  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+
+;
+; Defines:
+; Tool         = Tool name that should process this file
+; Version      = Minimum required version of the tool
+; Type         = Definitions -> Defines structures, Project -> Defines values for a platform
+; Platform     = A nice human readable name describing the platform that the file is intended to be used with.
+; ReqAlignment = The alignment required for each structure
+;
+[Defines]
+Tool             = EEPROM
+Version          = 0.6.0.1
+Type             = Definitions
+Platform         = Minnow Board 3
+ReqAlignment     = 0x10
+RequiredStructs  = EepromHeader|EepromMap|BoardInfoTable
+MaxReqStructSize = 0x1000
+RequiredIndex    = EepromHeader:0|EepromMap:1|BoardInfoTable:2
+
+;
+; Defines that if a structure contains a field with a specific name the filed must be updated with the
+; associated data.  Multiple fields can be specified using the pipe (|) character.
+;
+; StructSize = FieldName = Update the field with the length of the current structure.
+; BinSize    = FieldName = Update the filed with the length of the entire file.
+; Crc32      = FieldName = Update the field with the CRC32 value of the entire file.
+;
+[Patch]
+StructSize = Length
+BinSize    = StructLength
+Crc32      = Crc32
+
+;
+; Structure definitions:
+; FieldName = Offset|Width|Default
+;
+; Optional Values:
+; (Optional) RequiredFirst = 0/1 (Not required first/Required first) (Only one per active config)
+;
+[EepromHeader]
+Signature       = 0x00|0x08|"$Eeprom$"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000020
+StructLength    = 0x10|0x04|0x00000000      ; This field is filled in by the tool
+Crc32           = 0x14|0x04|0x00000000      ; This field is filled in by the tool
+CrcLength       = 0x18|0x04|0x00000000      ; This field is filled in by the tool
+Version         = 0x1C|0x04|0x00000000      ; Version of the EEPROM binary
+Reserved        = 0x20|0x10|0x00
+
+[AcpiTable]
+Signature       = 0x00|0x08|"$AcpiTbl"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+AcpiTbl         = 0x20|0x00|0x00            ; Load data using from_file
+
+[BoardInfoTable]
+Signature       = 0x00|0x08|"$BrdInfo"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+ManuName        = 0x10|0x10|""
+BrdName         = 0x20|0x10|""
+BrdSerial       = 0x30|0x10|""
+BoardId         = 0x40|0x04|0x00000000
+FabId           = 0x44|0x04|0x00000000
+EcId            = 0x48|0x04|0x00000000
+BoardType       = 0x4C|0x01|0x00
+Reserved        = 0x4D|0x13|0x00
+
+[EepromMap]
+Signature       = 0x00|0x08|"$EeprMap"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+PartLabel       = 0x10|0x10|""              ; Part label
+BlkLength       = 0x20|0x04|0x00010000      ; size of each map record
+PageSize        = 0x24|0x02|0x0100
+PartSize        = 0x26|0x04|0x00040000      ; total size of EEPROM
+BusNumber       = 0x2A|0x01|0x00            ; I2C bus number for this EEPROM
+Master          = 0x2B|0x01|0x01            ; 1 indicates this is the master EEPROM map structure
+Speed           = 0x2C|0x01|0x01            ; Speed EEPROM should run at
+                                            ;   1 - 100KHz (Standard speed)
+                                            ;   2 - 400KHz (Fast speed)
+                                            ;   3 - 3.4MHz (High speed)
+Reserved        = 0x2D|0x03|0x00
+MapData         = 0x30|0x00|0x00
+
+[EepromMapRecord]
+MapLabel        = 0x00|0x10|""
+Length          = 0x10|0x04|0x00000000
+Offset          = 0x14|0x04|0x00000000      ; offset in EEPROM binary
+Address         = 0x18|0x01|0x0000          ; EEPROM I2C address for this block, 7-bit
+Reserved        = 0x19|0x07|0x00
+
+[GpioDataHeader]
+Signature       = 0x00|0x08|"$GpioDat"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+GpioData        = 0x20|0x00|0x00
+
+[GpioDataRecord]
+GpioLabel       = 0x00|0x10|""
+Length          = 0x10|0x04|0x00000030
+Offset          = 0x14|0x04|0x00000000
+AndData         = 0x18|0x04|0xFFFFFFFF
+OrData          = 0x1C|0x04|0x00000000
+DataSize        = 0x20|0x01|0x00
+DataType        = 0x21|0x01|0x00
+Reserved        = 0x22|0x0E|0x00
+
+[HdaCodec]
+Signature       = 0x00|0x08|"$HdCodec"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+HdaCodec        = 0x20|0x00|0x00            ; Load data using from_file
+
+[MemoryData]
+Signature       = 0x00|0x08|"$MemCnfg"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+SpdSlot         = 0x10|0x02|0x0000
+Reserved        = 0x12|0x0E|0x00
+SpdData         = 0x20|0x00|0x00            ; Load data using from_file
+
+[NicInfo]
+Signature       = 0x00|0x08|"$MacInfo"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+NicId           = 0x10|0x08|""
+MacAddr         = 0x18|0x06|0x000000000000
+NicNum          = 0x1E|0x02|0x0000
+Reserved        = 0x20|0x10|0x00
+NicData         = 0x30|0x00|0x00            ; Load data using from_file
+
+[SignatureData]
+Signature       = 0x00|0x08|"$PromSig"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0a|0x02|0x0000
+Length          = 0x0c|0x04|0x00000000
+HashType        = 0x10|0x02|0x0000
+Reserved        = 0x12|0x0E|0x00
+EepromSig       = 0x20|0x00|0x00
+   ; - 0x0000 = None    - 0x00 byte hash
+   ; - 0x0001 = MD5     - 0x10 byte hash [signable]
+   ; - 0x0002 = SHA-1   - 0x14 byte hash [signable]
+   ; - 0x0003 = SHA-256 - 0x20 byte hash [signable]
+   ; - 0x0004 = SHA-384 - 0x30 byte hash
+   ; - 0x0005 = SHA-512 - 0x40 byte hash
+   ; - 0x8000 = Flag    - This hash is signed
+   ;                      Currently, UEFI OpenSSL only supports signed MD5,
+   ;                      SHA1, & SHA256 hashes. Since we store both the hash
+   ;                      and signed hash, it is possible to hash with one and
+   ;                      sign with another. Currently the code forces
+   ;                      compliance to the UEFI OpenSSL signable hashes.
+
+[Microcode]
+Signature       = 0x00|0x08|"$uCode$"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0A|0x02|0x0000
+Length          = 0x0C|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+UcodeData       = 0x20|0x00|0x00            ; Load data using from_file
+
+[VideoData]
+Signature       = 0x00|0x08|"$Video$"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0a|0x02|0x0000
+Length          = 0x0c|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+VideoData       = 0x20|0x00|0x00            ; Load data using from_file
+
+[LogoData]
+Signature       = 0x00|0x08|"$Logo$"
+VerMajor        = 0x08|0x02|0x0001
+VerMinor        = 0x0a|0x02|0x0000
+Length          = 0x0c|0x04|0x00000000
+Reserved        = 0x10|0x10|0x00
+LogoData        = 0x20|0x00|0x00            ; Load data using from_file
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Eeprom.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Eeprom.bin
new file mode 100644
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diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Prj.cfg b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Prj.cfg
new file mode 100644
index 0000000..4712e2e
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/MB3-Prj.cfg
@@ -0,0 +1,2252 @@
+; @file
+;  EEPROM project for Testing
+;
+;  Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
+;
+;  This program and the accompanying materials
+;  are licensed and made available under the terms and conditions of the BSD License
+;  which accompanies this distribution.  The full text of the license may be found at
+;  http://opensource.org/licenses/bsd-license.php.
+;
+;  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+
+;
+; Defines:
+; Tool           = Tool name that should process this file
+; Version        = Minimum required version of the tool
+; Type           = Definitions -> Defines structures, Project -> Defines values for a platform
+; Platform       = A nice human readable name describing the platform that the file is intended to be used with.
+; OutputFileName = The default file name to be generated for the project.
+;
+[Defines]
+Tool           = EEPROM
+Version        = 0.6.0.1
+Type           = Project
+Platform       = Minnow Board 3 Module
+OutputFileName = MB3-Eeprom.bin
+
+;
+; An ordered list of the structure names (section names) to be included.
+; Struct_n = Section
+;
+[Structures]
+Struct_01 = Header            ; $Eeprom$ structure
+Struct_02 = M24M02EepromMap   ; $EeprMap structure
+Struct_03 = MyBoardInfo       ; $BrdInfo structure
+Struct_04 = GpioData          ; $GpioDat structure
+Struct_05 = DsdtInfo          ; $AcpiTbl structure
+Struct_06 = VideoInfo         ; $Video$  structure
+Struct_07 = LogoInfo          ; $Logo$   structure
+;
+; The SignatureInfo structure needs to be the last structure.
+;
+Struct_99 = SignatureInfo
+
+;
+; Platform Specific Structures:
+; StructType = Structure_Name
+; FieldName  = Value -> Overrides default value
+; FieldName  = from_file(File) -> Loads the data from the specified file
+; FieldName  = from_struct(Section) -> Generates the data using the provided structure reference
+; FieldName  = from_struct_list(Section) -> Generates multiple structures based on a struct list section section reference
+;
+; If a field is not specified the default value is used from the MB3-Defs.cfg file
+;
+[Header]
+StructureType   = EepromHeader
+Version         = 0x00000000         ; Version of the EEPROM binary
+
+[MyBoardInfo]
+StructureType   = BoardInfoTable
+ManuName        = "MSC$"
+BrdName         = "Minnow Board 3$"
+BrdSerial       = ""
+BoardId         = 0x00000000
+FabId           = 0x00000000         ; Test board
+EcId            = 0x00000000
+BoardType       = 0x01
+
+;
+; Describes an StMicro M24M02
+; - Address = 1010xxx
+;                 ||+- A16 offset bit
+;                 |+-- A17 offset bit
+;                 +--- E2 address pin (internal pull-down)
+;
+[M24M02EepromMap]
+StructureType   = EepromMap
+PartLabel       = "StMicro M24M02"   ; Part label
+BlkLength       = 0x00010000         ; size of each map record
+PageSize        = 0x0100             ; part page size
+PartSize        = 0x00040000         ; total size of EEPROM
+BusNumber       = 0x07               ; I2C bus number for this EEPROM
+Speed           = 0x02               ; Fast speed - 400KHz
+MapData         = from_struct_list (M24M02MapDataList)
+
+[M24M02MapData001]
+MapLabel        = "M24M02 Blk #1$"
+StructureType   = EepromMapRecord
+Offset          = 0x00000000
+Address         = 0x54               ; 7-bit address
+
+[M24M02MapData002]
+MapLabel        = "M24M02 Blk #2$"
+StructureType   = EepromMapRecord
+Offset          = 0x00010000
+Address         = 0x55               ; 7-bit address
+
+[M24M02MapData003]
+MapLabel        = "M24M02 Blk #3$"
+StructureType   = EepromMapRecord
+Offset          = 0x00020000
+Address         = 0x56               ; 7-bit address
+
+[M24M02MapData004]
+MapLabel        = "M24M02 Blk #4$"
+StructureType   = EepromMapRecord
+Offset          = 0x00030000
+Address         = 0x57               ; 7-bit address
+
+[DsdtInfo]
+StructureType   = AcpiTable
+AcpiTbl         = from_asl (../Utilities/IASL,EepromAsl/EepromSsdt0.asl)
+;
+; Relative or absolute path to the ASL compiler is the first parameter
+; Relative or absolute path to the ASL file to compile and include
+;
+
+; You need to also uncomment Struct_06 = VideoInfo above
+[VideoInfo]
+StructureType   = VideoData
+VideoData       = from_file (VBT/Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin)
+;
+; 1 | HDMI & Tianma | Vbt_bxt_t_TianmaMipi.bin
+; 2 | HDMI only     | Vbt_bxt_t_fab_b.bin
+; 3 | HDMI & Truly  | Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin
+;
+
+; You need to also uncomment Struct_07 = LogoInfo above
+[LogoInfo]
+StructureType   = LogoData
+LogoData        = from_file (Logo/Intel.bmp)
+;
+; BMP file is the only supported format.
+; Recommend that the BMP file be less than 64KB in size.
+; Use blank.bmp to remove the logo completely.
+
+; You need to also uncomment Struct_99 = SignatureInfo above
+[SignatureInfo]
+StructureType   = SignatureData
+HashType        = 0x8003
+EepromSig       = NULL   ; This will get filled in by a separate utility
+   ; - 0x0000 = None    - 0x00 byte hash
+   ; - 0x0001 = MD5     - 0x10 byte hash [signable]
+   ; - 0x0002 = SHA-1   - 0x14 byte hash [signable]
+   ; - 0x0003 = SHA-256 - 0x20 byte hash [signable]
+   ; - 0x0004 = SHA-384 - 0x30 byte hash
+   ; - 0x0005 = SHA-512 - 0x40 byte hash
+   ; - 0x8000 = Flag    - This hash is signed
+   ;                      Currently, UEFI OpenSSL only supports signed MD5,
+   ;                      SHA1, & SHA256 hashes. Since we store both the hash
+   ;                      and signed hash, it is possible to hash with one and
+   ;                      sign with another. Currently the code forces the
+   ;                      hash and signed hash to be the same hash type.
+
+[GpioData]
+StructureType   = GpioDataHeader
+GpioData        = from_struct_list (GpioDataList)
+
+[GpioData001]
+; SMB_ALERT_1V8 <--> SW_SMB_ALERTB
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P1 PAD0$"
+Offset          = 0x00C005F8
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData002]
+; SMB_ALERT_1V8 <--> SW_SMB_ALERTB
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P1 PAD1$"
+Offset          = 0x00C005FC
+AndData         = 0x00000000
+OrData          = 0x0003F000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData003]
+; SPI0_CS1 <--> NW_GPIO_98
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P31 PAD0$"
+Offset          = 0x00C406B0
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData004]
+; SPI0_CS1 <--> NW_GPIO_98
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P31 PAD1$"
+Offset          = 0x00C406B4
+AndData         = 0x00000000
+OrData          = 0x0003FC4A
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData005]
+; SDIO_WP <--> SW_GPIO_186
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P33 PAD0$"
+Offset          = 0x00C005E0
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData006]
+; SDIO_WP <--> SW_GPIO_186
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P33 PAD1$"
+Offset          = 0x00C005E4
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData007]
+; SDIO_CMD <--> SW_GPIO_171
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P34 PAD0$"
+Offset          = 0x00C00598
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData008]
+; SDIO_CMD <--> SW_GPIO_171
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P34 PAD1$"
+Offset          = 0x00C0059C
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData009]
+; SDIO_CMD <--> SW_GPIO_178
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P34 PAD0$"
+Offset          = 0x00C005D0
+AndData         = 0x00000000
+OrData          = 0x42000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData010]
+; SDIO_CMD <--> SW_GPIO_178
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P34 PAD1$"
+Offset          = 0x00C005D4
+AndData         = 0x00000000
+OrData          = 0x00027000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData011]
+; SDIO_CD <--> SW_GPIO_177
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P35 PAD0$"
+Offset          = 0x00C005C8
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData012]
+; SDIO_CD <--> SW_GPIO_177
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P35 PAD1$"
+Offset          = 0x00C005CC
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData013]
+; SDIO_CK <--> SW_GPIO_166
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P36 PAD0$"
+Offset          = 0x00C00570
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData014]
+; SDIO_CK <--> SW_GPIO_166
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P36 PAD1$"
+Offset          = 0x00C00574
+AndData         = 0x00000000
+OrData          = 0x00005000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData015]
+; SDIO_CK <--> SW_GPIO_172
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P36 PAD0$"
+Offset          = 0x00C005A0
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData016]
+; SDIO_CK <--> SW_GPIO_172
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P36 PAD1$"
+Offset          = 0x00C005A4
+AndData         = 0x00000000
+OrData          = 0x00021100
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData017]
+; SDIO_PWR_EN <--> SW_GPIO_183
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P37 PAD0$"
+Offset          = 0x00C005F0
+AndData         = 0x00000000
+OrData          = 0x44000201
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData018]
+; SDIO_PWR_EN <--> SW_GPIO_183
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P37 PAD1$"
+Offset          = 0x00C005F4
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData019]
+; SDIO_D0 <--> SW_GPIO_167
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P39 PAD0$"
+Offset          = 0x00C00578
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData020]
+; SDIO_D0 <--> SW_GPIO_167
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P39 PAD1$"
+Offset          = 0x00C0057C
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData021]
+; SDIO_D0 <--> SW_GPIO_173
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P39 PAD0$"
+Offset          = 0x00C005A8
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData022]
+; SDIO_D0 <--> SW_GPIO_173
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P39 PAD1$"
+Offset          = 0x00C005AC
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData023]
+; SDIO_D1 <--> SW_GPIO_168
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P40 PAD0$"
+Offset          = 0x00C00580
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData024]
+; SDIO_D1 <--> SW_GPIO_168
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P40 PAD1$"
+Offset          = 0x00C00584
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData025]
+; SDIO_D1 <--> SW_GPIO_174
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P40 PAD0$"
+Offset          = 0x00C005B0
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData026]
+; SDIO_D1 <--> SW_GPIO_174
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P40 PAD1$"
+Offset          = 0x00C005B4
+AndData         = 0x00000000
+OrData          = 0x00023100
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData027]
+; SDIO_D2 <--> SW_GPIO_169
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P41 PAD0$"
+Offset          = 0x00C00588
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData028]
+; SDIO_D2 <--> SW_GPIO_169
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P41 PAD1$"
+Offset          = 0x00C0058C
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData029]
+; SDIO_D2 <--> SW_GPIO_175
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P41 PAD0$"
+Offset          = 0x00C005B8
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData030]
+; SDIO_D2 <--> SW_GPIO_175
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P41 PAD1$"
+Offset          = 0x00C005BC
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData031]
+; SDIO_D3 <--> SW_GPIO_170
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P42 PAD0$"
+Offset          = 0x00C00590
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData032]
+; SDIO_D3 <--> SW_GPIO_170
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P42 PAD1$"
+Offset          = 0x00C00594
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData033]
+; SDIO_D3 <--> SW_GPIO_176
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P42 PAD0$"
+Offset          = 0x00C005C0
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData034]
+; SDIO_D3 <--> SW_GPIO_176
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P42 PAD1$"
+Offset          = 0x00C005C4
+AndData         = 0x00000000
+OrData          = 0x00023000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData035]
+; SPI0_CS0 <--> NW_GPIO_97
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P43 PAD0$"
+Offset          = 0x00C406A8
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData036]
+; SPI0_CS0 <--> NW_GPIO_97
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P43 PAD1$"
+Offset          = 0x00C406AC
+AndData         = 0x00000000
+OrData          = 0x0003FC49
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData037]
+; SPI0_CK <--> NW_GPIO_103
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P44 PAD0$"
+Offset          = 0x00C406D8
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData038]
+; SPI0_CK <--> NW_GPIO_103
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P44 PAD1$"
+Offset          = 0x00C406DC
+AndData         = 0x00000000
+OrData          = 0x0003FC4F
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData039]
+; SPI0_DIN <--> NW_GPIO_100
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P45 PAD0$"
+Offset          = 0x00C406C0
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData040]
+; SPI0_DIN <--> NW_GPIO_100
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P45 PAD1$"
+Offset          = 0x00C406C4
+AndData         = 0x00000000
+OrData          = 0x0003FC4C
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData041]
+; SPI0_DO <--> NW_GPIO_99
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P46 PAD0$"
+Offset          = 0x00C406B8
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData042]
+; SPI0_DO <--> NW_GPIO_99
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P46 PAD1$"
+Offset          = 0x00C406BC
+AndData         = 0x00000000
+OrData          = 0x0003FC4B
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData043]
+; ESPI_CS0 <--> NW_GPIO_105
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P54 PAD0$"
+Offset          = 0x00C406F0
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData044]
+; ESPI_CS0 <--> NW_GPIO_105
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P54 PAD1$"
+Offset          = 0x00C406F4
+AndData         = 0x00000000
+OrData          = 0x00001051
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData045]
+; ESPI_CS1 <--> NW_GPIO_106
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P55 PAD0$"
+Offset          = 0x00C406F8
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData046]
+; ESPI_CS1 <--> NW_GPIO_106
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P55 PAD1$"
+Offset          = 0x00C406FC
+AndData         = 0x00000000
+OrData          = 0x00001052
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData047]
+; ESPI_CK <--> NW_GPIO_104
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P56 PAD0$"
+Offset          = 0x00C406E8
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData048]
+; ESPI_CK <--> NW_GPIO_104
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P56 PAD1$"
+Offset          = 0x00C406EC
+AndData         = 0x00000000
+OrData          = 0x00001050
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData049]
+; ESPI_IO_0 <--> NW_GPIO_109
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P57 PAD0$"
+Offset          = 0x00C40700
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData050]
+; ESPI_IO_0 <--> NW_GPIO_109
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P57 PAD1$"
+Offset          = 0x00C40704
+AndData         = 0x00000000
+OrData          = 0x0001D054
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData051]
+; ESPI_IO_1 <--> NW_GPIO_110
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P58 PAD0$"
+Offset          = 0x00C40708
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData052]
+; ESPI_IO_1 <--> NW_GPIO_110
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P58 PAD1$"
+Offset          = 0x00C4070C
+AndData         = 0x00000000
+OrData          = 0x00001055
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData053]
+; USB0_EN_OC <--> NW_GPIO_203
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P62 PAD0$"
+Offset          = 0x00C40580
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData054]
+; USB0_EN_OC <--> NW_GPIO_203
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P62 PAD1$"
+Offset          = 0x00C40584
+AndData         = 0x00000000
+OrData          = 0x0003F000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData055]
+; USB1_EN_OC <--> NW_GPIO_204
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P67 PAD0$"
+Offset          = 0x00C40588
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData056]
+; USB1_EN_OC <--> NW_GPIO_204
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P67 PAD1$"
+Offset          = 0x00C4058C
+AndData         = 0x00000000
+OrData          = 0x0003F000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData057]
+; PCIE_A_RST <--> W_PMU_PLTRST_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P75 PAD0$"
+Offset          = 0x00C70628
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData058]
+; PCIE_A_RST <--> W_PMU_PLTRST_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P75 PAD1$"
+Offset          = 0x00C7062C
+AndData         = 0x00000000
+OrData          = 0x0003C000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData059]
+; HDMI_HPD/DP1_HPD <--> NW_GPIO_199
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P104 PAD0$"
+Offset          = 0x00C40560
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData060]
+; HDMI_HPD/DP1_HPD <--> NW_GPIO_199
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P104 PAD1$"
+Offset          = 0x00C40564
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData061]
+; GPIO0/CAM0_PWR <--> N_GPIO_66
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P108 PAD0$"
+Offset          = 0x00C506B0
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData062]
+; GPIO0/CAM0_PWR <--> N_GPIO_66
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P108 PAD1$"
+Offset          = 0x00C506B4
+AndData         = 0x00000000
+OrData          = 0x0001D05F
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData063]
+; GPIO1/CAM1_PWR <--> N_GPIO_67
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P109 PAD0$"
+Offset          = 0x00C506B8
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData064]
+; GPIO1/CAM1_PWR <--> N_GPIO_67
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P109 PAD1$"
+Offset          = 0x00C506BC
+AndData         = 0x00000000
+OrData          = 0x0001D060
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData065]
+; GPIO2/CAM0_RST <--> N_GPIO_64
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P110 PAD0$"
+Offset          = 0x00C506A0
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData066]
+; GPIO2/CAM0_RST <--> N_GPIO_64
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P110 PAD1$"
+Offset          = 0x00C506A4
+AndData         = 0x00000000
+OrData          = 0x0001D05D
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData067]
+; GPIO3/CAM1_RST <--> N_GPIO_65
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P111 PAD0$"
+Offset          = 0x00C506A8
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData068]
+; GPIO3/CAM1_RST <--> N_GPIO_65
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P111 PAD1$"
+Offset          = 0x00C506AC
+AndData         = 0x00000000
+OrData          = 0x0001D05E
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData069]
+; GPIO4/HDA_RST <--> NW_GPIO_84
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P112 PAD0$"
+Offset          = 0x00C40660
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData070]
+; GPIO4/HDA_RST <--> NW_GPIO_84
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P112 PAD1$"
+Offset          = 0x00C40664
+AndData         = 0x00000000
+OrData          = 0x0000103D
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData071]
+; GPIO7 <--> N_GPIO_13
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P115 PAD0$"
+Offset          = 0x00C50568
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData072]
+; GPIO7 <--> N_GPIO_13
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P115 PAD1$"
+Offset          = 0x00C5056C
+AndData         = 0x00000000
+OrData          = 0x0001F070
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData073]
+; GPIO8 <--> N_GPIO_14
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P116 PAD0$"
+Offset          = 0x00C50570
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData074]
+; GPIO8 <--> N_GPIO_14
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P116 PAD1$"
+Offset          = 0x00C50574
+AndData         = 0x00000000
+OrData          = 0x0001F071
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData075]
+; GPIO9 <--> N_GPIO_2
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P117 PAD0$"
+Offset          = 0x00C50510
+AndData         = 0x00000000
+OrData          = 0x04000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData076]
+; GPIO9 <--> N_GPIO_2
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P117 PAD1$"
+Offset          = 0x00C50514
+AndData         = 0x00000000
+OrData          = 0x0001F065
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData077]
+; GPIO10 <--> N_GPIO_3
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P118 PAD0$"
+Offset          = 0x00C50518
+AndData         = 0x00000000
+OrData          = 0x04000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData078]
+; GPIO10 <--> N_GPIO_3
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P118 PAD1$"
+Offset          = 0x00C5051C
+AndData         = 0x00000000
+OrData          = 0x0001F066
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData079]
+; GPIO11 <--> N_GPIO_4
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P119 PAD0$"
+Offset          = 0x00C50520
+AndData         = 0x00000000
+OrData          = 0x04000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData080]
+; GPIO11 <--> N_GPIO_4
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P119 PAD1$"
+Offset          = 0x00C50524
+AndData         = 0x00000000
+OrData          = 0x0001F067
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData081]
+; I2C_PM_CK <--> W_GPIO_139
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P121 PAD0$"
+Offset          = 0x00C70578
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData082]
+; I2C_PM_CK <--> W_GPIO_139
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P121 PAD1$"
+Offset          = 0x00C7057C
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData083]
+; I2C_PM_DAT <--> W_GPIO_138
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P122 PAD0$"
+Offset          = 0x00C70570
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData084]
+; I2C_PM_DAT <--> W_GPIO_138
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P122 PAD1$"
+Offset          = 0x00C70574
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData085]
+; BOOT_SEL0 <--> N_GPIO_24
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P123 PAD0$"
+Offset          = 0x00C505C0
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData086]
+; BOOT_SEL0 <--> N_GPIO_24
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P123 PAD1$"
+Offset          = 0x00C505C4
+AndData         = 0x00000000
+OrData          = 0x0001F035
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData087]
+; BOOT_SEL1 <--> N_GPIO_23
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P124 PAD0$"
+Offset          = 0x00C505B8
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData088]
+; BOOT_SEL1 <--> N_GPIO_23
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P124 PAD1$"
+Offset          = 0x00C505BC
+AndData         = 0x00000000
+OrData          = 0x0001F034
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData089]
+; BOOT_SEL2 <--> N_GPIO_22
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P125 PAD0$"
+Offset          = 0x00C505B0
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData090]
+; BOOT_SEL2 <--> N_GPIO_22
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P125 PAD1$"
+Offset          = 0x00C505B4
+AndData         = 0x00000000
+OrData          = 0x0001F033
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData091]
+; SER0_TX <--> N_GPIO_39
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P129 PAD0$"
+Offset          = 0x00C50638
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData092]
+; SER0_TX <--> N_GPIO_39
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P129 PAD1$"
+Offset          = 0x00C5063C
+AndData         = 0x00000000
+OrData          = 0x00003044
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData093]
+; SER0_RX <--> N_GPIO_38
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P130 PAD0$"
+Offset          = 0x00C50630
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData094]
+; SER0_RX <--> N_GPIO_38
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P130 PAD1$"
+Offset          = 0x00C50634
+AndData         = 0x00000000
+OrData          = 0x00003043
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData095]
+; SER0_RTS <--> N_GPIO_40
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P131 PAD0$"
+Offset          = 0x00C50640
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData096]
+; SER0_RTS <--> N_GPIO_40
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P131 PAD1$"
+Offset          = 0x00C50644
+AndData         = 0x00000000
+OrData          = 0x00003145
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData097]
+; SER0_CTS <--> N_GPIO_41
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P132 PAD0$"
+Offset          = 0x00C50648
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData098]
+; SER0_CTS <--> N_GPIO_41
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P132 PAD1$"
+Offset          = 0x00C5064C
+AndData         = 0x00000000
+OrData          = 0x00023146
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData099]
+; SER1_TX <--> N_GPIO_43
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P134 PAD0$"
+Offset          = 0x00C50658
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData100]
+; SER1_TX <--> N_GPIO_43
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P134 PAD1$"
+Offset          = 0x00C5065C
+AndData         = 0x00000000
+OrData          = 0x00003048
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData101]
+; SER1_RX <--> N_GPIO_42
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P135 PAD0$"
+Offset          = 0x00C50650
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData102]
+; SER1_RX <--> N_GPIO_42
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P135 PAD1$"
+Offset          = 0x00C50654
+AndData         = 0x00000000
+OrData          = 0x00003047
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData103]
+; SER2_TX <--> N_GPIO_47
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P136 PAD0$"
+Offset          = 0x00C50678
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData104]
+; SER2_TX <--> N_GPIO_47
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P136 PAD1$"
+Offset          = 0x00C5067C
+AndData         = 0x00000000
+OrData          = 0x0000304C
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData105]
+; SER2_RX <--> N_GPIO_46
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P137 PAD0$"
+Offset          = 0x00C50670
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData106]
+; SER2_RX <--> N_GPIO_46
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P137 PAD1$"
+Offset          = 0x00C50674
+AndData         = 0x00000000
+OrData          = 0x0000304B
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData107]
+; SER2_RTS <--> N_GPIO_48
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P138 PAD0$"
+Offset          = 0x00C50680
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData108]
+; SER2_RTS <--> N_GPIO_48
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P138 PAD1$"
+Offset          = 0x00C50684
+AndData         = 0x00000000
+OrData          = 0x0000304D
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData109]
+; SER2_CTS <--> N_GPIO_49
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P139 PAD0$"
+Offset          = 0x00C50688
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData110]
+; SER2_CTS <--> N_GPIO_49
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P139 PAD1$"
+Offset          = 0x00C5068C
+AndData         = 0x00000000
+OrData          = 0x0000304E
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData111]
+; SER3_TX <--> NW_GPIO_113
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P140 PAD0$"
+Offset          = 0x00C40720
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData112]
+; SER3_TX <--> NW_GPIO_113
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P140 PAD1$"
+Offset          = 0x00C40724
+AndData         = 0x00000000
+OrData          = 0x00003058
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData113]
+; SER3_RX <--> NW_GPIO_112
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P141 PAD0$"
+Offset          = 0x00C40718
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData114]
+; SER3_RX <--> NW_GPIO_112
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC P141 PAD1$"
+Offset          = 0x00C4071C
+AndData         = 0x00000000
+OrData          = 0x00003057
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData115]
+; CSI1_TX+/I2C_CAM1_CK <--> W_GPIO_135
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S1 PAD0$"
+Offset          = 0x00C70558
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData116]
+; CSI1_TX+/I2C_CAM1_CK <--> W_GPIO_135
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S1 PAD1$"
+Offset          = 0x00C7055C
+AndData         = 0x00000000
+OrData          = 0x00006700
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData117]
+; CSI1_TX-/I2C_CAM1_DAT <--> W_GPIO_134
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S2 PAD0$"
+Offset          = 0x00C70550
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData118]
+; CSI1_TX-/I2C_CAM1_DAT <--> W_GPIO_134
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S2 PAD1$"
+Offset          = 0x00C70554
+AndData         = 0x00000000
+OrData          = 0x00006700
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData119]
+; CSI0_TX+/I2C_CAM0_CK <--> W_GPIO_133
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S5 PAD0$"
+Offset          = 0x00C70548
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData120]
+; CSI0_TX+/I2C_CAM0_CK <--> W_GPIO_133
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S5 PAD1$"
+Offset          = 0x00C7054C
+AndData         = 0x00000000
+OrData          = 0x00012700
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData121]
+; CAM_MCK <--> W_OSC_CLK_OUT_0
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S6 PAD0$"
+Offset          = 0x00C705F0
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData122]
+; CAM_MCK <--> W_OSC_CLK_OUT_0
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S6 PAD1$"
+Offset          = 0x00C705F4
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData123]
+; CSI0_TX-/I2C_CAM0_DAT <--> W_GPIO_132
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S7 PAD0$"
+Offset          = 0x00C70540
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData124]
+; CSI0_TX-/I2C_CAM0_DAT <--> W_GPIO_132
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S7 PAD1$"
+Offset          = 0x00C70544
+AndData         = 0x00000000
+OrData          = 0x00012700
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData125]
+; AUDIO_MCK <--> NW_GPIO_84
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S38 PAD0$"
+Offset          = 0x00C40660
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData126]
+; AUDIO_MCK <--> NW_GPIO_84
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S38 PAD1$"
+Offset          = 0x00C40664
+AndData         = 0x00000000
+OrData          = 0x0000103D
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData127]
+; I2S0_LRCK <--> NW_GPIO_86
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S39 PAD0$"
+Offset          = 0x00C40670
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData128]
+; I2S0_LRCK <--> NW_GPIO_86
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S39 PAD1$"
+Offset          = 0x00C40674
+AndData         = 0x00000000
+OrData          = 0x0003D03F
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData129]
+; I2S0_SDOUT <--> NW_GPIO_88
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S40 PAD0$"
+Offset          = 0x00C40680
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData130]
+; I2S0_SDOUT <--> NW_GPIO_88
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S40 PAD1$"
+Offset          = 0x00C40684
+AndData         = 0x00000000
+OrData          = 0x0003D041
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData131]
+; I2S0_SDIN <--> NW_GPIO_87
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S41 PAD0$"
+Offset          = 0x00C40678
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData132]
+; I2S0_SDIN <--> NW_GPIO_87
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S41 PAD1$"
+Offset          = 0x00C4067C
+AndData         = 0x00000000
+OrData          = 0x00025240
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData133]
+; I2S0_CK <--> NW_GPIO_85
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S42 PAD0$"
+Offset          = 0x00C40668
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData134]
+; I2S0_CK <--> NW_GPIO_85
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S42 PAD1$"
+Offset          = 0x00C4066C
+AndData         = 0x00000000
+OrData          = 0x0003D03E
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData135]
+; I2C_GP_CK <--> W_GPIO_137
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S48 PAD0$"
+Offset          = 0x00C70568
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData136]
+; I2C_GP_CK <--> W_GPIO_137
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S48 PAD1$"
+Offset          = 0x00C7056C
+AndData         = 0x00000000
+OrData          = 0x00013300
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData137]
+; I2C_GP_DAT <--> W_GPIO_136
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S49 PAD0$"
+Offset          = 0x00C70560
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData138]
+; I2C_GP_DAT <--> W_GPIO_136
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S49 PAD1$"
+Offset          = 0x00C70564
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData139]
+; HDA_SYNC/I2S2_LRCK <--> W_GPIO_147
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S50 PAD0$"
+Offset          = 0x00C70588
+AndData         = 0x00000000
+OrData          = 0x44000C00
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData140]
+; HDA_SYNC/I2S2_LRCK <--> W_GPIO_147
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S50 PAD1$"
+Offset          = 0x00C7058C
+AndData         = 0x00000000
+OrData          = 0x0003D000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData141]
+; HDA_SDO/I2S2_SDOUT <--> W_GPIO_149
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S51 PAD0$"
+Offset          = 0x00C70598
+AndData         = 0x00000000
+OrData          = 0x44000C00
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData142]
+; HDA_SDO/I2S2_SDOUT <--> W_GPIO_149
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S51 PAD1$"
+Offset          = 0x00C7059C
+AndData         = 0x00000000
+OrData          = 0x0003D000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData143]
+; HDA_SDI/I2S2_SDIN <--> W_GPIO_148
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S52 PAD0$"
+Offset          = 0x00C70590
+AndData         = 0x00000000
+OrData          = 0x44000C00
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData144]
+; HDA_SDI/I2S2_SDIN <--> W_GPIO_148
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S52 PAD1$"
+Offset          = 0x00C70594
+AndData         = 0x00000000
+OrData          = 0x0003C000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData145]
+; HDA_CK/I2S2_CK <--> W_GPIO_146
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S53 PAD0$"
+Offset          = 0x00C70580
+AndData         = 0x00000000
+OrData          = 0x44000C00
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData146]
+; HDA_CK/I2S2_CK <--> W_GPIO_146
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S53 PAD1$"
+Offset          = 0x00C70584
+AndData         = 0x00000000
+OrData          = 0x0003D000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData147]
+; SATA_ACT <--> N_GPIO_26
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S54 PAD0$"
+Offset          = 0x00C505D0
+AndData         = 0x00000000
+OrData          = 0x44001400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData148]
+; SATA_ACT <--> N_GPIO_26
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S54 PAD1$"
+Offset          = 0x00C505D4
+AndData         = 0x00000000
+OrData          = 0x00001037
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData149]
+; DP0_HPD <--> NW_GPIO_200
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S98 PAD0$"
+Offset          = 0x00C40568
+AndData         = 0x00000000
+OrData          = 0x44000802
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData150]
+; DP0_HPD <--> NW_GPIO_200
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S98 PAD1$"
+Offset          = 0x00C4056C
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData151]
+; LCD1_BKLT_EN <--> NW_GPIO_197
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S107 PAD0$"
+Offset          = 0x00C40550
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData152]
+; LCD1_BKLT_EN <--> NW_GPIO_197
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S107 PAD1$"
+Offset          = 0x00C40554
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData153]
+; LCD1_VDD_EN <--> NW_GPIO_196
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S116 PAD0$"
+Offset          = 0x00C40548
+AndData         = 0x00000000
+OrData          = 0x44000200
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData154]
+; LCD1_VDD_EN <--> NW_GPIO_196
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S116 PAD1$"
+Offset          = 0x00C4054C
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData155]
+; LCD1_BKLT_PWM <--> NW_GPIO_198
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S122 PAD0$"
+Offset          = 0x00C40558
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData156]
+; LCD1_BKLT_PWM <--> NW_GPIO_198
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S122 PAD1$"
+Offset          = 0x00C4055C
+AndData         = 0x00000000
+OrData          = 0x00001000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData157]
+; LCD0_VDD_EN <--> NW_GPIO_193
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S133 PAD0$"
+Offset          = 0x00C40530
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData158]
+; LCD0_VDD_EN <--> NW_GPIO_193
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S133 PAD1$"
+Offset          = 0x00C40534
+AndData         = 0x00000000
+OrData          = 0x00005000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData159]
+; I2C_LCD_CK <--> W_GPIO_127
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S139 PAD0$"
+Offset          = 0x00C70518
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData160]
+; I2C_LCD_CK <--> W_GPIO_127
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S139 PAD1$"
+Offset          = 0x00C7051C
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData161]
+; I2C_LCD_DAT <--> W_GPIO_126
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S140 PAD0$"
+Offset          = 0x00C70510
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData162]
+; I2C_LCD_DAT <--> W_GPIO_126
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S140 PAD1$"
+Offset          = 0x00C70514
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData163]
+; eDP0_HPD <--> NW_PMC_SPI_FS1
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S144 PAD0$"
+Offset          = 0x00C40598
+AndData         = 0x00000000
+OrData          = 0x44000800
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData164]
+; eDP0_HPD <--> NW_PMC_SPI_FS1
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S144 PAD1$"
+Offset          = 0x00C4059C
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData165]
+; PCIE_WAKE <--> SW_GPIO_206
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S146 PAD0$"
+Offset          = 0x00C00508
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData166]
+; PCIE_WAKE <--> SW_GPIO_206
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S146 PAD1$"
+Offset          = 0x00C0050C
+AndData         = 0x00000000
+OrData          = 0x0003F000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData167]
+; LID <--> N_GPIO_6
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S148 PAD0$"
+Offset          = 0x00C50530
+AndData         = 0x00000000
+OrData          = 0x46080102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData168]
+; LID <--> N_GPIO_6
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S148 PAD1$"
+Offset          = 0x00C50534
+AndData         = 0x00000000
+OrData          = 0x00003069
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData169]
+; SLEEP <--> N_GPIO_7
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S149 PAD0$"
+Offset          = 0x00C50538
+AndData         = 0x00000000
+OrData          = 0x42880102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData170]
+; SLEEP <--> N_GPIO_7
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S149 PAD1$"
+Offset          = 0x00C5053C
+AndData         = 0x00000000
+OrData          = 0x0000306A
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData171]
+; CHARGER_PRSNT <--> W_PMU_AC_PRESENT
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S152 PAD0$"
+Offset          = 0x00C70618
+AndData         = 0x00000000
+OrData          = 0x44000201
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData172]
+; CHARGER_PRSNT <--> W_PMU_AC_PRESENT
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S152 PAD1$"
+Offset          = 0x00C7061C
+AndData         = 0x00000000
+OrData          = 0x00003000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData173]
+; CARRIER_STBY <--> W_PMU_SLP_S3_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S153 PAD0$"
+Offset          = 0x00C70648
+AndData         = 0x00000000
+OrData          = 0x44000400
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData174]
+; CARRIER_STBY <--> W_PMU_SLP_S3_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S153 PAD1$"
+Offset          = 0x00C7064C
+AndData         = 0x00000000
+OrData          = 0x0003C000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData175]
+; FORCE_RECOV <--> N_GPIO_21
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S155 PAD0$"
+Offset          = 0x00C505A8
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData176]
+; FORCE_RECOV <--> N_GPIO_21
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S155 PAD1$"
+Offset          = 0x00C505AC
+AndData         = 0x00000000
+OrData          = 0x00003032
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData177]
+; BATLOW <--> W_PMU_BATLOW_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S156 PAD0$"
+Offset          = 0x00C70620
+AndData         = 0x00000000
+OrData          = 0x44000402
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData178]
+; BATLOW <--> W_PMU_BATLOW_B
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S156 PAD1$"
+Offset          = 0x00C70624
+AndData         = 0x00000000
+OrData          = 0x0003F000
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData179]
+; TEST <--> N_GPIO_25
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S157 PAD0$"
+Offset          = 0x00C505C8
+AndData         = 0x00000000
+OrData          = 0x44000102
+DataSize        = 0x04
+DataType        = 0x04
+
+[GpioData180]
+; TEST <--> N_GPIO_25
+StructureType   = GpioDataRecord
+GpioLabel       = "SMARC S157 PAD1$"
+Offset          = 0x00C505CC
+AndData         = 0x00000000
+OrData          = 0x0001F036
+DataSize        = 0x04
+DataType        = 0x04
+
+;
+; SMARC module pinout GPIO list
+;
+;===========+=======================+================================+============+===========+========================
+; SMARC pin | SMARC label           | GPIO label                     | SoC Pin    | Interrupt | GPIO Offset
+;-----------+-----------------------+--------------------------------+------------+-----------+------------------------
+; P1        | SMB_ALERT_1V8         | SW_SMB_ALERTB                  | R63        | -C-----   | 0x00C005F8
+; P31       | SPI0_CS1              | NW_GPIO_98                     | C57        | IC---4A   | 0x00C406B0
+; P33       | SDIO_WP               | SW_GPIO_186                    | AB55       | -C-----   | 0x00C005E0
+; P34       | SDIO_CMD              | SW_GPIO_171 & SW_GPIO_178      | T57 & AC52 | -C-----   | 0x00C00598 & 0x00C005D0
+; P35       | SDIO_CD               | SW_GPIO_177                    | AB54       | -C-----   | 0x00C005C8
+; P36       | SDIO_CK               | SW_GPIO_166 & SW_GPIO_172      | P58 & AB58 | -C-----   | 0x00C00570 & 0x00C005A0
+; P37       | SDIO_PWR_EN           | SW_GPIO_183                    | P51        | -CM----   | 0x00C005F0
+; P39       | SDIO_D0               | SW_GPIO_167 & SW_GPIO_173      | T52 & AC49 | -C-----   | 0x00C00578 & 0x00C005A8
+; P40       | SDIO_D1               | SW_GPIO_168 & SW_GPIO_174      | P57 & AC48 | -C-----   | 0x00C00580 & 0x00C005B0
+; P41       | SDIO_D2               | SW_GPIO_169 & SW_GPIO_175      | T54 & AC51 | -C-----   | 0x00C00588 & 0x00C005B8
+; P42       | SDIO_D3               | SW_GPIO_170 & SW_GPIO_176      | T55 & AB51 | -C-----   | 0x00C00590 & 0x00C005C0
+; P43       | SPI0_CS0              | NW_GPIO_97                     | B57        | IC---49   | 0x00C406A8
+; P44       | SPI0_CK               | NW_GPIO_103                    | C56        | IC---4F   | 0x00C406D8
+; P45       | SPI0_DIN              | NW_GPIO_100                    | B58        | IC---4C   | 0x00C406C0
+; P46       | SPI0_DO               | NW_GPIO_99                     | A58        | IC---4B   | 0x00C406B8
+; P54       | ESPI_CS0              | NW_GPIO_105                    | F52        | IC---51   | 0x00C406F0
+; P55       | ESPI_CS1              | NW_GPIO_106                    | H52        | IC---52   | 0x00C406F8
+; P56       | ESPI_CK               | NW_GPIO_104                    | F54        | IC---50   | 0x00C406E8
+; P57       | ESPI_IO_0             | NW_GPIO_109                    | H54        | IC---54   | 0x00C40700
+; P58       | ESPI_IO_1             | NW_GPIO_110                    | J52        | IC---55   | 0x00C40708
+; P62       | USB0_EN_OC            | NW_GPIO_203                    | B55        | -C-----   | 0x00C40580
+; P67       | USB1_EN_OC            | NW_GPIO_204                    | C55        | -C-----   | 0x00C40588
+; P71       | USB2_EN_OC            | NW_GPIO_204                    | C55        | -C-----   | 0x00C40588
+; P74       | USB3_EN_OC            | NW_GPIO_204                    | C55        | -C-----   | 0x00C40588
+; P75       | PCIE_A_RST            | W_PMU_PLTRST_B                 | AG57       | -------   | 0x00C70628
+; P76       | USB4_EN_OC            | NW_GPIO_204                    | C55        | -C-----   | 0x00C40588
+; P104      | HDMI_HPD/DP1_HPD      | NW_GPIO_199                    | A50        | -C-----   | 0x00C40560
+; P108      | GPIO0/CAM0_PWR        | N_GPIO_66                      | M37        | ICM--5F   | 0x00C506B0
+; P109      | GPIO1/CAM1_PWR        | N_GPIO_67                      | F30        | ICM--60   | 0x00C506B8
+; P110      | GPIO2/CAM0_RST        | N_GPIO_64                      | J34        | ICM--5D   | 0x00C506A0
+; P111      | GPIO3/CAM1_RST        | N_GPIO_65                      | H30        | ICM--5E   | 0x00C506A8
+; P112      | GPIO4/HDA_RST         | NW_GPIO_84                     | K58        | IC---3D   | 0x00C40660
+; P115      | GPIO7                 | N_GPIO_13                      | C30        | ICM--70   | 0x00C50568
+; P116      | GPIO8                 | N_GPIO_14                      | C38        | ICM--71   | 0x00C50570
+; P117      | GPIO9                 | N_GPIO_2                       | C39        | ICM--65   | 0x00C50510
+; P118      | GPIO10                | N_GPIO_3                       | B39        | ICM--66   | 0x00C50518
+; P119      | GPIO11                | N_GPIO_4                       | B35        | ICM--67   | 0x00C50520
+; P121      | I2C_PM_CK             | W_GPIO_139                     | T62        | -CM----   | 0x00C70578
+; P122      | I2C_PM_DAT            | W_GPIO_138                     | T61        | -CM----   | 0x00C70570
+; P123      | BOOT_SEL0             | N_GPIO_24                      | C25        | ICM--35   | 0x00C505C0
+; P124      | BOOT_SEL1             | N_GPIO_23                      | B25        | ICM--34   | 0x00C505B8
+; P125      | BOOT_SEL2             | N_GPIO_22                      | A26        | ICM--33   | 0x00C505B0
+; P126      | RESET_OUT             | W_PMU_PLTRST_B                 | AG57       | -------   | 0x00C70628
+; P129      | SER0_TX               | N_GPIO_39                      | B45        | ICM--44   | 0x00C50638
+; P130      | SER0_RX               | N_GPIO_38                      | C45        | ICM--43   | 0x00C50630
+; P131      | SER0_RTS              | N_GPIO_40                      | A46        | ICM--45   | 0x00C50640
+; P132      | SER0_CTS              | N_GPIO_41                      | C44        | ICM--46   | 0x00C50648
+; P134      | SER1_TX               | N_GPIO_43                      | B43        | ICM--48   | 0x00C50658
+; P135      | SER1_RX               | N_GPIO_42                      | C43        | ICM--47   | 0x00C50650
+; P136      | SER2_TX               | N_GPIO_47                      | H41        | ICM--4C   | 0x00C50678
+; P137      | SER2_RX               | N_GPIO_46                      | J41        | ICM--4B   | 0x00C50670
+; P138      | SER2_RTS              | N_GPIO_48                      | L41        | ICM--4D   | 0x00C50680
+; P139      | SER2_CTS              | N_GPIO_49                      | M41        | ICM--4E   | 0x00C50688
+; P140      | SER3_TX               | NW_GPIO_113                    | F61        | IC---58   | 0x00C40720
+; P141      | SER3_RX               | NW_GPIO_112                    | K55        | IC---57   | 0x00C40718
+;-----------+-----------------------+--------------------------------+------------+-----------+------------------------
+; S1        | CSI1_TX+/I2C_CAM1_CK  | W_GPIO_135                     | AP51       | -CM----   | 0x00C70558
+; S2        | CSI1_TX-/I2C_CAM1_DAT | W_GPIO_134                     | AP49       | -CM----   | 0x00C70550
+; S5        | CSI0_TX+/I2C_CAM0_CK  | W_GPIO_133                     | AP54       | -CM----   | 0x00C70548
+; S6        | CAM_MCK               | W_OSC_CLK_OUT_0                | AG62       | -------   | 0x00C705F0
+; S7        | CSI0_TX-/I2C_CAM0_DAT | W_GPIO_132                     | AP52       | -CM----   | 0x00C70540
+; S38       | AUDIO_MCK             | NW_GPIO_84                     | K58        | IC---3D   | 0x00C40660
+; S39       | I2S0_LRCK             | NW_GPIO_86                     | M57        | IC---3F   | 0x00C40670
+; S40       | I2S0_SDOUT            | NW_GPIO_88                     | M58        | IC---41   | 0x00C40680
+; S41       | I2S0_SDIN             | NW_GPIO_87                     | K59        | IC---40   | 0x00C40678
+; S42       | I2S0_CK               | NW_GPIO_85                     | H59        | IC---3E   | 0x00C40668
+; S48       | I2C_GP_CK             | W_GPIO_137                     | AK61       | -CM----   | 0x00C70568
+; S49       | I2C_GP_DAT            | W_GPIO_136                     | AL63       | -CM----   | 0x00C70560
+; S50       | HDA_SYNC/I2S2_LRCK    | W_GPIO_147                     | AK58       | -CM----   | 0x00C70588
+; S51       | HDA_SDO/I2S2_SDOUT    | W_GPIO_149                     | AM54       | -CM----   | 0x00C70598
+; S52       | HDA_SDI/I2S2_SDIN     | W_GPIO_148                     | AK51       | -CM----   | 0x00C70590
+; S53       | HDA_CK/I2S2_CK        | W_GPIO_146                     | AM48       | -CM----   | 0x00C70580
+; S54       | SATA_ACT              | N_GPIO_26                      | C31        | ICM--37   | 0x00C505D0
+; S55       | USB5_EN_OC            | NW_GPIO_204                    | C55        | -C-----   | 0x00C40588
+; S76       | PCIE_B_RST            | W_PMU_PLTRST_B                 | AG57       | -------   | 0x00C70628
+; S77       | PCIE_C_RST            | W_PMU_PLTRST_B                 | AG57       | -------   | 0x00C70628
+; S98       | DP0_HPD               | NW_GPIO_200                    | C50        | -C-----   | 0x00C40568
+; S107      | LCD1_BKLT_EN          | NW_GPIO_197                    | B53        | -C-----   | 0x00C40550
+; S116      | LCD1_VDD_EN           | NW_GPIO_196                    | C52        | -C-----   | 0x00C40548
+; S122      | LCD1_BKLT_PWM         | NW_GPIO_198                    | C53        | -C-----   | 0x00C40558
+; S133      | LCD0_VDD_EN           | NW_GPIO_193                    | C47        | -C-----   | 0x00C40530
+; S139      | I2C_LCD_CK            | W_GPIO_127                     | AM61       | -CM----   | 0x00C70518
+; S140      | I2C_LCD_DAT           | W_GPIO_126                     | AN62       | -CM----   | 0x00C70510
+; S144      | eDP0_HPD              | NW_PMC_SPI_FS1                 | P48        | -------   | 0x00C40598
+; S146      | PCIE_WAKE             | SW_GPIO_206                    | P62        | -CM----   | 0x00C00508
+; S148      | LID                   | N_GPIO_6                       | B31        | ICM--69   | 0x00C50530
+; S149      | SLEEP                 | N_GPIO_7                       | H39        | ICM--6A   | 0x00C50538
+; S152      | CHARGER_PRSNT         | W_PMU_AC_PRESENT               | AK49       | -------   | 0x00C70618
+; S153      | CARRIER_STBY          | W_PMU_SLP_S3_B                 | AC62       | -------   | 0x00C70648
+; S155      | FORCE_RECOV           | N_GPIO_21                      | C26        | ICM--32   | 0x00C505A8
+; S156      | BATLOW                | W_PMU_BATLOW_B                 | AH51       | -------   | 0x00C70620
+; S157      | TEST                  | N_GPIO_25                      | C27        | ICM--36   | 0x00C505C8
+;===========+=======================+================================+============+===========+========================
+
+;
+; Structure lists uses the same format as the Structures section to define a single data
+; blob.  This is then added to the existing structure that referenced it.
+;
+; Struct_n = Section
+[M24M02MapDataList]
+Struct_001 = M24M02MapData001
+Struct_002 = M24M02MapData002
+Struct_003 = M24M02MapData003
+Struct_004 = M24M02MapData004
+
+[GpioDataList]
+Struct_001 = GpioData001
+Struct_002 = GpioData002
+Struct_003 = GpioData003
+Struct_004 = GpioData004
+Struct_005 = GpioData005
+Struct_006 = GpioData006
+Struct_007 = GpioData007
+Struct_008 = GpioData008
+Struct_009 = GpioData009
+Struct_010 = GpioData010
+Struct_011 = GpioData011
+Struct_012 = GpioData012
+Struct_013 = GpioData013
+Struct_014 = GpioData014
+Struct_015 = GpioData015
+Struct_016 = GpioData016
+Struct_017 = GpioData017
+Struct_018 = GpioData018
+Struct_019 = GpioData019
+Struct_020 = GpioData020
+Struct_021 = GpioData021
+Struct_022 = GpioData022
+Struct_023 = GpioData023
+Struct_024 = GpioData024
+Struct_025 = GpioData025
+Struct_026 = GpioData026
+Struct_027 = GpioData027
+Struct_028 = GpioData028
+Struct_029 = GpioData029
+Struct_030 = GpioData030
+Struct_031 = GpioData031
+Struct_032 = GpioData032
+Struct_033 = GpioData033
+Struct_034 = GpioData034
+Struct_035 = GpioData035
+Struct_036 = GpioData036
+Struct_037 = GpioData037
+Struct_038 = GpioData038
+Struct_039 = GpioData039
+Struct_040 = GpioData040
+Struct_041 = GpioData041
+Struct_042 = GpioData042
+Struct_043 = GpioData043
+Struct_044 = GpioData044
+Struct_045 = GpioData045
+Struct_046 = GpioData046
+Struct_047 = GpioData047
+Struct_048 = GpioData048
+Struct_049 = GpioData049
+Struct_050 = GpioData050
+Struct_051 = GpioData051
+Struct_052 = GpioData052
+Struct_053 = GpioData053
+Struct_054 = GpioData054
+Struct_055 = GpioData055
+Struct_056 = GpioData056
+Struct_057 = GpioData057
+Struct_058 = GpioData058
+Struct_059 = GpioData059
+Struct_060 = GpioData060
+Struct_061 = GpioData061
+Struct_062 = GpioData062
+Struct_063 = GpioData063
+Struct_064 = GpioData064
+Struct_065 = GpioData065
+Struct_066 = GpioData066
+Struct_067 = GpioData067
+Struct_068 = GpioData068
+Struct_069 = GpioData069
+Struct_070 = GpioData070
+Struct_071 = GpioData071
+Struct_072 = GpioData072
+Struct_073 = GpioData073
+Struct_074 = GpioData074
+Struct_075 = GpioData075
+Struct_076 = GpioData076
+Struct_077 = GpioData077
+Struct_078 = GpioData078
+Struct_079 = GpioData079
+Struct_080 = GpioData080
+Struct_081 = GpioData081
+Struct_082 = GpioData082
+Struct_083 = GpioData083
+Struct_084 = GpioData084
+Struct_085 = GpioData085
+Struct_086 = GpioData086
+Struct_087 = GpioData087
+Struct_088 = GpioData088
+Struct_089 = GpioData089
+Struct_090 = GpioData090
+Struct_091 = GpioData091
+Struct_092 = GpioData092
+Struct_093 = GpioData093
+Struct_094 = GpioData094
+Struct_095 = GpioData095
+Struct_096 = GpioData096
+Struct_097 = GpioData097
+Struct_098 = GpioData098
+Struct_099 = GpioData099
+Struct_100 = GpioData100
+Struct_101 = GpioData101
+Struct_102 = GpioData102
+Struct_103 = GpioData103
+Struct_104 = GpioData104
+Struct_105 = GpioData105
+Struct_106 = GpioData106
+Struct_107 = GpioData107
+Struct_108 = GpioData108
+Struct_109 = GpioData109
+Struct_110 = GpioData110
+Struct_111 = GpioData111
+Struct_112 = GpioData112
+Struct_113 = GpioData113
+Struct_114 = GpioData114
+Struct_115 = GpioData115
+Struct_116 = GpioData116
+Struct_117 = GpioData117
+Struct_118 = GpioData118
+Struct_119 = GpioData119
+Struct_120 = GpioData120
+Struct_121 = GpioData121
+Struct_122 = GpioData122
+Struct_123 = GpioData123
+Struct_124 = GpioData124
+Struct_125 = GpioData125
+Struct_126 = GpioData126
+Struct_127 = GpioData127
+Struct_128 = GpioData128
+Struct_129 = GpioData129
+Struct_130 = GpioData130
+Struct_131 = GpioData131
+Struct_132 = GpioData132
+Struct_133 = GpioData133
+Struct_134 = GpioData134
+Struct_135 = GpioData135
+Struct_136 = GpioData136
+Struct_137 = GpioData137
+Struct_138 = GpioData138
+Struct_139 = GpioData139
+Struct_140 = GpioData140
+Struct_141 = GpioData141
+Struct_142 = GpioData142
+Struct_143 = GpioData143
+Struct_144 = GpioData144
+Struct_145 = GpioData145
+Struct_146 = GpioData146
+Struct_147 = GpioData147
+Struct_148 = GpioData148
+Struct_149 = GpioData149
+Struct_150 = GpioData150
+Struct_151 = GpioData151
+Struct_152 = GpioData152
+Struct_153 = GpioData153
+Struct_154 = GpioData154
+Struct_155 = GpioData155
+Struct_156 = GpioData156
+Struct_157 = GpioData157
+Struct_158 = GpioData158
+Struct_159 = GpioData159
+Struct_160 = GpioData160
+Struct_161 = GpioData161
+Struct_162 = GpioData162
+Struct_163 = GpioData163
+Struct_164 = GpioData164
+Struct_165 = GpioData165
+Struct_166 = GpioData166
+Struct_167 = GpioData167
+Struct_168 = GpioData168
+Struct_169 = GpioData169
+Struct_170 = GpioData170
+Struct_171 = GpioData171
+Struct_172 = GpioData172
+Struct_173 = GpioData173
+Struct_174 = GpioData174
+Struct_175 = GpioData175
+Struct_176 = GpioData176
+Struct_177 = GpioData177
+Struct_178 = GpioData178
+Struct_179 = GpioData179
+Struct_180 = GpioData180
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-private.pem b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-private.pem
new file mode 100644
index 0000000..b2c42f3
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-private.pem
@@ -0,0 +1,27 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIEowIBAAKCAQEA0j0qx88wAYmL61So6UERMLyu2IjuTqvzIE0MPRiuYDFGZvZ5
+13xUcnIcGtc4yCo3SLPqV8kswAMNeTW51x1Sg5k2P9VdBjtHLkp3MBlPTUDh7lKx
+TRk9q1LYBHoXH7dgSAu9CxuKVQo9I/DCUtt6OeX3aFmPZQ9U/01d+fmdU3aggiEW
+dSa5o4P0PkpCRCHFIdSADzutLptNP571/QD0/iEfAb2ipD9bOKhPo0+pbxu49+SW
+1dE3n5txs+k/oq4iZ97Q/aqXuRVeALbT2aDqz1V2oJGxan/xgVpzB7tOzuYpiv9U
+4Jx/sBzlnTw7pgwF9x34CZxY1xumzBIY3ZF9DQIDAQABAoIBAGr5qsH+v5uYpHR7
+IHOHozqcV49gpXmsbsqZycdwvpG9oOgVNEwcPE/7lidmKcNYD8dTnMNMXxPYucta
+NhSqG+lQVVVHuMzJ7t80Ds+PoVVa1VtSAluLo2CAh+BHS2rdAQXHy0pSmiHJUvDt
+ucM1YE0Doc8b+yXeFk7NzCq9A3uKreUmvVkyxrYNrjUtlKdFcI1UlpTHXegdLkwZ
+oyWLuDRwmINFM3Qcbzmjimhje3rq6lMIUxkPLsH00ETwd89NRK5GaDxmXHLoSj5p
+0g3oUHU8B0/xY43QB3NprAzNz8RuPFKW+jh5vkkpGCZLzPQG4VTlWGNkvVRkqBrT
+eyoPx3UCgYEA62XY/wDha6UnXamHSR8bzU7SMLVfl//JrGjyJXiauzQeOdrmXd+g
+FQ4Oq62DBldig1vRQJ4xUAlQIMpf4ix+tQlHfOABEVY8XbDhQ/ZJDeIV+/zc9zST
+yLK4XIugvwBCAp3hzfUpMit0kbnrqNoeLhp908WARBsburQTc7AL8TsCgYEA5KOg
+mB5jiWviYtUgP47PQ6CUJdbmkl2Z1mHpHzn/DP5SqmjTXPxy9+hzVSZu3Yaa2nCU
+yGpKKcyC7OpcKmuHeSJJ7TeBbg5dq+JUw5AjfxKxIXM0tklFeEo21LqYKoBoCVlB
+wWvqRdeSgfgWtBHERTKAVZOUWUO97Z4ish/fZlcCgYB1NlSTvWOBj04HxFd54ISe
+eYYN/PIppJNORz9zyxb46l22nzogOi7i7Qn/EDny2WZTVE/gpiSV3t1IRpzx6Qf6
+qzEui/fcIx2R5XZ1udfskswxmlqIuWRxBhTo+BnFoaI83VLHlDC8K4ky2unuPRXU
+DRrkbS6OOxVWpT4eV+XKawKBgFfCIosg5u3BViS/T2B17UI06YhYoym8+aZa8IMG
+3Mnc+FfmYnKHh412UIZ3eQhYeSmtGr6OZacDk6FiFzxFB7vMGHoP2wMmSngGKKjj
+s2w7/XcsZCgvmZWhTsh6UpvFq6ki9GVMiaCDLP3r/rLhOuegibfPLJrSsJz7HLAo
+IbSDAoGBAJSqWee/gUdW5QYFALyIYI+NJCy4VPRzqP2vL+iHukwZbIIyLo2aM63t
+30C3alFwd6dlVfz7LHdz9bRDDP8pQOpSaiWC0mpPqhKA18BlVAV5F4Bb3BG8LN8m
+C/axAlBtfdpVMywGgy3tnAbaJ+zGx+HTCA81/Hu97VRCUicLahTs
+-----END RSA PRIVATE KEY-----
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.bin
new file mode 100644
index 0000000000000000000000000000000000000000..b808e5f072590ef822d91da3363dad35ee18336c
GIT binary patch
literal 256
zcmV+b0ssEeJu1h~Fae2+>r|-eK@l*#uGom~POI}EO$<F4u3#}nX7+j4d{lCB92(a+
z$SOBTv+7sLEWiT|c{RD$9a4jtHb2!}20KSCN_Q|BPfbAK?ozQ$89l2~*aUhPAGcsg
z3%v^)id70dBk;mf+j=?W_h?y<We-&UO<no<ol|z8f*}@lCb^@7^gc>LL?Oi?)PN5=
ztuC8QKc4md0QCML9|66hq(56Ys86F$sc##&_vDt<(Knx)akJ?^qOKxm-q8K3m$?;Q
z0JhWFpz6<6cA$~5YJc&8T5|`xPR`~jivLvLoPV$!<()h`rVIu59ry{HSl1h-%n}&g
Gk$nx9T6tjr

literal 0
HcmV?d00001

diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.pem b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.pem
new file mode 100644
index 0000000..83ded0d
--- /dev/null
+++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/RSA-keys/MB3-public.pem
@@ -0,0 +1,9 @@
+-----BEGIN PUBLIC KEY-----
+MIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEA0j0qx88wAYmL61So6UER
+MLyu2IjuTqvzIE0MPRiuYDFGZvZ513xUcnIcGtc4yCo3SLPqV8kswAMNeTW51x1S
+g5k2P9VdBjtHLkp3MBlPTUDh7lKxTRk9q1LYBHoXH7dgSAu9CxuKVQo9I/DCUtt6
+OeX3aFmPZQ9U/01d+fmdU3aggiEWdSa5o4P0PkpCRCHFIdSADzutLptNP571/QD0
+/iEfAb2ipD9bOKhPo0+pbxu49+SW1dE3n5txs+k/oq4iZ97Q/aqXuRVeALbT2aDq
+z1V2oJGxan/xgVpzB7tOzuYpiv9U4Jx/sBzlnTw7pgwF9x34CZxY1xumzBIY3ZF9
+DQIDAQAB
+-----END PUBLIC KEY-----
diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_TianmaMipi.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_TianmaMipi.bin
new file mode 100644
index 0000000000000000000000000000000000000000..32c872a7e321d5ddc2c419734b410f2ba165090d
GIT binary patch
literal 6656
zcmeGgZEO@(aNh3T*W2Ce-4>-SwLSsqU6poQpcJgKch}Y)6nfWItkHxP?$E{pwG;)v
zSYu6^7|11lM2*oJV>I}OMEzxq`ol;<P%!c9mo>x$i6kUq^apUx+kL%KuyPQHqMgm`
z%$xV#yqVc~U%PO9yobfRI(vIM*D(PZFyXE8YJ6V^@nmQBhL%`QY(u=GGqHw!3D?6&
z`Pt(D8A8gndef{=ZXL-EM!KSG?Y4~rgW0;4?DhvowhggVBFSQ#Hf0C1!~G-K4C`Kh
zXN+-uI*sob7|gJBJGN}h4zFaW#KhLDerfHJrHnN!uQQj_HJJ6wux4d_<H}_#blTFI
z=v<phcEoy;Xn1EAYe{y;y1QG~#yjp|sjklUWIWl^+M?5GE+n=M?HV4q|A7$}Nkmx#
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z$>{FsN71QC|ABA-2oe)E2ddysIRYcH1W(FMFkd+U{s4np0wK5qF^zc8L*Z-09}s^=
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zZ&0t1Jhn7J>~PRI==g^<Tzh&Y&7r4A2&t!}8h1J0(xz6+)`rUF#9{R)I$4%}!*#V`
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diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b.bin
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diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3Module/Eeprom/VBT/Vbt_bxt_t_fab_b_TrulyMipi_Cmd.bin
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-- 
2.10.1.windows.1

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