From nobody Fri Mar 29 13:25:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from ml01.01.org (ml01.01.org [198.145.21.10]) by mx.zohomail.com with SMTPS id 1534498437559591.6918934070402; Fri, 17 Aug 2018 02:33:57 -0700 (PDT) Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3A260210F41FB; Fri, 17 Aug 2018 02:33:56 -0700 (PDT) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E134C210F41F3 for ; Fri, 17 Aug 2018 02:33:54 -0700 (PDT) Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Aug 2018 02:33:53 -0700 Received: from fmsmsx108.amr.corp.intel.com ([10.18.124.206]) by orsmga007.jf.intel.com with ESMTP; 17 Aug 2018 02:33:53 -0700 Received: from fmsmsx156.amr.corp.intel.com (10.18.116.74) by FMSMSX108.amr.corp.intel.com (10.18.124.206) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 17 Aug 2018 02:33:53 -0700 Received: from shsmsx101.ccr.corp.intel.com (10.239.4.153) by fmsmsx156.amr.corp.intel.com (10.18.116.74) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 17 Aug 2018 02:33:51 -0700 Received: from shsmsx103.ccr.corp.intel.com ([169.254.4.240]) by SHSMSX101.ccr.corp.intel.com ([169.254.1.205]) with mapi id 14.03.0319.002; Fri, 17 Aug 2018 17:33:49 +0800 X-Original-To: edk2-devel@lists.01.org Received-SPF: none (zoho.com: 198.145.21.10 is neither permitted nor denied by domain of lists.01.org) client-ip=198.145.21.10; envelope-from=edk2-devel-bounces@lists.01.org; helo=ml01.01.org; Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.93; helo=mga11.intel.com; envelope-from=mang.guo@intel.com; receiver=edk2-devel@lists.01.org X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,250,1531810800"; d="dat'59?scan'59,208,59";a="65665363" From: "Guo, Mang" To: "edk2-devel@lists.01.org" Thread-Topic: [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 7Merged the I2C libraries Thread-Index: AdQ2DWcfbcSgcKuTTDeG+6IwRxCnXA== Date: Fri, 17 Aug 2018 09:33:49 +0000 Message-ID: <22D2C85ED001C54AA20BFE3B0E4751D1526D13B1@SHSMSX103.ccr.corp.intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: <22D2C85ED001C54AA20BFE3B0E4751D1526D13B1@SHSMSX103.ccr.corp.intel.com> x-originating-ip: [10.239.127.40] MIME-Version: 1.0 X-Content-Filtered-By: Mailman/MimeDel 2.1.27 Subject: [edk2] [Patch][edk2-platforms/devel-IntelAtomProcessorE3900 7Merged the I2C libraries X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Wei, David" Content-Transfer-Encoding: quoted-printable Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" X-ZohoMail: RDMRC_1 RSF_4 Z_629925259 SPT_0 Content-Type: text/plain; charset="utf-8" 1. Merged the I2C libraries into one library in the silicon code. 2. Change MinnowBoard3Next to MinnowBoard3Module. 3. Correct code format. Cc: David Wei Cc: Mike Wu Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Kelly Steele Signed-off-by: Guo Mang --- .../AuroraGlacier/BoardInitPostMem/BoardInit.h | 4 +- .../BoardInitPostMem/BoardInitMiscs.h | 2 +- .../BoardInitPostMem/BoardInitPostMem.inf | 2 +- .../Board/AuroraGlacier/BoardInitPostMem/TypeC.h | 2 +- .../AuroraGlacier/BoardInitPreMem/BoardInit.c | 4 +- .../AuroraGlacier/BoardInitPreMem/BoardInit.h | 2 +- .../AuroraGlacier/BoardInitPreMem/PlatformId.c | 2 +- .../BensonGlacier/BoardInitPostMem/BoardInit.h | 6 +- .../BoardInitPostMem/BoardInitMiscs.h | 4 +- .../BoardInitPostMem/BoardInitPostMem.inf | 4 +- .../Board/BensonGlacier/BoardInitPostMem/TypeC.h | 4 +- .../BensonGlacier/BoardInitPreMem/BoardInit.c | 6 +- .../BensonGlacier/BoardInitPreMem/BoardInit.h | 4 +- .../BensonGlacier/BoardInitPreMem/PlatformId.c | 4 +- .../Board/LeafHill/BoardInitPreMem/PlatformId.c | 2 +- .../MinnowBoard3/BoardInitPreMem/PlatformId.c | 2 +- .../Board/UP2/BoardInitPreMem/PlatformId.c | 2 +- .../Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c | 4 +- .../Common/Include/Guid/PlatformInfo.h | 4 +- .../Common/Include/Guid/PlatformInfo_Aplk.h | 4 +- .../BroxtonPlatformPkg/Common/Include/UsbTypec.h | 4 +- .../PlatformPreMemPei/BoardGpiosPreMem.c | 8 +- .../PlatformPreMemPei/PlatformInitPreMem.c | 4 +- .../PlatformSetupDxe/PlatformSetupDxe.c | 9 + .../PlatformSetupDxe/SetupInfoRecords.c | 4 +- .../Common/Tools/Stitch/IFWIStitch_Simple.bat | 20 +- .../BroxtonPlatformPkg/PlatformDsc/Components.dsc | 22 +- .../Library/PmcIpcLib/InternalIpcLib.h | 4 +- .../SouthCluster/Include/Library/I2CLib.h | 134 +- .../SouthCluster/Library/I2CLib/I2CLib.c | 1581 ++++++++++++++--= ---- .../SouthCluster/Library/I2CLib/I2CLib.inf | 47 +- .../SouthCluster/Library/I2CLibPei/I2CAccess.h | 51 - .../SouthCluster/Library/I2CLibPei/I2CDelayPei.h | 34 - .../SouthCluster/Library/I2CLibPei/I2CIoLibPei.c | 175 --- .../SouthCluster/Library/I2CLibPei/I2CIoLibPei.h | 146 -- .../SouthCluster/Library/I2CLibPei/I2CLibPei.c | 665 -------- .../SouthCluster/Library/I2CLibPei/I2CLibPei.inf | 51 - .../SouthCluster/Library/I2cLib/I2cLib.h | 60 + .../SouthCluster/Library/I2cLib/I2cNullLib.c | 281 ++++ .../I2CDelayPei.c =3D> I2cLib/I2cNullLib.h} | 23 +- .../SouthCluster/Library/I2cLib/I2cNullLib.inf | 37 + 41 files changed, 1732 insertions(+), 1696 deletions(-) delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CAccess.h delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CDelayPei.h delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CIoLibPei.c delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CIoLibPei.h delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CLibPei.c delete mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= CLibPei/I2CLibPei.inf create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= cLib/I2cLib.h create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= cLib/I2cNullLib.c rename Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/{I2CLibPei/I2C= DelayPei.c =3D> I2cLib/I2cNullLib.h} (61%) create mode 100644 Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2= cLib/I2cNullLib.inf diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitP= ostMem/BoardInit.h index 8d6fcba..72614fd 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.h +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInit.h @@ -19,12 +19,12 @@ =20 #include =20 -#include +#include =20 #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/Board= InitPostMem/BoardInitMiscs.h index f915505..d86ef1d 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitMiscs.h +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitMiscs.h @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/B= oardInitPostMem/BoardInitPostMem.inf index f47cb4f..73205d7 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -42,7 +42,7 @@ IoLib SteppingLib GpioLib - I2cLibPei + I2cLib TimerLib =20 [Packages] diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/TypeC.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostM= em/TypeC.h index 9e9c8a8..6f50661 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Type= C.h +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPostMem/Type= C.h @@ -23,7 +23,7 @@ #include #include #include -#include +#include =20 // // Parade Tech PS8750 TypeC MUX diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMe= m/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPr= eMem/BoardInit.c index 41d1c5a..3304f54 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Board= Init.c +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Board= Init.c @@ -75,9 +75,9 @@ AuroraGlacierPreMemInit ( =20 =20 Status =3D AuroraGetFabId (PeiServices, &FabId); - if (FabId =3D=3D 1) { + if (FabId =3D=3D FAB_ID_B) { DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB B.\n")); - } else if (FabId =3D=3D 0) { + } else if (FabId =3D=3D FAB_ID_A) { DEBUG ((EFI_D_INFO, "This is Aurora Glacier FAB A.\n")); } =20 diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMe= m/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPr= eMem/BoardInit.h index 1cec6b1..472a7f9 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Board= Init.h +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Board= Init.h @@ -19,7 +19,7 @@ =20 #include =20 -#include +#include =20 #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMe= m/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitP= reMem/PlatformId.c index af1a0da..adaeb78 100644 --- a/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Platf= ormId.c +++ b/Platform/BroxtonPlatformPkg/Board/AuroraGlacier/BoardInitPreMem/Platf= ormId.c @@ -15,7 +15,7 @@ =20 #include #include -#include +#include #include #include #include "PlatformId.h" diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitP= ostMem/BoardInit.h index c065ed2..e951a6d 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInit.h @@ -2,7 +2,7 @@ GPIO setting for CherryView. This file includes package header files, library classes. =20 - Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -19,12 +19,12 @@ =20 #include =20 -#include +#include =20 #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInitMiscs.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/Board= InitPostMem/BoardInitMiscs.h index 2ac2859..ef33999 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitMiscs.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitMiscs.h @@ -2,7 +2,7 @@ Multiplatform initialization header file. This file includes package header files, library classes. =20 - Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/BoardInitPostMem.inf b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/B= oardInitPostMem/BoardInitPostMem.inf index c7499b5..3a804b9 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Boar= dInitPostMem.inf @@ -2,7 +2,7 @@ # Board detected module for Intel(R) Atom(TM) x5 Processor Series. # It will detect the board ID. # -# Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License @@ -42,7 +42,7 @@ IoLib SteppingLib GpioLib - I2cLibPei + I2cLib TimerLib =20 [Packages] diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/TypeC.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostM= em/TypeC.h index c145c69..e126ca9 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Type= C.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPostMem/Type= C.h @@ -2,7 +2,7 @@ Multiplatform initialization header file. This file includes package header files, library classes. =20 - Copyright (c) 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -23,7 +23,7 @@ #include #include #include -#include +#include =20 // // Parade Tech PS8750 TypeC MUX diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMe= m/BoardInit.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPr= eMem/BoardInit.c index 6c75f75..d44e824 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Board= Init.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Board= Init.c @@ -1,7 +1,7 @@ /** @file Board Init driver. =20 - Copyright (c) 2010 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2010 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -74,9 +74,9 @@ BensonGlacierPreMemInit ( DEBUG ((EFI_D_INFO, "This is Benson Glacier board.\n")); =20 Status =3D BensonGetFabId (PeiServices, &FabId); - if (FabId =3D=3D 1) { + if (FabId =3D=3D FAB_ID_B) { DEBUG ((EFI_D_INFO, "This is Benson Glacier FAB B.\n")); - } else if (FabId =3D=3D 0) { + } else if (FabId =3D=3D FAB_ID_A) { DEBUG ((EFI_D_INFO, "This is Benson Glacier FAB A.\n")); } =20 diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMe= m/BoardInit.h b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPr= eMem/BoardInit.h index 3153776..833bf55 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Board= Init.h +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Board= Init.h @@ -2,7 +2,7 @@ GPIO setting for CherryView. This file includes package header files, library classes. =20 - Copyright (c) 2013 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2013 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -19,7 +19,7 @@ =20 #include =20 -#include +#include =20 #include #include diff --git a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMe= m/PlatformId.c b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitP= reMem/PlatformId.c index 614ed66..c0dfd0f 100644 --- a/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Platf= ormId.c +++ b/Platform/BroxtonPlatformPkg/Board/BensonGlacier/BoardInitPreMem/Platf= ormId.c @@ -15,7 +15,7 @@ =20 #include #include -#include +#include #include #include #include "PlatformId.h" @@ -134,7 +134,7 @@ BensonGetFabId( GpioPadWrite (CommAndOffset + BXT_GPIO_PAD_CONF1_OFFSET, padConfg1.padCn= f1); =20 =20 - *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0F0) + BXT_GP= IO_PAD_CONF0_OFFSET) & BIT1) >> 1)); + *FabId =3D (UINT8) (((GpioPadRead (GetCommOffset (NORTH, 0x0F0) + BXT_GP= IO_PAD_CONF0_OFFSET) & BIT1) >> 1)) + 1; =20 DEBUG ((EFI_D_INFO, "FabId: %02X\n", *FabId)); =20 diff --git a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Pla= tformId.c b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/Plat= formId.c index aee2b0c..ecdcd83 100644 --- a/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId= .c +++ b/Platform/BroxtonPlatformPkg/Board/LeafHill/BoardInitPreMem/PlatformId= .c @@ -15,7 +15,7 @@ =20 #include #include -#include +#include #include #include #include "PlatformId.h" diff --git a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem= /PlatformId.c b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPre= Mem/PlatformId.c index f4cf51c..aaba9b7 100644 --- a/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/Platfo= rmId.c +++ b/Platform/BroxtonPlatformPkg/Board/MinnowBoard3/BoardInitPreMem/Platfo= rmId.c @@ -15,7 +15,7 @@ =20 #include #include -#include +#include #include #include #include "PlatformId.h" diff --git a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/Platform= Id.c b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c index cec7a7c..5708e05 100644 --- a/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c +++ b/Platform/BroxtonPlatformPkg/Board/UP2/BoardInitPreMem/PlatformId.c @@ -15,7 +15,7 @@ =20 #include #include -#include +#include #include #include #include "PlatformId.h" diff --git a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscD= xe/MiscOemType0x94Function.c b/Platform/BroxtonPlatformPkg/Common/Features/= Smbios/SmBiosMiscDxe/MiscOemType0x94Function.c index 41c59f1..cce4bbe 100644 --- a/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/Misc= OemType0x94Function.c +++ b/Platform/BroxtonPlatformPkg/Common/Features/Smbios/SmBiosMiscDxe/Misc= OemType0x94Function.c @@ -1,7 +1,7 @@ /** @file The function that processes the Smbios data type 0x94. =20 - Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -30,7 +30,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h= b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h index ee60046..0da592b 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo.h @@ -174,9 +174,9 @@ typedef enum { =20 typedef enum { BOARD_ID_UP2 =3D 0x01, // UP2 - BOARD_ID_MINNOW_NEXT =3D 0x03, // Minnow Board Next + BOARD_ID_MINNOW_MODULE =3D 0x03, // Minnow Board v3 Module BOARD_ID_LFH_CRB =3D 0x07, // Leaf Hill - BOARD_ID_MINNOW =3D 0x0F, // Minnow Board + BOARD_ID_MINNOW =3D 0x0F, // Minnow Board v3 BOARD_ID_BENSON =3D 0x0C, // Benson Glacier BOARD_ID_AURORA =3D 0x0E, // Aurora Glacier BOARD_ID_APL_UNKNOWN =3D 0xFF diff --git a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_A= plk.h b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h index c9f0a75..f949ba1 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/Guid/PlatformInfo_Aplk.h @@ -159,9 +159,9 @@ typedef struct { =20 typedef enum { BOARD_ID_UP2 =3D 0x01, // UP2 - BOARD_ID_MINNOW_NEXT =3D 0x03, // Minnow Board Next + BOARD_ID_MINNOW_MODULE =3D 0x03, // Minnow Board v3 Module BOARD_ID_LFH_CRB =3D 0x07, // Leaf Hill - BOARD_ID_MINNOW =3D 0x0F, // Minnow Board + BOARD_ID_MINNOW =3D 0x0F, // Minnow Board v3 BOARD_ID_BENSON =3D 0x0C, // Benson Glacier BOARD_ID_AURORA =3D 0x0E, // Aurora Glacier BOARD_ID_APL_UNKNOWN =3D 0xFF diff --git a/Platform/BroxtonPlatformPkg/Common/Include/UsbTypec.h b/Platfo= rm/BroxtonPlatformPkg/Common/Include/UsbTypec.h index ec70314..a86d2f4 100644 --- a/Platform/BroxtonPlatformPkg/Common/Include/UsbTypec.h +++ b/Platform/BroxtonPlatformPkg/Common/Include/UsbTypec.h @@ -1,5 +1,5 @@ /** @file - Copyright (c) 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -18,7 +18,7 @@ #include #include =20 -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPr= eMemPei/BoardGpiosPreMem.c b/Platform/BroxtonPlatformPkg/Common/PlatformSet= tings/PlatformPreMemPei/BoardGpiosPreMem.c index b95e907..d3ad7e2 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /BoardGpiosPreMem.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /BoardGpiosPreMem.c @@ -1,7 +1,7 @@ /** @file Gpio setting for multiplatform before Memory init. =20 - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -78,7 +78,7 @@ BXT_GPIO_PAD_INIT SignsOfLifeGpio[] =3D // // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,G= PO_STATE,INT_Trigger, Wake_Enabled ,Term_H_L,Inverted, GPI_ROUT, IOSstae, = IOSTerm, MMIO_Offset, Community // - BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_NONE , NA , NA, NA ,D= isPuPd, GPIO_PADBAR+0x00D0, NORTH), // MB3N - SATA_LED + BXT_GPIO_PAD_CONF(L"GPIO_26", M0 , GPO , GPIO_D,= LO , NA , Wake_Disabled, P_NONE , NA , NA, NA ,D= isPuPd, GPIO_PADBAR+0x00D0, NORTH), // MB3M - SATA_LED }; =20 // @@ -173,8 +173,8 @@ BXT_GPIO_PAD_INIT UartGpio [] =3D // // Group Pin#: pad_name, PMode,GPIO_Config,HostSw,= GPO_STATE,INT_Trigger,Wake_Enabled, Term_H_L, Inverted,GPI_ROUT,IOSstae, IO= STerm, MMIO_Offset, Community // - BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0130, NORTH), // SOC_UART1_TXD - BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0138, NORTH), // SOC_UART1_RXD + BXT_GPIO_PAD_CONF(L"GPIO_38 LPSS_UART0_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0130, NORTH), // SOC_UART0_TXD + BXT_GPIO_PAD_CONF(L"GPIO_39 LPSS_UART0_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0138, NORTH), // SOC_UART0_RXD BXT_GPIO_PAD_CONF(L"GPIO_42 LPSS_UART1_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0150, NORTH), // SOC_UART1_TXD BXT_GPIO_PAD_CONF(L"GPIO_43 LPSS_UART1_TXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0158, NORTH), // SOC_UART1_RXD BXT_GPIO_PAD_CONF(L"GPIO_46 LPSS_UART2_RXD", M1 , NA , NA ,= NA , NA , Wake_Disabled, P_20K_H, NA , NA, NA , = NA, GPIO_PADBAR+0x0170, NORTH), // SOC_UART2_TXD diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPr= eMemPei/PlatformInitPreMem.c b/Platform/BroxtonPlatformPkg/Common/PlatformS= ettings/PlatformPreMemPei/PlatformInitPreMem.c index f6d6910..a0c5e82 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /PlatformInitPreMem.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformPreMemPei= /PlatformInitPreMem.c @@ -1,7 +1,7 @@ /** @file Source code file for Platform Init Pre-Memory PEI module. =20 - Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -53,7 +53,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSe= tupDxe/PlatformSetupDxe.c b/Platform/BroxtonPlatformPkg/Common/PlatformSett= ings/PlatformSetupDxe/PlatformSetupDxe.c index bbb31b1..21fd328 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= PlatformSetupDxe.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= PlatformSetupDxe.c @@ -141,6 +141,15 @@ LoadPlatformDefaultValues ( IN EFI_CALLBACK_INFO *Private ) { + switch (Private->FakeNvData.BoardId) { + case BOARD_ID_LFH_CRB: + case BOARD_ID_MINNOW: + case BOARD_ID_BENSON: + + break; + default: + break; + } =20 Private->FakeNvData.PlatformSettingEn =3D 1; } diff --git a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSe= tupDxe/SetupInfoRecords.c b/Platform/BroxtonPlatformPkg/Common/PlatformSett= ings/PlatformSetupDxe/SetupInfoRecords.c index c3fd787..0bb5f00 100644 --- a/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= SetupInfoRecords.c +++ b/Platform/BroxtonPlatformPkg/Common/PlatformSettings/PlatformSetupDxe/= SetupInfoRecords.c @@ -1,7 +1,7 @@ /** @file To retrieve various platform info data for Setup menu. =20 - Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -25,7 +25,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Sim= ple.bat b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple= .bat index 125c8c2..c8d0973 100644 --- a/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat +++ b/Platform/BroxtonPlatformPkg/Common/Tools/Stitch/IFWIStitch_Simple.bat @@ -138,9 +138,9 @@ echo. echo %SpiAccessControl% echo Generating SPI Image... mkdir BIOS_COMPONENTS -copy /y /b %BIOS_Names%\IBBL.Fv .\BIOS_COMPONENTS -copy /y /b %BIOS_Names%\IBB.Fv .\BIOS_COMPONENTS -copy /y /b %BIOS_Names%\OBB.Fv .\BIOS_COMPONENTS +copy /y /b %BIOS_Names%\IBBL.Fv .\BIOS_COMPONENTS +copy /y /b %BIOS_Names%\IBB.Fv .\BIOS_COMPONENTS +copy /y /b %BIOS_Names%\OBB.Fv .\BIOS_COMPONENTS copy /y /b %BIOS_Names%\NvStorage.Fv .\BIOS_COMPONENTS =20 if %BoardId%=3D=3DBG ( @@ -151,8 +151,8 @@ if %BoardId%=3D=3DBG ( ) else ( copy /y /b ..\..\..\Board\BensonGlacier\IFWI\FAB_A\SpiChunk1.bin . copy /y /b ..\..\..\Board\BensonGlacier\IFWI\FAB_A\SpiChunk2.bin . - copy /y /b ..\..\..\Board\BensonGlacier\IFWI\FAB_A\SpiChunk3.bin . =20 - ) =20 + copy /y /b ..\..\..\Board\BensonGlacier\IFWI\FAB_A\SpiChunk3.bin . + ) copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB= .Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+S= piChunk3.bin spi_out.bin =20 ) else if %BoardId%=3D=3DAG ( @@ -161,7 +161,7 @@ if %BoardId%=3D=3DBG ( copy /y /b ..\..\..\Board\AuroraGlacier\IFWI\FAB_A\SpiChunk3.bin . =20 copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPONENTS\IBB= .Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvStorage.Fv+S= piChunk3.bin spi_out.bin - =20 + ) else if %BoardId%=3D=3DMN ( if %FabId%=3D=3DB ( copy /y /b ..\..\..\Board\MinnowBoard3\IFWI\FAB_B\SpiChunk1.bin= . @@ -175,10 +175,10 @@ if %BoardId%=3D=3DBG ( copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COMPO= NENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvSto= rage.Fv+SpiChunk3.bin spi_out.bin ) ) else if %BoardId%=3D=3DMX ( - copy /y /b ..\..\..\Board\MinnowBoard3Next\IFWI\FAB_A\SpiChunk1= .bin . - copy /y /b ..\..\..\Board\MinnowBoard3Next\IFWI\FAB_A\SpiChunk2= .bin . - copy /y /b ..\..\..\Board\MinnowBoard3Next\IFWI\FAB_A\SpiChunk3= .bin . - copy /y /b ..\..\..\Board\MinnowBoard3Next\IFWI\FAB_A\SpiChunk1= SpiAccessControl.bin . + copy /y /b ..\..\..\Board\MinnowBoard3Module\IFWI\FAB_A\SpiChun= k1.bin . + copy /y /b ..\..\..\Board\MinnowBoard3Module\IFWI\FAB_A\SpiChun= k2.bin . + copy /y /b ..\..\..\Board\MinnowBoard3Module\IFWI\FAB_A\SpiChun= k3.bin . + copy /y /b ..\..\..\Board\MinnowBoard3Module\IFWI\FAB_A\SpiChun= k1SpiAccessControl.bin . if %SpiAccessControl% EQU 0 ( copy /y /b SpiChunk1.bin+.\BIOS_COMPONENTS\IBBL.Fv+.\BIOS_COM= PONENTS\IBB.Fv+SpiChunk2.bin+.\BIOS_COMPONENTS\OBB.Fv+.\BIOS_COMPONENTS\NvS= torage.Fv+SpiChunk3.bin spi_out.bin ) else ( diff --git a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc b/Platf= orm/BroxtonPlatformPkg/PlatformDsc/Components.dsc index f49d4cc..696480b 100644 --- a/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc +++ b/Platform/BroxtonPlatformPkg/PlatformDsc/Components.dsc @@ -48,7 +48,7 @@ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } - =20 + UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCod= eRouterRuntimeDxe.inf @@ -182,8 +182,8 @@ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntim= eDxe.inf PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.i= nf { - =20 - gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2017=20 + + gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|2018 } MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf =20 @@ -193,8 +193,7 @@ NULL|$(PLATFORM_NAME)/Board/LeafHill/BoardInitDxe/BoardInitDxe.inf NULL|$(PLATFORM_NAME)/Board/BensonGlacier/BoardInitDxe/BoardInitDxe.= inf NULL|$(PLATFORM_NAME)/Board/AuroraGlacier/BoardInitDxe/BoardInitDxe.= inf - NULL|$(PLATFORM_NAME)/Board/MinnowBoard3Next/BoardInitDxe/BoardInitD= xe.inf - NULL|$(PLATFORM_NAME)/Board/UP2/BoardInitDxe/BoardInitDxe.inf + NULL|$(PLATFORM_NAME)/Board/MinnowBoard3Module/BoardInitDxe/BoardIni= tDxe.inf } =20 !if $(DATAHUB_ENABLE) =3D=3D TRUE @@ -504,27 +503,27 @@ =20 MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf { - DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=20 + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf } MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf { @@ -563,6 +562,7 @@ # $(PLATFORM_PACKAGE_COMMON)/Application/FirmwareUpdate/FirmwareUpdate.inf MdeModulePkg/Application/VariableInfo/VariableInfo.inf + $(PLATFORM_PACKAGE_COMMON)/Features/Eeprom/EepromApp/EepromApp.inf =20 # # VT-d for DMA Protection diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/InternalIpcL= ib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/InternalIpcLib.h index f8babb8..115da4c 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/InternalIpcLib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/Library/PmcIpcLib/InternalIpcLib.h @@ -1,7 +1,7 @@ /** @file Header file for Base IPC library. =20 - Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.
+ Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -21,7 +21,7 @@ // #include #include -#include +#include =20 // // Produced library class diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I= 2CLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CL= ib.h index 0c50a3d..1c715d5 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Include/Library/I2CLib.h @@ -1,7 +1,5 @@ /** @file - Register Definitions for I2C Library. - - Copyright (c) 1999 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -16,21 +14,133 @@ #ifndef _I2C_LIB_H_ #define _I2C_LIB_H_ =20 +//// +//// Header files +//// #include -#include + + +//// +//// Defines +//// +#define I2C_WRITE_TIMEOUT 5 +#define FIFO_WRITE_DELAY 5 +#define I2C_ROUTINE_DELAY 10 +#define INVALID_I2C_ADDRESS 0xFF +#define MAX_I2C_ADDRESS 0x7F +#define MAX_I2C_BUS 7 + + +//// +//// Enums +//// +typedef enum { + Standard_Speed =3D 1, + Fast_Speed =3D 2, + High_Speed =3D 3, + Max_Speed =3D 3 +} I2C_SPEED_ENUM; + + +//// +//// Functions +//// // -// FIFO write workaround value. +// Desc: Initializes the controller and returns the MMIO base address +// Input: Bus - I2C controller, 0 based +// Address - 7-bit slave address +// Speed - Uses the I2C_SPEED_ENUM enum to set th= e controller speed +// I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: EFI_SUCCESS - Initialization completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter // -#define FIFO_WRITE_DELAY 2 +EFI_STATUS +I2cInit ( + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed, + IN OUT UINT32 *I2cBaseAddress + ); =20 -/** - Program LPSS I2C PCI controller's BAR0 and enable memory decode. +EFI_STATUS +I2cPoll ( + IN UINT32 I2cBaseAddress + ); =20 - @retval EFI_SUCCESS - I2C controller's BAR0 is programmed and = memory decode enabled. -**/ +// +// Desc: Read a byte from the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Pointer to where to store the data +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Read completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cRead ( + IN UINT32 I2cBaseAddress, + IN OUT UINT8 *Data, + IN BOOLEAN Start, + IN BOOLEAN End + ); + +// +// Desc: Resets the I2C controller into a known good state +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cReset ( + IN UINT32 I2cBaseAddress, + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed + ); + +EFI_STATUS +I2cSendCommand ( + IN UINT32 I2cBaseAddress, + IN UINT32 *Data, + IN BOOLEAN Start, + IN BOOLEAN End + ); + +// +// Desc: Set I2C slave offset +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Offset - Pointer to offset data +// Size - Size of the offset data +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cSetOffset ( + IN UINT32 I2cBaseAddress, + IN UINT8 *Offset, + IN UINT8 Size + ); + +// +// Desc: Write a byte to the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Data from the I2C controller +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// EFI_STATUS -ProgramPciLpssI2C ( - IN UINT8 BusNo +I2cWrite ( + IN UINT32 I2cBaseAddress, + IN UINT8 Data, + IN BOOLEAN Start, + IN BOOLEAN End ); =20 /** diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2= CLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib= .c index f205a6c..b7ecaca 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.c @@ -1,8 +1,7 @@ /** @file - Dxe library for I2C bus driver. + I2C library instance. =20 -@copyright - Copyright (c) 1999 - 2018 Intel Corporation. All rights reserved + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -11,44 +10,15 @@ =20 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + **/ =20 -#include -#include -#include -#include -#include -#include -#include - -#pragma pack(push, 1) -typedef struct _LPSS_PCI_DEVICE_INFO { - UINTN Segment; - UINTN BusNum; - UINTN DeviceNum; - UINTN FunctionNum; - UINTN Bar0; - UINTN Bar1; -} LPSS_PCI_DEVICE_INFO; - -typedef enum { - Standard_Speed =3D 1, - Fast_Speed =3D 2, - High_Speed =3D 3, -} I2C_SPEED; - -typedef struct _LPSS_I2C_CLOCK_SCL_INFO { - UINT8 I2c_Speed; - UINT16 SS_SCL_HCNT; - UINT16 SS_SCL_LCNT; - UINT16 FS_SCL_HCNT; - UINT16 FS_SCL_LCNT; - UINT16 HS_SCL_HCNT; - UINT16 HS_SCL_LCNT; -} LPSS_I2C_CLOCK_SCL_INFO; -#pragma pack(pop) - -LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] =3D { +#include "I2cLib.h" + +// +// List of I2C controllers +// +I2C_LPSS_PCI_DEVICE_INFO mI2cLpssPciDeviceList[] =3D { {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C0, PCI_FUNCTI= ON_NUMBER_LPSS_I2C0, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*0), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*0) + LPSS_I2C_TMP_BAR1_OFFSET}, {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C0, PCI_FUNCTI= ON_NUMBER_LPSS_I2C1, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*1), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*1) + LPSS_I2C_TMP_BAR1_OFFSET}, {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C0, PCI_FUNCTI= ON_NUMBER_LPSS_I2C2, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*2), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*2) + LPSS_I2C_TMP_BAR1_OFFSET}, @@ -56,44 +26,405 @@ LPSS_PCI_DEVICE_INFO mLpssPciDeviceList[] =3D { {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C1, PCI_FUNCTI= ON_NUMBER_LPSS_I2C4, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*4), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*4) + LPSS_I2C_TMP_BAR1_OFFSET}, {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C1, PCI_FUNCTI= ON_NUMBER_LPSS_I2C5, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*5), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*5) + LPSS_I2C_TMP_BAR1_OFFSET}, {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C1, PCI_FUNCTI= ON_NUMBER_LPSS_I2C6, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*6), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*6) + LPSS_I2C_TMP_BAR1_OFFSET}, - {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C1, PCI_FUNCTI= ON_NUMBER_LPSS_I2C7, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*7), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*7) + LPSS_I2C_TMP_BAR1_OFFSET}, + {0, DEFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPSS_I2C1, PCI_FUNCTI= ON_NUMBER_LPSS_I2C7, LPSS_I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*7), LPSS= _I2C0_TMP_BAR0 + (LPSS_I2C_TMP_BAR0_DELTA*7) + LPSS_I2C_TMP_BAR1_OFFSET} }; +#define I2C_LPSS_PCI_DEVICE_NUMBER (sizeof (mI2cLpssPciDeviceList) / size= of (I2C_LPSS_PCI_DEVICE_INFO)) =20 -#define LPSS_PCI_DEVICE_NUMBER sizeof(mLpssPciDeviceList)/sizeof(LPSS_PCI= _DEVICE_INFO) - +// +// List of I2C controller clock values +// LPSS_I2C_CLOCK_SCL_INFO mLPSS_I2C_CLOCK_SCL_INFO[] =3D { - {Fast_Speed, 0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, - {Fast_Speed, 0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, - {Fast_Speed, 0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, - {High_Speed, 0x244, 0x2DA, 0x1E, 0x3C, 0x06, 0x13}, - {High_Speed, 0x244, 0x2DA, 0x1E, 0x50, 0x06, 0x13}, - {Fast_Speed, 0x244, 0x2D0, 0x69, 0xC8, 0x06, 0x13}, - {Fast_Speed, 0x244, 0x2D0, 0x69, 0xC8, 0x06, 0x13}, - {Fast_Speed, 0x244, 0x2D0, 0x70, 0xC8, 0x06, 0x13}, + {0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, + {0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, + {0x244, 0x2D0, 0x64, 0xC8, 0x06, 0x13}, + {0x244, 0x2DA, 0x1E, 0x3C, 0x06, 0x13}, + {0x244, 0x2DA, 0x1E, 0x50, 0x06, 0x13}, + {0x244, 0x2D0, 0x69, 0xC8, 0x06, 0x13}, + {0x244, 0x2D0, 0x69, 0xC8, 0x06, 0x13}, + {0x244, 0x2D0, 0x70, 0xC8, 0x06, 0x13} +}; +#define LPSS_I2C_CLOCK_SCL_INFO_NUMBER (sizeof (mLPSS_I2C_CLOCK_SCL_INFO)= / sizeof (LPSS_I2C_CLOCK_SCL_INFO)) + +// +// List of I2C controller PAD settings +// +BXT_GPIO_PAD_INIT mI2C_LPSS_PAD_INFO[] =3D { + BXT_GPIO_PAD_CONF (L"GPIO_124 LPSS_I2C0_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0000, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_125 LPSS_I2C0_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0008, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_126 LPSS_I2C1_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0010, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_127 LPSS_I2C1_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0018, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_128 LPSS_I2C2_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0020, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_129 LPSS_I2C2_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0028, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_130 LPSS_I2C3_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0030, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_131 LPSS_I2C3_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0038, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_132 LPSS_I2C4_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0040, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_133 LPSS_I2C4_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0048, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_134 LPSS_I2C5_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0050, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_135 LPSS_I2C5_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0058, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_136 LPSS_I2C6_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0060, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_137 LPSS_I2C6_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D1RxDRx1I, EnPu, GPIO_PADBAR + 0x0068, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_138 LPSS_I2C7_SDA", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D0RxDRx0I, EnPu, GPIO_PADBAR + 0x0070, WEST), + BXT_GPIO_PAD_CONF (L"GPIO_139 LPSS_I2C7_SCL", M1, NA, NA, NA, NA, Wake_D= isabled, P_20K_H, NA, NA, D0RxDRx0I, EnPu, GPIO_PADBAR + 0x0078, WEST) }; =20 -#define LPSS_I2C_CLOCK_SCL_INFO_NUMBER sizeof(mLPSS_I2C_CLOCK_SCL_INFO)/s= izeof(LPSS_I2C_CLOCK_SCL_INFO) +BOOLEAN gI2cDebugFlag =3D FALSE; + +//// +//// Internal I2C functions +//// +// +// Desc: Clears the interrupts on this I2C controller +// Input: I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: NA +// +VOID +I2cClearInterrupts ( + IN UINT32 I2cBaseAddress + ) +{ + MmioRead32 (I2cBaseAddress + R_IC_CLR_INTR); + return; +} =20 +// +// Desc: Clears the TX Abort on this I2C controller +// Input: I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: NA +// +VOID +I2cClearTxAbort ( + IN UINT32 I2cBaseAddress + ) +{ + MmioRead32 (I2cBaseAddress + R_IC_CLR_TX_ABRT); + return; +} + +// +// Desc: Disable this I2C controller +// Input: I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: Status - EFI_SUCCESS - I2C host controller is= completely inactive +// EFI_NOT_READY - I2C host controller is= still in an enabled state +// +EFI_STATUS +I2cDisable ( + IN UINT32 I2cBaseAddress + ) +{ + UINT32 NumTries; + EFI_STATUS Status; + + // + // Initialize variables + // + Status =3D EFI_SUCCESS; + + // + // Disable I2C controller + // + MmioWrite32 (I2cBaseAddress + R_IC_ENABLE, 0); + NumTries =3D 10000; // 0.1 seconds + while (0 !=3D (MmioRead32 (I2cBaseAddress + R_IC_ENABLE_STATUS) & 0x03))= { + MicroSecondDelay (10); + NumTries --; + if (0 =3D=3D NumTries) { + Status =3D EFI_NOT_READY; + goto Exit; + } + } + +Exit: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} + +/** + Enable I2C host controller + + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval EFI_SUCCESS - I2C host controller is in an enabled sta= te. + @retval EFI_NOT_READY - I2C host controller is still inactive. +**/ +EFI_STATUS +I2cEnable ( + IN UINT32 I2cBaseAddress + ) +{ + UINT32 NumTries; + EFI_STATUS Status; + + // + // Initialize variables + // + NumTries =3D 10000; // 0.1 seconds + Status =3D EFI_SUCCESS; + + // + // Enable I2C controller + // + MmioWrite32 (I2cBaseAddress + R_IC_ENABLE, I2C_ENABLE_ENABLE); + while (I2C_ENABLE_ENABLE !=3D (MmioRead32 (I2cBaseAddress + R_IC_ENABLE_= STATUS) & I2C_ENABLE_ENABLE)) { + MicroSecondDelay (10); + NumTries --; + if (0 =3D=3D NumTries) { + Status =3D EFI_NOT_READY; + goto Exit; + } + } + +Exit: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} + +UINT16 +I2cGetTxAbortStatus ( + IN UINT32 I2cBaseAddress + ) +{ + UINT16 TxAbortStatus; + + if (I2cBaseAddress =3D=3D 0) { + TxAbortStatus =3D 0xFFFF; + } else { + TxAbortStatus =3D (UINT16) (MmioRead32 (I2cBaseAddress + R_IC_TX_ABRT_= SOURCE) & 0xFFFF); + } + return TxAbortStatus; +} + +/** + Get I2C controller raw interrupt status + + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval UINT16 - Raw interrupt status bit flags +**/ +UINT16 +I2cGetRawStatus ( + IN UINT32 I2cBaseAddress + ) +{ + UINT16 RawStatus; + + if (I2cBaseAddress =3D=3D 0) { + RawStatus =3D 0xFFFF; + } else { + RawStatus =3D (UINT16) (MmioRead32 (I2cBaseAddress + R_IC_RAW_INTR_STA= T) & 0x3FFF); + } + + return RawStatus; +} + +/** + Get I2C controller RX FIFO count + + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval UINT16 - RX FIFO count +**/ +UINT16 +I2cGetRxFifo ( + IN UINT32 I2cBaseAddress + ) +{ + UINT16 RxFifo; + + if (I2cBaseAddress =3D=3D 0) { + RxFifo =3D 0xFFFF; + } else { + RxFifo =3D (UINT16) (MmioRead32 (I2cBaseAddress + R_IC_RXFLR) & 0x01FF= ); + } + + return RxFifo; +} + +/** + Get I2C controller status + + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval UINT16 - Status bit flags +**/ +UINT16 +I2cGetStatus ( + IN UINT32 I2cBaseAddress + ) +{ + UINT16 I2cStatus; + + if (I2cBaseAddress =3D=3D 0) { + I2cStatus =3D 0xFFFF; + } else { + I2cStatus =3D (UINT16) (MmioRead32 (I2cBaseAddress + R_IC_STATUS) & 0x= 007F); + } + + return I2cStatus; +} + +/** + Get I2C controller TX FIFO count + + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval UINT16 - TX FIFO count +**/ +UINT16 +I2cGetTxFifo ( + IN UINT32 I2cBaseAddress + ) +{ + UINT16 TxFifo; + + if (I2cBaseAddress =3D=3D 0) { + TxFifo =3D 0xFFFF; + } else { + TxFifo =3D (UINT16) (MmioRead32 (I2cBaseAddress + R_IC_TXFLR) & 0x01FF= ); + } + + return TxFifo; +} + +EFI_STATUS +I2cProgramPad ( + IN UINT8 Bus + ) +{ + UINT8 index; + EFI_STATUS Status; + + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Programming PADs for= bus #%d\n", __FUNCTION__, __LINE__, Bus)); + + // + // Initialize variables + // + Status =3D EFI_SUCCESS; + + // + // Sanity checks + // + if (Bus > MAX_I2C_BUS) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + + // + // Program SDA/SCL + // + for (index =3D 0; index < 2; index++) { + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Programming PAD %s= \n", __FUNCTION__, __LINE__, mI2C_LPSS_PAD_INFO[(Bus * 2) + index].pad_name= )); + GpioPadConfigTable (1, &mI2C_LPSS_PAD_INFO[(Bus * 2) + index]); + } + + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + +Exit: + return Status; +} + +/** + Set the I2C controller bus clock frequency. + + The software and controller do a best case effort of using the specified + frequency for the I2C bus. If the frequency does not match exactly then + the controller will use a slightly lower frequency for the I2C to avoid + exceeding the operating conditions for any of the I2C devices on the bus. + For example if 400 KHz was specified and the controller's divide network + only supports 402 KHz or 398 KHz then the controller would be set to 398 + KHz. However if the desired frequency is 400 KHz and the controller only + supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTE= D. + + @param[in] Bus - I2C Bus number to which the I2C device h= as been connected + @param[in] I2CBaseAddress - BAR0 address of I2C host controller + + @retval EFI_SUCCESS - The bus frequency was set successfully. +**/ +EFI_STATUS +I2cSetBusFrequency ( + IN UINT8 Bus, + IN UINT32 I2cBaseAddress + ) +{ + EFI_STATUS Status; + + // + // Initialize variables + // + Status =3D EFI_SUCCESS; + + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cBusFrequencySet b= us: %d\n", __FUNCTION__, __LINE__, Bus)); + ASSERT ((Bus < LPSS_I2C_CLOCK_SCL_INFO_NUMBER)); + // + // Set the 100 KHz clock divider according to SV result and I2C spec + // + MmioWrite32 (I2cBaseAddress + R_IC_SS_SCL_HCNT, (UINT16) mLPSS_I2C_CLOCK= _SCL_INFO[Bus].SS_SCL_HCNT); + MmioWrite32 (I2cBaseAddress + R_IC_SS_SCL_LCNT, (UINT16) mLPSS_I2C_CLOCK= _SCL_INFO[Bus].SS_SCL_LCNT); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cBusFrequencySet R= _IC_SS_SCL_HCNT: 0x%08X, R_IC_SS_SCL_LCNT: 0x%08X\r\n", + __FUNCTION__, + __LINE__, + MmioRead32 (I2cBaseAddress + R_IC_SS_SCL_HCNT), + MmioRead32 (I2cBaseAddress + R_IC_SS_SCL_LCNT))); + // + // Set the 400 KHz clock divider according to SV result and I2C spec + // + MmioWrite32 (I2cBaseAddress + R_IC_FS_SCL_HCNT, (UINT16) mLPSS_I2C_CLOCK= _SCL_INFO[Bus].FS_SCL_HCNT); + MmioWrite32 (I2cBaseAddress + R_IC_FS_SCL_LCNT, (UINT16) mLPSS_I2C_CLOCK= _SCL_INFO[Bus].FS_SCL_LCNT); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cBusFrequencySet R= _IC_FS_SCL_HCNT: 0x%08X, R_IC_FS_SCL_LCNT: 0x%08X\r\n", + __FUNCTION__, + __LINE__, + MmioRead32 (I2cBaseAddress + R_IC_FS_SCL_HCNT), + MmioRead32 (I2cBaseAddress + R_IC_FS_SCL_LCNT))); + // + // Set the 3.4MHz clock divider according to SV result and I2C spec + // + MmioWrite32 (I2cBaseAddress + R_IC_HS_SCL_HCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[Bus].HS_SCL_HCNT); + MmioWrite32 (I2cBaseAddress + R_IC_HS_SCL_LCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[Bus].HS_SCL_LCNT); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cBusFrequencySet R= _IC_HS_SCL_HCNT: 0x%08X, R_IC_HS_SCL_LCNT: 0x%08X\r\n", + __FUNCTION__, + __LINE__, + MmioRead32 (I2cBaseAddress + R_IC_HS_SCL_HCNT), + MmioRead32 (I2cBaseAddress + R_IC_HS_SCL_LCNT))); + + // + // Set hold register + // + MmioWrite32 (I2cBaseAddress + R_IC_SDA_HOLD, (UINT16) 0x06); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cBusFrequencySet R= _IC_SDA_HOLD: 0x%08X\r\n", __FUNCTION__, __LINE__, MmioRead32 (I2cBaseAddre= ss + R_IC_SDA_HOLD))); + + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} =20 /** Program LPSS I2C PCI controller's BAR0 and enable memory decode. =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected + @param[in] Bus - I2C Bus number to which the I2C device h= as been connected =20 @retval EFI_SUCCESS - I2C controller's BAR0 is programmed and = memory decode enabled. @retval EFI_NOT_READY - I2C controller's is not exist or its fun= ction has been disabled. + @retval EFI_DEVICE_ERROR - I2C controller can't be enabled. **/ EFI_STATUS ProgramPciLpssI2C ( - IN UINT8 BusNo + IN UINT8 Bus ) { - UINTN PciMmBase=3D0; - UINT32 I2CBar0; - UINT32 I2CBar1; - UINT32 PmcBase; - UINT32 D32; - UINT32 I2cPortDisable[] =3D { + UINT32 Data32; + UINT32 I2CBar0; + UINT32 I2CBar1; + UINTN PciMmBase; + UINT32 PmcBase; + EFI_STATUS Status; + UINT32 I2cPortDisable[] =3D { B_PMC_FUNC_DIS_LPSS_I2C0, B_PMC_FUNC_DIS_LPSS_I2C1, B_PMC_FUNC_DIS_LPSS_I2C2, @@ -104,43 +435,60 @@ ProgramPciLpssI2C ( B_PMC_FUNC_DIS_LPSS_I2C7 }; =20 - DEBUG ((DEBUG_INFO, "ProgramPciLpssI2C() Start\n")); + // + // Initialize variables + // + PciMmBase =3D 0; + Status =3D EFI_SUCCESS; + + // + // Set PADs to I2C mode + // + I2cProgramPad (Bus); =20 // // Check PMC disable register // PmcBase =3D PMC_BASE_ADDRESS; - D32 =3D MmioRead32 (PmcBase + R_PMC_FUNC_DIS); + Data32 =3D MmioRead32 (PmcBase + R_PMC_FUNC_DIS); =20 - if (D32 =3D=3D 0xFFFFFFFF) { - DEBUG ((DEBUG_INFO, "ProgramPciLpssI2C() PMC disable register not avai= lable. [%08x]\n", PMC_BASE_ADDRESS)); + if (Data32 =3D=3D 0xFFFFFFFF) { + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - ProgramPciLpssI2C(= ) PMC disable register not available. [%08x]\n", __FUNCTION__, __LINE__, PM= C_BASE_ADDRESS)); } else { - if ((D32 & I2cPortDisable[BusNo]) !=3D 0) { + if ((Data32 & I2cPortDisable[Bus]) !=3D 0) { // This I2C port is disabled. Turn it on. - D32 &=3D ~I2cPortDisable[BusNo]; - MmioWrite32 (PmcBase + R_PMC_FUNC_DIS, D32); - DEBUG ((DEBUG_INFO, "ProgramPciLpssI2C() enable I2C controller #%x\n= ", BusNo)); + Data32 &=3D ~I2cPortDisable[Bus]; + MmioWrite32 (PmcBase + R_PMC_FUNC_DIS, Data32); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - ProgramPciLpssI2= C() enable I2C controller #%x\n", __FUNCTION__, __LINE__, Bus)); // Make sure it took. - if (D32 !=3D MmioRead32 (PmcBase + R_PMC_FUNC_DIS)) { - DEBUG ((DEBUG_ERROR, "ProgramPciLpssI2C() failed to enable I2C con= troller #%x [%08x:%08x]\n", BusNo, D32, MmioRead32 (PmcBase + R_PMC_FUNC_DI= S))); - return EFI_DEVICE_ERROR; + if (Data32 !=3D MmioRead32 (PmcBase + R_PMC_FUNC_DIS)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - ProgramPciLpssI2C() failed to en= able I2C controller #%x [%08x:%08x]\n", + __FUNCTION__, + __LINE__, + Bus, + Data32, + MmioRead32 (PmcBase + R_PMC_FUNC_DIS))); + Status =3D EFI_DEVICE_ERROR; + goto Exit; } } } =20 - DEBUG ((DEBUG_INFO, "ProgramPciLpssI2C()------------BusNo=3D%x\n", BusNo= )); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - ProgramPciLpssI2C()-= -----------BusNo=3D%x\n", __FUNCTION__, __LINE__, Bus)); =20 PciMmBase =3D MmPciAddress ( - mLpssPciDeviceList[BusNo].Segment, - mLpssPciDeviceList[BusNo].BusNum, - mLpssPciDeviceList[BusNo].DeviceNum, - mLpssPciDeviceList[BusNo].FunctionNum, + mI2cLpssPciDeviceList[Bus].Segment, + mI2cLpssPciDeviceList[Bus].BusNum, + mI2cLpssPciDeviceList[Bus].DeviceNum, + mI2cLpssPciDeviceList[Bus].FunctionNum, 0 ); - DEBUG ((DEBUG_INFO, "Program Pci Lpss I2C Device %x %x %x PciMmBase:%x\= n", \ - mLpssPciDeviceList[BusNo].BusNum, \ - mLpssPciDeviceList[BusNo].DeviceNum, \ - mLpssPciDeviceList[BusNo].FunctionNum, PciMmBase)); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Program Pci Lpss I2C= Device %x %x %x PciMmBase:%x\n", + __FUNCTION__, + __LINE__, + mI2cLpssPciDeviceList[Bus].BusNum, + mI2cLpssPciDeviceList[Bus].DeviceNum, + mI2cLpssPciDeviceList[Bus].FunctionNum, PciMmBase)); =20 // // Check if device present @@ -153,290 +501,683 @@ ProgramPciLpssI2C ( // I2CBar0 =3D MmioRead32 (PciMmBase + R_LPSS_IO_BAR) & B_LPSS_IO_BAR_B= A; I2CBar1 =3D MmioRead32 (PciMmBase + R_LPSS_IO_BAR1) & B_LPSS_IO_BAR_= BA; - if ((I2CBar0 !=3D (UINT32)mLpssPciDeviceList[BusNo].Bar0) || (I2CBar= 1 !=3D (UINT32)mLpssPciDeviceList[BusNo].Bar1)) { - mLpssPciDeviceList[BusNo].Bar0 =3D MmioRead32 (PciMmBase + R_LPSS_= IO_BAR) & B_LPSS_IO_BAR_BA; // get the address allocated. - mLpssPciDeviceList[BusNo].Bar1 =3D MmioRead32 (PciMmBase + R_LPSS_= IO_BAR1) & B_LPSS_IO_BAR_BA; - DEBUG ((DEBUG_INFO, "Get bar0:0x%x bar1:0x%x\n", mLpssPciDeviceLis= t[BusNo].Bar0, mLpssPciDeviceList[BusNo].Bar1)); + if ((I2CBar0 !=3D (UINT32) mI2cLpssPciDeviceList[Bus].Bar0) || (I2CB= ar1 !=3D (UINT32) mI2cLpssPciDeviceList[Bus].Bar1)) { + mI2cLpssPciDeviceList[Bus].Bar0 =3D MmioRead32 (PciMmBase + R_LPSS= _IO_BAR) & B_LPSS_IO_BAR_BA; // get the address allocated. + mI2cLpssPciDeviceList[Bus].Bar1 =3D MmioRead32 (PciMmBase + R_LPSS= _IO_BAR1) & B_LPSS_IO_BAR_BA; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Get bar0:0x%x = bar1:0x%x\n", + __FUNCTION__, + __LINE__, + mI2cLpssPciDeviceList[Bus].Bar0, + mI2cLpssPciDeviceList[Bus].Bar1)); } } else { // // Program BAR 0 // - ASSERT (((mLpssPciDeviceList[BusNo].Bar0 & B_LPSS_IO_BAR_BA) =3D=3D = mLpssPciDeviceList[BusNo].Bar0) && (mLpssPciDeviceList[BusNo].Bar0 !=3D 0)); - MmioWrite32 ((UINTN) (PciMmBase + R_LPSS_IO_BAR), (UINT32) (mLpssPci= DeviceList[BusNo].Bar0 & B_LPSS_IO_BAR_BA)); + ASSERT (((mI2cLpssPciDeviceList[Bus].Bar0 & B_LPSS_IO_BAR_BA) =3D=3D= mI2cLpssPciDeviceList[Bus].Bar0) && (mI2cLpssPciDeviceList[Bus].Bar0 !=3D = 0)); + MmioWrite32 ((UINTN) (PciMmBase + R_LPSS_IO_BAR), (UINT32) (mI2cLpss= PciDeviceList[Bus].Bar0 & B_LPSS_IO_BAR_BA)); // // Program BAR 1 // - ASSERT (((mLpssPciDeviceList[BusNo].Bar1 & B_LPSS_IO_BAR1_BA) =3D=3D= mLpssPciDeviceList[BusNo].Bar1) && (mLpssPciDeviceList[BusNo].Bar1 !=3D 0)= ); - MmioWrite32 ((UINTN) (PciMmBase + R_LPSS_IO_BAR1), (UINT32) (mLpssPc= iDeviceList[BusNo].Bar1 & B_LPSS_IO_BAR1_BA)); + ASSERT (((mI2cLpssPciDeviceList[Bus].Bar1 & B_LPSS_IO_BAR1_BA) =3D= =3D mI2cLpssPciDeviceList[Bus].Bar1) && (mI2cLpssPciDeviceList[Bus].Bar1 != =3D 0)); + MmioWrite32 ((UINTN) (PciMmBase + R_LPSS_IO_BAR1), (UINT32) (mI2cLps= sPciDeviceList[Bus].Bar1 & B_LPSS_IO_BAR1_BA)); // // Bus Master Enable & Memory Space Enable // MmioOr32 ((UINTN) (PciMmBase + R_LPSS_IO_STSCMD), (UINT32) (B_LPSS_I= O_STSCMD_BME | B_LPSS_IO_STSCMD_MSE)); - ASSERT (MmioRead32 (mLpssPciDeviceList[BusNo].Bar0) !=3D 0xFFFFFFFF); + ASSERT (MmioRead32 (mI2cLpssPciDeviceList[Bus].Bar0) !=3D 0xFFFFFFFF= ); } =20 // // Release Resets // - MmioWrite32 (mLpssPciDeviceList[BusNo].Bar0 + R_LPSS_IO_MEM_RESETS, B_= LPSS_IO_MEM_HC_RESET_REL | B_LPSS_IO_MEM_iDMA_RESET_REL); + MmioWrite32 (mI2cLpssPciDeviceList[Bus].Bar0 + R_LPSS_IO_MEM_RESETS, B= _LPSS_IO_MEM_HC_RESET_REL | B_LPSS_IO_MEM_iDMA_RESET_REL); =20 - DEBUG ((DEBUG_INFO, "ProgramPciLpssI2C() Programmed()\n")); - return EFI_SUCCESS; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - ProgramPciLpssI2C(= ) Programmed()\n", __FUNCTION__, __LINE__)); + Status =3D EFI_SUCCESS; + goto Exit; } else { - DEBUG ((DEBUG_ERROR, "Pci Lpss I2C Device %x %x %x is not existing!\= n", - mLpssPciDeviceList[BusNo].BusNum, - mLpssPciDeviceList[BusNo].DeviceNum, - mLpssPciDeviceList[BusNo].FunctionNum)); + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Pci Lpss I2C Device %x %x %x does = not exist!\n", + __FUNCTION__, + __LINE__, + mI2cLpssPciDeviceList[Bus].BusNum, + mI2cLpssPciDeviceList[Bus].DeviceNum, + mI2cLpssPciDeviceList[Bus].FunctionNum)); + + Status =3D EFI_NOT_READY; + goto Exit; + } =20 - return EFI_NOT_READY; +Exit: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); } + return Status; } =20 -/** - Disable I2C host controller +//// +//// Public I2C functions +//// +// +// Desc: Initializes the controller and returns the MMIO base address +// Input: Bus - I2C controller, 0 based +// Address - 7-bit slave address +// Speed - Uses the I2C_SPEED_ENUM enum to set th= e controller speed +// I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: EFI_SUCCESS - Initialization completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cInit ( + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed, + IN OUT UINT32 *I2cBaseAddress + ) +{ + UINT32 BaseAddress; + UINTN PciMmBase; + EFI_STATUS Status; =20 - @param[in] I2CBaseAddress - BAR0 address of I2C host controller + // + // Sanity checks + // + if (Bus > MAX_I2C_BUS) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + if (Address > MAX_I2C_ADDRESS) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + if (Speed > Max_Speed) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + if (I2cBaseAddress =3D=3D NULL) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } =20 - @retval EFI_SUCCESS - I2C host controller is completely inacti= ve. - @retval EFI_NOT_READY - I2C host controller is still in an enabl= ed state. -**/ + // + // Initialize variables + // + *I2cBaseAddress =3D 0; + + // + // Get current MMIO base address + // + PciMmBase =3D MmPciAddress ( + mI2cLpssPciDeviceList[Bus].Segment, + mI2cLpssPciDeviceList[Bus].BusNum, + mI2cLpssPciDeviceList[Bus].DeviceNum, + mI2cLpssPciDeviceList[Bus].FunctionNum, + 0 + ); + BaseAddress =3D MmioRead32 (PciMmBase + R_LPSS_IO_BAR) & B_LPSS_IO_BAR_B= A; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2CBaseAddress =3D 0= x%08x:0x%08x \n", __FUNCTION__, __LINE__, BaseAddress, (UINT32) mI2cLpssPci= DeviceList[Bus].Bar0)); + + // + // Skip reinit if targeting the same I2C bus + // + if (BaseAddress =3D=3D (UINT32) mI2cLpssPciDeviceList[Bus].Bar0) { + MmioWrite32 (BaseAddress + R_IC_TAR, Address); + *I2cBaseAddress =3D BaseAddress; + Status =3D EFI_SUCCESS; + goto Exit; + } + + // + // Program I2C controller + // + Status =3D ProgramPciLpssI2C (Bus); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - ProgramPciLpssI2C failed! %r\n", __F= UNCTION__, __LINE__, Status)); + goto Exit; + } + + // + // Retrieve I2C MMIO base address + // + BaseAddress =3D (UINT32) mI2cLpssPciDeviceList[Bus].Bar0; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2CBaseAddress =3D 0= x%x \n", __FUNCTION__, __LINE__, BaseAddress)); + + // + // Reset controller + // + Status =3D I2cReset (BaseAddress, Bus, Address, Speed); + if (EFI_ERROR (Status)) { + goto Exit; + } + + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + + // + // Pass out MMIO base + // + *I2cBaseAddress =3D BaseAddress; + Status =3D EFI_SUCCESS; + +Exit: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} + +// +// Desc: Polls the I2C controller with reads until it responds. +// Input: I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: EFI_SUCCESS - Initialization completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_STATUS -I2cDisable ( - IN UINTN I2CBaseAddress +I2cPoll ( + IN UINT32 I2cBaseAddress ) { - UINT32 NumTries =3D 10000; // 0.1 seconds + EFI_STATUS Status; + UINT16 Timeout; + UINT8 Value; =20 - MmioWrite32 (I2CBaseAddress + R_IC_ENABLE, 0); - while (0 !=3D ( MmioRead32 ( I2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) { + // + // Use a read to poll the slave + // + Status =3D EFI_DEVICE_ERROR; + Timeout =3D 0; + while (EFI_ERROR (Status) && Timeout < 1000) { MicroSecondDelay (10); - NumTries --; - if (0 =3D=3D NumTries) return EFI_NOT_READY; + Status =3D I2cRead (I2cBaseAddress, &Value, TRUE, TRUE); + Timeout++; } - return EFI_SUCCESS; -} - -/** - Enable I2C host controller =20 - @param[in] I2CBaseAddress - BAR0 address of I2C host controller + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} =20 - @retval EFI_SUCCESS - I2C host controller is in an enabled sta= te. - @retval EFI_NOT_READY - I2C host controller is still inactive. -**/ +// +// Desc: Read a byte from the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Pointer to where to store the data +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Read completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// EFI_STATUS -I2cEnable ( - IN UINTN I2CBaseAddress +I2cRead ( + IN UINT32 I2cBaseAddress, + IN OUT UINT8 *Data, + IN BOOLEAN Start, + IN BOOLEAN End ) { - UINT32 NumTries =3D 10000; // 0.1 seconds + UINT32 Data32; + EFI_STATUS Status; =20 - MmioWrite32 (I2CBaseAddress + R_IC_ENABLE, 1); - while (0 =3D=3D (MmioRead32 (I2CBaseAddress + R_IC_ENABLE_STATUS) & 1)) { - MicroSecondDelay (10); - NumTries --; - if (0 =3D=3D NumTries) return EFI_NOT_READY; - } - return EFI_SUCCESS; -} + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Starting\n", __FUNCT= ION__, __LINE__)); =20 -/** - Set the I2C controller bus clock frequency. + // + // Sanity checks + // + if (Data =3D=3D NULL) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } =20 - The software and controller do a best case effort of using the specified - frequency for the I2C bus. If the frequency does not match exactly then - the controller will use a slightly lower frequency for the I2C to avoid - exceeding the operating conditions for any of the I2C devices on the bus. - For example if 400 KHz was specified and the controller's divide network - only supports 402 KHz or 398 KHz then the controller would be set to 398 - KHz. However if the desired frequency is 400 KHz and the controller only - supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTE= D. + // + // Send CMD for read + // + Data32 =3D B_READ_CMD; + Status =3D I2cSendCommand (I2cBaseAddress, &Data32, Start, End); + *Data =3D (UINT8) (Data32 & 0xFF); =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] I2CBaseAddress - BAR0 address of I2C host controller - @param[out] I2cMode - I2C operation mode. - Standard Speed: 100 KHz - Fast Speed : 400 KHz - High Speed : 3.4 MHz +Exit: + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Display error messages + // + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; +} =20 - @retval EFI_SUCCESS - The bus frequency was set successfully. -**/ +// +// Desc: Resets the I2C controller into a known good state +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Bus - I2C controller, 0 based +// Address - 7-bit slave address +// Speed - Uses the I2C_SPEED_ENUM enum to set th= e controller speed +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// EFI_STATUS -I2cBusFrequencySet ( - IN UINT8 BusNo, - IN UINTN I2CBaseAddress, - OUT UINT16 *I2cMode +I2cReset ( + IN UINT32 I2cBaseAddress, + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed ) { - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet bus: %d\r\n", BusNo)); - ASSERT ((BusNo < LPSS_I2C_CLOCK_SCL_INFO_NUMBER)); + UINT16 I2cMode; + UINT32 NumTries; + EFI_STATUS Status; + // - // Set the 100 KHz clock divider according to SV result and I2C spec + // Wait for master activity to stop // - MmioWrite32 (I2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].SS_SCL_HCNT); - MmioWrite32 (I2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].SS_SCL_LCNT); - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet R_IC_SS_SCL_HCNT: 0x%08X, R_IC_S= S_SCL_LCNT: 0x%08X\r\n",\ - MmioRead32 (I2CBaseAddress + R_IC_SS_SCL_HCNT), MmioRead32 (I2CBa= seAddress + R_IC_SS_SCL_LCNT))); + NumTries =3D 10000; // 1 seconds + while ((STAT_MST_ACTIVITY =3D=3D (I2cGetStatus (I2cBaseAddress) & STAT_M= ST_ACTIVITY))) { + MicroSecondDelay (10); + NumTries--; + if (0 =3D=3D NumTries) { + DEBUG ((DEBUG_ERROR, "%a(#%4d) - Try timeout\n", __FUNCTION__, __LIN= E__)); + Status =3D EFI_DEVICE_ERROR; + goto Exit; + } + } // - // Set the 400 KHz clock divider according to SV result and I2C spec + // Abort controller // - MmioWrite32 (I2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].FS_SCL_HCNT); - MmioWrite32 (I2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].FS_SCL_LCNT); - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet R_IC_FS_SCL_HCNT: 0x%08X, R_IC_F= S_SCL_LCNT: 0x%08X\r\n",\ - MmioRead32 (I2CBaseAddress + R_IC_FS_SCL_HCNT), MmioRead32 (I2CBa= seAddress + R_IC_FS_SCL_LCNT))); + MmioWrite32 (I2cBaseAddress + R_IC_ENABLE, I2C_ENABLE_ABORT); + MicroSecondDelay (10 * I2C_ROUTINE_DELAY); // - // Set the 3.4MHz clock divider according to SV result and I2C spec + // Disable I2C controller // - MmioWrite32 (I2CBaseAddress + R_IC_HS_SCL_HCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].HS_SCL_HCNT); - MmioWrite32 (I2CBaseAddress + R_IC_HS_SCL_LCNT, (UINT16)mLPSS_I2C_CLOCK_= SCL_INFO[BusNo].HS_SCL_LCNT); - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet R_IC_HS_SCL_HCNT: 0x%08X, R_IC_H= S_SCL_LCNT: 0x%08X\r\n",\ - MmioRead32 (I2CBaseAddress + R_IC_HS_SCL_HCNT), MmioRead32 (I2CBa= seAddress + R_IC_HS_SCL_LCNT))); - - switch (mLPSS_I2C_CLOCK_SCL_INFO[BusNo].I2c_Speed) { + Status =3D I2cDisable (I2cBaseAddress); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cDisable Status = =3D %r\n", __FUNCTION__, __LINE__, Status)); + if (EFI_ERROR (Status)) { + goto Exit; + } + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Set I2C controller speed + // + I2cSetBusFrequency (Bus, I2cBaseAddress); // Set I2cMode + MicroSecondDelay (I2C_ROUTINE_DELAY); + switch (Speed) { case Standard_Speed: - MmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x06); //100K - *I2cMode =3D V_SPEED_STANDARD; - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet I2cMode: 0x%04X\r\n", *I2cMo= de)); + //100K + I2cMode =3D V_SPEED_STANDARD; break; =20 case Fast_Speed: - MmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x06); //400K - *I2cMode =3D V_SPEED_FAST; - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet I2cMode: 0x%04X\r\n", *I2cMo= de)); + //400K + I2cMode =3D V_SPEED_FAST; break; =20 case High_Speed: - MmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x06); //3.4M - *I2cMode =3D V_SPEED_HIGH; - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet I2cMode: 0x%04X\r\n", *I2cMo= de)); + //3.4M + I2cMode =3D V_SPEED_HIGH; break; =20 default: - MmioWrite32 ( I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x06); //400K - *I2cMode =3D V_SPEED_FAST; - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet I2cMode: 0x%04X\r\n", *I2cMo= de)); + //400K + I2cMode =3D V_SPEED_FAST; } - + I2cMode |=3D B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE; + // + // Set slave address + // + MmioWrite32 (I2cBaseAddress + R_IC_INTR_MASK, 0x0); + if (Address > MAX_I2C_ADDRESS) { + Address =3D (Address & 0x3FF) | IC_TAR_10BITADDR_MASTER; + } + MmioWrite32 (I2cBaseAddress + R_IC_TAR, Address); + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Set RX & TX FIFO full threshold to 1 byte + // + MmioWrite32 (I2cBaseAddress + R_IC_RX_TL, 0); + MmioWrite32 (I2cBaseAddress + R_IC_TX_TL, 0); + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Set I2C Mode + // + MmioWrite32 (I2cBaseAddress + R_IC_CON, I2cMode); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cMode: 0x%04x\r\n"= , __FUNCTION__, __LINE__, I2cMode)); + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Enable I2C controller + // + Status =3D I2cEnable (I2cBaseAddress); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - I2cEnable Status =3D= %r\n", __FUNCTION__, __LINE__, Status)); + if (EFI_ERROR (Status)) { + goto Exit; + } + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Clear TX abort // - // Select the frequency counter - // Enable restart condition, - // Enable master FSM, disable slave FSM + I2cClearTxAbort (I2cBaseAddress); + MicroSecondDelay (I2C_ROUTINE_DELAY); // - *I2cMode |=3D B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE; - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet R_IC_SDA_HOLD: 0x%08X\r\n", Mmio= Read32 (I2CBaseAddress + R_IC_SDA_HOLD))); - DEBUG ((DEBUG_INFO, "I2cBusFrequencySet I2cMode: 0x%04X\r\n", *I2cMode)); + // Clear interrupts + // + I2cClearInterrupts (I2cBaseAddress); + MicroSecondDelay (I2C_ROUTINE_DELAY); =20 - return EFI_SUCCESS; +Exit: + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; } =20 -/** - Initializes the host controller to execute I2C commands. - - @param[in] BusNo - I2C Bus number to which the I2C device= has been connected - @param[in] SlaveAddress - Slave address of the I2C device - @param[out] I2CBaseAddress - Return BAR0 address of I2C host contro= ller - - @retval EFI_SUCCESS - Initialization on the I2C host control= ler completed. - @retval EFI_INVALID_PARAMETER - Invalid slave address - @retval EFI_DEVICE_ERROR - Operation failed, device error - @retval Others - Failed to initialize I2C host controll= er -**/ +// +// Desc: Write a byte to the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Data from the I2C controller +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// EFI_STATUS -I2CInit ( - IN UINT8 BusNo, - IN UINT16 SlaveAddress, - OUT UINTN *I2CBaseAddress +I2cSendCommand ( + IN UINT32 I2cBaseAddress, + IN UINT32 *Data, + IN BOOLEAN Start, + IN BOOLEAN End ) { - EFI_STATUS Status; - UINT32 NumTries; - UINT16 I2cMode; - UINTN PciMmBase; - UINTN BaseAddress; + BOOLEAN CommandSent; + UINT32 Count; + UINT32 CountOut; + UINT32 Data32; + BOOLEAN ReadFlag; + EFI_STATUS Status; + UINT16 TxAbortStatus; =20 // - // Verify the parameters + // Initialize variables // - if (1023 < SlaveAddress) { - Status =3D EFI_INVALID_PARAMETER; - DEBUG ((DEBUG_INFO, "I2cStartRequest Exit with Status %r\r\n", Status)= ); - return Status; + CommandSent =3D FALSE; + Count =3D 0; + CountOut =3D 0x00000100; + Status =3D EFI_NOT_READY; + if ((*Data & B_READ_CMD) =3D=3D B_READ_CMD) { + ReadFlag =3D TRUE; + } else { + ReadFlag =3D FALSE; } =20 - PciMmBase =3D MmPciAddress ( - mLpssPciDeviceList[BusNo].Segment, - mLpssPciDeviceList[BusNo].BusNum, - mLpssPciDeviceList[BusNo].DeviceNum, - mLpssPciDeviceList[BusNo].FunctionNum, - 0 - ); - - BaseAddress =3D MmioRead32 (PciMmBase + R_LPSS_IO_BAR) & B_LPSS_IO_BAR_B= A; + // + // Send a command byte + // + while (CountOut-- > 0) { + // + // Check for NACK + // + if ((I2cGetRawStatus (I2cBaseAddress) & I2C_INTR_TX_ABRT) !=3D 0) { + TxAbortStatus =3D I2cGetTxAbortStatus (I2cBaseAddress); + DEBUG ((DEBUG_ERROR, "%a (#%4d) - TX ABRT [%04x]\n", __FUNCTION__, _= _LINE__, TxAbortStatus)); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - RX FIFO =3D %04x= \n", __FUNCTION__, __LINE__, I2cGetRxFifo (I2cBaseAddress))); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - TX FIFO =3D %04x= \n", __FUNCTION__, __LINE__, I2cGetTxFifo (I2cBaseAddress))); + // + // Clear TX Abort + // + I2cClearTxAbort (I2cBaseAddress); + MicroSecondDelay (I2C_WRITE_TIMEOUT); + // + // Clear interrupts + // + I2cClearInterrupts (I2cBaseAddress); + MicroSecondDelay (I2C_WRITE_TIMEOUT); + // + // Set status + // + if (TxAbortStatus & (I2C_ABRT_7B_ADDR_NOACK | I2C_ABRT_10ADDR1_NOACK= | I2C_ABRT_10ADDR2_NOACK)) { + DEBUG ((DEBUG_ERROR, "%a(#%4d) - Nobody home!\n", __FUNCTION__, __= LINE__)); + Status =3D EFI_NO_RESPONSE; + } else { + Status =3D EFI_DEVICE_ERROR; + } + goto Exit; + } + // + // Determine if another byte was received and we were expecting it + // + if (((I2cGetStatus (I2cBaseAddress) & STAT_RFNE) !=3D 0) && ReadFlag) { + *Data =3D MmioRead32 (I2cBaseAddress + R_IC_DATA_CMD) & 0xFF; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - MmioRead32, byte= 0x%02x was received [%d:%d]\n", __FUNCTION__, __LINE__, *Data, Start, End)= ); + MicroSecondDelay (FIFO_WRITE_DELAY); + // + // Now empty the RX FIFO if stop bit set + // + while (End && ((I2cGetStatus (I2cBaseAddress) & STAT_RFNE) =3D=3D ST= AT_RFNE)) { + MmioRead32 (I2cBaseAddress + R_IC_DATA_CMD); + MicroSecondDelay (FIFO_WRITE_DELAY); + } + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - RX FIFO =3D %04x= \n", __FUNCTION__, __LINE__, I2cGetRxFifo (I2cBaseAddress))); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - TX FIFO =3D %04x= \n", __FUNCTION__, __LINE__, I2cGetTxFifo (I2cBaseAddress))); + Status =3D EFI_SUCCESS; + goto Exit; + } + // + // Wait for room in TX buffer + // + if ((I2cGetStatus (I2cBaseAddress) & STAT_TFNF) =3D=3D 0) { + MicroSecondDelay (FIFO_WRITE_DELAY); + continue; + } + if (!CommandSent) { + // + // Send CMD + // + Data32 =3D *Data; + if (Start) Data32 |=3D B_CMD_RESTART; + if (End) Data32 |=3D B_CMD_STOP; + MmioWrite32 (I2cBaseAddress + R_IC_DATA_CMD, Data32); + CommandSent =3D TRUE; + } + // + // Add a small delay to work around some odd behavior being seen. Wit= hout this delay bytes get dropped. + // + MicroSecondDelay (I2C_WRITE_TIMEOUT); + // + // Time out check for write CMD + // + while (!ReadFlag) { + if ((I2cGetRawStatus (I2cBaseAddress) & I2C_INTR_TX_ABRT) !=3D 0) { + TxAbortStatus =3D I2cGetTxAbortStatus (I2cBaseAddress); + DEBUG ((DEBUG_ERROR, "%a (#%4d) - TX ABRT [%04x]\n", __FUNCTION__,= __LINE__, TxAbortStatus)); + // + // Clear TX Abort + // + I2cClearTxAbort (I2cBaseAddress); + MicroSecondDelay (I2C_WRITE_TIMEOUT); + // + // Clear interrupts + // + I2cClearInterrupts (I2cBaseAddress); + MicroSecondDelay (I2C_WRITE_TIMEOUT); + // + // Set status + // + if (TxAbortStatus & (I2C_ABRT_7B_ADDR_NOACK | I2C_ABRT_10ADDR1_NOA= CK | I2C_ABRT_10ADDR2_NOACK)) { + DEBUG ((DEBUG_ERROR, "%a(#%4d) - Nobody home!\n", __FUNCTION__, = __LINE__)); + Status =3D EFI_NO_RESPONSE; + } else { + Status =3D EFI_DEVICE_ERROR; + } + } + if (I2cGetTxFifo (I2cBaseAddress) =3D=3D 0) { + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - MmioRead32, by= te 0x%04x was sent [%d:%d]\n", __FUNCTION__, __LINE__, Data32, Start, End)); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - RX FIFO =3D %0= 4x\n", __FUNCTION__, __LINE__, I2cGetRxFifo (I2cBaseAddress))); + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - TX FIFO =3D %0= 4x\n", __FUNCTION__, __LINE__, I2cGetTxFifo (I2cBaseAddress))); + Status =3D EFI_SUCCESS; + goto Exit; + } + MicroSecondDelay (I2C_WRITE_TIMEOUT); + if (Count++ < 1024) { //to avoid sys hung without ul-pmc device on R= VP + continue; //Waiting the last request to get data and make (Receive= DataEnd > ReadBuffer) =3DTRUE. + } else { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - hardware timeout, 1024 times try= !\n", __FUNCTION__, __LINE__)); + Status =3D EFI_TIMEOUT; + goto Exit; + } + } + } =20 // - // Skip reinit if targeting the same I2C bus + // Check for count out // - if (BaseAddress =3D=3D mLpssPciDeviceList[BusNo].Bar0) { - MmioWrite32 (BaseAddress + R_IC_TAR, SlaveAddress); - *I2CBaseAddress =3D BaseAddress; - return EFI_SUCCESS; + if (CountOut =3D=3D 0) { + Status =3D EFI_TIMEOUT; } =20 - Status =3D ProgramPciLpssI2C (BusNo); - if (Status !=3D EFI_SUCCESS) { - DEBUG((DEBUG_ERROR, "ProgramPciLpssI2C failed ! %r\r\n", Status)); - return Status; +Exit: + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Display error messages + // + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r [%x]\n", __FUNCTION= __, __LINE__, Status, CountOut)); } + return Status; +} =20 - BaseAddress =3D (UINT32) mLpssPciDeviceList[BusNo].Bar0; - DEBUG ((DEBUG_INFO, "I2CBaseAddress =3D 0x%x \n", BaseAddress)); +// +// Desc: Set I2C target slave offset +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Offset - Pointer to offset data +// Size - Size of the offset data +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cSetOffset ( + IN UINT32 I2cBaseAddress, + IN UINT8 *Offset, + IN UINT8 Size + ) +{ + UINT8 index; + EFI_STATUS Status; =20 - NumTries =3D 10000; // 1 seconds - while ((STAT_MST_ACTIVITY =3D=3D (MmioRead32 (BaseAddress + R_IC_STATUS)= & STAT_MST_ACTIVITY))) { - MicroSecondDelay (10); - NumTries --; - if (0 =3D=3D NumTries) { - DEBUG ((DEBUG_ERROR, "Try timeout\r\n")); - return EFI_DEVICE_ERROR; + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Starting\n", __FUNCT= ION__, __LINE__)); + + // + // Sanity checks + // + if (Offset =3D=3D NULL) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + if (Size =3D=3D 0) { + Status =3D EFI_INVALID_PARAMETER; + goto Exit; + } + // + // Set offset + // + for (index =3D 0; index < Size; index++) { + if (index =3D=3D 0) { + // + // First byte of the offset + // + Status =3D I2cWrite (I2cBaseAddress, Offset[index], TRUE, FALSE); + } else { + Status =3D I2cWrite (I2cBaseAddress, Offset[index], FALSE, FALSE); + } + if (EFI_ERROR (Status)) { + goto Exit; } + // + // Pause a bit + // + MicroSecondDelay (I2C_WRITE_TIMEOUT); } =20 - Status =3D I2cDisable(BaseAddress); - DEBUG ((DEBUG_INFO, "I2cDisable Status =3D %r\r\n", Status)); - I2cBusFrequencySet(BusNo, BaseAddress, &I2cMode); // Set I2cMode - - MmioWrite32 (BaseAddress + R_IC_INTR_MASK, 0x0); - if (0x7f < SlaveAddress) { - SlaveAddress =3D (SlaveAddress & 0x3ff) | IC_TAR_10BITADDR_MASTER; +Exit: + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Display error messages + // + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); } - MmioWrite32 (BaseAddress + R_IC_TAR, SlaveAddress); - MmioWrite32 (BaseAddress + R_IC_RX_TL, 0); - MmioWrite32 (BaseAddress + R_IC_TX_TL, 0); - MmioWrite32 (BaseAddress + R_IC_CON, I2cMode); - Status =3D I2cEnable(BaseAddress); + return Status; +} =20 - DEBUG((DEBUG_INFO, "I2cEnable Status =3D %r\r\n", Status)); - MmioRead32 (BaseAddress + R_IC_CLR_TX_ABRT); - *I2CBaseAddress =3D BaseAddress; - return EFI_SUCCESS; +// +// Desc: Write a byte to the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Data from the I2C controller +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cWrite ( + IN UINT32 I2cBaseAddress, + IN UINT8 Data, + IN BOOLEAN Start, + IN BOOLEAN End + ) +{ + UINT32 Data32; + EFI_STATUS Status; + + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a (#%4d) - Starting\n", __FUNCT= ION__, __LINE__)); + + // + // Send CMD for write + // + Data32 =3D Data; + Status =3D I2cSendCommand (I2cBaseAddress, &Data32, Start, End); + // + // Pause a bit + // + MicroSecondDelay (I2C_ROUTINE_DELAY); + // + // Display error messages + // + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - Ending with %r\n", __FUNCTION__, __L= INE__, Status)); + } + return Status; } =20 /** Read bytes from I2C Device This is actual I2C hardware operation function. =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] ReadBytes - Number of bytes to be read - @param[out] ReadBuffer - Address to which the value read has to b= e stored - @param[in] Start - It controls whether a RESTART is issued = before the byte is sent or received. - @param[in] End - It controls whether a STOP is issued aft= er the byte is sent or received. - - @retval EFI_SUCCESS - The byte value read successfully - @retval EFI_DEVICE_ERROR - Operation failed - @retval EFI_TIMEOUT - Hardware retry timeout - @retval Others - Failed to read a byte via I2C + @param[in] BusNo I2C Bus number to which the I2C device= has been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to= be stored + @param[in] Start It controls whether a RESTART is issue= d before the byte is sent or received. + @param[in] End It controls whether a STOP is issued a= fter the byte is sent or received. + + @retval EFI_SUCCESS The byte value read successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to read a byte via I2C + **/ EFI_STATUS ByteReadI2C_Basic ( @@ -448,104 +1189,51 @@ ByteReadI2C_Basic ( IN UINT8 End ) { - EFI_STATUS Status; - UINT32 I2cStatus; - UINT16 ReceiveData; - UINT8 *ReceiveDataEnd; - UINT8 *ReceiveRequest; - UINT16 raw_intr_stat; - UINT32 Count =3D 0; - UINTN I2CBaseAddress; - UINT8 *ReadPtr; + UINT32 I2cBaseAddress; + UINTN index; + EFI_STATUS Status; =20 // - // Read should always after write, so, base address should already be in= itialized, then get base address directly + // Init I2C controller // - I2CBaseAddress =3D (UINT32) mLpssPciDeviceList[BusNo].Bar0; - DEBUG ((DEBUG_INFO, "mLpssPciDeviceList returned base address =3D 0x%08x= \n", I2CBaseAddress)); - - Status =3D EFI_SUCCESS; - - ReceiveDataEnd =3D &ReadBuffer [ReadBytes]; - ReadPtr =3D ReadBuffer; - if (ReadBytes) { - ReceiveRequest =3D ReadBuffer; - //DEBUG((DEBUG_INFO,"Read: ---------------%d bytes to RX\r\n", Receive= DataEnd - ReceiveRequest)); - - while ((ReceiveDataEnd > ReceiveRequest) || (ReceiveDataEnd > ReadPtr)= ) { - // - // Check for NACK - // - raw_intr_stat =3D (UINT16)MmioRead32 (I2CBaseAddress + R_IC_RAW_INTR= _STAT); - if (0 !=3D (raw_intr_stat & I2C_INTR_TX_ABRT)) { - MmioRead32 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - Status =3D EFI_DEVICE_ERROR; - DEBUG ((DEBUG_ERROR, "TX ABRT ,%d bytes hasn't been transferred\r\= n", ReceiveDataEnd - ReceiveRequest)); - break; - } - =20 - // - // Determine if another byte was received - // - I2cStatus =3D (UINT16)MmioRead32 (I2CBaseAddress + R_IC_STATUS); - if (0 !=3D (I2cStatus & STAT_RFNE)) { - ReceiveData =3D (UINT16)MmioRead32 (I2CBaseAddress + R_IC_DATA_CMD= ); - *ReadPtr++ =3D (UINT8)ReceiveData; - DEBUG ((DEBUG_INFO, "MmioRead32 ,1 byte 0x:%x is received\r\n", Re= ceiveData)); - } - - if (ReceiveDataEnd =3D=3D ReceiveRequest) { - MicroSecondDelay (FIFO_WRITE_DELAY); - Count++; - if (Count < 1024) { // sys hung avoid no ul-pmc device - continue; // Waiting the last request to get data and make (Rece= iveDataEnd > ReadBuffer) =3DTRUE. - } else { - break; - } - } - // - // Wait until a read request will fit - // - if (0 =3D=3D (I2cStatus & STAT_TFNF)) { - MicroSecondDelay (10); - continue; - } + Status =3D I2cInit (BusNo, SlaveAddress, Standard_Speed, &I2cBaseAddress= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cInit() =3D %r\n", __FUNCTION__, _= _LINE__, Status)); + goto Exit; + } + // + // Read from I2C device + // + for (index =3D 0; index < ReadBytes; index++) { + Status =3D I2cRead (I2cBaseAddress, &ReadBuffer[index], Start, End); + if (EFI_ERROR (Status)) { // - // Issue the next read request + // Something went wrong. Bail from this for loop. // - if (End && Start) { - MmioWrite32 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_REST= ART|B_CMD_STOP); - } else if (!End && Start) { - MmioWrite32 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_REST= ART); - } else if (End && !Start) { - MmioWrite32 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD|B_CMD_STOP= ); - } else if (!End && !Start) { - MmioWrite32 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD); - } - MicroSecondDelay (FIFO_WRITE_DELAY); //wait after send cmd - - ReceiveRequest +=3D 1; + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cRead() =3D %r\n", __FUNCTION__,= __LINE__, Status)); + break; } } +Exit: return Status; - } =20 /** Write bytes to I2C Device This is actual I2C hardware operation function. =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] WriteBytes - Number of bytes to be written - @param[in] WriteBuffer - Address to which the byte value has to b= e written - @param[in] Start - It controls whether a RESTART is issued = before the byte is sent or received. - @param[in] End - It controls whether a STOP is issued aft= er the byte is sent or received. - - @retval EFI_SUCCESS - The byte value written successfully - @retval EFI_DEVICE_ERROR - Operation failed - @retval EFI_TIMEOUT - Hardware retry timeout - @retval Others - Failed to write a byte via I2C + @param[in] BusNo I2C Bus number to which the I2C device= has been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to= be written + @param[in] Start It controls whether a RESTART is issue= d before the byte is sent or received. + @param[in] End It controls whether a STOP is issued a= fter the byte is sent or received. + + @retval EFI_SUCCESS The byte value written successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to write a byte via I2C + **/ EFI_STATUS ByteWriteI2C_Basic ( @@ -557,104 +1245,47 @@ ByteWriteI2C_Basic ( IN UINT8 End ) { - UINT16 Data16; - EFI_STATUS Status; - UINT32 I2cStatus; - UINT8 *TransmitPtr; - UINT8 *TransmitEnd; - UINT16 raw_intr_stat; - UINT32 Count=3D0; - UINTN I2CBaseAddress; - - Status =3D I2CInit (BusNo, SlaveAddress, &I2CBaseAddress); - if (Status !=3D EFI_SUCCESS) { - DEBUG ((DEBUG_ERROR, "I2CInit failed ! %r\r\n", Status)); - return Status; - } - DEBUG ((DEBUG_INFO, "I2CInit returned base address =3D 0x%08x\n", I2CBas= eAddress)); - =20 - TransmitPtr =3D WriteBuffer; - TransmitEnd =3D &WriteBuffer [WriteBytes]; - if (WriteBytes) { - raw_intr_stat =3D (UINT16)MmioRead32 (I2CBaseAddress + R_IC_RAW_INTR_S= TAT); - if (0 !=3D (raw_intr_stat & I2C_INTR_TX_ABRT)) { - MmioRead32 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - DEBUG ((DEBUG_ERROR, "%a(#%d) - raw_intr_stat =3D %04x\n", __FUNCTIO= N__, __LINE__, TransmitEnd, TransmitPtr, raw_intr_stat)); - } - - //DEBUG ((DEBUG_INFO, "Write: --------------%d bytes to TX\r\n", Trans= mitEnd - WriteBuffer)); - while (TransmitEnd > TransmitPtr) { - I2cStatus =3D MmioRead32 (I2CBaseAddress + R_IC_STATUS); - raw_intr_stat =3D (UINT16)MmioRead32 (I2CBaseAddress + R_IC_RAW_INTR= _STAT); - if (0 !=3D (raw_intr_stat & I2C_INTR_TX_ABRT)) { - MmioRead32 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - Status =3D EFI_DEVICE_ERROR; - DEBUG ((DEBUG_ERROR, "%a(#%d) - TX ABRT TransmitEnd:0x%x WritePtr:= 0x%x\r\n", __FUNCTION__, __LINE__, TransmitEnd, TransmitPtr)); - break; - } - if (0 =3D=3D (I2cStatus & STAT_TFNF)) { - MicroSecondDelay (FIFO_WRITE_DELAY); - continue; - } - - Data16 =3D (UINT16) *TransmitPtr; - if (End && Start) { - Data16 |=3D (B_CMD_RESTART | B_CMD_STOP); - } else if (!End && Start) { - Data16 |=3D B_CMD_RESTART; - } else if (End && !Start) { - Data16 |=3D B_CMD_STOP; - } - Data16 =3D MmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, Data16); - TransmitPtr++; + UINT32 I2cBaseAddress; + UINTN index; + EFI_STATUS Status; =20 + // + // Init I2C controller + // + Status =3D I2cInit (BusNo, SlaveAddress, Standard_Speed, &I2cBaseAddress= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cInit() =3D %r\n", __FUNCTION__, _= _LINE__, Status)); + goto Exit; + } + // + // Write to I2C device + // + for (index =3D 0; index < WriteBytes; index++) { + Status =3D I2cWrite (I2cBaseAddress, WriteBuffer[index], Start, End); + if (EFI_ERROR (Status)) { // - // Add a small delay to work around some odd behavior being seen. W= ithout this delay bytes get dropped. - // - MicroSecondDelay (FIFO_WRITE_DELAY); - // - // Time out + // Something went wrong. Bail from this for loop. // - while (1) { - raw_intr_stat =3D MmioRead16 (I2CBaseAddress + R_IC_RAW_INTR_STAT); - if (0 !=3D ( raw_intr_stat & I2C_INTR_TX_ABRT)) { - MmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - Status =3D EFI_DEVICE_ERROR; - DEBUG ((DEBUG_ERROR, "TX ABRT TransmitEnd:0x%x WriteBuffer:0x%x\= r\n", TransmitEnd, WriteBuffer)); - } - if (0 =3D=3D MmioRead16(I2CBaseAddress + R_IC_TXFLR)) break; - - MicroSecondDelay (FIFO_WRITE_DELAY); - Count++; - if (Count < 1024) { //to avoid sys hung without ul-pmc device on R= VP - continue; //Waiting the last request to get data and make (Recei= veDataEnd > ReadBuffer) =3DTRUE. - } else { - DEBUG ((DEBUG_ERROR, "hardware timeout, 1024 times try!\r\n")); - Status =3D EFI_TIMEOUT; - break; - } - }//while( 1 ) - + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cWrite() =3D %r\n", __FUNCTION__= , __LINE__, Status)); + break; } - } - if (EFI_ERROR (Status)) - DEBUG ((DEBUG_ERROR, "I2cStartRequest Exit with Status %r\r\n", Status= )); - +Exit: return Status; } =20 /** Read bytes from I2C Device =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] Offset - Register offset from which the data has = to be read - @param[in] ReadBytes - Number of bytes to be read - @param[out] ReadBuffer - Address to which the value read has to b= e stored + @param[in] BusNo I2C Bus number to which the I2C device h= as been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] Offset Register offset from which the data has = to be read + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to b= e stored + + @retval EFI_SUCCESS Read bytes from I2C device successfully + @retval Others Return status depends on ByteReadI2C_Bas= ic =20 - @retval EFI_SUCCESS - Read bytes from I2C device successfully - @retval Others - Return status depends on ByteReadI2C_Bas= ic **/ EFI_STATUS ByteReadI2C ( @@ -665,33 +1296,47 @@ ByteReadI2C ( OUT UINT8 *ReadBuffer ) { + UINT32 I2cBaseAddress; EFI_STATUS Status; =20 - //DEBUG ((EFI_D_INFO, "ByteReadI2C:---offset:0x%x\n",Offset)); - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, 1, &Offset, TRUE, FA= LSE); - if (!EFI_ERROR (Status)) { - Status =3D ByteReadI2C_Basic (BusNo, SlaveAddress, ReadBytes, ReadBuff= er, TRUE, TRUE); - } else { - DEBUG ((DEBUG_ERROR, "ByteReadI2C/ByteWriteI2C_Basic: %r\n", Status)); + // + // Init I2C controller + // + Status =3D I2cInit (BusNo, SlaveAddress, Standard_Speed, &I2cBaseAddress= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cInit() =3D %r\n", __FUNCTION__, _= _LINE__, Status)); + goto Exit; + } + // + // Set offset + // + Status =3D I2cSetOffset (I2cBaseAddress, &Offset, 1); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cSetOffset() =3D %r [%02x:%02x:%04= x]\n", __FUNCTION__, __LINE__, Status, BusNo, SlaveAddress, Offset)); + goto Exit; } + Status =3D ByteReadI2C_Basic (BusNo, SlaveAddress, ReadBytes, ReadBuffer= , TRUE, TRUE); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "ByteReadI2C: %r\n", Status)); + DEBUG ((DEBUG_ERROR, "%a (#%4d) - ByteReadI2C_Basic() =3D %r\n", __FUN= CTION__, __LINE__, Status)); + goto Exit; } =20 +Exit: return Status; } =20 /** Write bytes to I2C Device =20 - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] Offset - Register offset from which the data has = to be read - @param[in] WriteBytes - Number of bytes to be written - @param[in] WriteBuffer - Address to which the byte value has to b= e written + @param[in] BusNo I2C Bus number to which the I2C device h= as been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] Offset Register offset from which the data has = to be read + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to b= e written + + @retval EFI_SUCCESS Write bytes to I2C device successfully + @retval Others Return status depends on ByteWriteI2C_Ba= sic =20 - @retval EFI_SUCCESS - Write bytes to I2C device successfully - @retval Others - Return status depends on ByteWriteI2C_Ba= sic **/ EFI_STATUS ByteWriteI2C ( @@ -702,18 +1347,32 @@ ByteWriteI2C ( IN UINT8 *WriteBuffer ) { + UINT32 I2cBaseAddress; EFI_STATUS Status; =20 - //DEBUG ((EFI_D_INFO, "ByteWriteI2C:---offset/bytes/buf:0x%x,0x%x,0x%x,0= x%x\n",Offset,WriteBytes,WriteBuffer,*WriteBuffer)); - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, 1, &Offset, TRUE, FA= LSE); - if (!EFI_ERROR (Status)) { - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, WriteBytes, WriteB= uffer, FALSE, TRUE); - } else { - DEBUG ((DEBUG_ERROR, "ByteWriteI2C/ByteWriteI2C_Basic: %r\n", Status)); + // + // Init I2C controller + // + Status =3D I2cInit (BusNo, SlaveAddress, Standard_Speed, &I2cBaseAddress= ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cInit() =3D %r\n", __FUNCTION__, _= _LINE__, Status)); + goto Exit; + } + // + // Set offset + // + Status =3D I2cSetOffset (I2cBaseAddress, &Offset, 1); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "%a (#%4d) - I2cSetOffset() =3D %r [%02x:%02x:%04= x]\n", __FUNCTION__, __LINE__, Status, BusNo, SlaveAddress, Offset)); + goto Exit; } + Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, WriteBytes, WriteBuf= fer, FALSE, TRUE); if (EFI_ERROR (Status)) { - DEBUG ((DEBUG_ERROR, "ByteWriteI2C: %r\n", Status)); + DEBUG ((DEBUG_ERROR, "%a (#%4d) - ByteWriteI2C_Basic() =3D %r\n", __FU= NCTION__, __LINE__, Status)); + goto Exit; } =20 +Exit: return Status; } + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2= CLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CL= ib.inf index 81fe55a..fb9210d 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.inf +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLib/I2CLib.inf @@ -1,50 +1,45 @@ -### @file -# Dxe library for I2C bus driver. +## @file +# Library producing I2C functionality. # -#@copyright -# Copyright (c) 2010 - 2018 Intel Corporation. All rights reserved +# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
# # This program and the accompanying materials # are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may = be found at +# which accompanies this distribution. The full text of the license may b= e found at # http://opensource.org/licenses/bsd-license.php. # # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -### +# +## =20 [Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D I2CLib - FILE_GUID =3D 7f62bf44-2ba7-4c2d-9d4a-91c8906ff053 - MODULE_TYPE =3D BASE + INF_VERSION =3D 0x00010017 + BASE_NAME =3D I2cLib + FILE_GUID =3D BF7853AF-54D6-4CA5-8449-D8E43CF13D10 VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D I2CLib -# CONSTRUCTOR =3D IntelI2CLibConstructor - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D I2cLib =20 -[Sources.common] - I2CLib.c +[Depex] + TRUE =20 [LibraryClasses] BaseLib - IoLib + DebugLib + GpioLib + PcdLib TimerLib =20 [Packages] MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec BroxtonSiPkg/BroxtonSiPkg.dec =20 -[Protocols] - [Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## SOMETIMES_CONSUMES gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress ## SOMETIMES_CONSUMES + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## SOMETIMES_CONSUMES =20 - - +[Sources] + I2cLib.c + I2cLib.h diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CAccess.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibP= ei/I2CAccess.h deleted file mode 100644 index 792a483..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CAcc= ess.h +++ /dev/null @@ -1,51 +0,0 @@ - -/** @file - Macros that simplify accessing I2C device's registers. - - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#ifndef _I2C_ACCESS_H_ -#define _I2C_ACCESS_H_ - -/// -/// Memory Mapped PCI Access macros -/// - -#include "I2CIoLibPei.h" - -#define DEFAULT_PCI_BUS_NUMBER_SC 0 - -#define PCI_DEVICE_NUMBER_LPC 31 -#define PCI_FUNCTION_NUMBER_LPC 0 - -#define R_LPC_ACPI_BASE 0x40 ///< ABASE, 16bit -#define R_LPC_ACPI_BASEADR 0x400 ///< ABASE, 16bit -#define B_LPC_ACPI_BASE_EN BIT1 ///< Enable Bit -#define B_LPC_ACPI_BASE_BAR 0x0000FF80 ///< Base Address, 128 Byt= es -#define V_ACPI_PM1_TMR_MAX_VAL 0x1000000 ///< The timer is 24 bit o= verflow -#define B_ACPI_PM1_TMR_VAL 0xFFFFFF ///< The timer value mask - -#define R_ACPI_PM1_TMR 0x08 ///< Power Management 1 Ti= mer -#define V_ACPI_PM1_TMR_FREQUENCY 3579545 ///< Timer Frequency - - -#define ScLpcPciCfg8(Register) I2CLibPeiMmioRead8 (MmPciAddress (0, D= EFAULT_PCI_BUS_NUMBER_SC, PCI_DEVICE_NUMBER_LPC, 0, Register)) - -#define MmPciAddress( Segment, Bus, Device, Function, Register ) \ - ( (UINTN)PcdGet64 (PcdPciExpressBaseAddress)+ \ - (UINTN)(Bus << 20) + \ - (UINTN)(Device << 15) + \ - (UINTN)(Function << 12) + \ - (UINTN)(Register) \ - ) -#endif diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CDelayPei.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLi= bPei/I2CDelayPei.h deleted file mode 100644 index 53ab6e0..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CDel= ayPei.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @file - imer prototype for I2C Pei Library. - - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#ifndef _I2C_DELAY_PEI_ -#define _I2C_DELAY_PEI_ - -#include - -/** - Stalls the CPU for at least the given number of microseconds. - - @param[in] MicroSeconds The minimum number of microseconds to delay. - - @retval EFI_SUCCESS Time delay successfully -**/ -EFI_STATUS -EFIAPI -MicroSecondDelay ( - IN UINTN MicroSeconds - ); - -#endif diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CIoLibPei.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLi= bPei/I2CIoLibPei.c deleted file mode 100644 index f4cc843..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CIoL= ibPei.c +++ /dev/null @@ -1,175 +0,0 @@ -/** @file - IO instance for I2C Pei Library. - - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include -#include -#include - - -/** - Reads an 8-bit MMIO register. - - Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 8-bit MMIO register operations are not supported, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT8 - The UINT8 value read. -**/ -UINT8 -EFIAPI -I2CLibPeiMmioRead8 ( - IN UINTN Address - ) -{ - UINT8 Value; - - Value =3D *(volatile UINT8*)Address; - return Value; -} - -/** - Reads a 16-bit MMIO register. - - Reads the 16-bit MMIO register specified by Address. The 16-bit read val= ue is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 16-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT16 - The UINT16 value read. -**/ -UINT16 -EFIAPI -I2CLibPeiMmioRead16 ( - IN UINTN Address - ) -{ - UINT16 Value; - - ASSERT ((Address & 1) =3D=3D 0); - Value =3D *(volatile UINT16*)Address; - return Value; -} - -/** - Writes a 16-bit MMIO register. - - Writes the 16-bit MMIO register specified by Address with the value spec= ified - by Value and returns Value. This function must guarantee that all MMIO r= ead - and write operations are serialized. - - If 16-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to write. - @param[in] Value - The value to write to the MMIO register. - - @retval UINT16 - The UINT16 value written. -**/ -UINT16 -EFIAPI -I2CLibPeiMmioWrite16 ( - IN UINTN Address, - IN UINT16 Value - ) -{ - ASSERT ((Address & 1) =3D=3D 0); - *(volatile UINT16*)Address =3D Value; - return Value; -} - -/** - Reads a 32-bit MMIO register. - - Reads the 32-bit MMIO register specified by Address. The 32-bit read val= ue is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 32-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT32 - The UINT32 value read. - -**/ -UINT32 -EFIAPI -I2CLibPeiMmioRead32 ( - IN UINTN Address - ) -{ - UINT32 Value; - - ASSERT ((Address & 3) =3D=3D 0); - Value =3D *(volatile UINT32*)Address; - - return Value; -} - -/** - Writes a 32-bit MMIO register. - - Writes the 32-bit MMIO register specified by Address with the value spec= ified - by Value and returns Value. This function must guarantee that all MMIO r= ead - and write operations are serialized. - - If 32-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to write. - @param[in] Value - The value to write to the MMIO register. - - @retval UINT32 - The UINT32 value written. -**/ -UINT32 -EFIAPI -I2CLibPeiMmioWrite32 ( - IN UINTN Address, - IN UINT32 Value - ) -{ - ASSERT ((Address & 3) =3D=3D 0); - *(volatile UINT32*)Address =3D Value; - return Value; -} - -/** - Do logical OR operation with the value read from the 32-bit MMIO regist= er - and write it back to 32-bit MMIO register. - - @param[in] Address - The MMIO register to write. - @param[in] OrData - The value to do logical OR operation with the val= ue read from the MMIO register. - - @retval UINT32 - The final value written to the MMIO register. -**/ -UINT32 -EFIAPI -I2CLibPeiMmioOr32 ( - IN UINTN Address, - IN UINT32 OrData - ) -{ - return I2CLibPeiMmioWrite32 (Address, I2CLibPeiMmioRead32 (Address) | Or= Data); -} - - diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CIoLibPei.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLi= bPei/I2CIoLibPei.h deleted file mode 100644 index 0ea1727..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CIoL= ibPei.h +++ /dev/null @@ -1,146 +0,0 @@ -/** @file - IO prototype for I2C Pei Library. - - Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#ifndef _I2C_IOLIB_PEI_ -#define _I2C_IOLIB_PEI_ - -#include - -/** - Reads an 8-bit MMIO register. - - Reads the 8-bit MMIO register specified by Address. The 8-bit read value= is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 8-bit MMIO register operations are not supported, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT8 - The UINT8 value read. -**/ -UINT8 -EFIAPI -I2CLibPeiMmioRead8 ( - IN UINTN Address - ); - - -/** - Reads a 16-bit MMIO register. - - Reads the 16-bit MMIO register specified by Address. The 16-bit read val= ue is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 16-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT16 - The UINT16 value read. -**/ -UINT16 -EFIAPI -I2CLibPeiMmioRead16 ( - IN UINTN Address - ); - - -/** - Writes a 16-bit MMIO register. - - Writes the 16-bit MMIO register specified by Address with the value spec= ified - by Value and returns Value. This function must guarantee that all MMIO r= ead - and write operations are serialized. - - If 16-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 16-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to write. - @param[in] Value - The value to write to the MMIO register. - - @retval UINT16 - The UINT16 value written. -**/ -UINT16 -EFIAPI -I2CLibPeiMmioWrite16 ( - IN UINTN Address, - IN UINT16 Value - ); - - -/** - Reads a 32-bit MMIO register. - - Reads the 32-bit MMIO register specified by Address. The 32-bit read val= ue is - returned. This function must guarantee that all MMIO read and write - operations are serialized. - - If 32-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to read. - - @retval UINT32 - The UINT32 value read. - -**/ -UINT32 -EFIAPI -I2CLibPeiMmioRead32 ( - IN UINTN Address - ); - - -/** - Writes a 32-bit MMIO register. - - Writes the 32-bit MMIO register specified by Address with the value spec= ified - by Value and returns Value. This function must guarantee that all MMIO r= ead - and write operations are serialized. - - If 32-bit MMIO register operations are not supported, then ASSERT(). - If Address is not aligned on a 32-bit boundary, then ASSERT(). - - @param[in] Address - The MMIO register to write. - @param[in] Value - The value to write to the MMIO register. - - @retval UINT32 - The UINT32 value written. -**/ -UINT32 -EFIAPI -I2CLibPeiMmioWrite32 ( - IN UINTN Address, - IN UINT32 Value - ); - - -/** - Do logical OR operation with the value read from the 32-bit MMIO regist= er - and write it back to 32-bit MMIO register. - - @param[in] Address - The MMIO register to write. - @param[in] OrData - The value to do logical OR operation with the val= ue read from the MMIO register. - - @retval UINT32 - The final value written to the MMIO register. -**/ -UINT32 -EFIAPI -I2CLibPeiMmioOr32 ( - IN UINTN Address, - IN UINT32 OrData - ); - -#endif diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CLibPei.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibP= ei/I2CLibPei.c deleted file mode 100644 index ad154d5..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CLib= Pei.c +++ /dev/null @@ -1,665 +0,0 @@ -/** @file - Pei library for I2C bus driver. - - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
- - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BS= D License - which accompanies this distribution. The full text of the license may b= e found at - http://opensource.org/licenses/bsd-license.php. - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. - -**/ - -#include "I2CDelayPei.h" -#include "I2CIoLibPei.h" -#include "I2CAccess.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -EFI_GUID mI2CPeiInitGuid =3D { - 0x96DED71A, 0xB9E7, 0x4EAD, {0x96, 0x2C, 0x01, 0x69, 0x3C, 0xED, 0x2A, 0= x64} -}; - - -#define LPSS_PCI_DEVICE_NUMBER 8 - - -#define GPIO_PAD_CFG_DW0_GPIO_124_OFFSET 0x400 ///< This is the first gp= io pin of I2C0 - -/* Name Function Offset of GPIO WEST - GPIO_124 LPSS_I2C0_SDA 0x400 + 16*0 - GPIO_125 LPSS_I2C0_SCL - - GPIO_126 LPSS_I2C1_SDA 0x400 + 16*1 - GPIO_127 LPSS_I2C1_SCL - - GPIO_128 LPSS_I2C2_SDA - GPIO_129 LPSS_I2C2_SCL - - GPIO_130 LPSS_I2C3_SDA - GPIO_131 LPSS_I2C3_SCL - - GPIO_132 LPSS_I2C4_SDA - GPIO_133 LPSS_I2C4_SCL - - GPIO_134 LPSS_I2C5_SDA - GPIO_135 LPSS_I2C5_SCL - - GPIO_136 LPSS_I2C6_SDA - GPIO_137 LPSS_I2C6_SCL - - GPIO_138 LPSS_I2C7_SDA 0x400 + 16*7 - GPIO_139 LPSS_I2C7_SCL -*/ - -EFI_STATUS -EFIAPI -IntelI2CPeiLibConstructor ( - VOID - ) -{ - UINTN Index; -//UINT32 Value; - UINT32 gpio_pad_cfg_dw0_offset; - - // Program GPIO pins for I2C 0~7, need to set GPIO to Function 1 and mis= c settings. - for (Index =3D 0; Index < 8; Index ++) { - // Config I2C[Index] SDA pin DW0 - gpio_pad_cfg_dw0_offset =3D GPIO_PAD_CFG_DW0_GPIO_124_OFFSET + 16 * In= dex; - { - //Value =3D 0; // FIXME: the right GPIO setting, need to get update= d from GPIO config owner. Dummy code here. - //SideBandCR32Write (SB_PORTID_GPIOW, gpio_pad_cfg_dw0_offset, Value= ); - } - - // Config I2C[Index] SDA pin DW1 - gpio_pad_cfg_dw0_offset +=3D 4; - { - //Value =3D 0; // FIXME: the right GPIO setting, need to get update= d from GPIO config owner. Dummy code here. - //SideBandCR32Write (SB_PORTID_GPIOW, gpio_pad_cfg_dw0_offset, Value= ); - } - - // Config I2C[Index] SCL pin DW0 - gpio_pad_cfg_dw0_offset +=3D 4; - { - //Value =3D 0; // FIXME: the right GPIO setting, need to get update= d from GPIO config owner. Dummy code here. - //SideBandCR32Write (SB_PORTID_GPIOW, gpio_pad_cfg_dw0_offset, Value= ); - } - - // Config I2C[Index] SCL pin DW1 - gpio_pad_cfg_dw0_offset +=3D 4; - { - //Value =3D 0; // FIXME: the right GPIO setting, need to get update= d from GPIO config owner. Dummy code here. - //SideBandCR32Write (SB_PORTID_GPIOW, gpio_pad_cfg_dw0_offset, Value= ); - } - } - - return EFI_SUCCESS; -} - -/** - Program LPSS I2C PCI controller's BAR0 and enable memory decode. - - @retval EFI_SUCCESS - I2C controller's BAR0 is programmed and = memory decode enabled. -**/ -EFI_STATUS -ProgramPciLpssI2C ( - IN UINT8 BusNo - ) -{ - UINT32 PmcBase; - UINT32 DevID; - UINTN PciMmBase=3D0; - UINTN Index; - UINTN Bar0; - UINTN Bar1; - - DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() Start\n")); - - // - // Set the BXT Function Disable Register to ZERO - // - PmcBase =3D PMC_BASE_ADDRESS; - - if (I2CLibPeiMmioRead32 (PmcBase + R_PMC_FUNC_DIS) & - (B_PMC_FUNC_DIS_LPSS_I2C0 | B_PMC_FUNC_DIS_LPSS_I2C1 | B_PMC_FUNC_DI= S_LPSS_I2C2 | B_PMC_FUNC_DIS_LPSS_I2C3| - B_PMC_FUNC_DIS_LPSS_I2C4 | B_PMC_FUNC_DIS_LPSS_I2C5 | B_PMC_FUNC_DI= S_LPSS_I2C6 | B_PMC_FUNC_DIS_LPSS_I2C7)) { - I2CLibPeiMmioWrite32 ( - PmcBase + R_PMC_FUNC_DIS, - I2CLibPeiMmioRead32 (PmcBase + R_PMC_FUNC_DIS) & - ~(B_PMC_FUNC_DIS_LPSS_I2C0| B_PMC_FUNC_DIS_LPSS_I2C1|B_PMC_FUN= C_DIS_LPSS_I2C2| B_PMC_FUNC_DIS_LPSS_I2C3| - B_PMC_FUNC_DIS_LPSS_I2C4| B_PMC_FUNC_DIS_LPSS_I2C5|B_PMC_FUN= C_DIS_LPSS_I2C6| B_PMC_FUNC_DIS_LPSS_I2C7) - ); - - DEBUG ((EFI_D_INFO, "ProgramPciLpssI2C() enable all I2C controllers\n"= )); - } - - for (Index =3D 0; Index < LPSS_PCI_DEVICE_NUMBER; Index ++) { - if (Index < 4) { - PciMmBase =3D MmPciAddress ( - 0, - DEFAULT_PCI_BUS_NUMBER_SC, - PCI_DEVICE_NUMBER_LPSS_I2C0, - Index, - 0 - ); - } else { - PciMmBase =3D MmPciAddress ( - 0, - DEFAULT_PCI_BUS_NUMBER_SC, - PCI_DEVICE_NUMBER_LPSS_I2C1, - (Index - 4), - 0 - ); - } - - DevID =3D I2CLibPeiMmioRead32 (PciMmBase); - Bar0 =3D LPSS_I2C0_TMP_BAR0 + Index * LPSS_I2C_TMP_BAR0_DELTA; - Bar1 =3D Bar0 + LPSS_I2C_TMP_BAR1_OFFSET; - - // - // Check if device present - // - if (DevID !=3D 0xFFFFFFFF) { - if ((I2CLibPeiMmioRead32 (PciMmBase + R_LPSS_I2C_STSCMD) & B_LPSS_I2= C_STSCMD_MSE)) { - // - // In PEI stage, we always disable Bus master, and memory space en= abling for BAR re-programming - // In DXE stage, will read existing BAR value instead of re-progra= mming - // - I2CLibPeiMmioWrite32 ((UINTN) (PciMmBase + R_LPSS_I2C_STSCMD), 0); - } - // - // Program BAR 0 - // - I2CLibPeiMmioWrite32 ((UINTN) (PciMmBase + R_LPSS_I2C_BAR), (UINT32)= (Bar0 & B_LPSS_I2C_BAR_BA)); - - // - // Program BAR 1 - // - I2CLibPeiMmioWrite32 ((UINTN) (PciMmBase + R_LPSS_I2C_BAR1), (UINT32= ) (Bar1 & B_LPSS_I2C_BAR1_BA)); - - // - // Bus Master Enable & Memory Space Enable - // - I2CLibPeiMmioWrite32 ((UINTN) (PciMmBase + R_LPSS_I2C_STSCMD), (UINT= 32) (B_LPSS_I2C_STSCMD_BME | B_LPSS_I2C_STSCMD_MSE)); - } - - // - // Release Resets - // - I2CLibPeiMmioWrite32 (Bar0 + R_LPSS_IO_MEM_RESETS, B_LPSS_IO_MEM_HC_RE= SET_REL | B_LPSS_IO_MEM_iDMA_RESET_REL); - } - - DEBUG ((EFI_D_INFO, "Pei ProgramPciLpssI2C() End\n")); - - return EFI_SUCCESS; -} - -/** - Disable I2C host controller - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - - @retval EFI_SUCCESS - I2C host controller is completely inacti= ve. - @retval EFI_NOT_READY - I2C host controller is still in an enabl= ed state. -**/ -EFI_STATUS -I2cDisable ( - IN UINT8 BusNo - ) -{ - UINTN I2CBaseAddress; - UINT32 NumTries =3D 10000; // 0.1 seconds - - I2CBaseAddress =3D (UINT32) LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TMP_B= AR0_DELTA); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 0); - while (0 !=3D (I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_ENABLE) & 1)) { - MicroSecondDelay (10); - NumTries--; - if (NumTries =3D=3D 0) return EFI_NOT_READY; - } - return EFI_SUCCESS; -} - - -/** - Enable I2C host controller - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - - @retval EFI_SUCCESS - I2C host controller is in an enabled sta= te. - @retval EFI_NOT_READY - I2C host controller is still inactive. -**/ -EFI_STATUS -I2cEnable ( - IN UINT8 BusNo - ) -{ - UINTN I2CBaseAddress; - UINT32 NumTries =3D 10000; //0.1 seconds - - I2CBaseAddress =3D (UINT32) LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TMP_B= AR0_DELTA); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_ENABLE, 1); - while (0 =3D=3D (I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_ENABLE ) & 1= )) { - MicroSecondDelay (10); - NumTries --; - if (NumTries =3D=3D 0) return EFI_NOT_READY; - } - return EFI_SUCCESS; -} - - -/** - Set the I2C controller bus clock frequency. - - The software and controller do a best case effort of using the specified - frequency for the I2C bus. If the frequency does not match exactly then - the controller will use a slightly lower frequency for the I2C to avoid - exceeding the operating conditions for any of the I2C devices on the bus. - For example if 400 KHz was specified and the controller's divide network - only supports 402 KHz or 398 KHz then the controller would be set to 398 - KHz. However if the desired frequency is 400 KHz and the controller only - supports 1 MHz and 100 KHz then this routine would return EFI_UNSUPPORTE= D. - - @param[in] I2CBaseAddress - BAR0 address of I2C host controller - @param[in] BusClockHertz - New I2C bus clock frequency in Hertz - @param[out] I2cMode - I2C operation mode. - Standard Speed: 100 KHz - Fast Speed : 400 KHz - High Speed : 3.4 MHz - - @retval EFI_SUCCESS - The bus frequency was set successfully. -**/ - -EFI_STATUS -I2cBusFrequencySet ( - IN UINTN I2CBaseAddress, - IN UINTN BusClockHertz, - OUT UINT16 *I2cMode, - IN BOOLEAN DebugFlag - ) -{ - if (DebugFlag) DEBUG ((EFI_D_INFO, "InputFreq BusClockHertz: %d\r\n", Bu= sClockHertz)); - - *I2cMode =3D B_IC_RESTART_EN | B_IC_SLAVE_DISABLE | B_MASTER_MODE; - - // - // Set the 100 KHz clock divider - // From Table 10 of the I2C specification - // High: 4.00 uS - // Low: 4.70 uS - // - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_SS_SCL_HCNT, (UINT16)0x214); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_SS_SCL_LCNT, (UINT16)0x272); - - // - // Set the 400 KHz clock divider - // From Table 10 of the I2C specification - // High: 0.60 uS - // Low: 1.30 uS - // - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_FS_SCL_HCNT, (UINT16)0x50); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_FS_SCL_LCNT, (UINT16)0xAD); - - switch (BusClockHertz) { - case 100 * 1000: - I2CLibPeiMmioWrite32 (I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x40);= //100K - *I2cMode |=3D V_SPEED_STANDARD; - break; - case 400 * 1000: - I2CLibPeiMmioWrite32 (I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x32);= //400K - *I2cMode |=3D V_SPEED_FAST; - break; - default: - I2CLibPeiMmioWrite32 (I2CBaseAddress + R_IC_SDA_HOLD, (UINT16)0x09);= //3.4M - *I2cMode |=3D V_SPEED_HIGH; - } - - return EFI_SUCCESS; -} - -/** - Initializes the host controller to execute I2C commands. - - @param[in] BusNo - I2C Bus number to which the I2C device= has been connected - @param[in] SlaveAddress - Slave address of the I2C device - - @retval EFI_SUCCESS - Opcode initialization on the I2C host = controller completed. - @retval EFI_INVALID_PARAMETER - Invalid slave address - @retval EFI_DEVICE_ERROR - Operation failed, device error - @retval Others - Failed to initialize I2C host controll= er -**/ -EFI_STATUS -I2CInit ( - IN UINT8 BusNo, - IN UINT16 SlaveAddress - ) -{ - EFI_STATUS Status; - UINT32 NumTries =3D 0; - UINTN I2CBaseAddress; - UINT16 I2cMode; - UINTN PciMmBase =3D 0; - BOOLEAN DebugFlag =3D TRUE; - - if (BusNo < 4) { - PciMmBase =3D MmPciAddress ( - 0, - DEFAULT_PCI_BUS_NUMBER_SC, - PCI_DEVICE_NUMBER_LPSS_I2C0, - BusNo, - 0 - ); - } else { - PciMmBase =3D MmPciAddress ( - 0, - DEFAULT_PCI_BUS_NUMBER_SC, - PCI_DEVICE_NUMBER_LPSS_I2C1, - (BusNo - 4), - 0 - ); - } - - I2CBaseAddress =3D (I2CLibPeiMmioRead32 (PciMmBase + R_LPSS_I2C_BAR) & 0= xFFFFFFF8); - - // - // Verify the parameters - // - if (1023 < SlaveAddress) { - Status =3D EFI_INVALID_PARAMETER; - if (DebugFlag) DEBUG ((DEBUG_ERROR, "I2cStartRequest Exit with Status = %r\r\n", Status)); - return Status; - } - - if (I2CBaseAddress =3D=3D (LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TMP_BA= R0_DELTA))) { - DebugFlag =3D FALSE; - } else { - // - // Need to enable the I2C PCI device - // - ProgramPciLpssI2C (BusNo); - - I2CBaseAddress =3D (UINT32) (LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TM= P_BAR0_DELTA)); - if (DebugFlag) DEBUG ((DEBUG_INFO, "I2CBaseAddress =3D 0x%x \n", I2CBa= seAddress)); - } - - NumTries =3D 10000; // 1 seconds=20 - while ((1 =3D=3D (I2CLibPeiMmioRead32 (I2CBaseAddress + R_IC_STATUS) & S= TAT_MST_ACTIVITY ))) { - MicroSecondDelay (10); - NumTries --; - if (0 =3D=3D NumTries) - return EFI_DEVICE_ERROR; - } - - Status =3D I2cDisable (BusNo); - if (DebugFlag) DEBUG ((DEBUG_INFO, "I2cDisable Status =3D %r\r\n", Statu= s)); - - I2cBusFrequencySet (I2CBaseAddress, 400 * 1000, &I2cMode, DebugFlag); //= Set I2cMode - - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_INTR_MASK, 0x0); - if (0x7F < SlaveAddress) { - SlaveAddress =3D (SlaveAddress & 0x3FF) | IC_TAR_10BITADDR_MASTER; - } - - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TAR, (UINT16) SlaveAddress= ); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_RX_TL, 0); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_TX_TL, 0); - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_CON, I2cMode); - - Status =3D I2cEnable (BusNo); - if (DebugFlag) DEBUG ((DEBUG_INFO, "I2cEnable Status =3D %r\r\n", Status= )); - - I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - return EFI_SUCCESS; -} - -/** - Read bytes from I2C Device - This is actual I2C hardware operation function. - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] ReadBytes - Number of bytes to be read - @param[out] ReadBuffer - Address to which the value read has to b= e stored - @param[in] Start - It controls whether a RESTART is issued = before the byte is sent or received. - @param[in] End - It controls whether a STOP is issued aft= er the byte is sent or received. - - @retval EFI_SUCCESS - The byte value read successfully - @retval EFI_DEVICE_ERROR - Operation failed - @retval EFI_TIMEOUT - Hardware retry timeout - @retval Others - Failed to read a byte via I2C -**/ -EFI_STATUS -ByteReadI2C_Basic ( - IN UINT8 BusNo, - IN UINT8 SlaveAddress, - IN UINTN ReadBytes, - OUT UINT8 *ReadBuffer, - IN UINT8 Start, - IN UINT8 End - ) -{ - EFI_STATUS Status; - UINT32 I2cStatus; - UINT16 ReceiveData; - UINT8 *ReceiveDataEnd; - UINT8 *ReceiveRequest; - UINT16 raw_intr_stat; - UINTN I2CBaseAddress; - - I2CBaseAddress =3D (UINT32) (LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TMP_= BAR0_DELTA)); - - Status =3D EFI_SUCCESS; - - I2CInit (BusNo, SlaveAddress); - - ReceiveDataEnd =3D &ReadBuffer [ReadBytes]; - if (ReadBytes) { - ReceiveRequest =3D ReadBuffer; - - while ((ReceiveDataEnd > ReceiveRequest) || - (ReceiveDataEnd > ReadBuffer)) { - // - // Check for NACK - // - raw_intr_stat =3D I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_RAW_INT= R_STAT); - if (0 !=3D (raw_intr_stat & I2C_INTR_TX_ABRT)) { - I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - Status =3D RETURN_DEVICE_ERROR; - DEBUG ((DEBUG_INFO,"TX ABRT ,%d bytes hasn't been transferred\r\n"= , ReceiveDataEnd - ReceiveRequest)); - break; - } - - // - // Determine if another byte was received - // - I2cStatus =3D I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_STATUS); - if (0 !=3D (I2cStatus & STAT_RFNE)) { - ReceiveData =3D I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_DATA_CM= D); - *ReadBuffer++ =3D (UINT8)ReceiveData; - } - - if (ReceiveDataEnd =3D=3D ReceiveRequest) { - continue; //Waiting the last request to get data and make (Receive= DataEnd > ReadBuffer) =3DTRUE. - } - - // - // Wait until a read request will fit - // - if (0 =3D=3D (I2cStatus & STAT_TFNF)) { - MicroSecondDelay (10); - continue; - } - - // - // Issue the next read request - // - if (End && Start) { - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD |= B_CMD_RESTART | B_CMD_STOP); - } else if (!End && Start) { - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD |= B_CMD_RESTART); - } else if (End && !Start) { - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD |= B_CMD_STOP); - } else if (!End && !Start) { - I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, B_READ_CMD); - } - ReceiveRequest +=3D 1; - } - } - return Status; - -} - -/** - Write bytes to I2C Device - This is actual I2C hardware operation function. - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] WriteBytes - Number of bytes to be written - @param[in] WriteBuffer - Address to which the byte value has to b= e written - @param[in] Start - It controls whether a RESTART is issued = before the byte is sent or received. - @param[in] End - It controls whether a STOP is issued aft= er the byte is sent or received. - - @retval EFI_SUCCESS - The byte value written successfully - @retval EFI_DEVICE_ERROR - Operation failed - @retval EFI_TIMEOUT - Hardware retry timeout - @retval Others - Failed to write a byte via I2C -**/ -EFI_STATUS -ByteWriteI2C_Basic ( - IN UINT8 BusNo, - IN UINT8 SlaveAddress, - IN UINTN WriteBytes, - IN UINT8 *WriteBuffer, - IN UINT8 Start, - IN UINT8 End - ) -{ - UINT16 Data16; - EFI_STATUS Status; - UINT32 I2cStatus; - UINT8 *TransmitPtr; - UINT8 *TransmitEnd; - UINT16 raw_intr_stat; - UINTN I2CBaseAddress; - - - I2CBaseAddress =3D (UINT32)LPSS_I2C0_TMP_BAR0 + (BusNo * LPSS_I2C_TMP_BA= R0_DELTA); - Status =3D EFI_SUCCESS; - I2CInit (BusNo, SlaveAddress); - - TransmitPtr =3D WriteBuffer; - TransmitEnd =3D &WriteBuffer[WriteBytes]; - if (WriteBytes > 0x00) { - - - while (TransmitEnd > TransmitPtr) { - I2cStatus =3D I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_STATUS); - raw_intr_stat =3D I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_RAW_INT= R_STAT); - if (0 !=3D (raw_intr_stat & I2C_INTR_TX_ABRT)) { - I2CLibPeiMmioRead16 (I2CBaseAddress + R_IC_CLR_TX_ABRT); - Status =3D RETURN_DEVICE_ERROR; - DEBUG ((DEBUG_ERROR,"TX ABRT TransmitEnd:0x%x WritePtr:0x%x\r\n", = TransmitEnd, TransmitPtr)); - break; - } - if (0 =3D=3D (I2cStatus & STAT_TFNF)) { - DEBUG ((DEBUG_INFO,"%a(#%d) - 0 =3D=3D (I2cStatus & STAT_TFNF)\n",= __FUNCTION__, __LINE__)); - continue; - } - - Data16 =3D (UINT16) *TransmitPtr; - if (End && Start) { - Data16 |=3D (B_CMD_RESTART | B_CMD_STOP); - } else if (!End && Start) { - Data16 |=3D B_CMD_RESTART; - } else if (End && !Start) { - Data16 |=3D B_CMD_STOP; - } - Data16 =3D I2CLibPeiMmioWrite16 (I2CBaseAddress + R_IC_DATA_CMD, Dat= a16); - TransmitPtr++; - - // - // Add a small delay to work around some odd behavior being seen. W= ithout this delay bytes get dropped. - // - MicroSecondDelay (FIFO_WRITE_DELAY); - } - - } - - if (EFI_ERROR (Status)) - DEBUG ((EFI_D_INFO,"I2cStartRequest Exit with Status %r\r\n", Status)); - - return Status; -} - - -/** - Read bytes from I2C Device - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] Offset - Register offset from which the data has = to be read - @param[in] ReadBytes - Number of bytes to be read - @param[out] ReadBuffer - Address to which the value read has to b= e stored - - @retval EFI_SUCCESS - Read bytes from I2C device successfully - @retval Others - Return status depends on ByteReadI2C_Bas= ic -**/ -EFI_STATUS -ByteReadI2C ( - IN UINT8 BusNo, - IN UINT8 SlaveAddress, - IN UINT8 Offset, - IN UINTN ReadBytes, - OUT UINT8 *ReadBuffer - ) -{ - EFI_STATUS Status; - - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, 1, &Offset, TRUE, FA= LSE); - if (EFI_ERROR (Status)) return Status; - Status =3D ByteReadI2C_Basic (BusNo, SlaveAddress, ReadBytes, ReadBuffer= , TRUE, TRUE); - - return Status; -} - -/** - Write bytes to I2C Device - - @param[in] BusNo - I2C Bus number to which the I2C device h= as been connected - @param[in] SlaveAddress - Slave address of the I2C device (7-bit) - @param[in] Offset - Register offset from which the data has = to be read - @param[in] WriteBytes - Number of bytes to be written - @param[in] WriteBuffer - Address to which the byte value has to b= e written - - @retval EFI_SUCCESS - Write bytes to I2C device successfully - @retval Others - Return status depends on ByteWriteI2C_Ba= sic -**/ -EFI_STATUS -ByteWriteI2C ( - IN UINT8 BusNo, - IN UINT8 SlaveAddress, - IN UINT8 Offset, - IN UINTN WriteBytes, - IN UINT8 *WriteBuffer - ) -{ - EFI_STATUS Status; - - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, 1, &Offset, TRUE, FA= LSE); - if (EFI_ERROR (Status)) return Status; - Status =3D ByteWriteI2C_Basic (BusNo, SlaveAddress, WriteBytes, WriteBuf= fer, FALSE, TRUE); - - return Status; -} diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CLibPei.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLi= bPei/I2CLibPei.inf deleted file mode 100644 index 1f920bb..0000000 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CLib= Pei.inf +++ /dev/null @@ -1,51 +0,0 @@ -## @file -# Pei library for I2C bus driver. -# -# Copyright (c) 1999 - 2017, Intel Corporation. All rights reserved.
-# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the B= SD License -# which accompanies this distribution. The full text of the license may b= e found at -# http://opensource.org/licenses/bsd-license.php. -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. -# -## - -[Defines] - INF_VERSION =3D 0x00010005 - BASE_NAME =3D I2CLibPei - FILE_GUID =3D 8EF61509-890B-4FF2-B352-1C0E9CDDEC8B - MODULE_TYPE =3D BASE - VERSION_STRING =3D 1.0 - LIBRARY_CLASS =3D I2CLibPei - - CONSTRUCTOR =3D IntelI2CPeiLibConstructor - -# -# The following information is for reference only and not required by the = build tools. -# -# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC -# - -[Sources.common] - I2CLibPei.c - I2CDelayPei.c - I2CIoLibPei.c - -[LibraryClasses] - -[PPIs] - gEfiPeiStallPpiGuid ## CONSUMES - -[Packages] - MdePkg/MdePkg.dec - BroxtonSiPkg/BroxtonSiPkg.dec - -[Pcd] - gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## SOMETIMES_CONSUMES - gEfiBxtTokenSpaceGuid.PcdPmcGcrBaseAddress ## CONSUMES - - - diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2= cLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cLib= .h new file mode 100644 index 0000000..0083211 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cLib.h @@ -0,0 +1,60 @@ +/** @file + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#ifndef _I2C_COMMON_H_ +#define _I2C_COMMON_H_ +//// +//// Header files +//// +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +// +// Externs +// +extern BOOLEAN gI2cDebugFlag; + +// +// Structures +// +typedef struct _I2C_LPSS_PCI_DEVICE_INFO { + UINT8 Segment; + UINT8 BusNum; + UINT8 DeviceNum; + UINT8 FunctionNum; + UINT32 Bar0; + UINT32 Bar1; +} I2C_LPSS_PCI_DEVICE_INFO; + +typedef struct _LPSS_I2C_CLOCK_SCL_INFO { + UINT16 SS_SCL_HCNT; + UINT16 SS_SCL_LCNT; + UINT16 FS_SCL_HCNT; + UINT16 FS_SCL_LCNT; + UINT16 HS_SCL_HCNT; + UINT16 HS_SCL_LCNT; +} LPSS_I2C_CLOCK_SCL_INFO; + +#endif // _I2C_COMMON_H_ + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2= cNullLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2= cNullLib.c new file mode 100644 index 0000000..6536939 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cNullLi= b.c @@ -0,0 +1,281 @@ +/** @file + I2C library instance. + + Copyright (c) 2017 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BS= D License + which accompanies this distribution. The full text of the license may b= e found at + http://opensource.org/licenses/bsd-license.php. + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMP= LIED. + +**/ + +#include "I2cLibNull.h" + +BOOLEAN gI2cDebugFlag =3D FALSE; + +//// +//// Public I2C functions +//// +// +// Desc: Initializes the controller and returns the MMIO base address +// Input: Bus - I2C controller, 0 based +// Address - 7-bit slave address +// Speed - Uses the I2C_SPEED_ENUM enum to set th= e controller speed +// I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: EFI_SUCCESS - Initialization completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cInit ( + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed, + IN OUT UINT32 *I2cBaseAddress + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Polls the I2C controller with reads until it responds. +// Input: I2cBaseAddress - Pointer to the MMIO base address for t= he I2C controller +// Output: EFI_SUCCESS - Initialization completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// +EFI_STATUS +I2cPoll ( + IN UINT32 I2cBaseAddress + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Read a byte from the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Pointer to where to store the data +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Read completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cRead ( + IN UINT32 I2cBaseAddress, + IN OUT UINT8 *Data, + IN BOOLEAN Start, + IN BOOLEAN End + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Resets the I2C controller into a known good state +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Bus - I2C controller, 0 based +// Address - 7-bit slave address +// Speed - Uses the I2C_SPEED_ENUM enum to set th= e controller speed +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cReset ( + IN UINT32 I2cBaseAddress, + IN UINT8 Bus, + IN UINT16 Address, + IN UINT8 Speed + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Write a byte to the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Data from the I2C controller +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cSendCommand ( + IN UINT32 I2cBaseAddress, + IN UINT32 *Data, + IN BOOLEAN Start, + IN BOOLEAN End + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Set I2C target slave offset +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Offset - Pointer to offset data +// Size - Size of the offset data +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cSetOffset ( + IN UINT32 I2cBaseAddress, + IN UINT8 *Offset, + IN UINT8 Size + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +// +// Desc: Write a byte to the I2C controller +// Input: I2cBaseAddress - MMIO base address for the I2C controll= er +// Data - Data from the I2C controller +// Start - Send start bit? +// End - Send end bit? +// Output: EFI_SUCCESS - Write completed successfully +// EFI_DEVICE_ERROR - I2C controller error +// EFI_INVALID_PARAMETER - Invalid input parameter +// +EFI_STATUS +I2cWrite ( + IN UINT32 I2cBaseAddress, + IN UINT8 Data, + IN BOOLEAN Start, + IN BOOLEAN End + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +/** + Read bytes from I2C Device + This is actual I2C hardware operation function. + + @param[in] BusNo I2C Bus number to which the I2C device= has been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to= be stored + @param[in] Start It controls whether a RESTART is issue= d before the byte is sent or received. + @param[in] End It controls whether a STOP is issued a= fter the byte is sent or received. + + @retval EFI_SUCCESS The byte value read successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to read a byte via I2C + +**/ +EFI_STATUS +ByteReadI2C_Basic ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer, + IN UINT8 Start, + IN UINT8 End + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +/** + Write bytes to I2C Device + This is actual I2C hardware operation function. + + @param[in] BusNo I2C Bus number to which the I2C device= has been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to= be written + @param[in] Start It controls whether a RESTART is issue= d before the byte is sent or received. + @param[in] End It controls whether a STOP is issued a= fter the byte is sent or received. + + @retval EFI_SUCCESS The byte value written successfully + @retval EFI_DEVICE_ERROR Operation failed + @retval EFI_TIMEOUT Hardware retry timeout + @retval Others Failed to write a byte via I2C + +**/ +EFI_STATUS +ByteWriteI2C_Basic ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer, + IN UINT8 Start, + IN UINT8 End + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +/** + Read bytes from I2C Device + + @param[in] BusNo I2C Bus number to which the I2C device h= as been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] Offset Register offset from which the data has = to be read + @param[in] ReadBytes Number of bytes to be read + @param[out] ReadBuffer Address to which the value read has to b= e stored + + @retval EFI_SUCCESS Read bytes from I2C device successfully + @retval Others Return status depends on ByteReadI2C_Bas= ic + +**/ +EFI_STATUS +ByteReadI2C ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN ReadBytes, + OUT UINT8 *ReadBuffer + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + +/** + Write bytes to I2C Device + + @param[in] BusNo I2C Bus number to which the I2C device h= as been connected + @param[in] SlaveAddress Slave address of the I2C device (7-bit) + @param[in] Offset Register offset from which the data has = to be read + @param[in] WriteBytes Number of bytes to be written + @param[in] WriteBuffer Address to which the byte value has to b= e written + + @retval EFI_SUCCESS Write bytes to I2C device successfully + @retval Others Return status depends on ByteWriteI2C_Ba= sic + +**/ +EFI_STATUS +ByteWriteI2C ( + IN UINT8 BusNo, + IN UINT8 SlaveAddress, + IN UINT8 Offset, + IN UINTN WriteBytes, + IN UINT8 *WriteBuffer + ) +{ + if (gI2cDebugFlag) DEBUG ((DEBUG_INFO, "%a(#%4d) - Starting...\n", __FUN= CTION__, __LINE__)); + return EFI_NOT_READY; +} + diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei= /I2CDelayPei.c b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLi= b/I2cNullLib.h similarity index 61% rename from Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/= I2CDelayPei.c rename to Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cNu= llLib.h index 89c3e02..45ca316 100644 --- a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2CLibPei/I2CDel= ayPei.c +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cNullLi= b.h @@ -1,7 +1,5 @@ /** @file - Timer instance for I2C Pei Library. - - Copyright (c) 2014 - 2018, Intel Corporation. All rights reserved.
+ Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
=20 This program and the accompanying materials are licensed and made available under the terms and conditions of the BS= D License @@ -13,11 +11,20 @@ =20 **/ =20 -#include -#include "I2CAccess.h" -#include "I2CDelayPei.h" +#ifndef _I2C_COMMON_NULL_H_ +#define _I2C_COMMON_NULL_H_ +//// +//// Header files +//// +#include + #include -#include -#include +#include + +// +// Externs +// +extern BOOLEAN gI2cDebugFlag; =20 +#endif // _I2C_COMMON_NULL_H_ =20 diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2= cNullLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/= I2cNullLib.inf new file mode 100644 index 0000000..aec234c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/SouthCluster/Library/I2cLib/I2cNullLi= b.inf @@ -0,0 +1,37 @@ +## @file +# Library producing I2C functionality. +# +# Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the B= SD License +# which accompanies this distribution. The full text of the license may b= e found at +# http://opensource.org/licenses/bsd-license.php. +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IM= PLIED. +# +## + +[Defines] + INF_VERSION =3D 0x00010017 + BASE_NAME =3D I2cNullLib + FILE_GUID =3D AFFEF156-2BF4-46C7-B93B-CFAA4093DFEC + VERSION_STRING =3D 1.0 + MODULE_TYPE =3D BASE + LIBRARY_CLASS =3D I2cNullLib + +[Depex] + TRUE + +[LibraryClasses] + DebugLib + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + BroxtonSiPkg/BroxtonSiPkg.dec + +[Sources] + I2cLib.c + I2cLib.h --=20 2.10.1.windows.1 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel