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Fri, 26 Jan 2024 07:12:07 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Eric Xing , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V3 07/32] AMD/VanGoghBoard: Check in PciPlatform Date: Fri, 26 Jan 2024 21:11:00 +0800 Message-ID: <20240126131125.1881-8-duke.zhai@amd.com> In-Reply-To: <20240126131125.1881-1-duke.zhai@amd.com> References: <20240126131125.1881-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|BY5PR12MB4274:EE_ X-MS-Office365-Filtering-Correlation-Id: 93dd25b8-8c6f-49b1-a43d-08dc1e706743 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: frnYmpB14zM5UlVIucBKsB/Ij7p2lqTJNHkajszfaoUxyusXJ/ioHnaKb142mUU5eYnZYbuy/hW5zpYSh5NHJvQwelkg1C0Yo3DaEIo/+s1d22TpelzK8U7BHd54YMR5AK7FIG2VzIXLuKzObapklPflf1uqwjPe4/zpw7LgHvkWBuGNohZOpFKJvGCjfpUaIc++wdUFCh6zih78Z4QTvN1wWjpBkMYg67fPjIbCaHPjchpoh36kt6YB1jEv9YSWg0YnYjCqD871PfLZh7t9EOYTxbh8I3EaRrnPzyX3SImmPBOvHNPwIaeXOL49qJmpjswjvXMAGzQNMehca59UAvuIll9Jkt0eCHoJJZ5GZb/aFJO9RuG6Q3TIrmzWymUHbs4r7+oJHZlbmBpeOd0szqVyWbJWt1uVpcy4nRQS0bZzZn+48kkYl2WIgKTWIAE1ow2brRA9fiaq2oHOPaaVBtYN68D5+K+LRtwEOt6jxqhvqkDw8nVg7oS1067Puk5l0i+oSE6sIEG7yRFtXI6jkE/HRzXA0iFbFvsPEZB4vrOuBHHE9lf9qNPEqYKDvDiNIUgqh2PwBlK6ufhNimIfLhe8SaYkkUn8iaS16gpMypcrtSGt/15nF2mWHb14Rpo4NJf2DCC/BSj50pVJLQerLe7Fie/LrvfngUPJj6NXGDbocTPmDJlULP+twJVKN8isGfAbF+m1DS5O24UDrNps8AsGSCV/8Jx2B9KeJtj05ajVX6ByQRYVHx9OQTD9W0lwkbvQL4JqsvcKZiUnLJLbag== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 13:12:09.6486 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 93dd25b8-8c6f-49b1-a43d-08dc1e706743 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4274 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: X9SwlRnhbbQ6cgFogmjDFU0Bx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706274733974100006 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 In V3: Improve coding style follow edk2 C coding standard. 1.Remove macro definition extra underscores. 2.Putting some AMD copyright in the right place. In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: BIOS detects current IGPU device ID and install corresponding VBIOS. Inital PciPlatform module to load VBIOS and to provide interface for other option ROMs if necessary. Signed-off-by: Duke Zhai Cc: Eric Xing Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Include/Protocol/GlobalNvsArea.h | 63 ++++++ .../PciPlatform/CommonHeader.h | 27 +++ .../PciPlatform/PciPlatform.c | 183 ++++++++++++++++++ .../PciPlatform/PciPlatform.h | 89 +++++++++ .../PciPlatform/PciPlatform.inf | 51 +++++ 5 files changed, 413 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Prot= ocol/GlobalNvsArea.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/= CommonHeader.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/= PciPlatform.c create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/= PciPlatform.h create mode 100644 Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/= PciPlatform.inf diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/Gl= obalNvsArea.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol= /GlobalNvsArea.h new file mode 100644 index 0000000000..36d4f43ebd --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/Include/Protocol/GlobalNvs= Area.h @@ -0,0 +1,63 @@ +/** @file +Definition of the global NVS area protocol. This protocol +publishes the address and format of a global ACPI NVS buffer +used as a communications buffer between SMM code and ASL code. +The format is derived from the ACPI reference code, version 0.95. +Note: Data structures defined in this protocol are not naturally aligned. + +Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef GLOBAL_NVS_AREA_H_ +#define GLOBAL_NVS_AREA_H_ + +// +// Includes +// +#define GLOBAL_NVS_DEVICE_ENABLE 1 +#define GLOBAL_NVS_DEVICE_DISABLE 0 + +// +// Global NVS Area Protocol GUID +// +#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \ +{ 0x74e1e48, 0x8132, 0x47a1, {0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0x= dc} } + +// +// Revision id - Added TPM related fields +// +#define GLOBAL_NVS_AREA_RIVISION_1 1 + +// +// Extern the GUID for protocol users. +// +extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid; + +// +// Global NVS Area definition +// +#pragma pack (1) +typedef struct { + // + // Miscellaneous Dynamic Values, the definitions below need to be matched + // GNVS definitions in Platform.ASL + // + UINT32 TopOfMem; // TOPM + UINT8 NbIoApic; // NAPC + UINT32 PcieBaseAddress; // PCBA + UINT32 PcieBaseLimit; // PCBL +} EFI_GLOBAL_NVS_AREA; +#pragma pack () + +// +// Global NVS Area Protocol +// +typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL { + EFI_GLOBAL_NVS_AREA *Area; +} EFI_GLOBAL_NVS_AREA_PROTOCOL; + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonH= eader.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHead= er.h new file mode 100644 index 0000000000..1297de6369 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/CommonHeader.h @@ -0,0 +1,27 @@ +/** @file + Implements CommonHeader.h + This file includes package header files, library classes and protocol, P= PI & GUID definitions. + + Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef COMMON_HEADER_H_ +#define COMMON_HEADER_H_ + +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlat= form.c b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform= .c new file mode 100644 index 0000000000..aa0a133b1f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.c @@ -0,0 +1,183 @@ +/** @file + Implements PciPlatform.c + Registers onboard PCI ROMs with PCI.IO + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "CommonHeader.h" + +#include "PciPlatform.h" + +PCI_OPTION_ROM_TABLE mPciOptionRomTable[] =3D { + { ONBOARD_SPH_VIDEO_OPTION_ROM_FILE_GUID, 0x1002, 0x1435 }, + { NULL_ROM_FILE_GUID, 0xffff, 0xffff } +}; + +EFI_PCI_PLATFORM_PROTOCOL mPciPlatform =3D { + PhaseNotify, + PlatformPrepController, + GetPlatformPolicy, + GetPciRom +}; + +EFI_HANDLE mPciPlatformHandle =3D NULL; +EFI_HANDLE mImageHandle =3D NULL; + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ) +{ + return EFI_UNSUPPORTED; +} + +/** + Get PlatformPolicy for VGA IO ALIAS + + @param This Protocol instance pointer. + @param PciPolicy PCI Platform Policy. + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ) +{ + *PciPolicy |=3D EFI_RESERVE_VGA_IO_ALIAS; + return EFI_SUCCESS; +} + +/** + Return a PCI ROM image for the onboard device represented by PciHandle + + @param This Protocol instance pointer. + @param PciHandle PCI device to return the ROM image for. + @param RomImage PCI Rom Image for onboard device + @param RomSize Size of RomImage in bytes + + @retval EFI_SUCCESS - RomImage is valid + @retval EFI_NOT_FOUND - No RomImage + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ) +{ + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *PciIo; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Function; + UINT16 VendorId; + UINT16 DeviceId; + UINTN TableIndex; + + Status =3D gBS->HandleProtocol ( + PciHandle, + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + return EFI_NOT_FOUND; + } + + PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Function); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 0, 1, &VendorId); + + PciIo->Pci.Read (PciIo, EfiPciIoWidthUint16, 2, 1, &DeviceId); + + // + // Loop through table of video option rom descriptions + // + for (TableIndex =3D 0; mPciOptionRomTable[TableIndex].VendorId !=3D 0xff= ff; TableIndex++) { + // + // See if the PCI device specified by PciHandle matches at device in m= PciOptionRomTable + // + if ((VendorId !=3D mPciOptionRomTable[TableIndex].VendorId) || + (DeviceId !=3D mPciOptionRomTable[TableIndex].DeviceId)) + { + continue; + } + + Status =3D GetSectionFromAnyFv ( + &mPciOptionRomTable[TableIndex].FileName, + EFI_SECTION_RAW, + 0, + RomImage, + RomSize + ); + + if (EFI_ERROR (Status)) { + continue; + } + + return EFI_SUCCESS; + } + + return EFI_NOT_FOUND; +} + +/** + + @param ImageHandle Handle of driver image. + @param SystemTable Pointer to system table. + + @retval EFI_STATUS return status of InstallProtocolInterface. + +**/ +EFI_STATUS +EFIAPI +PciPlatformDriverEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + + mImageHandle =3D ImageHandle; + + // + // Install on a new handle + // + Status =3D gBS->InstallProtocolInterface ( + &mPciPlatformHandle, + &gEfiPciPlatformProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPciPlatform + ); + + return Status; +} diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlat= form.h b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform= .h new file mode 100644 index 0000000000..a0a4e01161 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.h @@ -0,0 +1,89 @@ +/** @file + Implements PciPlatform.h + This code supports a the private implementation + of the Legacy BIOS Platform protocol + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCI_PLATFORM_H_ +#define PCI_PLATFORM_H_ + +#include +#include +// +// Global variables for Option ROMs +// +#define NULL_ROM_FILE_GUID \ +{ 0x00000000, 0x0000, 0x0000, {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00 }} + +#define ONBOARD_SPH_VIDEO_OPTION_ROM_FILE_GUID \ +{ 0xE7D31EB4, 0x90F3, 0x4A14, {0x8A, 0x28, 0x48, 0xD0, 0x47, 0x42, 0xF8, 0= xE1 }} + +typedef struct { + EFI_GUID FileName; + UINT16 VendorId; + UINT16 DeviceId; +} PCI_OPTION_ROM_TABLE; + +EFI_STATUS +EFIAPI +PhaseNotify ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + +EFI_STATUS +EFIAPI +PlatformPrepController ( + IN EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE HostBridge, + IN EFI_HANDLE RootBridge, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase, + IN EFI_PCI_CHIPSET_EXECUTION_PHASE ChipsetPhase + ); + +/** + Get PlatformPolicy for VGA IO ALIAS + + @param This Protocol instance pointer. + @param PciPolicy PCI Platform Policy. + + @retval EFI_SUCCESS + +**/ +EFI_STATUS +EFIAPI +GetPlatformPolicy ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + OUT EFI_PCI_PLATFORM_POLICY *PciPolicy + ); + +/** + Return a PCI ROM image for the onboard device represented by PciHandle + + @param This Protocol instance pointer. + @param PciHandle PCI device to return the ROM image for. + @param RomImage PCI Rom Image for onboard device + @param RomSize Size of RomImage in bytes + + @retval EFI_SUCCESS - RomImage is valid + @retval EFI_NOT_FOUND - No RomImage + +**/ +EFI_STATUS +EFIAPI +GetPciRom ( + IN CONST EFI_PCI_PLATFORM_PROTOCOL *This, + IN EFI_HANDLE PciHandle, + OUT VOID **RomImage, + OUT UINTN *RomSize + ); + +#endif diff --git a/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlat= form.inf b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatfo= rm.inf new file mode 100644 index 0000000000..16028400ce --- /dev/null +++ b/Platform/AMD/VanGoghBoard/ChachaniBoardPkg/PciPlatform/PciPlatform.inf @@ -0,0 +1,51 @@ +## @file +# PCI Platform INF file +# This driver installs pciplatform protocol to provide access interfaces t= o the onboard pci roms. +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013-2015 Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciPlatform + FILE_GUID =3D E78AE2BF-D5E8-4846-9B0A-2D54AEC3BAF9 + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D PciPlatformDriverEntry + +# +# The following information is for reference only and not required by the = build tools. +# +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC +# + +[Sources] + PciPlatform.c + PciPlatform.h + CommonHeader.h + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + PciLib + PcdLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + UefiDriverEntryPoint + DxeServicesLib + +[Guids] + +[Protocols] + gEfiPciIoProtocolGuid # PROTOCOL ALWAYS_CONSUMED + gEfiPciPlatformProtocolGuid # PROTOCOL ALWAYS_PRODUCED + +[Pcd] + +[Depex] + TRUE --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114582): https://edk2.groups.io/g/devel/message/114582 Mute This Topic: https://groups.io/mt/103975445/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-