From nobody Mon Sep 16 19:52:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114606+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706274817625656.6339156576755; Fri, 26 Jan 2024 05:13:37 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=eadD5PXrB0IpNHy32i1SFdjqj7Nrz1HiaV3TpNz8k6w=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Received-SPF:From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1706274817; v=1; b=blDUt0CJgexoqtrNDNWPos4WSEEufkEobjGdzDet6LI3+WpImSIcAmvukbangUcsrE3wNIJJ PB7JG1qfFF2eSacOLnHzuHBefZ94WnaMCIWToJC9w9TT++5xHDiLS1Q7Mc31+Ov2WHxFfGCmQYk va7Z1LxprkwZ/V+sxRJzvL50= X-Received: by 127.0.0.2 with SMTP id 3akFYY1788612xYjFmaYGykQ; Fri, 26 Jan 2024 05:13:37 -0800 X-Received: from NAM02-BN1-obe.outbound.protection.outlook.com (NAM02-BN1-obe.outbound.protection.outlook.com [40.107.212.69]) by mx.groups.io with SMTP id smtpd.web10.15514.1706274816557313974 for ; Fri, 26 Jan 2024 05:13:36 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=SKtVYffAIpQk0RIsAUrdQMrbJhdWmtHFmdZabmUj2EIvjBh16UTJq5Cu+mL/ziAOjMS+SV/VoObUhiqq/6J7tRAM5Fyn/MQMAYl+oMrjmKeS9mdlzkJcYfctWqDxGenfVW1juoNyFI17HSCB1FmA8ZbL+ayb14GfQgF2IKh/ZZiUrQOhkfrnOWY4loorOLRJFM8dHku0ltyeHAaxG9xbu7EnxUy9B0zII35iA5Vu728O1U6vy4R/1T+5D8mGxgfHXc0MN9X9XW4cNCtat90ZSOwBXppGWOrZBbyx167TizbzU9VtvB8Z7Ll68vWr/HJ8z1IfuVkZtihXBYJ41jZXZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=6DVZIGNoC6u+vDuRuBowghJYmZ8OA24wHea3n5jTaRc=; b=LER0R2NN9FfgNTPYECmM+z3YQyCJoWPbzqdj7Lz8Jv4LbDd40qMHthJEoY11SNdYjgkexaHkA/6ZRTw5GhSyPgUDxXaGcwcZNUO80SyOCefvvzAta4CvbDas9W51LiKEdxetQTD6ZBWCYb9/gHRTMIg7bAMQIdVk+pxcEOuxU5rripFGDK0DQwzs4qm3OjihyLTDF63QewFVQVJwgtOLlbRoW6Z3P+o03zZlpQgwRzNFfZSt/RhV5Alq10yYV6gyueAXh8wNBVTBG0rMsA6piiVCcWFHVyccDvdz6G4WdyMJOmt1rK+V/yikIt2Kgi1BWMJYfDcnPouNurwGJ1V2nw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) X-Received: from CY5PR15CA0092.namprd15.prod.outlook.com (2603:10b6:930:7::6) by LV8PR12MB9133.namprd12.prod.outlook.com (2603:10b6:408:188::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.27; Fri, 26 Jan 2024 13:13:31 +0000 X-Received: from CY4PEPF0000E9D2.namprd03.prod.outlook.com (2603:10b6:930:7:cafe::69) by CY5PR15CA0092.outlook.office365.com (2603:10b6:930:7::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.27 via Frontend Transport; Fri, 26 Jan 2024 13:13:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114606+1787277+3901457@groups.io; helo=mail02.groups.io; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9D2.mail.protection.outlook.com (10.167.241.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 13:13:31 +0000 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 07:13:29 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Eric Xing , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V3 31/32] AMD/VanGoghBoard: Check in AMD SmmControlPei module Date: Fri, 26 Jan 2024 21:11:24 +0800 Message-ID: <20240126131125.1881-32-duke.zhai@amd.com> In-Reply-To: <20240126131125.1881-1-duke.zhai@amd.com> References: <20240126131125.1881-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D2:EE_|LV8PR12MB9133:EE_ X-MS-Office365-Filtering-Correlation-Id: 6c7d47cd-d723-4b62-2791-08dc1e7097ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: 7nTrBNe67w0vF7lFRO9twc7GfWdzz9XHcsRwF78QSfAifLMmqPSXUkQ/pQLTexQuVOnLdHrztqtvBw3UEtqQoRFpykEhiV/s8SW4FUjIg569G8/Nh4vi0sn4SClz0ifEqQuoSzPTf0Xgb0sj+9cy8BLc6iqVxYg0gZnCChA0flWGyS2SRqKhg+P24B+GhaVPfO+xW59V8BeoxhleEq4x05Lu7mhBvhVV2ll5G0Th+OLs4uf7EUJ1Ot8cAOg65ZMgkYql0IQlfaki9PTT52hlJZD+7XEunvD22aPu8AmgLL4lUym/rkW85S83BL6dmnTWhzTi4VCH/M+pBnkwa3cyvZOU4TxuNj3or36SExPJ62NuaTeT36DYqpfQgT0km2byP/Jw4EeTokU/KRKnBWRDS/L+h4D8CvaisTGcOJvruDkZ8/2xTyT+ocJkGcmBfBL3W7nSqa2z4izZOIo6rYdqM5pcL0mlaFCecz/x1byUH0Ui62F0JnsLTEQBgA3iOI47hFTgXIF7vNQVq6yv/pott8NGPtvXppPr0Aq332/XPuFvM3Wl3rGzMH0YouHjtisu+PDrC/ZCXvilEd9EUEdObUMVuXA2H52ypw256SEQ9f61DqcM/0oM8O2981Qd51dOXDIqOsqAiuHEevNgQMNU0T+mGYaOq0iTuz6TxP0v8zJUrtv5916tyo+Z1C+VThtcjYgKTumdJBqpiJAvHBttUv4qWHGOrcCxvYNQtRFrKPHdtBkb5++wPoZ6wTa8BAzw6m5JelnbAXuAvkH40/6HLw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 13:13:31.2705 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6c7d47cd-d723-4b62-2791-08dc1e7097ea X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9D2.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9133 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 2q132kZDu0PbZ57NFtBXhKNLx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706274818208100001 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Initial AMD SmmControlPei module in Silicon folder. This module initializes SMM-related registers, and installs gPeiSmmContro= lPpi. Signed-off-by: Duke Zhai Cc: Eric Xing Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Smm/SmmControlPei/SmmControlPei.c | 307 ++++++++++++++++++ .../Smm/SmmControlPei/SmmControlPei.inf | 40 +++ 2 files changed, 347 insertions(+) create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPe= i.c create mode 100644 Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPe= i.inf diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c b/S= ilicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c new file mode 100644 index 0000000000..4752aede9c --- /dev/null +++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.c @@ -0,0 +1,307 @@ +/** @file + Implements SmmControlPei.c + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include +#include +#include +#include +#include + +/** + This routine generates an SMI + + @param[in] PeiServices Describes the list of possible PE= I Services. + @param[in] This The pointer to this instance of t= his PPI. + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic TRUE to indicate a periodical SMI + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI_SUCCESS SMI generated. + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +PeiTrigger ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ); + +/** + Clear SMI related chipset status. + + @param[in] PeiServices Describes the list of possible PEI Ser= vices. + @param[in] This The pointer to this instance of this P= PI. + @param[in] Periodic TRUE to indicate a periodical SMI. + + @return Return value from ClearSmi() +**/ +EFI_STATUS +EFIAPI +PeiClear ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ); + +STATIC PEI_SMM_CONTROL_PPI mSmmControlPpi =3D { + PeiTrigger, + PeiClear +}; + +STATIC EFI_PEI_PPI_DESCRIPTOR mPpiList =3D { + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), + &gPeiSmmControlPpiGuid, + &mSmmControlPpi +}; + +/** + Init related registers + + @param [in] None + + @retval EFI_LOAD_ERROR Get ACPI MMIO base error. + @retval EFI_SUCCESS The function completed successfully.. +*/ +EFI_STATUS +SmmControlPeiPreInit ( + VOID + ) +{ + UINT16 SmmControlData16; + UINT16 SmmControlMask16; + UINT32 SmmControlData32; + UINT8 SmmControlIndex; + UINT16 AcpiPmBase; + + // + // Get ACPI MMIO base and AcpiPm1EvtBlk address + // + AcpiPmBase =3D MmioRead16 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG60); + + if (0 =3D=3D AcpiPmBase) { + return EFI_LOAD_ERROR; + } + + // + // Clean up all SMI status and enable bits + // + // Clear all SmiControl registers + SmmControlData32 =3D 0; + for (SmmControlIndex =3D FCH_SMI_REGA0; SmmControlIndex <=3D FCH_SMI_REG= C4; SmmControlIndex +=3D 4) { + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + SmmControlIndex, SmmControlDa= ta32); + } + + // Clear all SmiStatus registers (SmiStatus0-4) + SmmControlData32 =3D 0xFFFFFFFF; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG80, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG84, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG8C, SmmControlData32= ); + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG90, SmmControlData32= ); + + // + // If SCI is not enabled, clean up all ACPI PM status/enable registers + // + SmmControlData16 =3D IoRead16 (AcpiPmBase + R_FCH_ACPI_PM_CONTROL); + if (!(SmmControlData16 & BIT0)) { + // Clear WAKE_EN, RTC_EN, SLPBTN_EN, GBL_EN and TMR_EN + SmmControlData16 =3D 0; + SmmControlMask16 =3D (UINT16) ~(BIT15 + BIT10 + BIT9 + BIT5 + BIT0); + IoAndThenOr16 (AcpiPmBase + R_FCH_ACPI_PM1_ENABLE, SmmControlMask16, S= mmControlData16); + + // Clear WAKE_STS, RTC_STS, SLPBTN_STS, GBL_STS and TMR_STS + SmmControlData16 =3D BIT15 + BIT10 + BIT9 + BIT5 + BIT0; + IoWrite16 (AcpiPmBase + R_FCH_ACPI_PM1_STATUS, SmmControlData16); + } + + // + // Set the EOS Bit + // Clear SmiEnB to enable SMI function + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= G98); + SmmControlData32 |=3D BIT28; + SmmControlData32 &=3D ~BIT31; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98, SmmControlData32= ); + + // + // Enable CmdPort SMI + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= GB0); + SmmControlData32 &=3D ~(BIT22 + BIT23); + SmmControlData32 |=3D BIT22; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, SmmControlData32= ); + + return EFI_SUCCESS; +} + +/** + Clear the SMI status + + + @retval EFI_SUCCESS The function completes successfully +**/ +EFI_STATUS +ClearSmi ( + VOID + ) +{ + UINT32 SmmControlData32; + + // + // Clear SmiCmdPort Status Bit + // + SmmControlData32 =3D BIT11; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG88, SmmControlData32= ); + + // + // Set the EOS Bit if it is currently cleared so we can get an SMI other= wise + // leave the register alone + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG= 98); + if ((SmmControlData32 & BIT28) =3D=3D 0) { + SmmControlData32 |=3D BIT28; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REG98, SmmControlData= 32); + } + + return EFI_SUCCESS; +} + +/** + This routine generates an SMI + + @param[in] PeiServices Describes the list of possible PE= I Services. + @param[in] This The pointer to this instance of t= his PPI. + @param[in, out] ArgumentBuffer The buffer of argument + @param[in, out] ArgumentBufferSize The size of the argument buffer + @param[in] Periodic TRUE to indicate a periodical SMI + @param[in] ActivationInterval Interval of periodic SMI + + @retval EFI_SUCCESS SMI generated. + @retval EFI_INVALID_PARAMETER Some parameter value passed is not suppo= rted +**/ +EFI_STATUS +EFIAPI +PeiTrigger ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN OUT INT8 *ArgumentBuffer OPTIONAL, + IN OUT UINTN *ArgumentBufferSize OPTIONAL, + IN BOOLEAN Periodic OPTIONAL, + IN UINTN ActivationInterval OPTIONAL + ) +{ + UINT8 bIndex; + UINT8 bData; + UINT32 SmmControlData32; + UINT16 SmiCmdPort; + + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + if (NULL =3D=3D ArgumentBuffer) { + bIndex =3D 0xff; + } else { + bIndex =3D *ArgumentBuffer; + } + + if (NULL =3D=3D ArgumentBufferSize) { + bData =3D 0xff; + } else { + bData =3D (UINT8)*ArgumentBufferSize; + } + + // + // Enable CmdPort SMI + // + SmmControlData32 =3D MmioRead32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_RE= GB0); + SmmControlData32 &=3D ~(BIT22 + BIT23); + SmmControlData32 |=3D BIT22; + MmioWrite32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0, SmmControlData32= ); + + SmiCmdPort =3D PcdGet16 (PcdAmdFchCfgSmiCmdPortAddr); + + // + // Issue command port SMI + // + IoWrite16 (SmiCmdPort, (bData << 8) + bIndex); + return EFI_SUCCESS; +} + +/** + Clear SMI related chipset status. + + @param[in] PeiServices Describes the list of possible PEI Ser= vices. + @param[in] This The pointer to this instance of this P= PI. + @param[in] Periodic TRUE to indicate a periodical SMI. + + @return Return value from ClearSmi() +**/ +EFI_STATUS +EFIAPI +PeiClear ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_CONTROL_PPI *This, + IN BOOLEAN Periodic OPTIONAL + ) +{ + if (Periodic) { + return EFI_INVALID_PARAMETER; + } + + return ClearSmi (); +} + +/** + This is the constructor for the SMM Control Ppi. + + This function installs PEI_SMM_CONTROL_PPI. + + @param FileHandle Handle of the file being invoked. + @param PeiServices Describes the list of possible PEI Services. + + @retval EFI_UNSUPPORTED There's no Intel ICH on this platform + @return The status returned from PeiServicesInstallPpi(). + +--*/ +EFI_STATUS +SmmControlPeiEntry ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + + Status =3D PeiServicesGetBootMode (&BootMode); + ASSERT_EFI_ERROR (Status); + + DEBUG ((DEBUG_INFO, "PeiSmmControl Enter\n")); + + if (BootMode !=3D BOOT_ON_S3_RESUME) { + return EFI_UNSUPPORTED; + } + + // + // Initialize EFI library + // + Status =3D SmmControlPeiPreInit (); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D PeiServicesInstallPpi (&mPpiList); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf b= /Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf new file mode 100644 index 0000000000..d6c984f02a --- /dev/null +++ b/Silicon/AMD/VanGoghBoard/Smm/SmmControlPei/SmmControlPei.inf @@ -0,0 +1,40 @@ +## @file +# AMD Smm Contro lPei +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PeiSmmControl + FILE_GUID =3D EC9519B1-E788-4C45-B695-244457442D64 + MODULE_TYPE =3D PEIM + VERSION_STRING =3D 1.0 + ENTRY_POINT =3D SmmControlPeiEntry + +[Sources.common] + SmmControlPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + AgesaPublic/AgesaPublic.dec + +[LibraryClasses] + IoLib + DebugLib + PeiServicesLib + PeimEntryPoint + +[Guids] + +[Pcd] + gEfiAmdAgesaPkgTokenSpaceGuid.PcdAmdFchCfgSmiCmdPortAddr ## CONSUMES + +[Ppis] + gPeiSmmControlPpiGuid #PRODUCED + +[Depex] + gEfiPeiMasterBootModePpiGuid --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114606): https://edk2.groups.io/g/devel/message/114606 Mute This Topic: https://groups.io/mt/103975490/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-