From nobody Mon Sep 16 19:58:10 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce+27952+114595+1787277+3901457@groups.io; arc=fail (BodyHash is different from the expected one) Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by mx.zohomail.com with SMTPS id 1706274789257620.5158098664078; Fri, 26 Jan 2024 05:13:09 -0800 (PST) Return-Path: DKIM-Signature: a=rsa-sha256; bh=LvUcaJ03wAa43x4gTpxsAX3IbYDNgK8mo6O6BDVa3TE=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:Received-SPF:From:To:CC:Subject:Date:Message-ID:In-Reply-To:References:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Transfer-Encoding:Content-Type; s=20140610; t=1706274788; v=1; b=kXLGZou0tv5SVOfDAN00CiVZmKpyqV7EghPqYY0DAmoqJMs4WMBf84eE9xcsPcU9HOMfK5Zl c23RkxC+3l/6ZdOCxlal7Ww2IWLdfP+ZX26sDNjmfjdorJde0hxhleuFXFLY6wWe1ArrZRmOy+v JOGKnIH+/ms+QnNgbYfhbWGI= X-Received: by 127.0.0.2 with SMTP id rVHqYY1788612xYazfjGGP76; Fri, 26 Jan 2024 05:13:08 -0800 X-Received: from NAM11-BN8-obe.outbound.protection.outlook.com (NAM11-BN8-obe.outbound.protection.outlook.com [40.107.236.41]) by mx.groups.io with SMTP id smtpd.web11.15473.1706274787769553065 for ; Fri, 26 Jan 2024 05:13:08 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=dtS3vu/AQmlJt29g//oJBSv7ji51EZXj5JezLMYy+VdrL5lRZe4qcG/z7FwbRoW9p3eHsnmsVY6dSBz+RLhxgCPTpC6oqG1rBpuHYHlz6Dy6qh2auF6CTFCFVdWzf3maILs0ItsByro57S6IZfkpO/TF4JwqKAHqOyM1DtAIJ9JdBju452iBIKyd0v9K0OHfM6YW3anMroE7LqIfH+d3Ym6CyqjCrGEfyZ5g00aS+WF9K9PkWqUX1/CxzA3PPj69yeSDyw3SnTr+fszNY9NAXYINs6/19W4y2krXoByMPpwnBDSzkvRkuC82DXb17wtZjd7hJe3FxPSwx6cfWKcKrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=P4QRmle5nIwdjf7hBKfvfDrNNvBva9t7mqjGJdUPGFU=; b=ViT1S0f+X1r7BE27m+Y+Dm+c4JMu5jh47XCrJjtS93+UxoCyH7ZFk+x07Y/ZKur9+e7WduAjFKwemScahQoKMM3ZWfm4eIx/WucTfM9iUkeBp0kAquQ+JKidRPkZ0XJ1YqesCATCnkMZ9Ij9pcUnTL1lN7oLgE8h6CUyo/J8/Z4hPKhyHn71oPueOnSN9fAM7Vr/46Gla5qBpeQBu/VBS7opC+rcfuYkdpdeDABJP0Mown1S0u8+lM8g2dW/u5MqZLR79vuA+3goNQQxDKRxJSb0jGRYqbuHonRG126nDc6wBMCiNaVjeUCtlybMdO5Ux38kR1ia4UPysLWyMNm6ow== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 165.204.84.17) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=amd.com; dmarc=pass (p=quarantine sp=quarantine pct=100) action=none header.from=amd.com; dkim=none (message not signed); arc=none (0) X-Received: from CY5PR15CA0121.namprd15.prod.outlook.com (2603:10b6:930:68::12) by CH2PR12MB4245.namprd12.prod.outlook.com (2603:10b6:610:af::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.27; Fri, 26 Jan 2024 13:13:01 +0000 X-Received: from CY4PEPF0000E9CE.namprd03.prod.outlook.com (2603:10b6:930:68:cafe::e4) by CY5PR15CA0121.outlook.office365.com (2603:10b6:930:68::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7228.22 via Frontend Transport; Fri, 26 Jan 2024 13:13:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: pass (zohomail.com: domain of groups.io designates 66.175.222.108 as permitted sender) client-ip=66.175.222.108; envelope-from=bounce+27952+114595+1787277+3901457@groups.io; helo=mail02.groups.io; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C X-Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000E9CE.mail.protection.outlook.com (10.167.241.141) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7228.16 via Frontend Transport; Fri, 26 Jan 2024 13:13:00 +0000 X-Received: from SHA-LX-MINGXZHA.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 26 Jan 2024 07:12:57 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Eric Xing , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V3 18/32] AMD/VanGoghBoard: Check in PciHostBridge module Date: Fri, 26 Jan 2024 21:11:11 +0800 Message-ID: <20240126131125.1881-19-duke.zhai@amd.com> In-Reply-To: <20240126131125.1881-1-duke.zhai@amd.com> References: <20240126131125.1881-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CH2PR12MB4245:EE_ X-MS-Office365-Filtering-Correlation-Id: 74f863fd-9ed3-4fd1-f64a-08dc1e7085a5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: WHeGF145zXDed/0kxioWx0c3+Pq7UHCrtk0qIkyGoyJhA2jJbTHdZ/Ml0+QeiJIM5yZvZtvo2eSwz3FcVbWsbkqiPZz4hukgxQMoafc3xIBJ9zWupb8qIFwdoRRuMA/CP9+7l+LtqLMlw9R1fnZf/WpK0Ai6WmynOLsPA1o0PN5UhYJJ8BTXa+ReGhS5DxvBYe2djaZfTKB2/o6P9fB30T2df+c2a9duGsDpL96pMgCKbLjXPFOQ6yBJo0zpU6sDEZi8Rz3yB0e/7suNA+0oVn0vJxBUomfFjUDOrnQdPwVO4LPjbEUV0s7NYPGCaKlxg3cWfjwcXmTMdQOuMs3W5cixOFm7Se2X+7uSafg0R+u/41Yetk+m9DkaFkvqEHnNmlihMkgj0aflKfvxgPtl/2ssBmuN/yUjXaJAZa/+YWaA0R7/coXeK+KbeKuZ3ryq5k5NZkA+6uRSn9buM8RMexvCpnNYIyxcSTqXO33T5OR+dGq/imDkDucDvq+krYu/DlpOlsR3V6+8Qe5HD5+MzmQErHkDOd/0dqPRDM674hpz0y2vEfFMvQQH68/Uk26m0wO5+vr6p6zKND+d80Zch9wJF9LV014X7HEpsLbK0l4vdYE1zzfKmAuTJ5Y8jGzJ05h3R64hCHwY56WLU5Z/dqo4O0nIz0FNh65Y2ySn18kAyCJbAdxQPLOYo/3M4wUOeYY9+Y5X4w9gneE4PV6Lmt0258tnLT+DW4070TO58fzF+na+T0GGIiVmojW9jK+ceYuwHMNovgyoWazmXghECTXcMtHlqurBrzxu2GXX8SM= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 13:13:00.6090 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74f863fd-9ed3-4fd1-f64a-08dc1e7085a5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4245 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: lhfoG5NbCyiiwo652JsdlfNAx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706274790264100013 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 In V3: Improve coding style follow edk2 C coding standard. 1.Remove macro definition extra underscores. 2.Putting some AMD copyright in the right place. In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Initial PciHostBridge module. Provides the basic interfaces to abstract a PCI Host Bridge Resource Allocation. Signed-off-by: Duke Zhai Cc: Eric Xing Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Bus/Pci/PciHostBridgeDxe/IoFifo.h | 170 ++ .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.c | 1370 ++++++++++ .../Bus/Pci/PciHostBridgeDxe/PciHostBridge.h | 624 +++++ .../Pci/PciHostBridgeDxe/PciHostBridge.uni | Bin 0 -> 1290 bytes .../Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf | 54 + .../PciHostBridgeDxe/PciHostBridgeExtra.uni | Bin 0 -> 826 bytes .../Pci/PciHostBridgeDxe/PciRootBridgeIo.c | 2421 +++++++++++++++++ 7 files changed, 4639 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/IoFifo.h create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciHostBridge.c create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciHostBridge.h create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciHostBridge.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciHostBridgeExtra.uni create mode 100644 Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bu= s/Pci/PciHostBridgeDxe/PciRootBridgeIo.c diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/IoFifo.h b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModul= ePkg/Bus/Pci/PciHostBridgeDxe/IoFifo.h new file mode 100644 index 0000000000..cd6ed34f22 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/PciHostB= ridgeDxe/IoFifo.h @@ -0,0 +1,170 @@ +/** @file + Implementation of IoFifo.h + I/O FIFO routines + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef IO_FIFO_H_INCLUDED_ +#define IO_FIFO_H_INCLUDED_ + +/** + Reads an 8-bit I/O port fifo into a block of memory. + + Reads the 8-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Reads a 16-bit I/O port fifo into a block of memory. + + Reads the 16-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Reads a 32-bit I/O port fifo into a block of memory. + + Reads the 32-bit I/O fifo port specified by Port. + + The port is read Count times, and the read data is + stored in the provided Buffer. + + This function must guarantee that all I/O read and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to read. + @param Count The number of times to read I/O port. + @param Buffer The buffer to store the read data into. + +**/ +VOID +EFIAPI +IoReadFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into an 8-bit I/O port fifo. + + Writes the 8-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 8-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo8 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 16-bit I/O port fifo. + + Writes the 16-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 16-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo16 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Writes a block of memory into a 32-bit I/O port fifo. + + Writes the 32-bit I/O fifo port specified by Port. + + The port is written Count times, and the write data is + retrieved from the provided Buffer. + + This function must guarantee that all I/O write and write operations are + serialized. + + If 32-bit I/O port operations are not supported, then ASSERT(). + + @param Port The I/O port to write. + @param Count The number of times to write I/O port. + @param Buffer The buffer to store the write data into. + +**/ +VOID +EFIAPI +IoWriteFifo32 ( + IN UINTN Port, + IN UINTN Count, + OUT VOID *Buffer + ); + +#endif diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciHostBridge.c b/Platform/AMD/VanGoghBoard/Override/edk2/M= deModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.c new file mode 100644 index 0000000000..6fc9b22b8f --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/PciHostB= ridgeDxe/PciHostBridge.c @@ -0,0 +1,1370 @@ +/** @file + Implementation of PciHostBridge.c + Provides the basic interfaces to abstract a PCI Host Bridge Resource + Allocation + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciHostBridge.h" +#define TOP_MEM 0xC001001Aul + +// +// Hard code: Root Bridge Number within the host bridge +// Root Bridge's attribute +// Root Bridge's device path +// Root Bridge's resource aperture +// +UINTN RootBridgeNumber[1] =3D { 1 }; + +UINT64 RootBridgeAttribute[1][1] =3D { + { EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM } +}; + +EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[1][1] =3D { + { + { + { + { + ACPI_DEVICE_PATH, + ACPI_DP, + { + (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), + (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) + } + }, + EISA_PNP_ID (0x0A03), + 0 + }, + + { + END_DEVICE_PATH_TYPE, + END_ENTIRE_DEVICE_PATH_SUBTYPE, + { + END_DEVICE_PATH_LENGTH, + 0 + } + } + } + } +}; + +PCI_ROOT_BRIDGE_RESOURCE_APERTURE mResAperture[1][1] =3D { + { + { 0, 0xff, 0xE0000000, 0xffffffff, 0, 0xffff } + } +}; + +EFI_HANDLE mDriverImageHandle; + +PCI_HOST_BRIDGE_INSTANCE mPciHostBridgeInstanceTemplate =3D { + PCI_HOST_BRIDGE_SIGNATURE, // Signature + NULL, // HostBridgeHandle + 0, // RootBridgeNumber + { NULL, NULL }, // Head + FALSE, // ResourceSubiteed + TRUE, // CanRestarted + { + NotifyPhase, + GetNextRootBridge, + GetAttributes, + StartBusEnumeration, + SetBusNumbers, + SubmitResources, + GetProposedResources, + PreprocessController + } +}; + +// +// Implementation +// + +/** + Entry point of this driver + + @param ImageHandle Handle of driver image + @param SystemTable Point to EFI_SYSTEM_TABLE + + @retval EFI_OUT_OF_RESOURCES Can not allocate memory resource + @retval EFI_DEVICE_ERROR Can not install the protocol instance + @retval EFI_SUCCESS Success to initialize the Pci host bridge. +**/ +EFI_STATUS +EFIAPI +InitializePciHostBridge ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + UINTN Loop1; + UINTN Loop2; + PCI_HOST_BRIDGE_INSTANCE *HostBridge; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + EFI_PHYSICAL_ADDRESS TopOfLowMem; + + mDriverImageHandle =3D ImageHandle; + TopOfLowMem =3D AsmReadMsr64 (TOP_MEM); + mResAperture[0][0].MemBase =3D TopOfLowMem; + + // + // Create Host Bridge Device Handle + // + for (Loop1 =3D 0; Loop1 < HOST_BRIDGE_NUMBER; Loop1++) { + HostBridge =3D AllocateCopyPool ( + sizeof (PCI_HOST_BRIDGE_INSTANCE), + &mPciHostBridgeInstanceTemplate + ); + if (HostBridge =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + HostBridge->RootBridgeNumber =3D RootBridgeNumber[Loop1]; + InitializeListHead (&HostBridge->Head); + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &HostBridge->HostBridgeHandle, + &gEfiPciHostBridgeResourceAllocationProtocolGuid, + &HostBridge->ResAlloc, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (HostBridge); + return EFI_DEVICE_ERROR; + } + + // + // Create Root Bridge Device Handle in this Host Bridge + // + + for (Loop2 =3D 0; Loop2 < HostBridge->RootBridgeNumber; Loop2++) { + PrivateData =3D AllocateZeroPool (sizeof (PCI_ROOT_BRIDGE_INSTANCE)); + if (PrivateData =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + PrivateData->Signature =3D PCI_ROOT_BRIDGE_SIGNATURE; + PrivateData->DevicePath =3D + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[Loop1][Lo= op2]; + + RootBridgeConstructor ( + &PrivateData->Io, + HostBridge->HostBridgeHandle, + RootBridgeAttribute[Loop1][Loop2], + &mResAperture[Loop1][Loop2] + ); + + Status =3D gBS->InstallMultipleProtocolInterfaces ( + &PrivateData->Handle, + &gEfiDevicePathProtocolGuid, + PrivateData->DevicePath, + &gEfiPciRootBridgeIoProtocolGuid, + &PrivateData->Io, + NULL + ); + if (EFI_ERROR (Status)) { + FreePool (PrivateData); + return EFI_DEVICE_ERROR; + } + + InsertTailList (&HostBridge->Head, &PrivateData->Link); + } + } + + Status =3D gDS->AddIoSpace ( + EfiGcdIoTypeIo, + 0x2000, + 0xFFFF-0x2000 + ); + ASSERT_EFI_ERROR (Status); + TopOfLowMem =3D AsmReadMsr64 (TOP_MEM); + Status =3D gDS->AddMemorySpace ( + EfiGcdMemoryTypeMemoryMappedIo, + TopOfLowMem, + 0xF8000000-TopOfLowMem, + 0 + ); + + return EFI_SUCCESS; +} + +/** + These are the notifications from the PCI bus driver that it is about to = enter + a certain phase of the PCI enumeration process. + + This member function can be used to notify the host bridge driver to per= form + specific actions, including any chipset-specific initialization, so that= the + chipset is ready to enter the next phase. Eight notification points are + defined at this time. See belows: + + EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertu= res + and internal data structures. The= PCI + enumerator should issue this + notification before starting a fr= esh + enumeration process. Enumeration + cannot be restarted after sending= any + other notification such as + EfiPciHostBridgeBeginBusAllocatio= n. + + EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about= to + begin. No specific action is requ= ired + here. This notification can be us= ed to + perform any chipset-specific + programming. + + EfiPciHostBridgeEndBusAllocation The bus allocation and bus progra= mming + phase is complete. No specific ac= tion + is required here. This notificati= on + can be used to perform any + chipset-specific programming. + + EfiPciHostBridgeBeginResourceAllocation + The resource allocation phase is = about + to begin. No specific action is + required here. This notification = can + be used to perform any + chipset-specific programming. + + EfiPciHostBridgeAllocateResources Allocates resources per previously + submitted requests for all the PCI + root bridges. These resource sett= ings + are returned on the next call to + GetProposedResources(). Before ca= lling + NotifyPhase() with a Phase of + EfiPciHostBridgeAllocateResource,= the + PCI bus enumerator is responsible= for + gathering I/O and memory requests= for + all the PCI root bridges and + submitting these requests using + SubmitResources(). This function = pads + the resource amount to suit the r= oot + bridge hardware, takes care of + dependencies between the PCI root + bridges, and calls the Global + Coherency Domain (GCD) with the + allocation request. In the case of + padding, the allocated range coul= d be + bigger than what was requested. + + EfiPciHostBridgeSetResources Programs the host bridge hardware= to + decode previously allocated resou= rces + (proposed resources) for all the = PCI + root bridges. After the hardware = is + programmed, reassigning resources= will + not be supported. The bus setting= s are + not affected. + + EfiPciHostBridgeFreeResources Deallocates resources that were + previously allocated for all the = PCI + root bridges and resets the I/O a= nd + memory apertures to their initial + state. The bus settings are not + affected. If the request to alloc= ate + resources fails, the PCI enumerat= or + can use this notification to + deallocate previous resources, ad= just + the requests, and retry allocatio= n. + + EfiPciHostBridgeEndResourceAllocation The resource allocation phase is + completed. No specific action is + required here. This notification = can + be used to perform any chipsetspe= cific + programming. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_P= ROTOCOL + @param[in] Phase The phase during enumeration + + @retval EFI_NOT_READY This phase cannot be entered at this time= . For + example, this error is valid for a Phase = of + EfiPciHostBridgeAllocateResources if + SubmitResources() has not been called for= one + or more PCI root bridges before this call + @retval EFI_DEVICE_ERROR Programming failed due to a hardware erro= r. + This error is valid for a Phase of + EfiPciHostBridgeSetResources. + @retval EFI_INVALID_PARAMETER Invalid phase parameter + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. This error is valid fo= r a + Phase of EfiPciHostBridgeAllocateResource= s if + the previously submitted resource requests + cannot be fulfilled or were only partially + fulfilled. + @retval EFI_SUCCESS The notification was accepted without any + errors. +**/ +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + PCI_RESOURCE_TYPE Index; + LIST_ENTRY *List; + EFI_PHYSICAL_ADDRESS BaseAddress; + UINT64 AddrLen; + UINTN BitsOfAlignment; + EFI_STATUS Status; + EFI_STATUS ReturnStatus; + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + + switch (Phase) { + case EfiPciHostBridgeBeginEnumeration: + if (HostBridgeInstance->CanRestarted) { + // + // Reset the Each Root Bridge + // + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index =3D TypeIo; Index < TypeMax; Index++) { + RootBridgeInstance->ResAllocNode[Index].Type =3D Index; + RootBridgeInstance->ResAllocNode[Index].Base =3D 0; + RootBridgeInstance->ResAllocNode[Index].Length =3D 0; + RootBridgeInstance->ResAllocNode[Index].Status =3D ResNone; + } + + List =3D List->ForwardLink; + } + + HostBridgeInstance->ResourceSubmited =3D FALSE; + HostBridgeInstance->CanRestarted =3D TRUE; + } else { + // + // Can not restart + // + return EFI_NOT_READY; + } + + break; + + case EfiPciHostBridgeEndEnumeration: + break; + + case EfiPciHostBridgeBeginBusAllocation: + // + // No specific action is required here, can perform any chipset spec= ific + // programing + // + HostBridgeInstance->CanRestarted =3D FALSE; + break; + + case EfiPciHostBridgeEndBusAllocation: + // + // No specific action is required here, can perform any chipset spec= ific + // programing + // + // HostBridgeInstance->CanRestarted =3D FALSE; + break; + + case EfiPciHostBridgeBeginResourceAllocation: + // + // No specific action is required here, can perform any chipset spec= ific + // programing + // + // HostBridgeInstance->CanRestarted =3D FALSE; + break; + + case EfiPciHostBridgeAllocateResources: + ReturnStatus =3D EFI_SUCCESS; + if (HostBridgeInstance->ResourceSubmited) { + // + // Take care of the resource dependencies between the root bridges + // + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index =3D TypeIo; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNon= e) { + AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; + + // + // Get the number of '1' in Alignment. + // + BitsOfAlignment =3D + (UINTN)(HighBitSet64 ( + RootBridgeInstance->ResAllocNode[Index].Alignment + ) + 1); + + switch (Index) { + case TypeIo: + // + // It is impossible for this chipset to align 0xFFFF for= IO16 + // So clear it + // + if (BitsOfAlignment >=3D 16) { + BitsOfAlignment =3D 0; + } + + Status =3D gDS->AllocateIoSpace ( + EfiGcdAllocateAnySearchBottomUp, + EfiGcdIoTypeIo, + BitsOfAlignment, + AddrLen, + &BaseAddress, + mDriverImageHandle, + NULL + ); + + if (!EFI_ERROR (Status)) { + RootBridgeInstance->ResAllocNode[Index].Base =3D + (UINTN)BaseAddress; + RootBridgeInstance->ResAllocNode[Index].Status =3D + ResAllocated; + } else { + ReturnStatus =3D Status; + if (Status !=3D EFI_OUT_OF_RESOURCES) { + RootBridgeInstance->ResAllocNode[Index].Length =3D 0; + } + } + + break; + + case TypeMem32: + // + // It is impossible for this chipset to align 0xFFFFFFFF= for + // Mem32 + // So clear it + // + + if (BitsOfAlignment >=3D 32) { + BitsOfAlignment =3D 0; + } + + Status =3D gDS->AllocateMemorySpace ( + EfiGcdAllocateAnySearchBottomUp, + EfiGcdMemoryTypeMemoryMappedIo, + BitsOfAlignment, + AddrLen, + &BaseAddress, + mDriverImageHandle, + NULL + ); + + if (!EFI_ERROR (Status)) { + // We were able to allocate the PCI memory + RootBridgeInstance->ResAllocNode[Index].Base =3D + (UINTN)BaseAddress; + RootBridgeInstance->ResAllocNode[Index].Status =3D + ResAllocated; + } else { + // Not able to allocate enough PCI memory + ReturnStatus =3D Status; + + if (Status !=3D EFI_OUT_OF_RESOURCES) { + RootBridgeInstance->ResAllocNode[Index].Length =3D 0; + } + + ASSERT (FALSE); + } + + break; + + case TypePMem32: + case TypeMem64: + case TypePMem64: + ReturnStatus =3D EFI_ABORTED; + break; + default: + ASSERT (FALSE); + break; + } // end switch + } + } + + List =3D List->ForwardLink; + } + + return ReturnStatus; + } else { + return EFI_NOT_READY; + } + + break; + + case EfiPciHostBridgeSetResources: + break; + + case EfiPciHostBridgeFreeResources: + ReturnStatus =3D EFI_SUCCESS; + List =3D HostBridgeInstance->Head.ForwardLink; + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + for (Index =3D TypeIo; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status =3D=3D ResAll= ocated) { + AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Length; + BaseAddress =3D RootBridgeInstance->ResAllocNode[Index].Base; + switch (Index) { + case TypeIo: + Status =3D gDS->FreeIoSpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus =3D Status; + } + + break; + + case TypeMem32: + Status =3D gDS->FreeMemorySpace (BaseAddress, AddrLen); + if (EFI_ERROR (Status)) { + ReturnStatus =3D Status; + } + + break; + + case TypePMem32: + break; + + case TypeMem64: + break; + + case TypePMem64: + break; + + default: + ASSERT (FALSE); + break; + } // end switch + + RootBridgeInstance->ResAllocNode[Index].Type =3D Index; + RootBridgeInstance->ResAllocNode[Index].Base =3D 0; + RootBridgeInstance->ResAllocNode[Index].Length =3D 0; + RootBridgeInstance->ResAllocNode[Index].Status =3D ResNone; + } + } + + List =3D List->ForwardLink; + } + + HostBridgeInstance->ResourceSubmited =3D FALSE; + HostBridgeInstance->CanRestarted =3D TRUE; + return ReturnStatus; + + case EfiPciHostBridgeEndResourceAllocation: + HostBridgeInstance->CanRestarted =3D FALSE; + break; + + default: + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} + +/** + Return the device handle of the next PCI root bridge that is associated = with + this Host Bridge. + + This function is called multiple times to retrieve the device handles of= all + the PCI root bridges that are associated with this PCI host bridge. Each= PCI + host bridge is associated with one or more PCI root bridges. On each cal= l, + the handle that was returned by the previous call is passed into the + interface, and on output the interface returns the device handle of the = next + PCI root bridge. The caller can use the handle to obtain the instance of= the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no = more + PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI + enumerator must enumerate the PCI root bridges in the order that they are + returned by this function. + + For D945 implementation, there is only one root bridge in PCI host bridg= e. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATI= ON_PROTOCOL + @param[in, out] RootBridgeHandle Returns the device handle of the next= PCI + root bridge. + + @retval EFI_SUCCESS If parameter RootBridgeHandle =3D NULL, t= hen + return the first Rootbridge handle of the + specific Host bridge and return EFI_SUCCE= SS. + @retval EFI_NOT_FOUND Can not find the any more root bridge in + specific host bridge. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE tha= t was + returned on a previous call to + GetNextRootBridge(). +**/ +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHa= ndle + ) +{ + BOOLEAN NoRootBridge; + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + NoRootBridge =3D TRUE; + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + NoRootBridge =3D FALSE; + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (*RootBridgeHandle =3D=3D NULL) { + // + // Return the first Root Bridge Handle of the Host Bridge + // + *RootBridgeHandle =3D RootBridgeInstance->Handle; + return EFI_SUCCESS; + } else { + if (*RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + // + // Get next if have + // + List =3D List->ForwardLink; + if (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + *RootBridgeHandle =3D RootBridgeInstance->Handle; + return EFI_SUCCESS; + } else { + return EFI_NOT_FOUND; + } + } + } + + List =3D List->ForwardLink; + } // end while + + if (NoRootBridge) { + return EFI_NOT_FOUND; + } else { + return EFI_INVALID_PARAMETER; + } +} + +/** + Returns the allocation attributes of a PCI root bridge. + + The function returns the allocation attributes of a specific PCI root br= idge. + The attributes can vary from one PCI root bridge to another. These attri= butes + are different from the decode-related attributes that are returned by the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The + RootBridgeHandle parameter is used to specify the instance of the PCI ro= ot + bridge. The device handles of all the root bridges that are associated w= ith + this host bridge must be obtained by calling GetNextRootBridge(). The + attributes are static in the sense that they do not change during or aft= er + the enumeration process. The hardware may provide mechanisms to change t= he + attributes on the fly, but such changes must be completed before + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permi= tted + values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined= in + "Related Definitions" below. The caller uses these attributes to combine + multiple resource requests. + + For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, th= e PCI + bus enumerator needs to include requests for the prefetchable memory in = the + nonprefetchable memory pool and not request any prefetchable memory. + + Attribute Description + ------------------------------------ ----------------------------------= ----- + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI r= oot + bridge does not support separate + windows for nonprefetchable and + prefetchable memory. A PCI bus dri= ver + needs to include requests for + prefetchable memory in the + nonprefetchable memory pool. + + EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI r= oot + bridge supports 64-bit memory wind= ows. + If this bit is not set, the PCI bus + driver needs to include requests f= or a + 64-bit memory address in the + corresponding 32-bit memory pool. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_= PROTOCOL + @param[in] RootBridgeHandle The device handle of the PCI root bridge= in + which the caller is interested. Type + EFI_HANDLE is defined in + InstallProtocolInterface() in the UEFI 2= .0 + Specification. + @param[out] Attributes The pointer to attribte of root bridge, = it is + output parameter + + @retval EFI_INVALID_PARAMETER Attribute pointer is NULL + @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. + @retval EFI_SUCCESS Success to get attribute of interested r= oot + bridge. +**/ +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + + if (Attributes =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + *Attributes =3D RootBridgeInstance->RootBridgeAttrib; + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + // + // RootBridgeHandle is not an EFI_HANDLE + // that was returned on a previous call to GetNextRootBridge() + // + return EFI_INVALID_PARAMETER; +} + +/** + Sets up the specified PCI root bridge for the bus enumeration process. + + This member function sets up the root bridge for bus enumeration and ret= urns + the PCI bus range over which the search should be performed in ACPI 2.0 + resource descriptor format. + + @param[in] This The + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_P= ROTOCOL + instance. + @param[in] RootBridgeHandle The PCI Root Bridge to be set up. + @param[out] Configuration Pointer to the pointer to the PCI bus res= ource + descriptor. + + @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle + @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor = tag. + @retval EFI_SUCCESS Sucess to allocate ACPI resource descripto= r. +**/ +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + VOID *Buffer; + UINT8 *Temp; + UINT64 BusStart; + UINT64 BusEnd; + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + // + // Set up the Root Bridge for Bus Enumeration + // + BusStart =3D RootBridgeInstance->BusBase; + BusEnd =3D RootBridgeInstance->BusLimit; + // + // Program the Hardware(if needed) if error return EFI_DEVICE_ERROR + // + + Buffer =3D AllocatePool ( + sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) + ); + if (Buffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Temp =3D (UINT8 *)Buffer; + + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Desc = =3D 0x8A; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->Len = =3D 0x2B; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->ResType = =3D 2; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->GenFlag = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->SpecificFlag = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrSpaceGranularity = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMin = =3D BusStart; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrRangeMax = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrTranslationOffset = =3D 0; + ((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp)->AddrLen = =3D + BusEnd - BusStart + 1; + + Temp =3D Temp + sizeof (E= FI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc =3D 0x79; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum =3D 0x0; + + *Configuration =3D Buffer; + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Programs the PCI root bridge hardware so that it decodes the specified P= CI + bus range. + + This member function programs the specified PCI root bridge to decode th= e bus + range that is specified by the input parameter Configuration. + The bus range information is specified in terms of the ACPI 2.0 resource + descriptor format. + + @param[in] This The + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance + @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be + programmed + @param[in] Configuration The pointer to the PCI bus resource descrip= tor + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root brid= ge + handle. + @retval EFI_INVALID_PARAMETER Configuration is NULL. + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid A= CPI + 2.0 resource descriptor. + @retval EFI_INVALID_PARAMETER Configuration does not include a valid AC= PI + 2.0 bus resource descriptor. + @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 res= ource + descriptors other than bus descriptors. + @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid + ACPI resource descriptors. + @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for th= is + root bridge. + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this + root bridge. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware erro= r. + @retval EFI_SUCCESS The bus range for the PCI root bridge was + programmed. +**/ +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINT8 *Ptr; + UINTN BusStart; + UINTN BusEnd; + UINTN BusLen; + + if (Configuration =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + Ptr =3D Configuration; + + // + // Check the Configuration is valid + // + if (*Ptr !=3D ACPI_ADDRESS_SPACE_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + if (((EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr)->ResType !=3D 2) { + return EFI_INVALID_PARAMETER; + } + + Ptr +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + if (*Ptr !=3D ACPI_END_TAG_DESCRIPTOR) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + Ptr =3D Configuration; + + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; + + Desc =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Ptr; + BusStart =3D (UINTN)Desc->AddrRangeMin; + BusLen =3D (UINTN)Desc->AddrLen; + BusEnd =3D BusStart + BusLen - 1; + + if (BusStart > BusEnd) { + return EFI_INVALID_PARAMETER; + } + + if ((BusStart < RootBridgeInstance->BusBase) || + (BusEnd > RootBridgeInstance->BusLimit)) + { + return EFI_INVALID_PARAMETER; + } + + // + // Update the Bus Range + // + RootBridgeInstance->ResAllocNode[TypeBus].Base =3D BusStart; + RootBridgeInstance->ResAllocNode[TypeBus].Length =3D BusLen; + RootBridgeInstance->ResAllocNode[TypeBus].Status =3D ResAllocated; + + // + // Program the Root Bridge Hardware + // + + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Submits the I/O and memory resource requirements for the specified PCI r= oot + bridge. + + This function is used to submit all the I/O and memory resources that are + required by the specified PCI root bridge. The input parameter Configura= tion + is used to specify the following: + - The various types of resources that are required + - The associated lengths in terms of ACPI 2.0 resource descriptor format + + @param[in] This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory + resource requirements are being submitted. + @param[in] Configuration The pointer to the PCI I/O and PCI memory + resource descriptor. + + @retval EFI_SUCCESS The I/O and memory resource requests for = a PCI + root bridge were accepted. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root brid= ge + handle. + @retval EFI_INVALID_PARAMETER Configuration is NULL. + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid A= CPI + 2.0 resource descriptor. + @retval EFI_INVALID_PARAMETER Configuration includes requests for one or + more resource types that are not supporte= d by + this PCI root bridge. This error will hap= pen + if the caller did not combine resources + according to Attributes that were returne= d by + GetAllocAttributes(). + @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid. + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for thi= s PCI + root bridge. + @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for + this PCI root bridge. +**/ +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; + UINT64 AddrLen; + UINT64 Alignment; + + // + // Check the input parameter: Configuration + // + if (Configuration =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + Temp =3D (UINT8 *)Configuration; + while ( *Temp =3D=3D 0x8A) { + Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + + if (*Temp !=3D 0x79) { + return EFI_INVALID_PARAMETER; + } + + Temp =3D (UINT8 *)Configuration; + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + while ( *Temp =3D=3D 0x8A) { + Ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp; + + // + // Check Address Length + // + if (Ptr->AddrLen > 0xffffffff) { + return EFI_INVALID_PARAMETER; + } + + // + // Check address range alignment + // + if ((Ptr->AddrRangeMax >=3D 0xffffffff) || + (Ptr->AddrRangeMax !=3D (GetPowerOfTwo64 ( + Ptr->AddrRangeMax + 1 + ) - 1))) + { + return EFI_INVALID_PARAMETER; + } + + switch (Ptr->ResType) { + case 0: + + // + // Check invalid Address Sapce Granularity + // + if (Ptr->AddrSpaceGranularity !=3D 32) { + return EFI_INVALID_PARAMETER; + } + + // + // check the memory resource request is supported by PCI root = bridge + // + if ((RootBridgeInstance->RootBridgeAttrib =3D=3D + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM) && + (Ptr->SpecificFlag =3D=3D 0x06)) + { + return EFI_INVALID_PARAMETER; + } + + AddrLen =3D Ptr->AddrLen; + Alignment =3D Ptr->AddrRangeMax; + if (Ptr->AddrSpaceGranularity =3D=3D 32) { + if (Ptr->SpecificFlag =3D=3D 0x06) { + // + // Apply from GCD + // + RootBridgeInstance->ResAllocNode[TypePMem32].Status =3D + ResSubmitted; + } else { + RootBridgeInstance->ResAllocNode[TypeMem32].Length =3D = AddrLen; + RootBridgeInstance->ResAllocNode[TypeMem32].Alignment =3D + Alignment; + RootBridgeInstance->ResAllocNode[TypeMem32].Status =3D + ResRequested; + HostBridgeInstance->ResourceSubmited =3D TRUE; + } + } + + if (Ptr->AddrSpaceGranularity =3D=3D 64) { + if (Ptr->SpecificFlag =3D=3D 0x06) { + RootBridgeInstance->ResAllocNode[TypePMem64].Status =3D + ResSubmitted; + } else { + RootBridgeInstance->ResAllocNode[TypeMem64].Status =3D + ResSubmitted; + } + } + + break; + + case 1: + AddrLen =3D (UINTN)= Ptr->AddrLen; + Alignment =3D (UINTN)= Ptr->AddrRangeMax; + RootBridgeInstance->ResAllocNode[TypeIo].Length =3D AddrLen; + RootBridgeInstance->ResAllocNode[TypeIo].Alignment =3D Alignme= nt; + RootBridgeInstance->ResAllocNode[TypeIo].Status =3D ResRequ= ested; + HostBridgeInstance->ResourceSubmited =3D TRUE; + break; + + default: + break; + } + + Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Returns the proposed resource settings for the specified PCI root bridg= e. + + This member function returns the proposed resource settings for the + specified PCI root bridge. The proposed resource settings are prepared = when + NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResourc= es. + The output parameter Configuration specifies the following: + - The various types of resources, excluding bus resources, that are + allocated + - The associated lengths in terms of ACPI 2.0 resource descriptor format + + @param[in] This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HAND= LE is + defined in InstallProtocolInterface() in = the + UEFI 2.0 Specification. + @param[out] Configuration The pointer to the pointer to the PCI I/O= and + memory resource descriptor. + + @retval EFI_SUCCESS The requested parameters were returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge + handle. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a + lack of resources. +**/ +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ) +{ + LIST_ENTRY *List; + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + UINTN Index; + UINTN Number; + VOID *Buffer; + UINT8 *Temp; + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Ptr; + UINT64 ResStatus; + + Buffer =3D NULL; + Number =3D 0; + // + // Get the Host Bridge Instance from the resource allocation protocol + // + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + // + // Enumerate the root bridges in this host bridge + // + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + for (Index =3D 0; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNone) { + Number++; + } + } + + if (Number =3D=3D 0) { + return EFI_INVALID_PARAMETER; + } + + Buffer =3D AllocateZeroPool ( + Number * sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) + + sizeof (EFI_ACPI_END_TAG_DESCRIPTOR) + ); + if (Buffer =3D=3D NULL) { + return EFI_OUT_OF_RESOURCES; + } + + Temp =3D Buffer; + for (Index =3D 0; Index < TypeBus; Index++) { + if (RootBridgeInstance->ResAllocNode[Index].Status !=3D ResNone) { + Ptr =3D (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Temp; + ResStatus =3D RootBridgeInstance->ResAllocNode[Index].Status; + + switch (Index) { + case TypeIo: + // + // Io + // + Ptr->Desc =3D 0x8A; + Ptr->Len =3D 0x2B; + Ptr->ResType =3D 1; + Ptr->GenFlag =3D 0; + Ptr->SpecificFlag =3D 0; + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocN= ode[Index].Base; + Ptr->AddrRangeMax =3D 0; + Ptr->AddrTranslationOffset =3D (ResStatus =3D=3D ResAllocate= d) ? + EFI_RESOURCE_SATISFIED : + EFI_RESOURCE_LESS; + Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Len= gth; + break; + + case TypeMem32: + // + // Memory 32 + // + Ptr->Desc =3D 0x8A; + Ptr->Len =3D 0x2B; + Ptr->ResType =3D 0; + Ptr->GenFlag =3D 0; + Ptr->SpecificFlag =3D 0; + Ptr->AddrSpaceGranularity =3D 32; + Ptr->AddrRangeMin =3D RootBridgeInstance->ResAllocN= ode[Index].Base; + Ptr->AddrRangeMax =3D 0; + Ptr->AddrTranslationOffset =3D (ResStatus =3D=3D ResAllocate= d) ? + EFI_RESOURCE_SATISFIED : + EFI_RESOURCE_LESS; + Ptr->AddrLen =3D RootBridgeInstance->ResAllocNode[Index].Len= gth; + break; + + case TypePMem32: + // + // Prefetch memory 32 + // + Ptr->Desc =3D 0x8A; + Ptr->Len =3D 0x2B; + Ptr->ResType =3D 0; + Ptr->GenFlag =3D 0; + Ptr->SpecificFlag =3D 6; + Ptr->AddrSpaceGranularity =3D 32; + Ptr->AddrRangeMin =3D 0; + Ptr->AddrRangeMax =3D 0; + Ptr->AddrTranslationOffset =3D EFI_RESOURCE_NONEXISTENT; + Ptr->AddrLen =3D 0; + break; + + case TypeMem64: + // + // Memory 64 + // + Ptr->Desc =3D 0x8A; + Ptr->Len =3D 0x2B; + Ptr->ResType =3D 0; + Ptr->GenFlag =3D 0; + Ptr->SpecificFlag =3D 0; + Ptr->AddrSpaceGranularity =3D 64; + Ptr->AddrRangeMin =3D 0; + Ptr->AddrRangeMax =3D 0; + Ptr->AddrTranslationOffset =3D EFI_RESOURCE_NONEXISTENT; + Ptr->AddrLen =3D 0; + break; + + case TypePMem64: + // + // Prefetch memory 64 + // + Ptr->Desc =3D 0x8A; + Ptr->Len =3D 0x2B; + Ptr->ResType =3D 0; + Ptr->GenFlag =3D 0; + Ptr->SpecificFlag =3D 6; + Ptr->AddrSpaceGranularity =3D 64; + Ptr->AddrRangeMin =3D 0; + Ptr->AddrRangeMax =3D 0; + Ptr->AddrTranslationOffset =3D EFI_RESOURCE_NONEXISTENT; + Ptr->AddrLen =3D 0; + break; + } + + Temp +=3D sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR); + } + } + + ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Desc =3D 0x79; + ((EFI_ACPI_END_TAG_DESCRIPTOR *)Temp)->Checksum =3D 0x0; + + *Configuration =3D Buffer; + + return EFI_SUCCESS; + } + + List =3D List->ForwardLink; + } + + return EFI_INVALID_PARAMETER; +} + +/** + Provides the hooks from the PCI bus driver to every PCI controller + (device/function) at various stages of the PCI enumeration process that = allow + the host bridge driver to preinitialize individual PCI controllers before + enumeration. + + This function is called during the PCI enumeration process. No specific + action is expected from this member function. It allows the host bridge + driver to preinitialize individual PCI controllers before enumeration. + + @param This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param RootBridgeHandle The associated PCI root bridge handle. Type + EFI_HANDLE is defined in InstallProtocolInterfa= ce() + in the UEFI 2.0 Specification. + @param PciAddress The address of the PCI device on the PCI bus. T= his + address can be passed to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member function= s to + access the PCI configuration space of the devic= e. + See Table 12-1 in the UEFI 2.0 Specification fo= r the + definition of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. + @param Phase The phase of the PCI device enumeration. + + @retval EFI_SUCCESS The requested parameters were returned. + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root br= idge + handle. + @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defi= ned + in + EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_P= HASE. + @retval EFI_DEVICE_ERROR Programming failed due to a hardware er= ror. + The PCI enumerator should not enumerate= this + device, including its child devices if = it is + a PCI-to-PCI bridge. +**/ +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ) +{ + PCI_HOST_BRIDGE_INSTANCE *HostBridgeInstance; + PCI_ROOT_BRIDGE_INSTANCE *RootBridgeInstance; + LIST_ENTRY *List; + + HostBridgeInstance =3D INSTANCE_FROM_RESOURCE_ALLOCATION_THIS (This); + List =3D HostBridgeInstance->Head.ForwardLink; + + // + // Enumerate the root bridges in this host bridge + // + while (List !=3D &HostBridgeInstance->Head) { + RootBridgeInstance =3D DRIVER_INSTANCE_FROM_LIST_ENTRY (List); + if (RootBridgeHandle =3D=3D RootBridgeInstance->Handle) { + break; + } + + List =3D List->ForwardLink; + } + + if (List =3D=3D &HostBridgeInstance->Head) { + return EFI_INVALID_PARAMETER; + } + + if ((UINT32)Phase > EfiPciBeforeResourceCollection) { + return EFI_INVALID_PARAMETER; + } + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciHostBridge.h b/Platform/AMD/VanGoghBoard/Override/edk2/M= deModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.h new file mode 100644 index 0000000000..8182697994 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/PciHostB= ridgeDxe/PciHostBridge.h @@ -0,0 +1,624 @@ +/** @file + Implementation of PciHostBridge.h + The Header file of the Pci Host Bridge Driver + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2008 - 2010, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef PCI_HOST_BRIDGE_H_ +#define PCI_HOST_BRIDGE_H_ + +#include + +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// Hard code the host bridge number in the platform. +// In this chipset, there is only one host bridge. +// +#define HOST_BRIDGE_NUMBER 1 + +#define MAX_PCI_DEVICE_NUMBER 31 +#define MAX_PCI_FUNCTION_NUMBER 7 +#define MAX_PCI_REG_ADDRESS 0xFF + +typedef enum { + IoOperation, + MemOperation, + PciOperation +} OPERATION_TYPE; + +#define PCI_HOST_BRIDGE_SIGNATURE SIGNATURE_32('e', 'h', 's', 't') +typedef struct { + UINTN Signature; + EFI_HANDLE HostBridgeHandle; + UINTN RootBridgeNumber; + LIST_ENTRY Head; + BOOLEAN ResourceSubmited; + BOOLEAN CanRestarted; + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL ResAlloc; +} PCI_HOST_BRIDGE_INSTANCE; + +#define INSTANCE_FROM_RESOURCE_ALLOCATION_THIS(a) \ + CR(a, PCI_HOST_BRIDGE_INSTANCE, ResAlloc, PCI_HOST_BRIDGE_SIGNATURE) + +// +// HostBridge Resource Allocation interface +// + +/** + These are the notifications from the PCI bus driver that it is about to = enter + a certain phase of the PCI enumeration process. + + This member function can be used to notify the host bridge driver to per= form + specific actions, including any chipset-specific initialization, so that= the + chipset is ready to enter the next phase. Eight notification points are + defined at this time. See belows: + + EfiPciHostBridgeBeginEnumeration Resets the host bridge PCI apertu= res + and internal data structures. The= PCI + enumerator should issue this + notification before starting a fr= esh + enumeration process. Enumeration + cannot be restarted after sending= any + other notification such as + EfiPciHostBridgeBeginBusAllocatio= n. + + EfiPciHostBridgeBeginBusAllocation The bus allocation phase is about= to + begin. No specific action is requ= ired + here. This notification can be us= ed to + perform any chipset-specific + programming. + + EfiPciHostBridgeEndBusAllocation The bus allocation and bus progra= mming + phase is complete. No specific ac= tion + is required here. This notificati= on + can be used to perform any + chipset-specific programming. + + EfiPciHostBridgeBeginResourceAllocation + The resource allocation phase is = about + to begin. No specific action is + required here. This notification = can + be used to perform any + chipset-specific programming. + + EfiPciHostBridgeAllocateResources Allocates resources per previously + submitted requests for all the PCI + root bridges. These resource sett= ings + are returned on the next call to + GetProposedResources(). Before ca= lling + NotifyPhase() with a Phase of + EfiPciHostBridgeAllocateResource,= the + PCI bus enumerator is responsible= for + gathering I/O and memory requests= for + all the PCI root bridges and + submitting these requests using + SubmitResources(). This function = pads + the resource amount to suit the r= oot + bridge hardware, takes care of + dependencies between the PCI root + bridges, and calls the Global + Coherency Domain (GCD) with the + allocation request. In the case of + padding, the allocated range coul= d be + bigger than what was requested. + + EfiPciHostBridgeSetResources Programs the host bridge hardware= to + decode previously allocated resou= rces + (proposed resources) for all the = PCI + root bridges. After the hardware = is + programmed, reassigning resources= will + not be supported. The bus setting= s are + not affected. + + EfiPciHostBridgeFreeResources Deallocates resources that were + previously allocated for all the = PCI + root bridges and resets the I/O a= nd + memory apertures to their initial + state. The bus settings are not + affected. If the request to alloc= ate + resources fails, the PCI enumerat= or + can use this notification to + deallocate previous resources, ad= just + the requests, and retry allocatio= n. + + EfiPciHostBridgeEndResourceAllocation The resource allocation phase is + completed. No specific action is + required here. This notification = can + be used to perform any chipsetspe= cific + programming. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + @param[in] Phase The phase during enumeration + + @retval EFI_NOT_READY This phase cannot be entered at this time= . For + example, this error is valid for a Phase = of + EfiPciHostBridgeAllocateResources if + SubmitResources() has not been called for= one + or more PCI root bridges before this call + + @retval EFI_DEVICE_ERROR Programming failed due to a hardware erro= r. + This error is valid for a Phase of + EfiPciHostBridgeSetResources. + + @retval EFI_INVALID_PARAMETER Invalid phase parameter + + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. This error is valid fo= r a + Phase of EfiPciHostBridgeAllocateResource= s if + the previously submitted resource requests + cannot be fulfilled or were only partially + fulfilled. + + @retval EFI_SUCCESS The notification was accepted without any + errors. +**/ +EFI_STATUS +EFIAPI +NotifyPhase ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE Phase + ); + +/** + Return the device handle of the next PCI root bridge that is associated = with + this Host Bridge. + + This function is called multiple times to retrieve the device handles of= all + the PCI root bridges that are associated with this PCI host bridge. Each= PCI + host bridge is associated with one or more PCI root bridges. On each cal= l, + the handle that was returned by the previous call is passed into the + interface, and on output the interface returns the device handle of the = next + PCI root bridge. The caller can use the handle to obtain the instance of= the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL for that root bridge. When there are no = more + PCI root bridges to report, the interface returns EFI_NOT_FOUND. A PCI + enumerator must enumerate the PCI root bridges in the order that they are + returned by this function. + + For D945 implementation, there is only one root bridge in PCI host bridg= e. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + @param[in, out] RootBridgeHandle Returns the device handle of the next= PCI + root bridge. + + @retval EFI_SUCCESS If parameter RootBridgeHandle =3D NULL, t= hen + return the first Rootbridge handle of the + specific Host bridge and return EFI_SUCCE= SS. + + @retval EFI_NOT_FOUND Can not find the any more root bridge in + specific host bridge. + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not an EFI_HANDLE tha= t was + returned on a previous call to + GetNextRootBridge(). +**/ +EFI_STATUS +EFIAPI +GetNextRootBridge ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN OUT EFI_HANDLE *RootBridgeHa= ndle + ); + +/** + Returns the allocation attributes of a PCI root bridge. + + The function returns the allocation attributes of a specific PCI root br= idge. + The attributes can vary from one PCI root bridge to another. These attri= butes + are different from the decode-related attributes that are returned by the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.GetAttributes() member function. The + RootBridgeHandle parameter is used to specify the instance of the PCI ro= ot + bridge. The device handles of all the root bridges that are associated w= ith + this host bridge must be obtained by calling GetNextRootBridge(). The + attributes are static in the sense that they do not change during or aft= er + the enumeration process. The hardware may provide mechanisms to change t= he + attributes on the fly, but such changes must be completed before + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL is installed. The permi= tted + values of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_ATTRIBUTES are defined= in + "Related Definitions" below. The caller uses these attributes to combine + multiple resource requests. + + For example, if the flag EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM is set, th= e PCI + bus enumerator needs to include requests for the prefetchable memory in = the + nonprefetchable memory pool and not request any prefetchable memory. + + Attribute Description + ------------------------------------ ----------------------------------= ----- + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM If this bit is set, then the PCI r= oot + bridge does not support separate + windows for nonprefetchable and + prefetchable memory. A PCI bus dri= ver + needs to include requests for + prefetchable memory in the + nonprefetchable memory pool. + + EFI_PCI_HOST_BRIDGE_MEM64_DECODE If this bit is set, then the PCI r= oot + bridge supports 64-bit memory wind= ows. + If this bit is not set, the PCI bus + driver needs to include requests f= or a + 64-bit memory address in the + corresponding 32-bit memory pool. + + @param[in] This The instance pointer of + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + @param[in] RootBridgeHandle The device handle of the PCI root bridge= in + which the caller is interested. Type + EFI_HANDLE is defined in + InstallProtocolInterface() in the UEFI 2= .0 + Specification. + @param[out] Attributes The pointer to attribte of root bridge, = it is + output parameter + + @retval EFI_INVALID_PARAMETER Attribute pointer is NULL + + @retval EFI_INVALID_PARAMETER RootBridgehandle is invalid. + + @retval EFI_SUCCESS Success to get attribute of interested r= oot + bridge. +**/ +EFI_STATUS +EFIAPI +GetAttributes ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT UINT64 *Attributes + ); + +/** + Sets up the specified PCI root bridge for the bus enumeration process. + + This member function sets up the root bridge for bus enumeration and ret= urns + the PCI bus range over which the search should be performed in ACPI 2.0 + resource descriptor format. + + @param[in] This The + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance. + @param[in] RootBridgeHandle The PCI Root Bridge to be set up. + @param[out] Configuration Pointer to the pointer to the PCI bus res= ource + descriptor. + + @retval EFI_INVALID_PARAMETER Invalid Root bridge's handle + + @retval EFI_OUT_OF_RESOURCES Fail to allocate ACPI resource descriptor = tag. + + @retval EFI_SUCCESS Sucess to allocate ACPI resource descripto= r. +**/ +EFI_STATUS +EFIAPI +StartBusEnumeration ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + Programs the PCI root bridge hardware so that it decodes the specified P= CI + bus range. + + This member function programs the specified PCI root bridge to decode th= e bus + range that is specified by the input parameter Configuration. + The bus range information is specified in terms of the ACPI 2.0 resource + descriptor format. + + @param[in] This The + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance + @param[in] RootBridgeHandle The PCI Root Bridge whose bus range is to be + programmed + @param[in] Configuration The pointer to the PCI bus resource descrip= tor + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root brid= ge + handle. + + @retval EFI_INVALID_PARAMETER Configuration is NULL. + + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid A= CPI + 2.0 resource descriptor. + + @retval EFI_INVALID_PARAMETER Configuration does not include a valid AC= PI + 2.0 bus resource descriptor. + + @retval EFI_INVALID_PARAMETER Configuration includes valid ACPI 2.0 res= ource + descriptors other than bus descriptors. + + @retval EFI_INVALID_PARAMETER Configuration contains one or more invalid + ACPI resource descriptors. + + @retval EFI_INVALID_PARAMETER "Address Range Minimum" is invalid for th= is + root bridge. + + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for this + root bridge. + + @retval EFI_DEVICE_ERROR Programming failed due to a hardware erro= r. + + @retval EFI_SUCCESS The bus range for the PCI root bridge was + programmed. +**/ +EFI_STATUS +EFIAPI +SetBusNumbers ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + Submits the I/O and memory resource requirements for the specified PCI r= oot + bridge. + + This function is used to submit all the I/O and memory resources that are + required by the specified PCI root bridge. The input parameter Configura= tion + is used to specify the following: + - The various types of resources that are required + - The associated lengths in terms of ACPI 2.0 resource descriptor format + + @param[in] This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge whose I/O and memory + resource requirements are being submitted. + @param[in] Configuration The pointer to the PCI I/O and PCI memory + resource descriptor. + + @retval EFI_SUCCESS The I/O and memory resource requests for = a PCI + root bridge were accepted. + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root brid= ge + handle. + + @retval EFI_INVALID_PARAMETER Configuration is NULL. + + @retval EFI_INVALID_PARAMETER Configuration does not point to a valid A= CPI + 2.0 resource descriptor. + + @retval EFI_INVALID_PARAMETER Configuration includes requests for one or + more resource types that are not supporte= d by + this PCI root bridge. This error will hap= pen + if the caller did not combine resources + according to Attributes that were returne= d by + GetAllocAttributes(). + + @retval EFI_INVALID_PARAMETER Address Range Maximum" is invalid. + + @retval EFI_INVALID_PARAMETER "Address Range Length" is invalid for thi= s PCI + root bridge. + + @retval EFI_INVALID_PARAMETER "Address Space Granularity" is invalid for + this PCI root bridge. +**/ +EFI_STATUS +EFIAPI +SubmitResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN VOID *Configuration + ); + +/** + Returns the proposed resource settings for the specified PCI root bridg= e. + + This member function returns the proposed resource settings for the + specified PCI root bridge. The proposed resource settings are prepared = when + NotifyPhase() is called with a Phase of EfiPciHostBridgeAllocateResourc= es. + The output parameter Configuration specifies the following: + - The various types of resources, excluding bus resources, that are + allocated + - The associated lengths in terms of ACPI 2.0 resource descriptor format + + @param[in] This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PRO= TOCOL + instance. + @param[in] RootBridgeHandle The PCI root bridge handle. Type EFI_HAND= LE is + defined in InstallProtocolInterface() in = the + UEFI 2.0 Specification. + @param[out] Configuration The pointer to the pointer to the PCI I/O= and + memory resource descriptor. + + @retval EFI_SUCCESS The requested parameters were returned. + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root bri= dge + handle. + + @retval EFI_DEVICE_ERROR Programming failed due to a hardware err= or. + + @retval EFI_OUT_OF_RESOURCES The request could not be completed due t= o a + lack of resources. +**/ +EFI_STATUS +EFIAPI +GetProposedResources ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + OUT VOID **Configuration + ); + +/** + Provides the hooks from the PCI bus driver to every PCI controller + (device/function) at various stages of the PCI enumeration process that = allow + the host bridge driver to preinitialize individual PCI controllers before + enumeration. + + This function is called during the PCI enumeration process. No specific + action is expected from this member function. It allows the host bridge + driver to preinitialize individual PCI controllers before enumeration. + + @param This Pointer to the + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL + instance. + @param RootBridgeHandle The associated PCI root bridge handle. Type + EFI_HANDLE is defined in InstallProtocolInterfa= ce() + in the UEFI 2.0 Specification. + @param PciAddress The address of the PCI device on the PCI bus. T= his + address can be passed to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL member function= s to + access the PCI configuration space of the devic= e. + See Table 12-1 in the UEFI 2.0 Specification fo= r the + definition of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS. + @param Phase The phase of the PCI device enumeration. + + @retval EFI_SUCCESS The requested parameters were returned. + + @retval EFI_INVALID_PARAMETER RootBridgeHandle is not a valid root br= idge + handle. + + @retval EFI_INVALID_PARAMETER Phase is not a valid phase that is defi= ned + in + EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_P= HASE. + + @retval EFI_DEVICE_ERROR Programming failed due to a hardware er= ror. + The PCI enumerator should not enumerate= this + device, including its child devices if = it is + a PCI-to-PCI bridge. +**/ +EFI_STATUS +EFIAPI +PreprocessController ( + IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *This, + IN EFI_HANDLE RootBridgeHandle, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS PciAddress, + IN EFI_PCI_CONTROLLER_RESOURCE_ALLOCATION_PHASE Phase + ); + +// +// Define resource status constant +// +#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL +#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL + +// +// Driver Instance Data Prototypes +// + +typedef struct { + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation; + UINTN NumberOfBytes; + UINTN NumberOfPages; + EFI_PHYSICAL_ADDRESS HostAddress; + EFI_PHYSICAL_ADDRESS MappedHostAddress; +} MAP_INFO; + +typedef struct { + ACPI_HID_DEVICE_PATH AcpiDevicePath; + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; + +typedef struct { + UINT64 BusBase; + UINT64 BusLimit; + + UINT64 MemBase; + UINT64 MemLimit; + + UINT64 IoBase; + UINT64 IoLimit; +} PCI_ROOT_BRIDGE_RESOURCE_APERTURE; + +typedef enum { + TypeIo =3D 0, + TypeMem32, + TypePMem32, + TypeMem64, + TypePMem64, + TypeBus, + TypeMax +} PCI_RESOURCE_TYPE; + +typedef enum { + ResNone =3D 0, + ResSubmitted, + ResRequested, + ResAllocated, + ResStatusMax +} RES_STATUS; + +typedef struct { + PCI_RESOURCE_TYPE Type; + UINT64 Base; + UINT64 Length; + UINT64 Alignment; + RES_STATUS Status; +} PCI_RES_NODE; + +#define PCI_ROOT_BRIDGE_SIGNATURE SIGNATURE_32('e', '2', 'p', 'b') + +typedef struct { + UINT32 Signature; + LIST_ENTRY Link; + EFI_HANDLE Handle; + UINT64 RootBridgeAttrib; + UINT64 Attributes; + UINT64 Supports; + + // + // Specific for this memory controller: Bus, I/O, Mem + // + PCI_RES_NODE ResAllocNode[6]; + + // + // Addressing for Memory and I/O and Bus arrange + // + UINT64 BusBase; + UINT64 MemBase; + UINT64 IoBase; + UINT64 BusLimit; + UINT64 MemLimit; + UINT64 IoLimit; + + EFI_DEVICE_PATH_PROTOCOL *DevicePath; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL Io; +} PCI_ROOT_BRIDGE_INSTANCE; + +// +// Driver Instance Data Macros +// +#define DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS(a) \ + CR(a, PCI_ROOT_BRIDGE_INSTANCE, Io, PCI_ROOT_BRIDGE_SIGNATURE) + +#define DRIVER_INSTANCE_FROM_LIST_ENTRY(a) \ + CR(a, PCI_ROOT_BRIDGE_INSTANCE, Link, PCI_ROOT_BRIDGE_SIGNATURE) + +/** + + Construct the Pci Root Bridge Io protocol + + @param Protocol Point to protocol instance + @param HostBridgeHandle Handle of host bridge + @param Attri Attribute of host bridge + @param ResAperture ResourceAperture for host bridge + + @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. +**/ +EFI_STATUS +RootBridgeConstructor ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN UINT64 Attri, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture + ); + +#endif diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciHostBridge.uni b/Platform/AMD/VanGoghBoard/Override/edk2= /MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridge.uni new file mode 100644 index 0000000000000000000000000000000000000000..311a1c450d0faa5317ad3b25439= 0f866e813e712 GIT binary patch literal 1290 zcmdUt-%A2P5Xa{^=3Dzm!BrJ_@d9wH*r3=3D;YwocWMWE#@#9O&sU$B+|wW<=3D%qOJ zc6WAX=3DJTDMx7WJV#W8mHoSe!~5*f=3DtHe~~=3Do^@m*&t{uoPo~hXplCg_r#QmDgxR&p{%Cy&I*If+;&7I%Q(5NpJFZr1NI7i4qXb`~Win{w-J zz}mAa+Zh^MN#{QCIXIPej#mb)*X?JA_Z0mvc54KCL98vT+symYU>vY&5@!xgYVL!JJYulgIRW!*w5-6-3p(8WA~^KDE2&O>W3=3D3(+~dre)NVCi(i@TlZCs zMq|w&(Y|)3ARt!Ax`OxL?dnQdo1fLCO?5&l(&MGNDCo05bzw1)t-F(Nq10q7q A8~^|S literal 0 HcmV?d00001 diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciHostBridgeDxe.inf b/Platform/AMD/VanGoghBoard/Override/e= dk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf new file mode 100644 index 0000000000..05eec84d7e --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/PciHostB= ridgeDxe/PciHostBridgeDxe.inf @@ -0,0 +1,54 @@ +## @file +# Platform Boot Manager Lib Module +# The basic interfaces implementation to a single segment PCI Host Bridge +# driver. +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D PciHostBridge + MODULE_UNI_FILE =3D PciHostBridge.uni + FILE_GUID =3D ACAB2797-6602-4B27-925F-B43483C630CE + MODULE_TYPE =3D DXE_DRIVER + VERSION_STRING =3D 1.0 + + ENTRY_POINT =3D InitializePciHostBridge + +[Packages] + MdePkg/MdePkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + UefiBootServicesTableLib + DxeServicesTableLib + UefiLib + MemoryAllocationLib + BaseMemoryLib + BaseLib + DebugLib + DevicePathLib + IoLib + PciLib + +[Sources] + PciHostBridge.c + PciRootBridgeIo.c + PciHostBridge.h + IoFifo.h + +[Protocols] + gEfiPciHostBridgeResourceAllocationProtocolGuid ## PRODUCES + gEfiPciRootBridgeIoProtocolGuid ## PRODUCES + gEfiMetronomeArchProtocolGuid ## CONSUMES + gEfiDevicePathProtocolGuid ## PRODUCES + +[depex] + gEfiMetronomeArchProtocolGuid + +[UserExtensions.TianoCore."ExtraFiles"] + PciHostBridgeExtra.uni diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciHostBridgeExtra.uni b/Platform/AMD/VanGoghBoard/Override= /edk2/MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeExtra.uni new file mode 100644 index 0000000000000000000000000000000000000000..819a077f54064dbbd5e260aaecd= b4615149eee47 GIT binary patch literal 826 zcmbu7+e-pb5XQgfp#R}uFBPd}Jw-(6E+k}$Yv7y6dTGHM>xJr%uYPmZRfBqpWzOuG zIrGgom#@#V%5umlpVOU&N;K9$hdRJ&zPcuwd)oy2R7>@cL^J*!=3Da93h7|R2<1-`0M zZheh-ALvf}uIL=3DO;_n`;wa1J%`5NSoiJIXJu&w=3DlK<+avb+X4)Wsze(w})@+ zQX&>eN}Ta8>4wg literal 0 HcmV?d00001 diff --git a/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/P= ciHostBridgeDxe/PciRootBridgeIo.c b/Platform/AMD/VanGoghBoard/Override/edk2= /MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciRootBridgeIo.c new file mode 100644 index 0000000000..b70e4745cc --- /dev/null +++ b/Platform/AMD/VanGoghBoard/Override/edk2/MdeModulePkg/Bus/Pci/PciHostB= ridgeDxe/PciRootBridgeIo.c @@ -0,0 +1,2421 @@ +/** @file + Implementation of PciRootBridgeIo.c + PCI Root Bridge Io Protocol implementation + + Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+ Copyright (c) 2008 - 2012, Intel Corporation. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "PciHostBridge.h" +#include "IoFifo.h" + +typedef struct { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR SpaceDesp[TypeMax]; + EFI_ACPI_END_TAG_DESCRIPTOR EndDesp; +} RESOURCE_CONFIGURATION; + +RESOURCE_CONFIGURATION Configuration =3D { + { + { 0x8A, 0x2B, 1, 0, 0, 0, 0, 0, 0, 0 }, + { 0x8A, 0x2B, 0, 0, 0, 32, 0, 0, 0, 0 }, + { 0x8A, 0x2B, 0, 0, 6, 32, 0, 0, 0, 0 }, + { 0x8A, 0x2B, 0, 0, 0, 64, 0, 0, 0, 0 }, + { 0x8A, 0x2B, 0, 0, 6, 64, 0, 0, 0, 0 }, + { 0x8A, 0x2B, 2, 0, 0, 0, 0, 0, 0, 0 } + }, + { 0x79, 0 } +}; + +// +// Protocol Member Function Prototypes +// + +/** + Polls an address in memory mapped I/O space until an exit condition is m= et, + or a timeout occurs. + + This function provides a standard way to poll a PCI memory location. A P= CI + memory read operation is performed at the PCI memory address specified by + Address for the width specified by Width. The result of this PCI memory = read + operation is stored in Result. This PCI memory read operation is repeated + until either a timeout of Delay 100 ns units has expired, or (Result & M= ask) + is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the memory operations. The ca= ller + is responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above W= idth + in Mask are ignored. The bits in the bytes below = Width + which are zero in Mask are ignored when polling t= he + memory address. + @param[in] Value The comparison value used for the polling exit + criteria. + @param[in] Delay The number of 100 ns units to poll. Note that tim= er + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory + location. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the + polling exit criteria is satisfied or after a defined duration. + + This function provides a standard way to poll a PCI I/O location. A PCI = I/O + read operation is performed at the PCI I/O address specified by Address = for + the width specified by Width. The result of this PCI I/O read operation = is + stored in Result. This PCI I/O read operation is repeated until either a + timeout of Delay 100 ns units has expired, or (Result & Mask) is equal to + Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller = is + responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Wid= th in + Mask are ignored. The bits in the bytes below Width + which are zero in Mask are ignored when polling the= I/O + address. + @param[in] Value The comparison value used for the polling exit crit= eria. + @param[in] Delay The number of 100 ns units to poll. Note that timer + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory loca= tion. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ); + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[out] UserBuffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + OUT VOID *UserBuffer + ); + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[in] UserBuffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 UserAddress, + IN UINTN Count, + IN VOID *UserBuffer + ); + +/** + Enables a PCI driver to copy one region of PCI root bridge memory space = to + another region of PCI root bridge memory space. + + The CopyMem() function enables a PCI driver to copy one region of PCI ro= ot + bridge memory space to another region of PCI root bridge memory space. T= his + is especially useful for video scroll operation on a memory mapped video + buffer. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI root bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] DestAddress The destination address of the memory operation. = The + caller is responsible for aligning the DestAddres= s if + required. + @param[in] SrcAddress The source address of the memory operation. The c= aller + is responsible for aligning the SrcAddress if + required. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at DestAddr= ess + and SrcAddress. + + + @retval EFI_SUCCESS The data was copied from one memory reg= ion + to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ); + +/** + Enables a PCI driver to access PCI controller registers in a PCI root + bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI + configuration registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. T= he + caller is responsible for any alignment and PCI configuration width issu= es + that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space fo= r the + PCI controller. + @param[in] Count The number of PCI configuration operations to per= form. + Bytes moved is Width size * Count, starting at + Address. + @param[out] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ); + +/** + Enables a PCI driver to access PCI controller registers in a PCI root + bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI + configuration registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. T= he + caller is responsible for any alignment and PCI configuration width issu= es + that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space fo= r the + PCI controller. + @param[in] Count The number of PCI configuration operations to per= form. + Bytes moved is Width size * Count, starting at + Address. + @param[in] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ); + +/** + Provides the PCI controller-specific addresses required to access system + memory from a DMA bus master. + + The Map() function provides the PCI controller specific addresses needed= to + access system memory. This function is used to map system memory for PCI= bus + master DMA accesses. + + @param[in] This A pointer to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Operation Indicates if the bus master is going to= read + or write to system memory. + @param[in] HostAddress The system memory address to map to the= PCI + controller. + @param[in, out] NumberOfBytes On input the number of bytes to map. On + output the number of bytes that were ma= pped. + @param[out] DeviceAddress The resulting map address for the bus m= aster + PCI controller to use to access the sys= tem + memory's HostAddress. + @param[out] Mapping The value to pass to Unmap() when the b= us + master DMA operation is complete. + + @retval EFI_SUCCESS The range was mapped for the returned + NumberOfBytes. + @retval EFI_INVALID_PARAMETER Operation is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. + @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. + @retval EFI_INVALID_PARAMETER Mapping is NULL. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a com= mon + buffer. + @retval EFI_DEVICE_ERROR The system hardware could not map the + requested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ); + +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any + corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target sys= tem + memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by + Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target + system memory. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ); + +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonB= uffer + or EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of = the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated + range. Only the attributes + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, + EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and + EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with= this + function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal + attribute bits are MEMORY_WRITE_COMBINE, + MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ); + +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with + AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress= and + Pages was not allocated with AllocateBuff= er(). +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ); + +/** + Flushes all PCI posted write transactions from a PCI host bridge to syst= em + memory. + + The Flush() function flushes any PCI posted write transactions from a PCI + host bridge to system memory. Posted write transactions are generated by= PCI + bus masters when they perform write transactions to target addresses in + system memory. + This function does not flush posted write transactions from any PCI brid= ges. + A PCI controller specific action must be taken to guarantee that the pos= ted + write transactions have been flushed from the PCI controller and from al= l the + PCI bridges into the PCI host bridge. This is typically done with a PCI = read + transaction from the PCI controller prior to calling Flush(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed + from the PCI host bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not fl= ushed + from the PCI host bridge due to a hardware er= ror. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ); + +/** + Gets the attributes that a PCI root bridge supports setting with + SetAttributes(), and the attributes that a PCI root bridge is currently + using. + + The GetAttributes() function returns the mask of attributes that this PCI + root bridge supports and the mask of attributes that the PCI root bridge= is + currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root + bridge supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root + bridge is currently using. + + + @retval EFI_SUCCESS If Supports is not NULL, then the attribu= tes + that the PCI root bridge supports is retu= rned + in Supports. If Attributes is not NULL, t= hen + the attributes that the PCI root bridge is + currently using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ); + +/** + Sets attributes for a resource range on a PCI root bridge. + + The SetAttributes() function sets the attributes specified in Attributes= for + the PCI root bridge on the resource range specified by ResourceBase and + ResourceLength. Since the granularity of setting these attributes may va= ry + from resource type to resource type, and from platform to platform, the + actual resource range and the one passed in by the caller may differ. As= a + result, this function may set the attributes specified by Attributes on a + larger resource range than the caller requested. The actual range is ret= urned + in ResourceBase and ResourceLength. The caller is responsible for verify= ing + that the actual range for which the attributes were set is acceptable. + + @param[in] This A pointer to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Attributes The mask of attributes to set. If the + attribute bit MEMORY_WRITE_COMBINE, + MEMORY_CACHED, or MEMORY_DISABLE is set, + then the resource range is specified by + ResourceBase and ResourceLength. If + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and + MEMORY_DISABLE are not set, then + ResourceBase and ResourceLength are ign= ored, + and may be NULL. + + @param[in, out] ResourceBase A pointer to the base address of the + resource range to be modified by the + attributes specified by Attributes. + @param[in, out] ResourceLength A pointer to the length of the resource + range to be modified by the attributes + specified by Attributes. + + @retval EFI_SUCCESS The current configuration of this PCI root brid= ge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root brid= ge + could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + +**/ +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ); + +/** + Retrieves the current resource settings of this PCI root bridge in the f= orm + of a set of ACPI 2.0 resource descriptors. + + There are only two resource descriptor types from the ACPI Specification= that + may be used to describe the current resources allocated to a PCI root br= idge. + These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1= ), + and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space + Descriptor can describe memory, I/O, and bus number ranges for dynamic or + fixed resources. The configuration of a PCI root bridge is described wit= h one + or more QWORD Address Space Descriptors followed by an End Tag. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[out] Resources A pointer to the ACPI 2.0 resource descriptors = that + describe the current configuration of this PCI = root + bridge. The storage for the ACPI 2.0 resource + descriptors is allocated by this function. The + caller must treat the return buffer as read-only + data, and the buffer must not be freed by the + caller. + + @retval EFI_SUCCESS The current configuration of this PCI root brid= ge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root brid= ge + could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL +**/ +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ); + +// +// Memory Controller Pci Root Bridge Io Module Variables +// +EFI_METRONOME_ARCH_PROTOCOL *mMetronome; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mInStride[] =3D { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 0, // EfiPciWidthFifoUint8 + 0, // EfiPciWidthFifoUint16 + 0, // EfiPciWidthFifoUint32 + 0, // EfiPciWidthFifoUint64 + 1, // EfiPciWidthFillUint8 + 2, // EfiPciWidthFillUint16 + 4, // EfiPciWidthFillUint32 + 8 // EfiPciWidthFillUint64 +}; + +// +// Lookup table for increment values based on transfer widths +// +UINT8 mOutStride[] =3D { + 1, // EfiPciWidthUint8 + 2, // EfiPciWidthUint16 + 4, // EfiPciWidthUint32 + 8, // EfiPciWidthUint64 + 1, // EfiPciWidthFifoUint8 + 2, // EfiPciWidthFifoUint16 + 4, // EfiPciWidthFifoUint32 + 8, // EfiPciWidthFifoUint64 + 0, // EfiPciWidthFillUint8 + 0, // EfiPciWidthFillUint16 + 0, // EfiPciWidthFillUint32 + 0 // EfiPciWidthFillUint64 +}; + +/** + Construct the Pci Root Bridge Io protocol + + @param Protocol Point to protocol instance + @param HostBridgeHandle Handle of host bridge + @param Attri Attribute of host bridge + @param ResAperture ResourceAperture for host bridge + + @retval EFI_SUCCESS Success to initialize the Pci Root Bridge. +**/ +EFI_STATUS +RootBridgeConstructor ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *Protocol, + IN EFI_HANDLE HostBridgeHandle, + IN UINT64 Attri, + IN PCI_ROOT_BRIDGE_RESOURCE_APERTURE *ResAperture + ) +{ + EFI_STATUS Status; + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + PCI_RESOURCE_TYPE Index; + + PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (Protocol); + + // + // The host to pci bridge, the host memory and io addresses are + // direct mapped to pci addresses, so no need translate, set bases to 0. + // + PrivateData->MemBase =3D ResAperture->MemBase; + PrivateData->IoBase =3D ResAperture->IoBase; + + // + // The host bridge only supports 32bit addressing for memory + // and standard IA32 16bit io + // + PrivateData->MemLimit =3D ResAperture->MemLimit; + PrivateData->IoLimit =3D ResAperture->IoLimit; + + // + // Bus Aperture for this Root Bridge (Possible Range) + // + PrivateData->BusBase =3D ResAperture->BusBase; + PrivateData->BusLimit =3D ResAperture->BusLimit; + + // + // Specific for this chipset + // + for (Index =3D TypeIo; Index < TypeMax; Index++) { + PrivateData->ResAllocNode[Index].Type =3D Index; + PrivateData->ResAllocNode[Index].Base =3D 0; + PrivateData->ResAllocNode[Index].Length =3D 0; + PrivateData->ResAllocNode[Index].Status =3D ResNone; + } + + PrivateData->RootBridgeAttrib =3D Attri; + + PrivateData->Supports =3D EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | + EFI_PCI_ATTRIBUTE_ISA_IO_16 | + EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | + EFI_PCI_ATTRIBUTE_VGA_MEMORY | + EFI_PCI_ATTRIBUTE_VGA_IO_16 | + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16; + PrivateData->Attributes =3D PrivateData->Supports; + + Protocol->ParentHandle =3D HostBridgeHandle; + + Protocol->PollMem =3D RootBridgeIoPollMem; + Protocol->PollIo =3D RootBridgeIoPollIo; + + Protocol->Mem.Read =3D RootBridgeIoMemRead; + Protocol->Mem.Write =3D RootBridgeIoMemWrite; + + Protocol->Io.Read =3D RootBridgeIoIoRead; + Protocol->Io.Write =3D RootBridgeIoIoWrite; + + Protocol->CopyMem =3D RootBridgeIoCopyMem; + + Protocol->Pci.Read =3D RootBridgeIoPciRead; + Protocol->Pci.Write =3D RootBridgeIoPciWrite; + + Protocol->Map =3D RootBridgeIoMap; + Protocol->Unmap =3D RootBridgeIoUnmap; + + Protocol->AllocateBuffer =3D RootBridgeIoAllocateBuffer; + Protocol->FreeBuffer =3D RootBridgeIoFreeBuffer; + + Protocol->Flush =3D RootBridgeIoFlush; + + Protocol->GetAttributes =3D RootBridgeIoGetAttributes; + Protocol->SetAttributes =3D RootBridgeIoSetAttributes; + + Protocol->Configuration =3D RootBridgeIoConfiguration; + + Protocol->SegmentNumber =3D 0; + + Status =3D gBS->LocateProtocol ( + &gEfiMetronomeArchProtocolGuid, + NULL, + (VOID **)&mMetronome + ); + ASSERT_EFI_ERROR (Status); + + return EFI_SUCCESS; +} + +/** + Check parameters for IO,MMIO,PCI read/write services of PCI Root Bridge = IO. + + The I/O operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and I/O width restrictions that= a PI + System on a platform might require. For example on some platforms, width + requests of EfiCpuIoWidthUint64 do not work. Misaligned buffers, on the = other + hand, will be handled by the driver. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOC= OL. + @param[in] OperationType I/O operation type: IO/MMIO/PCI. + @param[in] Width Signifies the width of the I/O or Memory opera= tion. + @param[in] Address The base address of the I/O operation. + @param[in] Count The number of I/O operations to perform. The n= umber + of bytes moved is Width size * Count, starting= at + Address. + @param[in] Buffer For read operations, the destination buffer to + store the results. For write operations, the s= ource + buffer from which to write data. + + @retval EFI_SUCCESS The parameters for this request pass the + checks. + @retval EFI_INVALID_PARAMETER Width is invalid for this PI system. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_UNSUPPORTED The Buffer is not aligned for the given W= idth. + @retval EFI_UNSUPPORTED The address range specified by Address, W= idth, + and Count is not valid for this PI system. +**/ +EFI_STATUS +RootBridgeIoCheckParameter ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN OPERATION_TYPE OperationType, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; + UINT64 MaxCount; + UINT64 Base; + UINT64 Limit; + + // + // Check to see if Buffer is NULL + // + if (Buffer =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Width is in the valid range + // + if ((UINT32)Width >=3D EfiPciWidthMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // For FIFO type, the target address won't increase during the access, + // so treat Count as 1 + // + if ((Width >=3D EfiPciWidthFifoUint8) && (Width <=3D EfiPciWidthFifoUint= 64)) { + Count =3D 1; + } + + // + // Check to see if Width is in the valid range for I/O Port operations + // + Width =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); + if ((OperationType !=3D MemOperation) && (Width =3D=3D EfiPciWidthUint64= )) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + // + // Check to see if Address is aligned + // + if ((Address & (UINT64)(mInStride[Width] - 1)) !=3D 0) { + return EFI_UNSUPPORTED; + } + + PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + // + // Check to see if any address associated with this transfer exceeds the + // maximum allowed address. The maximum address implied by the paramete= rs + // passed in is Address + Size * Count. If the following condition is m= et, + // then the transfer is not supported. + // + // Address + Size * Count > Limit + 1 + // + // Since Limit can be the maximum integer value supported by the CPU and + // Count can also be the maximum integer value supported by the CPU, this + // range check must be adjusted to avoid all oveflow conditions. + // + // The following form of the range check is equivalent but assumes that + // Limit is of the form (2^n - 1). + // + if (OperationType =3D=3D IoOperation) { + Base =3D PrivateData->IoBase; + Limit =3D PrivateData->IoLimit; + } else if (OperationType =3D=3D MemOperation) { + Base =3D PrivateData->MemBase; + Limit =3D PrivateData->MemLimit; + } else { + PciRbAddr =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address; + if ((PciRbAddr->Bus < PrivateData->BusBase) || + (PciRbAddr->Bus > PrivateData->BusLimit)) + { + return EFI_INVALID_PARAMETER; + } + + if ((PciRbAddr->Device > MAX_PCI_DEVICE_NUMBER) || + (PciRbAddr->Function > MAX_PCI_FUNCTION_NUMBER)) + { + return EFI_INVALID_PARAMETER; + } + + if (PciRbAddr->ExtendedRegister !=3D 0) { + Address =3D PciRbAddr->ExtendedRegister; + } else { + Address =3D PciRbAddr->Register; + } + + Base =3D 0; + Limit =3D MAX_PCI_REG_ADDRESS; + } + + if (Address < Base) { + return EFI_INVALID_PARAMETER; + } + + if (Count =3D=3D 0) { + if (Address > Limit) { + return EFI_UNSUPPORTED; + } + } else { + MaxCount =3D RShiftU64 (Limit, Width); + if (MaxCount < (Count - 1)) { + return EFI_UNSUPPORTED; + } + + if (Address > LShiftU64 (MaxCount - Count + 1, Width)) { + return EFI_UNSUPPORTED; + } + } + + return EFI_SUCCESS; +} + +/** + Internal help function for read and write memory space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTO= COL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration spac= e for + the PCI controller. + @param[in] Count The number of PCI configuration operations to + perform. Bytes moved is Width size * Count, + starting at Address. + @param[in, out] UserBuffer For read operations, the destination buffer to + store the results. For write operations, the + source buffer to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +RootBridgeIoMemRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D RootBridgeIoCheckParameter ( + This, + MemOperation, + Width, + Address, + Count, + Buffer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; + Count > 0; + Address +=3D InStride, Uint8Buffer +=3D OutStride, Count--) + { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + MmioWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + MmioWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + MmioWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + case EfiPciWidthUint64: + MmioWrite64 ((UINTN)Address, *((UINT64 *)Uint8Buffer)); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer =3D MmioRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) =3D MmioRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) =3D MmioRead32 ((UINTN)Address); + break; + case EfiPciWidthUint64: + *((UINT64 *)Uint8Buffer) =3D MmioRead64 ((UINTN)Address); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Internal help function for read and write IO space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTO= COL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration spac= e for + the PCI controller. + @param[in] Count The number of PCI configuration operations to + perform. Bytes moved is Width size * Count, + starting at Address. + @param[in, out] UserBuffer For read operations, the destination buffer to + store the results. For write operations, the + source buffer to write data from. + + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +RootBridgeIoIoRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + + Status =3D RootBridgeIoCheckParameter ( + This, + IoOperation, + Width, + Address, + Count, + Buffer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); + + #if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64) + if (InStride =3D=3D 0) { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoWriteFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint16: + IoWriteFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint32: + IoWriteFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoReadFifo8 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint16: + IoReadFifo16 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + case EfiPciWidthUint32: + IoReadFifo32 ((UINTN)Address, Count, Buffer); + return EFI_SUCCESS; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + #endif + + for (Uint8Buffer =3D Buffer; + Count > 0; + Address +=3D InStride, Uint8Buffer +=3D OutStride, Count--) + { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + IoWrite8 ((UINTN)Address, *Uint8Buffer); + break; + case EfiPciWidthUint16: + IoWrite16 ((UINTN)Address, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + IoWrite32 ((UINTN)Address, *((UINT32 *)Uint8Buffer)); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer =3D IoRead8 ((UINTN)Address); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) =3D IoRead16 ((UINTN)Address); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) =3D IoRead32 ((UINTN)Address); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Internal help function for read and write PCI configuration space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTO= COL. + @param[in] Write Switch value for Read or Write. + @param[in] Width Signifies the width of the memory operations. + @param[in] UserAddress The address within the PCI configuration spac= e for + the PCI controller. + @param[in] Count The number of PCI configuration operations to + perform. Bytes moved is Width size * Count, + starting at Address. + @param[in, out] UserBuffer For read operations, the destination buffer to + store the results. For write operations, the + source buffer to write data from. + + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +RootBridgeIoPciRW ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN BOOLEAN Write, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN OUT VOID *Buffer + ) +{ + EFI_STATUS Status; + UINT8 InStride; + UINT8 OutStride; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH OperationWidth; + UINT8 *Uint8Buffer; + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *PciRbAddr; + UINTN PcieRegAddr; + + Status =3D RootBridgeIoCheckParameter ( + This, + PciOperation, + Width, + Address, + Count, + Buffer + ); + if (EFI_ERROR (Status)) { + return Status; + } + + PciRbAddr =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_PCI_ADDRESS *)&Address; + + PcieRegAddr =3D (UINTN)PCI_LIB_ADDRESS ( + PciRbAddr->Bus, + PciRbAddr->Device, + PciRbAddr->Function, + (PciRbAddr->ExtendedRegister !=3D 0) ? \ + PciRbAddr->ExtendedRegister : + PciRbAddr->Register + ); + + InStride =3D mInStride[Width]; + OutStride =3D mOutStride[Width]; + OperationWidth =3D (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)(Width & 0x03); + for (Uint8Buffer =3D Buffer; + Count > 0; + PcieRegAddr +=3D InStride, Uint8Buffer +=3D OutStride, Count--) + { + if (Write) { + switch (OperationWidth) { + case EfiPciWidthUint8: + PciWrite8 (PcieRegAddr, *Uint8Buffer); + break; + case EfiPciWidthUint16: + PciWrite16 (PcieRegAddr, *((UINT16 *)Uint8Buffer)); + break; + case EfiPciWidthUint32: + PciWrite32 (PcieRegAddr, *((UINT32 *)Uint8Buffer)); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } else { + switch (OperationWidth) { + case EfiPciWidthUint8: + *Uint8Buffer =3D PciRead8 (PcieRegAddr); + break; + case EfiPciWidthUint16: + *((UINT16 *)Uint8Buffer) =3D PciRead16 (PcieRegAddr); + break; + case EfiPciWidthUint32: + *((UINT32 *)Uint8Buffer) =3D PciRead32 (PcieRegAddr); + break; + default: + // + // The RootBridgeIoCheckParameter call above will ensure that th= is + // path is not taken. + // + ASSERT (FALSE); + break; + } + } + } + + return EFI_SUCCESS; +} + +/** + Polls an address in memory mapped I/O space until an exit condition is m= et, + or a timeout occurs. + + This function provides a standard way to poll a PCI memory location. A P= CI + memory read operation is performed at the PCI memory address specified by + Address for the width specified by Width. The result of this PCI memory = read + operation is stored in Result. This PCI memory read operation is repeated + until either a timeout of Delay 100 ns units has expired, or (Result & M= ask) + is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the memory operations. The ca= ller + is responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above W= idth + in Mask are ignored. The bits in the bytes below = Width + which are zero in Mask are ignored when polling t= he + memory address. + @param[in] Value The comparison value used for the polling exit + criteria. + @param[in] Delay The number of 100 ns units to poll. Note that tim= er + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory + location. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + + if (Result =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ((UINT32)Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + // + // No matter what, always do a single poll. + // + Status =3D This->Mem.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + if (Delay =3D=3D 0) { + return EFI_SUCCESS; + } else { + // + // Determine the proper # of metronome ticks to wait for polling the + // location. The nuber of ticks is Roundup (Delay / + // mMetronome->TickPeriod)+1 + // The "+1" to account for the possibility of the first tick being sho= rt + // because we started in the middle of a tick. + // + // BugBug: overriding mMetronome->TickPeriod with UINT32 until Metrono= me + // protocol definition is updated. + // + NumberOfTicks =3D DivU64x32Remainder ( + Delay, + (UINT32)mMetronome->TickPeriod, + &Remainder + ); + if (Remainder !=3D 0) { + NumberOfTicks +=3D 1; + } + + NumberOfTicks +=3D 1; + + while (NumberOfTicks !=3D 0) { + mMetronome->WaitForTick (mMetronome, 1); + + Status =3D This->Mem.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + NumberOfTicks -=3D 1; + } + } + + return EFI_TIMEOUT; +} + +/** + Reads from the I/O space of a PCI Root Bridge. Returns when either the + polling exit criteria is satisfied or after a defined duration. + + This function provides a standard way to poll a PCI I/O location. A PCI = I/O + read operation is performed at the PCI I/O address specified by Address = for + the width specified by Width. + The result of this PCI I/O read operation is stored in Result. This PCI = I/O + read operation is repeated until either a timeout of Delay 100 ns units = has + expired, or (Result & Mask) is equal to Value. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the I/O operations. + @param[in] Address The base address of the I/O operations. The caller = is + responsible for aligning Address if required. + @param[in] Mask Mask used for the polling criteria. Bytes above Wid= th in + Mask are ignored. The bits in the bytes below Width + which are zero in Mask are ignored when polling the= I/O + address. + @param[in] Value The comparison value used for the polling exit crit= eria. + @param[in] Delay The number of 100 ns units to poll. Note that timer + available may be of poorer granularity. + @param[out] Result Pointer to the last value read from the memory loca= tion. + + @retval EFI_SUCCESS The last data returned from the access ma= tched + the poll exit criteria. + @retval EFI_INVALID_PARAMETER Width is invalid. + @retval EFI_INVALID_PARAMETER Result is NULL. + @retval EFI_TIMEOUT Delay expired before a match occurred. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPollIo ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINT64 Mask, + IN UINT64 Value, + IN UINT64 Delay, + OUT UINT64 *Result + ) +{ + EFI_STATUS Status; + UINT64 NumberOfTicks; + UINT32 Remainder; + + // + // No matter what, always do a single poll. + // + + if (Result =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + if ((UINT32)Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + Status =3D This->Io.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + if (Delay =3D=3D 0) { + return EFI_SUCCESS; + } else { + // + // Determine the proper # of metronome ticks to wait for polling the + // location. The number of ticks is Roundup (Delay / + // mMetronome->TickPeriod)+1 + // The "+1" to account for the possibility of the first tick being sho= rt + // because we started in the middle of a tick. + // + NumberOfTicks =3D DivU64x32Remainder ( + Delay, + (UINT32)mMetronome->TickPeriod, + &Remainder + ); + if (Remainder !=3D 0) { + NumberOfTicks +=3D 1; + } + + NumberOfTicks +=3D 1; + + while (NumberOfTicks !=3D 0) { + mMetronome->WaitForTick (mMetronome, 1); + + Status =3D This->Io.Read (This, Width, Address, 1, Result); + if (EFI_ERROR (Status)) { + return Status; + } + + if ((*Result & Mask) =3D=3D Value) { + return EFI_SUCCESS; + } + + NumberOfTicks -=3D 1; + } + } + + return EFI_TIMEOUT; +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + return RootBridgeIoMemRW (This, FALSE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge memory space. + + The Mem.Read(), and Mem.Write() functions enable a driver to access PCI + controller registers in the PCI root bridge memory space. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operation. + @param[in] Address The base address of the memory operation. The cal= ler + is responsible for aligning the Address if requir= ed. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMemWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + return RootBridgeIoMemRW (This, TRUE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[out] Buffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + return RootBridgeIoIoRW (This, FALSE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in the PCI root + bridge I/O space. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The base address of the I/O operation. The call= er is + responsible for aligning the Address if require= d. + @param[in] Count The number of I/O operations to perform. Bytes = moved + is Width size * Count, starting at Address. + @param[in] Buffer For read operations, the destination buffer to = store + the results. For write operations, the source b= uffer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to th= e PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoIoWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + return RootBridgeIoIoRW (This, TRUE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to copy one region of PCI root bridge memory space = to + another region of PCI root bridge memory space. + + The CopyMem() function enables a PCI driver to copy one region of PCI ro= ot + bridge memory space to another region of PCI root bridge memory space. T= his + is especially useful for video scroll operation on a memory mapped video + buffer. + The memory operations are carried out exactly as requested. The caller is + responsible for satisfying any alignment and memory width restrictions t= hat a + PCI root bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL + instance. + @param[in] Width Signifies the width of the memory operations. + @param[in] DestAddress The destination address of the memory operation. = The + caller is responsible for aligning the DestAddres= s if + required. + @param[in] SrcAddress The source address of the memory operation. The c= aller + is responsible for aligning the SrcAddress if + required. + @param[in] Count The number of memory operations to perform. Bytes + moved is Width size * Count, starting at DestAddr= ess + and SrcAddress. + + @retval EFI_SUCCESS The data was copied from one memory reg= ion + to another memory region. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root brid= ge. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due = to a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoCopyMem ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 DestAddress, + IN UINT64 SrcAddress, + IN UINTN Count + ) +{ + EFI_STATUS Status; + BOOLEAN Direction; + UINTN Stride; + UINTN Index; + UINT64 Result; + + if ((UINT32)Width > EfiPciWidthUint64) { + return EFI_INVALID_PARAMETER; + } + + if (DestAddress =3D=3D SrcAddress) { + return EFI_SUCCESS; + } + + Stride =3D (UINTN)(1 << Width); + + Direction =3D TRUE; + if ((DestAddress > SrcAddress) && + (DestAddress < (SrcAddress + Count * Stride))) + { + Direction =3D FALSE; + SrcAddress =3D SrcAddress + (Count-1) * Stride; + DestAddress =3D DestAddress + (Count-1) * Stride; + } + + for (Index =3D 0; Index < Count; Index++) { + Status =3D RootBridgeIoMemRead ( + This, + Width, + SrcAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + Status =3D RootBridgeIoMemWrite ( + This, + Width, + DestAddress, + 1, + &Result + ); + if (EFI_ERROR (Status)) { + return Status; + } + + if (Direction) { + SrcAddress +=3D Stride; + DestAddress +=3D Stride; + } else { + SrcAddress -=3D Stride; + DestAddress -=3D Stride; + } + } + + return EFI_SUCCESS; +} + +/** + Enables a PCI driver to access PCI controller registers in a PCI root + bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI + configuration registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. T= he + caller is responsible for any alignment and PCI configuration width issu= es + that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space fo= r the + PCI controller. + @param[in] Count The number of PCI configuration operations to per= form. + Bytes moved is Width size * Count, starting at + Address. + @param[out] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciRead ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + OUT VOID *Buffer + ) +{ + return RootBridgeIoPciRW (This, FALSE, Width, Address, Count, Buffer); +} + +/** + Enables a PCI driver to access PCI controller registers in a PCI root + bridge's configuration space. + + The Pci.Read() and Pci.Write() functions enable a driver to access PCI + configuration registers for a PCI controller. + The PCI Configuration operations are carried out exactly as requested. T= he + caller is responsible for any alignment and PCI configuration width issu= es + that a PCI Root Bridge on a platform might require. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Width Signifies the width of the memory operations. + @param[in] Address The address within the PCI configuration space fo= r the + PCI controller. + @param[in] Count The number of PCI configuration operations to per= form. + Bytes moved is Width size * Count, starting at + Address. + @param[in] Buffer For read operations, the destination buffer to st= ore + the results. For write operations, the source buf= fer + to write data from. + + @retval EFI_SUCCESS The data was read from or written to the = PCI + root bridge. + @retval EFI_INVALID_PARAMETER Width is invalid for this PCI root bridge. + @retval EFI_INVALID_PARAMETER Buffer is NULL. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoPciWrite ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width, + IN UINT64 Address, + IN UINTN Count, + IN VOID *Buffer + ) +{ + return RootBridgeIoPciRW (This, TRUE, Width, Address, Count, Buffer); +} + +/** + Provides the PCI controller-specific addresses required to access system + memory from a DMA bus master. + + The Map() function provides the PCI controller specific addresses needed= to + access system memory. This function is used to map system memory for PCI= bus + master DMA accesses. + + @param[in] This A pointer to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Operation Indicates if the bus master is going to= read + or write to system memory. + @param[in] HostAddress The system memory address to map to the= PCI + controller. + @param[in, out] NumberOfBytes On input the number of bytes to map. On + output the number of bytes that were ma= pped. + @param[out] DeviceAddress The resulting map address for the bus m= aster + PCI controller to use to access the sys= tem + memory's HostAddress. + @param[out] Mapping The value to pass to Unmap() when the b= us + master DMA operation is complete. + + @retval EFI_SUCCESS The range was mapped for the returned + NumberOfBytes. + @retval EFI_INVALID_PARAMETER Operation is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_INVALID_PARAMETER NumberOfBytes is NULL. + @retval EFI_INVALID_PARAMETER DeviceAddress is NULL. + @retval EFI_INVALID_PARAMETER Mapping is NULL. + @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a com= mon + buffer. + @retval EFI_DEVICE_ERROR The system hardware could not map the + requested address. + @retval EFI_OUT_OF_RESOURCES The request could not be completed due to= a + lack of resources. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoMap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_OPERATION Operation, + IN VOID *HostAddress, + IN OUT UINTN *NumberOfBytes, + OUT EFI_PHYSICAL_ADDRESS *DeviceAddress, + OUT VOID **Mapping + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + MAP_INFO *MapInfo; + + if ((HostAddress =3D=3D NULL) || (NumberOfBytes =3D=3D NULL) || (DeviceA= ddress =3D=3D NULL) || + (Mapping =3D=3D NULL)) + { + return EFI_INVALID_PARAMETER; + } + + // + // Initialize the return values to their defaults + // + *Mapping =3D NULL; + + // + // Make sure that Operation is valid + // + if ((UINT32)Operation >=3D EfiPciOperationMaximum) { + return EFI_INVALID_PARAMETER; + } + + // + // Most PCAT like chipsets can not handle performing DMA above 4GB. + // If any part of the DMA transfer being mapped is above 4GB, then + // map the DMA transfer to a buffer below 4GB. + // + PhysicalAddress =3D (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress; + if ((PhysicalAddress + *NumberOfBytes) > 0x100000000ULL) { + // + // Common Buffer operations can not be remapped. If the common buffer + // if above 4GB, then it is not possible to generate a mapping, so ret= urn + // an error. + // + if ((Operation =3D=3D EfiPciOperationBusMasterCommonBuffer) || + (Operation =3D=3D EfiPciOperationBusMasterCommonBuffer64)) + { + return EFI_UNSUPPORTED; + } + + // + // Allocate a MAP_INFO structure to remember the mapping when Unmap() = is + // called later. + // + Status =3D gBS->AllocatePool ( + EfiBootServicesData, + sizeof (MAP_INFO), + (VOID **)&MapInfo + ); + if (EFI_ERROR (Status)) { + *NumberOfBytes =3D 0; + return Status; + } + + // + // Return a pointer to the MAP_INFO structure in Mapping + // + *Mapping =3D MapInfo; + + // + // Initialize the MAP_INFO structure + // + MapInfo->Operation =3D Operation; + MapInfo->NumberOfBytes =3D *NumberOfBytes; + MapInfo->NumberOfPages =3D EFI_SIZE_TO_PAGES (*NumberOfBytes); + MapInfo->HostAddress =3D PhysicalAddress; + MapInfo->MappedHostAddress =3D 0x00000000ffffffff; + + // + // Allocate a buffer below 4GB to map the transfer to. + // + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiBootServicesData, + MapInfo->NumberOfPages, + &MapInfo->MappedHostAddress + ); + if (EFI_ERROR (Status)) { + gBS->FreePool (MapInfo); + *NumberOfBytes =3D 0; + return Status; + } + + // + // If this is a read operation from the Bus Master's point of view, + // then copy the contents of the real buffer into the mapped buffer + // so the Bus Master can read the contents of the real buffer. + // + if ((Operation =3D=3D EfiPciOperationBusMasterRead) || + (Operation =3D=3D EfiPciOperationBusMasterRead64)) + { + CopyMem ( + (VOID *)(UINTN)MapInfo->MappedHostAddress, + (VOID *)(UINTN)MapInfo->HostAddress, + MapInfo->NumberOfBytes + ); + } + + // + // The DeviceAddress is the address of the maped buffer below 4GB + // + *DeviceAddress =3D MapInfo->MappedHostAddress; + } else { + // + // The transfer is below 4GB, so the DeviceAddress is simply the + // HostAddress + // + *DeviceAddress =3D PhysicalAddress; + } + + return EFI_SUCCESS; +} + +/** + Completes the Map() operation and releases any corresponding resources. + + The Unmap() function completes the Map() operation and releases any + corresponding resources. + If the operation was an EfiPciOperationBusMasterWrite or + EfiPciOperationBusMasterWrite64, the data is committed to the target sys= tem + memory. + Any resources used for the mapping are freed. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Mapping The mapping value returned from Map(). + + @retval EFI_SUCCESS The range was unmapped. + @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned = by + Map(). + @retval EFI_DEVICE_ERROR The data was not committed to the target + system memory. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoUnmap ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN VOID *Mapping + ) +{ + MAP_INFO *MapInfo; + + // + // See if the Map() operation associated with this Unmap() required a ma= pping + // buffer. If a mapping buffer was not required, then this function simp= ly + // returns EFI_SUCCESS. + // + if (Mapping !=3D NULL) { + // + // Get the MAP_INFO structure from Mapping + // + MapInfo =3D (MAP_INFO *)Mapping; + + // + // If this is a write operation from the Bus Master's point of view, + // then copy the contents of the mapped buffer into the real buffer + // so the processor can read the contents of the real buffer. + // + if ((MapInfo->Operation =3D=3D EfiPciOperationBusMasterWrite) || + (MapInfo->Operation =3D=3D EfiPciOperationBusMasterWrite64)) + { + CopyMem ( + (VOID *)(UINTN)MapInfo->HostAddress, + (VOID *)(UINTN)MapInfo->MappedHostAddress, + MapInfo->NumberOfBytes + ); + } + + // + // Free the mapped buffer and the MAP_INFO structure. + // + gBS->FreePages (MapInfo->MappedHostAddress, MapInfo->NumberOfPages); + gBS->FreePool (Mapping); + } + + return EFI_SUCCESS; +} + +/** + Allocates pages that are suitable for an EfiPciOperationBusMasterCommonB= uffer + or EfiPciOperationBusMasterCommonBuffer64 mapping. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Type This parameter is not used and must be ignored. + @param MemoryType The type of memory to allocate, EfiBootServicesData or + EfiRuntimeServicesData. + @param Pages The number of pages to allocate. + @param HostAddress A pointer to store the base system memory address of = the + allocated range. + @param Attributes The requested bit mask of attributes for the allocated + range. Only the attributes + EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE, + EFI_PCI_ATTRIBUTE_MEMORY_CACHED, and + EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE may be used with= this + function. + + @retval EFI_SUCCESS The requested memory pages were allocated. + @retval EFI_INVALID_PARAMETER MemoryType is invalid. + @retval EFI_INVALID_PARAMETER HostAddress is NULL. + @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal + attribute bits are MEMORY_WRITE_COMBINE, + MEMORY_CACHED, and DUAL_ADDRESS_CYCLE. + @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoAllocateBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN EFI_ALLOCATE_TYPE Type, + IN EFI_MEMORY_TYPE MemoryType, + IN UINTN Pages, + OUT VOID **HostAddress, + IN UINT64 Attributes + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PhysicalAddress; + + // + // Validate Attributes + // + if ((Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) !=3D 0)= { + return EFI_UNSUPPORTED; + } + + // + // Check for invalid inputs + // + if (HostAddress =3D=3D NULL) { + return EFI_INVALID_PARAMETER; + } + + // + // The only valid memory types are EfiBootServicesData and + // EfiRuntimeServicesData + // + if ((MemoryType !=3D EfiBootServicesData) && + (MemoryType !=3D EfiRuntimeServicesData)) + { + return EFI_INVALID_PARAMETER; + } + + // + // Limit allocations to memory below 4GB + // + PhysicalAddress =3D (EFI_PHYSICAL_ADDRESS)(0xffffffff); + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + MemoryType, + Pages, + &PhysicalAddress + ); + if (EFI_ERROR (Status)) { + return Status; + } + + *HostAddress =3D (VOID *)(UINTN)PhysicalAddress; + + return EFI_SUCCESS; +} + +/** + Frees memory that was allocated with AllocateBuffer(). + + The FreeBuffer() function frees memory that was allocated with + AllocateBuffer(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Pages The number of pages to free. + @param HostAddress The base system memory address of the allocated range. + + @retval EFI_SUCCESS The requested memory pages were freed. + @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress= and + Pages was not allocated with AllocateBuff= er(). +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFreeBuffer ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINTN Pages, + OUT VOID *HostAddress + ) +{ + return gBS->FreePages ((EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, Pages); +} + +/** + Flushes all PCI posted write transactions from a PCI host bridge to syst= em + memory. + + The Flush() function flushes any PCI posted write transactions from a PCI + host bridge to system memory. Posted write transactions are generated by= PCI + bus masters when they perform write transactions to target addresses in + system memory. + This function does not flush posted write transactions from any PCI brid= ges. + A PCI controller specific action must be taken to guarantee that the pos= ted + write transactions have been flushed from the PCI controller and from al= l the + PCI bridges into the PCI host bridge. This is typically done with a PCI = read + transaction from the PCI controller prior to calling Flush(). + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + + @retval EFI_SUCCESS The PCI posted write transactions were flushed + from the PCI host bridge to system memory. + @retval EFI_DEVICE_ERROR The PCI posted write transactions were not fl= ushed + from the PCI host bridge due to a hardware er= ror. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoFlush ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This + ) +{ + // + // not supported yet + // + return EFI_SUCCESS; +} + +/** + Gets the attributes that a PCI root bridge supports setting with + SetAttributes(), and the attributes that a PCI root bridge is currently + using. + + The GetAttributes() function returns the mask of attributes that this PCI + root bridge supports and the mask of attributes that the PCI root bridge= is + currently using. + + @param This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param Supported A pointer to the mask of attributes that this PCI root + bridge supports setting with SetAttributes(). + @param Attributes A pointer to the mask of attributes that this PCI root + bridge is currently using. + + @retval EFI_SUCCESS If Supports is not NULL, then the attribu= tes + that the PCI root bridge supports is retu= rned + in Supports. If Attributes is not NULL, t= hen + the attributes that the PCI root bridge is + currently using is returned in Attributes. + @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL. +**/ +EFI_STATUS +EFIAPI +RootBridgeIoGetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT UINT64 *Supported, + OUT UINT64 *Attributes + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if ((Attributes =3D=3D NULL) && (Supported =3D=3D NULL)) { + return EFI_INVALID_PARAMETER; + } + + // + // Set the return value for Supported and Attributes + // + if (Supported !=3D NULL) { + *Supported =3D PrivateData->Supports; + } + + if (Attributes !=3D NULL) { + *Attributes =3D PrivateData->Attributes; + } + + return EFI_SUCCESS; +} + +/** + Sets attributes for a resource range on a PCI root bridge. + + The SetAttributes() function sets the attributes specified in Attributes= for + the PCI root bridge on the resource range specified by ResourceBase and + ResourceLength. Since the granularity of setting these attributes may va= ry + from resource type to resource type, and from platform to platform, the + actual resource range and the one passed in by the caller may differ. As= a + result, this function may set the attributes specified by Attributes on a + larger resource range than the caller requested. The actual range is ret= urned + in ResourceBase and ResourceLength. The caller is responsible for verify= ing + that the actual range for which the attributes were set is acceptable. + + @param[in] This A pointer to the + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL. + @param[in] Attributes The mask of attributes to set. If the + attribute bit MEMORY_WRITE_COMBINE, + MEMORY_CACHED, or MEMORY_DISABLE is set, + then the resource range is specified by + ResourceBase and ResourceLength. If + MEMORY_WRITE_COMBINE, MEMORY_CACHED, and + MEMORY_DISABLE are not set, then + ResourceBase and ResourceLength are ign= ored, + and may be NULL. + @param[in, out] ResourceBase A pointer to the base address of the + resource range to be modified by the + attributes specified by Attributes. + @param[in, out] ResourceLength A pointer to the length of the resource + range to be modified by the attributes + specified by Attributes. + + @retval EFI_SUCCESS The current configuration of this PCI root brid= ge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root brid= ge + could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL +**/ +EFI_STATUS +EFIAPI +RootBridgeIoSetAttributes ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + IN UINT64 Attributes, + IN OUT UINT64 *ResourceBase, + IN OUT UINT64 *ResourceLength + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + + PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + if (Attributes !=3D 0) { + if ((Attributes & (~(PrivateData->Supports))) !=3D 0) { + return EFI_UNSUPPORTED; + } + } + + // + // This is a generic driver for a PC-AT class system. It does not have = any + // chipset specific knowlegde, so none of the attributes can be set or + // cleared. Any attempt to set attribute that are already set will succ= eed, + // and any attempt to set an attribute that is not supported will fail. + // + if (Attributes & (~PrivateData->Attributes)) { + return EFI_UNSUPPORTED; + } + + return EFI_SUCCESS; +} + +/** + Retrieves the current resource settings of this PCI root bridge in the f= orm + of a set of ACPI 2.0 resource descriptors. + + There are only two resource descriptor types from the ACPI Specification= that + may be used to describe the current resources allocated to a PCI root br= idge. + These are the QWORD Address Space Descriptor (ACPI 2.0 Section 6.4.3.5.1= ), + and the End Tag (ACPI 2.0 Section 6.4.2.8). The QWORD Address Space + Descriptor can describe memory, I/O, and bus number ranges for dynamic or + fixed resources. The configuration of a PCI root bridge is described wit= h one + or more QWORD Address Space Descriptors followed by an End Tag. + + @param[in] This A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCO= L. + @param[out] Resources A pointer to the ACPI 2.0 resource descriptors = that + describe the current configuration of this PCI = root + bridge. The storage for the ACPI 2.0 resource + descriptors is allocated by this function. The + caller must treat the return buffer as read-only + data, and the buffer must not be freed by the + caller. + + @retval EFI_SUCCESS The current configuration of this PCI root brid= ge + was returned in Resources. + @retval EFI_UNSUPPORTED The current configuration of this PCI root brid= ge + could not be retrieved. + @retval EFI_INVALID_PARAMETER Invalid pointer of + EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL +**/ +EFI_STATUS +EFIAPI +RootBridgeIoConfiguration ( + IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *This, + OUT VOID **Resources + ) +{ + PCI_ROOT_BRIDGE_INSTANCE *PrivateData; + UINTN Index; + + PrivateData =3D DRIVER_INSTANCE_FROM_PCI_ROOT_BRIDGE_IO_THIS (This); + + for (Index =3D 0; Index < TypeMax; Index++) { + if (PrivateData->ResAllocNode[Index].Status =3D=3D ResAllocated) { + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Desc; + + Desc =3D &Configuration.SpaceDesp[Index]; + Desc->AddrRangeMin =3D PrivateData->ResAllocNode[Index].Base; + Desc->AddrRangeMax =3D PrivateData->ResAllocNode[Index].Base + + PrivateData->ResAllocNode[Index].Length - 1; + Desc->AddrLen =3D PrivateData->ResAllocNode[Index].Length; + } + } + + *Resources =3D &Configuration; + return EFI_SUCCESS; +} --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114595): https://edk2.groups.io/g/devel/message/114595 Mute This Topic: https://groups.io/mt/103975472/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-