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Fri, 26 Jan 2024 07:12:55 -0600 From: "Zhai, MingXin (Duke) via groups.io" To: CC: Eric Xing , Ken Yao , Igniculus Fu , Abner Chang Subject: [edk2-devel] [PATCH V3 17/32] AMD/VanGoghBoard: Check in Smm access module Date: Fri, 26 Jan 2024 21:11:10 +0800 Message-ID: <20240126131125.1881-18-duke.zhai@amd.com> In-Reply-To: <20240126131125.1881-1-duke.zhai@amd.com> References: <20240126131125.1881-1-duke.zhai@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CE:EE_|CY5PR12MB6382:EE_ X-MS-Office365-Filtering-Correlation-Id: 205262ec-aa55-40ae-f951-08dc1e708567 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Message-Info: FhZxmBrWopmmaT3Ng5PUyt93Zib+l03ipupM/6S4fUJrwFywSrBODKMaofGeJ0Tk5ptR+peiKHzD587FWUHm5+7OntxaZfeIM1gh4RBI+CyfYuaR9INY6WoMe0kjyXO+Sic5NYDeFQLToYgxO8BmOmK8j5YHYUHMsqoB/e73QstBXpipwleDssMlSVsPibVf3puqXo6OHjfdWyLvVyqXuGjB0ZanEQtam0Kj8Rd5CDC/rJOX3uhnT5+N+J2+zstCrPaj0gmur56j6Zz9ZWJm5IsEGEYKyCYtAVHKw8cWvO24UMUhdXSLB/TVf12MhoKEOfISQ4FI30pPcAWm99Yjm2ieuL8ZO1pkkUTTtxXqyj7TZN52oQzGqhNcF15/idlhd78kA6GLhEoMzXV/cf7Zg0ePG8wzchvWWquRmQyblifei+cCjdVFSzX+iSz8DddAop5QlaBzCtDt/3rFAriD9r0r/Hu2HADV82R1oBjnppODFCBvzcnyzC8hypKkwG27iIcrpVey7KQvO8fOr57ZfkR3mRJLynwMcizAJ1mzM0FnaRsR/xk4qmyKD+n3yjY3KGEL9r63gA3/08/SBjV++jBIOoZd8c/QnXHfJMdIctQ5e3zRkOURX7rzxUYkTVQ2Bn5C9mIXnREZ68C2kXo+2BfWnzqE5eiC6kIiV+CMlnI++uIWCEKhUKFReasYjO4GXQTyr5GvbcROWaqEwjQOXYgNimhQY3HB3idpz45yoNMvm6AdZrGDnRDVYXb+PCVuYPJQk8/MTSCko4P8A8L7lw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Jan 2024 13:13:00.2028 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 205262ec-aa55-40ae-f951-08dc1e708567 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000E9CE.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6382 Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,duke.zhai@amd.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: n8d7Mal19zvp0HKsYT9zvRqSx1787277AA= Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @groups.io) X-ZM-MESSAGEID: 1706274786178100005 Content-Type: text/plain; charset="utf-8" From: Duke Zhai BZ #:4640 In V2: Improve coding style. 1.Remove the leading underscore and use double underscore at trailing in = C header files. 2.Remove old tianocore licenses and redundant license description. 3.Improve coding style. For example: remove space between @param. In V1: Initial AMD Smm access module. Contains description files for ACPI SMM Platform handler module. Signed-off-by: Duke Zhai Cc: Eric Xing Cc: Ken Yao Cc: Igniculus Fu Cc: Abner Chang --- .../Smm/AcpiSmm/AcpiSmmPlatform.c | 183 ++++++++ .../Smm/AcpiSmm/AcpiSmmPlatform.h | 50 ++ .../Smm/AcpiSmm/AcpiSmmPlatform.inf | 57 +++ .../Smm/SmmAccessPei/SmmAccessPei.c | 436 ++++++++++++++++++ .../Smm/SmmAccessPei/SmmAccessPei.inf | 43 ++ 5 files changed, 769 insertions(+) create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/= AcpiSmmPlatform.c create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/= AcpiSmmPlatform.h create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/= AcpiSmmPlatform.inf create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAcces= sPei/SmmAccessPei.c create mode 100644 Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAcces= sPei/SmmAccessPei.inf diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmm= Platform.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmm= Platform.c new file mode 100644 index 0000000000..20a0ed6cb7 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatfor= m.c @@ -0,0 +1,183 @@ +/** @file +ACPISMM Driver implementation file. + +This is QNC Smm platform driver + +Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include + +/** + Allocate EfiACPIMemoryNVS below 4G memory address. + + This function allocates EfiACPIMemoryNVS below 4G memory address. + + @param[in] Size Size of memory to allocate. + + @return Allocated address for output. + +**/ +VOID * +AllocateAcpiNvsMemoryBelow4G ( + IN UINTN Size + ) +{ + UINTN Pages; + EFI_PHYSICAL_ADDRESS Address; + EFI_STATUS Status; + VOID *Buffer; + + Pages =3D EFI_SIZE_TO_PAGES (Size); + Address =3D 0xffffffff; + + Status =3D gBS->AllocatePages ( + AllocateMaxAddress, + EfiACPIMemoryNVS, + Pages, + &Address + ); + if (EFI_ERROR (Status)) { + return NULL; + } + + Buffer =3D (VOID *)(UINTN)Address; + ZeroMem (Buffer, Size); + + return Buffer; +} + +/** + Reserved S3 memory for InstallS3Memory + + @retval EFI_OUT_OF_RESOURCES Insufficient resources to complete fun= ction. + @retval EFI_SUCCESS Function has completed successfully. + +**/ +EFI_STATUS +EFIAPI +ReservedS3Memory ( + UINTN SystemMemoryLength + + ) + +{ + VOID *GuidHob; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock; + VOID *AcpiReservedBase; + + UINTN TsegIndex; + UINTN TsegSize; + UINTN TsegBase; + RESERVED_ACPI_S3_RANGE *AcpiS3Range; + + DEBUG ((DEBUG_INFO, "ReservedS3Memory, SystemMemoryLength: 0x%08X\n", Sy= stemMemoryLength)); + // + // Get Hob list for SMRAM desc + // + GuidHob =3D GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid); + ASSERT (GuidHob !=3D NULL); + DEBUG ((DEBUG_INFO, "gEfiSmmPeiSmramMemoryReserveGuid: 0x%X \n", (UINTN)= GuidHob)); + DescriptorBlock =3D GET_GUID_HOB_DATA (GuidHob); + ASSERT (DescriptorBlock !=3D NULL); + + // + // Use the hob to get SMRAM capabilities + // + TsegIndex =3D DescriptorBlock->NumberOfSmmReservedRegions - 1; + DEBUG ((DEBUG_INFO, "DescriptorBlock->NumberOfSmmReservedRegions: 0x%X\n= ", DescriptorBlock->NumberOfSmmReservedRegions)); + DEBUG ((DEBUG_INFO, "TsegIndex: 0x%X\n", TsegIndex)); + ASSERT (TsegIndex <=3D (MAX_SMRAM_RANGES - 1)); + TsegBase =3D (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalStart; + TsegSize =3D (UINTN)DescriptorBlock->Descriptor[TsegIndex].PhysicalSize; + + DEBUG ((DEBUG_INFO, "SMM Base: %08X\n", TsegBase)); + DEBUG ((DEBUG_INFO, "SMM Size: %08X\n", TsegSize)); + + // + // Now find the location of the data structure that is used to store the= address + // of the S3 reserved memory. + // + AcpiS3Range =3D (RESERVED_ACPI_S3_RANGE *)(UINTN)(TsegBase + RESERVED_AC= PI_S3_RANGE_OFFSET); + DEBUG ((DEBUG_INFO, "AcpiS3Range: %08X\n", (UINTN)AcpiS3Range)); + // + // Allocate reserved ACPI memory for S3 resume. Pointer to this region = is + // stored in SMRAM in the first page of TSEG. + // + AcpiReservedBase =3D AllocateAcpiNvsMemoryBelow4G (PcdGet32 (PcdS3AcpiRe= servedMemorySize)); + DEBUG ((DEBUG_INFO, "AcpiReservedBase: %08X\n", (UINTN)AcpiReservedBase)= ); + ASSERT (AcpiReservedBase !=3D NULL); + if (AcpiReservedBase !=3D NULL) { + AcpiS3Range->AcpiReservedMemoryBase =3D (UINT32)(UINTN)AcpiReservedBas= e; + AcpiS3Range->AcpiReservedMemorySize =3D PcdGet32 (PcdS3AcpiReservedMem= orySize); + } + + AcpiS3Range->SystemMemoryLength =3D (UINT32)SystemMemoryLength; + + DEBUG ((DEBUG_INFO, "S3 Memory Base: %08X\n", AcpiS3Range->AcpiReser= vedMemoryBase)); + DEBUG ((DEBUG_INFO, "S3 Memory Size: %08X\n", AcpiS3Range->AcpiReser= vedMemorySize)); + DEBUG ((DEBUG_INFO, "S3 SysMemoryLength: %08X\n", AcpiS3Range->SystemMem= oryLength)); + + return EFI_SUCCESS; +} + +/** + Initializes the SMM S3 Handler Driver. + + @param[in] ImageHandle The image handle of Sleep State Wake driver. + @param[in] SystemTable The starndard EFI system table. + + @retval EFI_OUT_OF_RESOURCES Insufficient resources to complete fun= ction. + @retval EFI_SUCCESS Function has completed successfully. + @retval Other Error occured during execution. + +**/ +EFI_STATUS +EFIAPI +InitAcpiSmmPlatform ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) + +{ + EFI_STATUS Status; + EFI_GLOBAL_NVS_AREA_PROTOCOL *AcpiNvsProtocol =3D NULL; + UINTN MemoryLength; + EFI_PEI_HOB_POINTERS Hob; + + Status =3D gBS->LocateProtocol ( + &gEfiGlobalNvsAreaProtocolGuid, + NULL, + (VOID **)&AcpiNvsProtocol + ); + ASSERT_EFI_ERROR (Status); + + // + // Calculate the system memory length by memory hobs + // + MemoryLength =3D 0x100000; + Hob.Raw =3D GetFirstHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR); + ASSERT (Hob.Raw !=3D NULL); + while ((Hob.Raw !=3D NULL) && (!END_OF_HOB_LIST (Hob))) { + if (Hob.ResourceDescriptor->ResourceType =3D=3D EFI_RESOURCE_SYSTEM_ME= MORY) { + // + // Skip the memory region below 1MB + // + if (Hob.ResourceDescriptor->PhysicalStart >=3D 0x100000) { + MemoryLength +=3D (UINTN)Hob.ResourceDescriptor->ResourceLength; + } + } + + Hob.Raw =3D GET_NEXT_HOB (Hob); + Hob.Raw =3D GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, Hob.Raw); + } + + Status =3D ReservedS3Memory (MemoryLength); + ASSERT_EFI_ERROR (Status); + + return Status; +} diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmm= Platform.h b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmm= Platform.h new file mode 100644 index 0000000000..31ab4f083d --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatfor= m.h @@ -0,0 +1,50 @@ +/** @file +Header file for SMM S3 Handler Driver. + +Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#ifndef ACPI_SMM_DRIVER_H_ +#define ACPI_SMM_DRIVER_H_ +// +// Include files +// +// +// Driver Consumed Protocol Prototypes +// +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +// +// This structure stores the base and size of the ACPI reserved memory use= d when +// resuming from S3. This region must be allocated by the platform code. +// +typedef struct { + UINT32 AcpiReservedMemoryBase; + UINT32 AcpiReservedMemorySize; + UINT32 SystemMemoryLength; +} RESERVED_ACPI_S3_RANGE; + +#define RESERVED_ACPI_S3_RANGE_OFFSET (EFI_PAGE_SIZE - sizeof (RESERVED_A= CPI_S3_RANGE)) +#define MAX_SMRAM_RANGES 4 + +#endif diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmm= Platform.inf b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiS= mmPlatform.inf new file mode 100644 index 0000000000..428e04b7d2 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/AcpiSmm/AcpiSmmPlatfor= m.inf @@ -0,0 +1,57 @@ +## @file +# Component description file for ACPI SMM Platform handler module +# +# This is QNC Smm platform driver . +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013-2019 Intel Corporation. +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + + +[Defines] + INF_VERSION =3D 0x00010005 + BASE_NAME =3D AcpiSmmPlatform + FILE_GUID =3D 833AF7CC-C58F-4BF6-8FCD-A46667F2BAD3 + MODULE_TYPE =3D DXE_SMM_DRIVER + VERSION_STRING =3D 1.0 + PI_SPECIFICATION_VERSION =3D 0x0001000A + ENTRY_POINT =3D InitAcpiSmmPlatform + +[Sources] + AcpiSmmPlatform.c + AcpiSmmPlatform.h + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ChachaniBoardPkg/Project.dec + +[LibraryClasses] + UefiBootServicesTableLib + UefiRuntimeServicesTableLib + ReportStatusCodeLib + UefiDriverEntryPoint + DebugLib + IoLib + PciLib + BaseMemoryLib + BaseLib + SmmServicesTableLib + PcdLib + HobLib + S3BootScriptLib + LockBoxLib + +[Protocols] + gEfiGlobalNvsAreaProtocolGuid + +[Guids] + gEfiSmmPeiSmramMemoryReserveGuid + +[Pcd] + gPlatformPkgTokenSpaceGuid.PcdS3AcpiReservedMemorySize + +[Depex] + gEfiGlobalNvsAreaProtocolGuid diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/Sm= mAccessPei.c b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/= SmmAccessPei.c new file mode 100644 index 0000000000..7880acc2f3 --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccess= Pei.c @@ -0,0 +1,436 @@ +/** @file +This is the driver that publishes the SMM Access Ppi +instance for the Quark SOC. + +Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+ +SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#define SMMMASK_ADDRESS 0xC0010113 + +#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \ + CR ( \ + a, \ + SMM_ACCESS_PRIVATE_DATA, \ + SmmAccess, \ + SMM_ACCESS_PRIVATE_DATA_SIGNATURE \ + ) + +typedef struct { + UINTN Signature; + EFI_HANDLE Handle; + PEI_SMM_ACCESS_PPI SmmAccess; + UINTN NumberRegions; + EFI_SMRAM_DESCRIPTOR *SmramDesc; +} SMM_ACCESS_PRIVATE_DATA; + +#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a= ') + +/** + CpuOpenSMRAM - read/write A0000-BFFFF + + @param VOID None. + + @retval VOID None. +**/ +VOID +EFIAPI +OpenSMRAM ( + VOID + ) +{ + volatile UINT64 RegValue; + + // Disable protection in ASeg and TSeg + RegValue =3D AsmReadMsr64 (SMMMASK_ADDRESS); + RegValue &=3D (UINT64)(~BIT0); + RegValue &=3D (UINT64)(~BIT1); + AsmWriteMsr64 (SMMMASK_ADDRESS, RegValue); + + // Enable FixMtrrModEn + RegValue =3D AsmReadMsr64 (SYS_CFG); + RegValue |=3D (UINT64)(1 << 19); + AsmWriteMsr64 (SYS_CFG, RegValue); + + // Enable Rd/Wr DRAM in ASeg + RegValue =3D AsmReadMsr64 (AMD_AP_MTRR_FIX16k_A0000); + RegValue |=3D 0x1010101010101010; + RegValue |=3D 0x0808080808080808; + AsmWriteMsr64 (AMD_AP_MTRR_FIX16k_A0000, RegValue); + + // Disable FixMtrrModEn + RegValue =3D AsmReadMsr64 (SYS_CFG); + RegValue &=3D ~(UINT64)(1 << 19); + AsmWriteMsr64 (SYS_CFG, RegValue); +} + +/** + CpuSmramWP - write protect from A0000-BFFFF + + @param VOID None. + + @retval VOID None. +**/ +VOID +EFIAPI +CloseSmram ( + VOID + ) +{ + volatile UINT64 RegValue; + + // Enable FixMtrrModEn + RegValue =3D AsmReadMsr64 (SYS_CFG); + RegValue |=3D (UINT64)(1 << 19); + AsmWriteMsr64 (SYS_CFG, RegValue); + + // Disable Rd/Wr DRAM in ASeg + RegValue =3D AsmReadMsr64 (AMD_AP_MTRR_FIX16k_A0000); + RegValue &=3D 0xEFEFEFEFEFEFEFEF; + RegValue &=3D 0xF7F7F7F7F7F7F7F7; + AsmWriteMsr64 (AMD_AP_MTRR_FIX16k_A0000, RegValue); + + // Disable FixMtrrModEn + RegValue =3D AsmReadMsr64 (SYS_CFG); + RegValue &=3D ~(UINT64)(1 << 19); + AsmWriteMsr64 (SYS_CFG, RegValue); + + RegValue =3D AsmReadMsr64 (SMMMASK_ADDRESS); + RegValue |=3D (UINT64)BIT0; + RegValue |=3D (UINT64)BIT1; + AsmWriteMsr64 (SMMMASK_ADDRESS, RegValue); +} + +/** + Setting the bit0 of MSRC001_0015 Hardware Configuration (HWCR) to do SMM= code lock. + + @param VOID None. + + @retval VOID None. +**/ +VOID +EFIAPI +LockSmm ( + VOID + ) +{ + volatile UINT64 Data64; + + Data64 =3D AsmReadMsr64 (HWCR); + Data64 |=3D (UINT64)BIT0; // SMM_LOCK + AsmWriteMsr64 (HWCR, Data64); +} + +/** + This routine accepts a request to "open" a region of SMRAM. The + region could be legacy ABSEG, HSEG, or TSEG near top of physical memory. + The use of "open" means that the memory is visible from all PEIM + and SMM agents. + + @param[in] PeiServices General purpose services available to eve= ry PEIM. + @param[in] This Pointer to the SMM Access Interface. + @param[in] DescriptorIndex Region of SMRAM to Open. + + @retval EFI_SUCCESS The region was successfully opened. + @retval EFI_DEVICE_ERROR The region could not be opened becaus= e locked by + chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bound= s. + +**/ +EFI_STATUS +EFIAPI +Open ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range in Open\n")); + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM= _LOCKED) { + DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region in Open\n")); + return EFI_DEVICE_ERROR; + } + + // + // Open TSEG + // + OpenSMRAM (); + + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D ~(EFI_SMRAM_CLOSE= D | EFI_ALLOCATED); + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_OPEN; + SmmAccess->SmmAccess.OpenState =3D TRUE; + + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "close" a region of SMRAM. This is va= lid for + compatible SMRAM region. + + @param[in] PeiServices General purpose services available to eve= ry PEIM. + @param[in] This Pointer to the SMM Access Interface. + @param[in] DescriptorIndex Region of SMRAM to Close. + + @retval EFI_SUCCESS The region was successfully closed. + @retval EFI_DEVICE_ERROR The region could not be closed becaus= e locked by + chipset. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bound= s. + +**/ +EFI_STATUS +EFIAPI +Close ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + BOOLEAN OpenState; + UINT8 Index; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range in Close\n")); + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM= _LOCKED) { + DEBUG ((DEBUG_WARN, "SmmAccess Close region is locked:%d\n", Descripto= rIndex)); + return EFI_DEVICE_ERROR; + } + + if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & EFI_SMRAM_CLOSED= ) { + DEBUG ((DEBUG_WARN, "SmmAccess Close region is closed already:%d\n", D= escriptorIndex)); + return EFI_DEVICE_ERROR; + } + + // + // Close TSEG + // + CloseSmram (); + + SmmAccess->SmramDesc[DescriptorIndex].RegionState &=3D ~EFI_SMRAM_OPEN; + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D (EFI_SMRAM_CLOSED= | EFI_ALLOCATED); + + // + // Find out if any regions are still open + // + OpenState =3D FALSE; + for (Index =3D 0; Index < SmmAccess->NumberRegions; Index++) { + if ((SmmAccess->SmramDesc[Index].RegionState & EFI_SMRAM_OPEN) =3D=3D = EFI_SMRAM_OPEN) { + OpenState =3D TRUE; + } + } + + SmmAccess->SmmAccess.OpenState =3D OpenState; + + return EFI_SUCCESS; +} + +/** + This routine accepts a request to "lock" SMRAM. The + region could be legacy AB or TSEG near top of physical memory. + The use of "lock" means that the memory can no longer be opened + to PEIM. + + @param[in] PeiServices General purpose services available to eve= ry PEIM. + @param[in] This Pointer to the SMM Access Interface. + @param[in] DescriptorIndex Region of SMRAM to Lock. + + @retval EFI_SUCCESS The region was successfully locked. + @retval EFI_DEVICE_ERROR The region could not be locked becaus= e at least + one range is still open. + @retval EFI_INVALID_PARAMETER The descriptor index was out of bound= s. + +**/ +EFI_STATUS +EFIAPI +Lock ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN UINTN DescriptorIndex + ) +{ + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + + if (DescriptorIndex >=3D SmmAccess->NumberRegions) { + DEBUG ((DEBUG_WARN, "SMRAM region out of range in Lock\n")); + return EFI_INVALID_PARAMETER; + } else if (SmmAccess->SmmAccess.OpenState) { + DEBUG ((DEBUG_WARN, "Cannot lock SMRAM when SMRAM regions are still op= en\n")); + return EFI_DEVICE_ERROR; + } + + // + // Lock TSEG + // + LockSmm (); + SmmAccess->SmramDesc[DescriptorIndex].RegionState |=3D EFI_SMRAM_LOCKED; + SmmAccess->SmmAccess.LockState =3D TRUE; + + return EFI_SUCCESS; +} + +/** + This routine services a user request to discover the SMRAM + capabilities of this platform. This will report the possible + ranges that are possible for SMRAM access, based upon the + memory controller capabilities. + + @param[in] PeiServices General purpose services available to e= very PEIM. + @param[in] This Pointer to the SMRAM Access Interface. + @param[in, out] SmramMapSize Pointer to the variable containing siz= e of the + buffer to contain the description info= rmation. + @param[in, out] SmramMap Buffer containing the data describing = the Smram + region descriptors. + + @retval EFI_BUFFER_TOO_SMALL The user did not provide a sufficient = buffer. + @retval EFI_SUCCESS The user provided a sufficiently-sized= buffer. + +**/ +EFI_STATUS +EFIAPI +GetCapabilities ( + IN EFI_PEI_SERVICES **PeiServices, + IN PEI_SMM_ACCESS_PPI *This, + IN OUT UINTN *SmramMapSize, + IN OUT EFI_SMRAM_DESCRIPTOR *SmramMap + ) +{ + EFI_STATUS Status; + SMM_ACCESS_PRIVATE_DATA *SmmAccess; + UINTN BufferSize; + + SmmAccess =3D SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This); + BufferSize =3D SmmAccess->NumberRegions * sizeof (EFI_SMRAM_DESCRIPTOR); + + if (*SmramMapSize < BufferSize) { + DEBUG ((DEBUG_WARN, "SMRAM Map Buffer too small\n")); + Status =3D EFI_BUFFER_TOO_SMALL; + } else { + CopyMem (SmramMap, SmmAccess->SmramDesc, BufferSize); + Status =3D EFI_SUCCESS; + } + + *SmramMapSize =3D BufferSize; + + return Status; +} + +/** + This is the constructor for the SMM Access Ppi + + @param[in] FfsHeader FfsHeader. + @param[in] PeiServices General purpose services available to eve= ry PEIM. + + @retval EFI_SUCCESS Protocol successfully started and installed. + @retval EFI_UNSUPPORTED Protocol can't be started. +**/ +EFI_STATUS +EFIAPI +SmmAccessPeiEntryPoint ( + IN EFI_PEI_FILE_HANDLE FileHandle, + IN CONST EFI_PEI_SERVICES **PeiServices + ) +{ + EFI_STATUS Status; + EFI_BOOT_MODE BootMode; + UINTN Index; + EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock =3D NULL; + SMM_ACCESS_PRIVATE_DATA *SmmAccessPrivate; + EFI_PEI_PPI_DESCRIPTOR *PpiList; + EFI_HOB_GUID_TYPE *GuidHob; + + Status =3D (*PeiServices)->GetBootMode (PeiServices, &BootMode); + if (EFI_ERROR (Status) || (BootMode !=3D BOOT_ON_S3_RESUME)) { + // + // If not in S3 boot path. do nothing + // + return EFI_SUCCESS; + } + + // + // Initialize private data + // + SmmAccessPrivate =3D AllocateZeroPool (sizeof (*SmmAccessPrivate)); + ASSERT (SmmAccessPrivate !=3D NULL); + + PpiList =3D AllocateZeroPool (sizeof (*PpiList)); + ASSERT (PpiList !=3D NULL); + + // + // Build SMM related information + // + SmmAccessPrivate->Signature =3D SMM_ACCESS_PRIVATE_DATA_SIGNATURE; + SmmAccessPrivate->Handle =3D NULL; + + // + // Get Hob list + // + GuidHob =3D GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid); + ASSERT (GuidHob !=3D NULL); + DescriptorBlock =3D GET_GUID_HOB_DATA (GuidHob); + ASSERT (DescriptorBlock !=3D NULL); + + // + // Alloc space for SmmAccessPrivate->SmramDesc + // + SmmAccessPrivate->SmramDesc =3D AllocateZeroPool ((DescriptorBlock->Numb= erOfSmmReservedRegions) * sizeof (EFI_SMRAM_DESCRIPTOR)); + if (SmmAccessPrivate->SmramDesc =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Alloc SmmAccessPrivate->SmramDesc fail.\n")); + return EFI_OUT_OF_RESOURCES; + } + + // + // Use the hob to publish SMRAM capabilities + // + for (Index =3D 0; Index < DescriptorBlock->NumberOfSmmReservedRegions; I= ndex++) { + SmmAccessPrivate->SmramDesc[Index].PhysicalStart =3D DescriptorBlock->= Descriptor[Index].PhysicalStart; + SmmAccessPrivate->SmramDesc[Index].CpuStart =3D DescriptorBlock->= Descriptor[Index].CpuStart; + SmmAccessPrivate->SmramDesc[Index].PhysicalSize =3D DescriptorBlock->= Descriptor[Index].PhysicalSize; + SmmAccessPrivate->SmramDesc[Index].RegionState =3D DescriptorBlock->= Descriptor[Index].RegionState; + } + + SmmAccessPrivate->NumberRegions =3D Index; + SmmAccessPrivate->SmmAccess.Open =3D Open; + SmmAccessPrivate->SmmAccess.Close =3D Close; + SmmAccessPrivate->SmmAccess.Lock =3D Lock; + SmmAccessPrivate->SmmAccess.GetCapabilities =3D GetCapabilities; + SmmAccessPrivate->SmmAccess.LockState =3D FALSE; + SmmAccessPrivate->SmmAccess.OpenState =3D FALSE; + + PpiList->Flags =3D (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_= TERMINATE_LIST); + PpiList->Guid =3D &gPeiSmmAccessPpiGuid; + PpiList->Ppi =3D &SmmAccessPrivate->SmmAccess; + + Status =3D (**PeiServices).InstallPpi (PeiServices, PpiList); + ASSERT_EFI_ERROR (Status); + + DEBUG ( + (EFI_D_INFO, "SMM Base:Size %08X:%08X\n", + (UINTN)(SmmAccessPrivate->SmramDesc[SmmAccessPrivate->NumberRegions-1= ].PhysicalStart), + (UINTN)(SmmAccessPrivate->SmramDesc[SmmAccessPrivate->NumberRegions-1= ].PhysicalSize) + )); + + return EFI_SUCCESS; +} diff --git a/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/Sm= mAccessPei.inf b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPe= i/SmmAccessPei.inf new file mode 100644 index 0000000000..741eddd43c --- /dev/null +++ b/Platform/AMD/VanGoghBoard/VanGoghCommonPkg/Smm/SmmAccessPei/SmmAccess= Pei.inf @@ -0,0 +1,43 @@ +## @file +# Component description file for SmmAccessPei module +# +# Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
+# Copyright (c) 2013-2019 Intel Corporation. All rights reserved.
+# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +## + +[Defines] +INF_VERSION =3D 0x00010005 +BASE_NAME =3D SmmAccessPei +FILE_GUID =3D C6E6E43A-5DB1-4810-AAB7-C5A2A0914713 +MODULE_TYPE =3D PEIM +VERSION_STRING =3D 1.0 +ENTRY_POINT =3D SmmAccessPeiEntryPoint + +[Sources] + SmmAccessPei.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + ChachaniBoardPkg/Project.dec + AgesaPublic/AgesaPublic.dec + +[LibraryClasses] + PeimEntryPoint + PeiServicesLib + BaseMemoryLib + MemoryAllocationLib + DebugLib + HobLib + +[Ppis] + gPeiSmmAccessPpiGuid # ALWAYS_PRODUCED + +[Guids] + gEfiSmmPeiSmramMemoryReserveGuid + +[Depex] + gEfiPeiMasterBootModePpiGuid AND gEfiPeiMemoryDiscoveredPpiGuid --=20 2.31.1 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#114593): https://edk2.groups.io/g/devel/message/114593 Mute This Topic: https://groups.io/mt/103975468/1787277 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [importer@patchew.org] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-